Module-5 8051 Interrupts and Interfacing Application Interrupts

8051 Interrupts
Atria Institute of Technology 0000h
0001h
Reset

Timer Program Example:

Bengaluru-560024 0002h

Department of Electronics and Communication Engineering MOV TMOD,#20H ;T1/8-bit/auto reload 0003h INT0
MOV TH1,#5 ;TH1 = 5 0004h
SETB TR1 ;start the timer 1 …….
BACK: JNB TF1,BACK ;till timer rolls over 000Bh T0
CPL P1.0 ;P1.0 to hi, lo 000Ch
CLR TF1 ;clear Timer 1 flag
……
SJMP BACK ;mode 2 is auto-reload
0013h INT1
……
001Bh T1
8051 Interrupts and Interfacing Application ……
0023h Serial COM
By,
Module-5 NATARAJA N
….
0030h Main
Asst. Prof, Dept. of ECE,
Atria IT-Bangalore. 0031h
…….

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

8051 Interrupts:
 Polling can monitor the status of several devices and serve each of them as certain
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a
conditions are met
device needs its service
 The polling method is not efficient, since it wastes much of the microcontroller’s time by
 A single microcontroller can serve several devices by two ways: Interrupts & Polling polling devices that do not need service
 Interrupts  ex. JNB TF,target

 Whenever any device needs its service, the device notifies the microcontroller by sending
it an interrupt signal  The advantage of interrupts is that the microcontroller can serve many devices (not all at
 Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing the same time)
and serves the device  Each devices can get the attention of the microcontroller based on the assigned
 The program which is associated with the interrupt is called the interrupt service routine priority
(ISR) or interrupt handler  For the polling method, it is not possible to assign priority since it checks all devices in a
 Polling round-robin fashion
 The microcontroller continuously monitors the status of a given device  The microcontroller can also ignore (mask) a device request for service
 When the conditions met, it performs the service  This is not possible for the polling method
 After that, it moves on to monitor the next device until every one is serviced.

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Steps in Executing an Interrupt:

 Upon activation of an interrupt, the microcontroller goes through the following steps:
Interrupt Service Routine: 1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the
 For every interrupt, there must be an interrupt service routine (ISR), or stack
interrupt handler 2. It also saves the current status of all the interrupts internally (i.e: not on the stack)
 When an interrupt is invoked, the micro-controller runs the interrupt service 3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of
routine the ISR
 For every interrupt, there is a fixed location in memory that holds the address 4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it
of its ISR  It starts to execute the interrupt service subroutine until it reaches the last instruction of the
 The group of memory locations set aside to hold the addresses of ISRs is subroutine which is RETI (return from interrupt)
called interrupt vector table 4. Upon executing the RETI instruction, the microcontroller returns to the place where it was
interrupted
 First, it gets the program counter (PC) address from the stack by popping the top two bytes of
the stack into the PC
 Then it starts to execute from that address

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Interrupt vector table

Six Interrupts in 8051:
INTERRUPTS Interrupt ROM Location Pin
 Six interrupts are allocated as follows: (hex)
Reset 0000 9
 Reset – power-up reset
External HW (INT0) 0003 P3.2 (12)
 Two interrupts are set aside for the timers: one for timer 0 and one for timer 1 Timer 0 (TF0) 000B
 Two interrupts are set aside for hardware external interrupts External HW (INT1) 0013 P3.3 (13)
 P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1), and Timer 1 (TF1) 001B
INT1 (or EX2) Serial COM (RI and TI) 0023

 Serial communication has a single interrupt that belongs to both receive and ORG 0 ;wake-up ROM reset location
transfer LJMP MAIN ;by-pass int. vector table
;---- the wake-up program
ORG 30H
MAIN: Only three bytes of ROM space
.... assigned to the reset pin. We put
the LJMP as the first instruction
END and redirect the processor away
from the interrupt vector table.

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Enabling and Disabling an Interrupt: IE (Interrupt Enable) Register

 Upon reset, all interrupts are disabled (masked), meaning that none will be responded D7 D0
to by the microcontroller if they are activated EA -- ET2 ES ET1 EX1 ET0 EX0
 The interrupts must be enabled by software in order for the microcontroller to
EA (enable all) must be set to 1 in order
respond to them for rest of the register to take effect
 There is a register called IE (interrupt enable) that is responsible for enabling
(unmasking) and disabling (masking) the interrupts EA IE.7 Disables all interrupts
-- IE.6 Not implemented, reserved for future use
ET2 IE.5 Enables or disables timer 2 overflow or capture
interrupt (8952)
ES IE.4 Enables or disables the serial port interrupt
ET1 IE.3 Enables or disables timer 1 overflow interrupt
EX1 IE.2 Enables or disables external interrupt 1
ET0 IE.1 Enables or disables timer 0 overflow interrupt
EX0 IE.0 Enables or disables external interrupt 0

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-1
 To enable an interrupt, we take the following steps: Show the instructions to (a) enable the serial interrupt, timer 0
interrupt, and external hardware interrupt 1 (EX1),and (b) disable
1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take
(mask) the timer 0 interrupt, then (c) show how to disable all the
effect interrupts with a single instruction.
2. The value of EA Solution:
 If EA = 1, interrupts are enabled and will be responded to if their corresponding (a) MOV IE,#10010110B ;enable serial,
bits in IE are high ;timer 0, EX1
 If EA = 0, no interrupt will be responded to, even if the associated bit in the IE Another way to perform the same manipulation is
register is high SETB IE.7 ;EA=1, global enable
SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
(b) CLR IE.1 ;mask (disable) timer 0
;interrupt only
(c) CLR IE.7 ;disable all interrupts
D7 D0
EA -- ET2 ES ET1 EX1 ET0 EX0
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Timer Interrupts Example 11-2

Write a program that continuously get 8-bit data from P0 and sends it
 The timer flag (TF) is raised when the timer rolls over to P1 while simultaneously creating a square wave of 200 s period
 In polling TF, we have to wait until the TF is raised on pin P2.1. Use timer 0 to create the square wave. Assume that
XTAL = 11.0592 MHz.
 The problem with this method is that the microcontroller is tied down while waiting for TF
to be raised, and can not do anything else Solution:
 Using interrupts solves this problem and, avoids tying down the controller We will use timer 0 in mode 2 (auto reload). TH0 = 100/1.085 us = 92
 If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is ;--upon wake-up go to main, avoid using
raised, and the microcontroller is interrupted in whatever it is doing, and jumps to the ;memory allocated to Interrupt Vector Table
interrupt vector table to service the ISR ORG 0000H
 In this way, the microcontroller can do other task until it is notified that the timer has rolled LJMP MAIN ;by-pass interrupt vector table
over ;
;--ISR for timer 0 to generate square wave
ORG 000BH ;Timer 0 interrupt vector table
CPL P2.1 ;toggle P2.1 pin
TF0 Timer 0 Interrupt Vector TF1 Timer 1 Interrupt Vector RETI ;return from ISR
...
1 000BH 1 001BH
Jumps to Jumps to

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-4
Write a program to generate a square wave if 50Hz frequency on pin
... P1.2. This is similar to Example 9-12 except that it uses an interrupt
;--The main program for initialization for timer 0. Assume that XTAL=11.0592 MHz
ORG 0030H ;after vector table space Solution:
MAIN: MOV TMOD,#02H ;Timer 0, mode 2 ORG 0
MOV P0,#0FFH ;make P0 an input port LJMP MAIN
MOV TH0,#-92 ;TH0=A4H for -92 ORG 000BH ;ISR for Timer 0
MOV IE,#82H ;IE=10000010 (bin) enable CPL P1.2
;Timer 0 MOV TL0,#00
SETB TR0 ;Start Timer 0 MOV TH0,#0DCH
RETI
BACK: MOV A,P0 ;get data from P0 ORG 30H
MOV P1,A ;issue it to P1 ;--------main program for initialization
SJMP BACK ;keep doing it loop MAIN:MOV TM0D,#00000001B ;Timer 0, Mode 1
;unless interrupted by TF0 MOV TL0,#00
END MOV TH0,#0DCH
MOV IE,#82H ;enable Timer 0 interrupt
SETB TR0
HERE:SJMP HERE
END

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

EXTERNAL HARDWARE INTERRUPTS:

Activation of INT0
 The 8051 has two external hardware interrupts
Level-triggered
 Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INT0 and INT1, are used 0
as external hardware interrupts INT0
(Pin 3.2)
IT0 0003
1 IE0
 The interrupt vector table locations 0003H and 0013H are set aside for INT0 Edge-triggered (TCON.1)
and INT1
 There are two activation levels for the external hardware interrupts
 Level trigged Activation of INT1
 Edge trigged Level-triggered
0
INT1 IT1 0013
(Pin 3.3)
1 IE1
Edge-triggered (TCON.3)

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-5
Level-Triggered Interrupt: Assume that the INT1 pin is connected to a switch that is normally
 In the level-triggered mode, INT0 and INT1 pins are normally high
high. Whenever it goes low, it should turn on an LED. The LED is
connected to P1.3 and is normally off. When it is turned on it should Vcc
 If a low-level signal is applied to them, it triggers the interrupt stay on for a fraction of a second. As long as the switch is pressed low, P1.3 to LED
the LED should stay on.
 Then the microcontroller stops whatever it is doing and jumps to the interrupt INT1

vector table to service that interrupt Solution: P1.3

ORG 0000H
 The low-level signal at the INT pin must be removed before the execution of the LJMP MAIN ;by-pass inte rrupt
;vector table
last instruction of the ISR, RETI; otherwise, ;--ISR for INT1 to turn on LED
another interrupt will be generated ORG 0013H ;INT1 ISR Pressing the switch
while
SETB P1.3 ;turn on LED will cause the LED
 This is called a level-triggered or level- activated interrupt and is the default mode upon MOV R3,#255 to be turned on. If
BACK: DJNZ R3,BACK ;keep LED on for a while it is kept activated,
reset of the 8051 CLR P1.3 ;turn off the LED the LED stays on
RETI ;return from ISR

;--MAIN program for initialization

ORG 30H
MAIN: MOV IE,#10000100B ;enable external INT 1
HERE: SJMP HERE ;stay here until get interrupted
END

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Sampling Low Level-Triggered Interrupt:  To ensure the activation of the hardware interrupt at the INTn pin, make sure that
 Pins P3.2 and P3.3 are used for normal I/O unless the INT0 and INT1 bits in the IE the duration of the low-level signal is around 4 machine cycles, but no more
register are enabled
 This is due to the fact that the level-triggered interrupt is not latched
 After the hardware interrupts in the IE register are enabled, the controller keeps
 Thus the pin must be held in a low state until the start of the ISR execution
sampling the INTn pin for a low-level signal once each machine cycle
 According to one manufacturer’s data sheet,
 The pin must be held in a low state until the start of the execution of ISR
 If the INTn pin is brought back to a logic high before the start of the
execution of ISR there will be no interrupt 1 MC
 If INTn pin is left at a logic low after the RETI instruction of the ISR, another
4 machine cycles
interrupt will be activated after one instruction is executed To INT0 or
1.085us INT1 pins
4  1.085us
note: On reset, IT0 (TCON.0) and IT1 (TCON.2) are both
low, making external interrupt level-triggered

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

TCON (Timer/Counter) Register (Bit-addressable)

Edge-Triggered Interrupt:
 To make INT0 and INT1 edge- triggered interrupts, we must program the bits of the D7 D0
TCON register TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
 The TCON register holds, among other bits, the IT0 and IT1 flag bits that determine
TF1 TCON.7 Timer 1 overflow flag. Set by
level- or edge-triggered mode of the hardware interrupt
hardware when timer/counter
 IT0 and IT1 are bits D0 and D2 of the TCON register 1 overflows. Cleared by hardware as
 They are also referred to as TCON.0 and TCON.2 since the TCON register the processor vectors to the interrupt
service routine
is bit- addressable
TR1 TCON.6 Timer 1 run control bit. Set/cleared by
software to turn timer/counter 1 on/off
TF0 TCON.5 Timer 0 overflow flag. Set by
hardware when timer/counter 0
overflows. Cleared by hardware as the
processor vectors to the interrupt
service routine
TR0 TCON.4 Timer 0 run control bit. Set/cleared by
software to turn timer/counter 0 on/off
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Assume that pin 3.3 (INT1) is connected to a pulse generator, write a

TCON (Timer/Counter) Register (Bit-addressable) (cont’) program in which the falling edge of the pulse will send a high to
P1.3, which is connected to an LED (or buzzer). In other words, the
LED is turned on and off at the same rate as the pulses are applied to
IE1 TCON.3 External interrupt 1 edge flag. Set by
the INT1 pin.
CPU when the external interrupt edge When the falling edge of the signal
(H-to-L transition) is detected. Cleared is applied to pin INT1, the LED
Solution:
by CPU when the interrupt is processed ORG 0000H
will be turned on momentarily.

IT1 TCON.2 Interrupt 1 type control bit. Set/cleared LJMP MAIN

by software to specify falling edge/low- ;--ISR for hardware interrupt INT1 to turn on LED
ORG 0013H ;INT1 ISR
level triggered external interrupt
SETB P1.3 ;turn on LED
IE0 TCON.1 External interrupt 0 edge flag. Set by MOV R3,#255
CPU when the external interrupt edge BACK: DJNZ R3,BACK ;keep the buzzer on for a while
(H-to-L transition) is detected. Cleared The on-state duration
CLR P1.3 ;turn off the buzzer
by CPU when the interrupt is processed RETI ;return from ISR
depends on the time ;------MAIN program for initialization
delay inside the ISR
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared ORG 30H
for INT1
by software to specify falling edge/low- MAIN: SETB TCON.2 ;make INT1 edge-triggered int.
level triggered external interrupt MOV IE,#10000100B ;enable External INT 1
HERE: SJMP HERE ;stay here until get interrupted
END

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Sampling Edge- Triggered Interrupt:  Regarding the IE0 and IE1 bits in the TCON register, the following two points must be
 In edge-triggered interrupts emphasized
 The external source must be held high for at least one machine cycle, and then held  When the ISRs are finished (that is, upon execution of RETI), these bits (TCON.1 and
low for at least one machine cycle TCON.3) are cleared, indicating that the interrupt is finished and the 8051 is ready
to respond to another interrupt on that pin
 The falling edge of pins INT0 and INT1 are latched by the 8051 and are held by
 During the time that the interrupt service routine is being executed, the INTn pin
the TCON.1 and TCON.3 bits of TCON register
is ignored, no matter how many times it makes a high-to-low transition
 Function as interrupt-in-service flags  RETI clears the corresponding bit in TCON register (TCON.1 or TCON.3)
 It indicates that the interrupt is being serviced now and on this INTn pin, and no  There is no need for instruction CLR TCON.1 before RETI in the ISR
new interrupt will be responded to until this service is finished associated with INT0

Minimum pulse duration to

detect edge-triggered 1 MC 1 MC
interrupts XTAL=11.0592MHz 1.085us 1.085us

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-7
What is the difference between the RET and RETI instructions? SERIAL COMMUNICATION INTERRUPT
 TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is
Explain why we can not use RET instead of RETI as the last
instruction of an ISR.
transferred, indicating that the SBUF register is ready to transfer the next byte
Solution:  RI (received interrupt) is raised when the entire frame of data, including the stop bit,
Both perform the same actions of popping off the top two bytes of the is received
stack into the program counter, and marking the 8051 return to where
it left off.  In other words, when the SBUF register has a byte, RI is raised to indicate that the

However, RETI also performs an additional task of clearing the received byte needs to be picked up before it is lost (overrun) by new incoming
interrupt-in-service flag, indicating that the servicing of the interrupt serial data
is over and the 8051 now can accept a new interrupt on that pin. If
you use RET instead of RETI as the last instruction of the interrupt
service routine, you simply block any new interrupt on that pin after
the first interrupt, since the pin status would indicate that the interrupt
is still being serviced. In the cases of TF0, TF1, TCON.1, and
TCON.3, they are cleared due to the execution of RETI.

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

RI and TI Flags and Interrupts Use of Serial COM in 8051

 In the 8051 there is only one interrupt set aside for serial communication  The serial interrupt is used mainly for receiving data and is rarely used for sending data
 This interrupt is used to both send and receive data serially
 If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the  This is like getting a telephone call in which we need a ring to be notified
8051 gets interrupted and jumps to memory location 0023H to execute the ISR  If we need to make a phone call there are other ways to remind ourselves and there is
 In that ISR we must examine the TI and RI flags to see which one caused the no need for ringing
interrupt and respond accordingly  However in receiving the phone call, we must respond immediately no matter what we
are doing or we will miss the call

TI
0023H
RI
Serial interrupt is invoked by TI or RI flags

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-8
Write a program in which the 8051 reads data from P1 and writes it to ...
P2 continuously while giving a copy of it to the serial COM port to be ;-----------------SERIAL PORT ISR
transferred serially. Assume that XTAL=11.0592. Set the baud rate at ORG 100H
9600. SERIAL: JB TI,TRANS;jump if TI is high
Solution: MOV A,SBUF ;otherwise due to receive
ORG 0000H CLR RI ;clear RI since CPU doesn’t
LJMP MAIN RETI ;return from ISR
ORG 23H TRANS: CLR TI ;clear TI since CPU doesn’t
LJMP SERIAL ;jump to serial int ISR
RETI ;return from ISR
ORG 30H
MAIN: MOV P1,#0FFH ;make P1 an input port END
MOV TMOD,#20H ;timer 1, auto reload
MOV TH1,#0FDH ;9600 baud rate The moment a byte is written into SBUF it is framed and transferred
MOV SCON,#50H ;8-bit,1 stop, ren enabled serially. As a result, when the last bit (stop bit) is transferred the TI is
MOV IE,10010000B ;enable serial int. raised, and that causes the serial interrupt to be invoked since the
SETB TR1 ;start timer 1 corresponding bit in the IE register is high. In the serial ISR, we check
BACK: MOV A,P1 ;read data from port 1 for both TI and RI since both could have invoked interrupt.
MOV SBUF,A ;give a copy to SBUF
MOV P2,A ;send it to P2
SJMP BACK ;stay in loop indefinitely
...
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-9
Write a program in which the 8051 gets data from P1 and sends it to
P2 continuously while incoming data from the serial port is sent to P0. ...
Assume that XTAL=11.0592. Set the baud rata at 9600. ;-----------------SERIAL PORT ISR
ORG 100H
Solution: SERIAL: JB TI,TRANS;jump if TI is high
ORG 0000H MOV A,SBUF ;otherwise due to receive
LJMP MAIN MOV P0,A ;send incoming data to P0
ORG 23H CLR RI ;clear RI since CPU doesn’t
LJMP SERIAL ;jump to serial int ISR RETI ;return from ISR
ORG 30H TRANS: CLR TI ;clear TI since CPU doesn’t
MAIN: MOV P1,#0FFH ;make P1 an input port RETI ;return from ISR
MOV TMOD,#20H ;timer 1, auto reload END
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8-bit,1 stop, ren enabled
MOV IE,10010000B ;enable serial int.
SETB TR1 ;start timer 1
BACK: MOV A,P1 ;read data from port 1
MOV P2,A ;send it to P2
SJMP BACK ;stay in loop indefinitely
...
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-10
Clearing RI and Write a program using interrupts to do the following: ...
MOV IE,10010010B ;enable serial int.
TI before RETI (a) Receive data serially and sent it to P0,
(b) Have P1 port read and transmitted serially, and a copy given to SETB TR1 ;start timer 1
P2, SETB TR0 ;start timer 0
(c) Make timer 0 generate a square wave of 5kHz frequency on P0.1. BACK: MOV A,P1 ;read data from port 1
Assume that XTAL-11,0592. Set the baud rate at 4800. MOV SBUF,A ;give a copy to SBUF
MOV P2,A ;send it to P2
Solution:
ORG 0 SJMP BACK ;stay in loop indefinitely
LJMP MAIN ;-----------------SERIAL PORT ISR
ORG 000BH ;ISR for timer 0 ORG 100H
CPL P0.1 ;toggle P0.1 SERIAL:JB TI,TRANS;jump if TI is high
RETI ;return from ISR MOV A,SBUF ;otherwise due to receive
ORG 23H ; MOV P0,A ;send serial data to P0
LJMP SERIAL ;jump to serial interrupt ISR CLR RI ;clear RI since CPU doesn’t
ORG 30H RETI ;return from ISR
MAIN: MOV P1,#0FFH ;make P1 an input port
TRANS: CLR TI ;clear TI since CPU doesn’t
MOV TMOD,#22H;timer 1,mode 2(auto reload)
RETI ;return from ISR
MOV TH1,#0F6H;4800 baud rate
END
MOV SCON,#50H;8-bit, 1 stop, ren enabled
MOV TH0,#-92 ;for 5kHZ wave
...
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

 The TCON register holds four of the interrupt INTERRUPT PRIORITY

Interrupt flags, in the 8051 the SCON register has the RI  When the 8051 is powered up, the priorities are assigned according to the
Flag Bits and TI flags following
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0  In reality, the priority scheme is nothing but an internal polling sequence in
which the 8051 polls the interrupts in the sequence listed and responds
SM0 SM1 SM2 REN TB8 RB8 TI RI accordingly

Interrupt Flag SFR Register Bit

Interrupt Priority Upon Reset
External 0 IE0 TCON.1
External 1 IE1 TCON.3 Highest To Lowest Priority
Timer 0 TF0 TCON.5 External Interrupt 0 (INT0)
Timer 1 TF1 TCON.7 Timer Interrupt 0 (TF0)
Serial Port T1 SCON.1 External Interrupt 1 (INT1)
Timer 2 TF2 T2CON.7 (AT89C52) Timer Interrupt 1 (TF1)
Interrupt Flag Bits Timer 2 EXF2 T2CON.6 (AT89C52) Serial Communication (RI + TI)
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-11  We can alter the sequence of interrupt priority by assigning a higher priority to any one of
Discuss what happens if interrupts INT1, TF0, and INT0 are
activated at the same time. Assume priority levels were set by the
the interrupts by programming a register called IP (interrupt priority)
power-up reset and the external hardware interrupts are edge-  To give a higher priority to any of the interrupts, we make the corresponding bit in the
triggered. IP register high
Solution:  When two or more interrupt bits in the IP register are set to high
If these three interrupts are activated at the same time, they are  While these interrupts have a higher priority than others, they are serviced
latched and kept internally. Then the 8051 checks all five interrupts
according to the sequence of Table 11-13
according to the sequence listed in Table 11-3. If any is activated, it
services it in sequence. Therefore, when the above three interrupts
are activated, IE0 (external interrupt 0) is serviced first, then timer 0
(TF0), and finally IE1 (external interrupt 1).

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Interrupt Priority Register (Bit-addressable) Example 11-12

(a) Program the IP register to assign the highest priority to
D7 D0 INT1(external interrupt 1), then
-- -- PT2 PS PT1 PX1 PT0 PX0 (b) discuss what happens if INT0, INT1, and TF0 are activated at the
same time. Assume the interrupts are both edge-triggered.
-- IP.7 Reserved
Solution:
-- IP.6 Reserved
(a)MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority. The
PT2 IP.5 Timer 2 interrupt priority bit (8052 only) instruction SETB IP.2 also will do the same thing as the above
PS IP.4 Serial port interrupt priority bit line since IP is bit-addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than
PT1 IP.3 Timer 1 interrupt priority bit
the others; therefore, when INT0, INT1, and TF0 interrupts are
PX1 IP.2 External interrupt 1 priority bit activated at the same time, the 8051 services INT1 first, then it
PT0 IP.1 Timer 0 interrupt priority bit services INT0, then TF0. This is due to the fact that INT1 has a
higher priority than the other two because of the instruction in
PX0 IP.0 External interrupt 0 priority bit
Step (a). The instruction in Step (a) makes both the INT0 and
TF0 bits in the IP register 0. As a result, the sequence in Table
Priority bit=1 assigns high priority
11-3 is followed which gives a higher priority to INT0 over TF0
Priority bit=0 assigns low priority

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-13 Interrupt inside an Interrupt

Assume that after reset, the interrupt priority is set the instruction
MOV IP,#00001100B. Discuss the sequence in which the  In the 8051 a low-priority interrupt can be interrupted by a higher-priority interrupt

interrupts are serviced. but not by another low- priority interrupt

 Although all the interrupts are latched and kept internally, no low-priority interrupt
Solution:
The instruction “MOV IP #00001100B” sets INT1 and timer 1 can get the immediate attention of the CPU until the 8051 has finished servicing the
(TF1)to a higher priority level compared with the reset of the high-priority interrupts
interrupts. However, since they are polled according to Table, Triggering Interrupt by Software
 To test an ISR by way of simulation can be done with simple instructions to set the
they will have the following priority.

Highest Priority External Interrupt 1 (INT1)

interrupts high and thereby cause the 8051 to jump to the interrupt vector table
Timer Interrupt 1 (TF1)  ex. If the IE bit for timer 1 is set, an instruction such as SETB TF1 will interrupt the
External Interrupt 0 (INT0) 8051 in whatever it is doing and will force it to jump to the interrupt vector table
Timer Interrupt 0 (TF0)
Lowest Priority Serial Communication (RI+TI)  We do not need to wait for timer 1 go roll over to have an interrupt

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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-14
PROGRAMMING IN C Write a C program that continuously gets a single bit of data from P1.7
and sends it to P1.0, while simultaneously creating a square wave of
 The 8051 compiler have extensive support for the interrupts 200 s period on pin P2.5. Use Timer 0 to create the square wave.
 They assign a unique number to each of the 8051 interrupts Assume that XTAL = 11.0592 MHz.
Solution:
We will use timer 0 mode 2 (auto-reload). One half of the period is
Interrupt Name Numbers
100 s. 100/1.085 s = 92, and TH0 = 256 - 92 = 164 or A4H
External Interrupt 0 (INT0) 0 #include <reg51.h>
Timer Interrupt 0 (TF0) 1 sbit SW =P1^7;
sbit IND =P1^0;
External Interrupt 1 (INT1) 2 sbit WAVE =P2^5;
Timer Interrupt 1 (TF1) 3 void timer0(void) interrupt 1 {
WAVE=~WAVE; //toggle pin
Serial Communication (RI + TI) 4 }
void main() {
Timer 2 (8052 only) (TF2) 5 SW=1; //make switch input
TMOD=0x02;
TH0=0xA4; //TH0=-92
IE=0x82; //enable interrupt for timer 0
 It can assign a register bank to an ISR while (1) {
 This avoids code overhead due to the pushes and pops of the R0 – R7 registers IND=SW; //send switch to LED
}
}
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Module-5 8051 Interrupts and Interfacing Application Interrupts Module-5 8051 Interrupts and Interfacing Application Interrupts

Example 11-16
Write a C program using interrupts to do the following: .....
(a) Receive data serially and send it to P0
(b) Read port P1, transmit data serially, and give a copy to P2 void main() {
(c)Make timer 0 generate a square wave of 5 kHz frequency on P0.1 unsigned char x;
Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800. P1=0xFF; //make P1 an input
Solution: TMOD=0x22;
TH1=0xF6; //4800 baud rate
#include <reg51.h>
sbit WAVE =P0^1; SCON=0x50;
TH0=0xA4; //5 kHz has T=200us
void timer0() interrupt 1 {
WAVE=~WAVE; //toggle pin IE=0x92; //enable interrupts
} TR1=1; //start timer 1
TR0=1; //start timer 0
void serial0() interrupt 4 {
if (TI==1) { while (1) {
TI=0; //clear interrupt x=P1; //read value from pins
}
else { SBUF=x; //put value in buffer
P0=SBUF; //put value on pins P2=x; //write value to pins
RI=0; //clear interrupt }
}
} }
.....
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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

LCD Interfacing

LCD is finding widespread use replacing LEDs

The declining prices of LCD
The ability to display numbers, characters, and graphics
Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the
task of refreshing the LCD
Ease of programming for characters and graphics

LCD Connections:

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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

Display on LCD

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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

RS 0
R/W 1
En L-H
D7 Busy Flag

Communication
Using Busy Flag
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Module-5 8051 Interrupts and Interfacing Application LCD Module-5 8051 Interrupts and Interfacing Application LCD

6d.Write ALP to interface an LCD display and to display a message on it.

org 0000h commwrt: mov p2,a ; send command to lcd through p2 org 0300h
sjmp 0030h clr p3.7 ; RS=0 for command mcomm: db 38h,0eh,01h,06h,00h,0 ; commands and null
org 0030h clr p3.6 ; R/W= for write mdata: db " microcontroller " ; data and null
mov dptr,#mcomm setb p3.5 ; E=1 end
c1: clr a acall delay ; delay
movc a,@a+dptr clr p3.5 ; E=0 for H to L
acall commwrt ; call command subroutine ret
acall delay ; give LCD some time datawrt: mov p2,a ; send data to p2
jz send_dat setb p3.7 ; RS=1 for data
inc dptr clr p3.6 ; R/W=0 for write
sjmp c1 setb p3.5 ; E=1
send_dat: mov dptr,#mdata acall delay ; delay
d1: clr a clr p3.5 ; E=0 for H to L pulse
movc a,@a+dptr ret
acall datawrt ; call data with subroutine delay: mov r3,#50 ; Long delay
acall delay ; give LCD some time here2: mov r4,#255
inc dptr here: djnz r4,here
jz again djnz r3,here2
sjmp d1 ret
again: sjmp again ;stay here
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Module-5 8051 Interrupts and Interfacing Application TX Module-5 8051 Interrupts and Interfacing Application RX

Transmit serially Receive serially void display(unsigned char value) void main()
#include<reg51.h> 6b. Write an ALP to transfer data serially at 4800
baud rate continuously. Check the output on serial #include<reg51.h> { {
void main()
window1. sbit rs=P3^7; P2=value; char data1;
{
char A[]="microcontrollerlab,0"; sbit rw=P3^6; rs=1; lcdinit();
unsigned char i=0; sbit en=P3^5; rw=0; TMOD=0x20;
//P3=0x03; void delay(unsigned int time) en=1; TH1=0xFD;
TMOD=0x20; { delay(50); SCON =0x50;
TH1=0xFD; unsigned int i,j; en=0; TR1=1;
SCON=0x50; for(i=0;i<time;i++) delay(50); while(1)
TR1=1; for(j=0;j<5;j++); } {
while(1)
} void lcdinit(void) while(SBUF!=0x0D)
{
while(A[i]!='\0') void lcdcmd(unsigned char value) { {
{ { lcdcmd(0x38); while(RI==0);
SBUF=A[i]; P2=value; delay(50); data1=SBUF;
while(TI==0); rs=0; lcdcmd(0x0E); RI=0;
TI=0; rw=0; delay(50); display(data1);
i++; en=1; lcdcmd(0x01); delay(50);
} delay(50); delay(50); }
i=0;
en=0; lcdcmd(0x06); }
}
delay(50); delay(50); }
} }
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 Module-5 8051 Interrupts and Interfacing Application DAC

Atria Institute of Technology Digital-to-Analog Converter (DAC):

Bengaluru-560024
 Device that is widely used to convert Digital Pulses to Analog Signals
Department of Electronics and Communication Engineering
 In vast majority of DACs, MC1408(DAC0808) is used which uses R/2R Ladder
 R/2R Ladder is used because it gives Higher degree of Precision
 Resolution is Very important in DAC
 It is Function of Number of Binary inputs
 If n is the Number of Data bit Inputs, 𝟐𝒏 is the number of Analog output levels

8051 Interrupts and Interfacing Application  8-input DAC means 256 Discrete Voltage Values.
 Similarly we can go for 12,16-bit…. DAC
By,
Module-5 NATARAJA N
Asst. Prof, Dept. of ECE,
Atria IT-Bangalore.

Atria Institute of Technology NATARAJA N, Dept. of ECE, AIT

Module-5 8051 Interrupts and Interfacing Application DAC Module-5 8051 Interrupts and Interfacing Application DAC

MC1408(DAC0808):
The Total Current Provided by Iout is a function of Iref & D0-D7 Inputs
We take Iref =2mA , Max Iout =1.99mA

Fig: 8051 Connection

of DAC 0808

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Module-5 8051 Interrupts and Interfacing Application DAC Module-5 8051 Interrupts and Interfacing Application DAC

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Module-5 8051 Interrupts and Interfacing Application DAC Module-5 8051 Interrupts and Interfacing Application DAC

Generation of Sine Wave:

In the CKT, connect a switch SW to pin
P0.0. Write a program to do the
following:
a) When SW=0, DAC output gives a
Staircase Waveform
b) When SW=1, DAC output gives a
Triangular Waveform

Solution: Let us Design a Staircase

waveform for 5 Steps. Now 255/5
=51. After the Max value is
reached, the output drops to Zero
& Next Cycle Starts.

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Module-5 8051 Interrupts and Interfacing Application DAC Module-5 8051 Interrupts and Interfacing Application DAC

Write a ALP to Generate a Sine Wave using DAC0808. Show the Calculation for Full Scale Voltage of 10V at the output.

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 Module-5 8051 Interrupts and Interfacing Application Stepper Motor

A
Atria Institute of Technology
Bengaluru-560024
Department of Electronics and Communication Engineering
N
Stepper Motor:
 Translates Electrical Pulses into Mechanical
S
D B Movement
 Disk Drive, Robotics etc…. for Position Control
 It Consists of Rotor & Stator

8051 Interrupts and Interfacing Application C

By,
Module-5 NATARAJA N Fig: Rotor Alignment
Asst. Prof, Dept. of ECE,
Atria IT-Bangalore.

Atria Institute of Technology NATARAJA N, Dept. of ECE, AIT

Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

0 0
A A
Step # A B C D HEX S Step # A B C D HEX
1 0 1 1 0 6 1 0 1 1 0 6
N

N N
0 1 0 S N S N 1
S S
D B D B

N
1 C 1 C

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

0 0
A A
S Step # A B C D HEX S Step # A B C D HEX
1 0 1 1 0 6 1 0 1 1 0 6
N N
2 0 0 1 1 3

0 S N S N 1 1 N S N S 0

D B D B

S S

N N
1 C 1 C

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

0 1
A A
S Step # A B C D HEX N Step # A B C D HEX
1 0 1 1 0 6 1 0 1 1 0 6
N S
2 0 0 1 1 3 2 0 0 1 1 3

1 N S N S 0 1 N S N S 0 3 1 0 0 1 9

D B D B

S N

N S
1 C 0 C

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

1 1
A A
N Step # A B C D HEX N Step # A B C D HEX
1 0 1 1 0 6 1 0 1 1 0 6
S S
2 0 0 1 1 3 2 0 0 1 1 3

1 N S N S 0 3 1 0 0 1 9 0 S N S N 1 3 1 0 0 1 9

D B D B 4 1 1 0 0 C
N N

S S
0 C 0 C

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

1
A Program:
N Step # A B C D HEX
1 0 1 1 0 6
S
2 0 0 1 1 3

0 S N S N 1 3 1 0 0 1 9

D B 4 1 1 0 0 C
N

S
0 C

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

1 1
A Step Angle: Min degree of Rotation Associated with Single Step A
N N
Step per Revolution: Total No. of Steps need to Rotate one
S Complete rotation(360 degree) S Step Angle: 90 Degree
Step per Revolution =4
Eg: Step Angle = 2𝑜 if No. of Steps per Revolution is 180. No. of Rotor Teeth =4/4 =1
0 S N 0 S N Moves per 4-Step Sequence =360
S N 1 S N 1
After Completing every 4 Steps, The Rotor move only one tooth
D B Pitch D B

N In a Stepper Motor with 200 Step per Revolution, the Motor has N
50 Teeth since 4 X 50 =200 Steps.
S S
0 C 0 C

𝑟𝑝𝑚 𝑋 𝑆𝑡𝑒𝑝𝑠 𝑝𝑒𝑟 𝑟𝑒𝑣𝑜𝑙𝑢𝑡𝑖𝑜𝑛

Step per Second =
60

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

Ex: Write a Program to rotate a motor 64 Degree in the Clock wise. The Motor has a step angle of 2 Degree.
Use the 4-StepSequence.
Table: Normal 4-Step Sequence (Two Phase Sequence)

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

Table: Wave Drive 4-Step Sequence (Single Phase Sequence)

Fig: 8051 Connection to Stepper Motor

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

Table: Half-Step 8-Step Sequence A Switch is Connected to pin

P2.7. Write a Program to
Monitor the status of SW &
perform the Following:
a) If SW=0, Stepper motor
moves Clockwise
b) If SW=1, Stepper motor
moves Anti-Clockwise

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Module-5 8051 Interrupts and Interfacing Application Stepper Motor Module-5 8051 Interrupts and Interfacing Application Stepper Motor

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