VHDL Programming for
Sequential Circuits
The SR Latch circuit diagram using Nand gate
S R Q
0 0 not allowed
0 1 1
1 0 0
1 1 no change
VHDL Code for an SR Latch using Nand gate
library ieee;
use ieee.std_logic_1164.all;
entity srl is
port(r,s:in bit;
q,qbar:buffer bit);
end srl;
architecture virat of srl is
signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end virat;
Gated D Latch Operation
The logic symbol for a gated D latch
o On the above gated D latch, D is the data input, Q is the data
output and EN is the active high enable.
o The gated D latch will only reflect the D input on the Q output
when EN is active.
o When EN is not active, the last state of Q is latched (the last state
of Q when EN was last active).
Gated D Latch VHDL Code
o There is usually more than one way to implement a logic design
in VHDL code.
o The same D latch is implemented in two different ways below to
illustrate this point.
First D Latch VHDL code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_top is
Port ( D : in STD_LOGIC;
EN : in STD_LOGIC;
Q : out STD_LOGIC);
end d_latch_top;
architecture Behavioral of d_latch_top is
signal DATA : STD_LOGIC;
begin
DATA <= D when (EN = '1') else DATA;
Q <= DATA;
end Behavioral;
o In the above VHDL code, the signal DATA is used to store the
state of the data that is to be latched.
o DATA is made to be the same as the D input when EN is high.
o When EN is low, DATA will equal DATA – in other words the
value that was last stored in data when EN was high is now
latched in DATA.
o The Q output of the latch is made to reflect the logic state stored
in DATA.
Second D Latch VHDL code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_2_top is
Port ( EN : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end d_latch_2_top;
architecture Behavioral of d_latch_2_top is
begin
process (EN, D)
begin
if (EN = '1') then
Q <= D;
end if;
end process;
end Behavioral;
o This second VHDL code gated D latch is implemented in a
VHDL process.
o In the process, if EN is high, then the D input is reflected on the
Q output.
o When EN is low nothing happens, which means that Q stays at
the same
The clocked SR Latch (flip-flop) circuit
In this project, we will,
o Write a VHDL program to build a clocked SR Latch (flip-flop) circuit
o Verify the output waveform of the program (the digital circuit) with the flip-flop
circuit’s truth table
A clocked SR latch circuit:
Truth table
VHDL program for A clocked SR latch
library ieee;
use ieee.std_logic_1164.all;
entity RS_FF is
port (clk,r,s : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
end RS_FF;
architecture RSFF_arch of RS_FF is
signal t1,t2 : std_logic;
begin
t1 <= r nor t2;
t2 <= s nor t1;
process (clk,r,s)
begin
if(clk’event and clk=’1′ ) then
if(r=’0′ and s=’0′) then
Q <=t1;
Qnot <= t2;
elsif(r=’0′ and s=’1′) then
Q <=’1′;
Qnot <=’0′;
elsif(r=’1′ and s=’0′) then
Q <=’0′;
Qnot <=’1′;
elsif(r=’1′ and s=’1′) then
Q <=’X’;
Qnot <=’X’;
end if;
end if;
end process;
end RSFF_arch;
Simulation waveform
As shown in this figure,
o when the clock input is ‘1,’ then “s” is ‘1.’
o And when “r” is ‘0,’ the flip-flop is set – which means that the
Q output is ‘1’ and the Qnot is ‘0.’
The JK flip-flop with a preset and a clear circuit:
o Write a VHDL program to build a JK flip-flop circuit
o Verify the output waveform of the program (the digital
circuit) with the flip-flop truth table.
JK flip-flop with a preset and a clear Truth table
Note 1: when J=1 and K=1, the Q output toggles every time (from
0 to 1 and 1 to 0)
Note 2: when J=0 and K=0, the Q output retains its previous state
VHDL program for JK flip-flop with a preset and a clear
library ieee;
use ieee.std_logic_1164.all;
entity JK_flip_flop is
port (clk,J,K,prs,clr : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
end JK_flip_flop;
architecture JKFF_arch of JK_flip_flop is
signal nxt_state,prv_state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin
input <= J & K;
process(clk, prs,clr) is
begin
if (clr=’1′) then
nxt_state <= ‘0’;
elsif (prs=’1′) then
nxt_state <= ‘1’;
elsif (clk’event and clk=’1′) then
case (input) is
when “10” => nxt_state <= ‘1’;
when “01” => nxt_state <= ‘0’;
when “00” => nxt_state <= prv_state;
when “11” => nxt_state <= not prv_state;
when others => null;
end case;
end if;
end process;
Q <= nxt_state;
Qnot <= not nxt_state;
prv_state <= nxt_state;
end JKFF_arch;
Simulation waveform
o As shown in this figure,
o there are three cases are highlighted in red, green, and blue:
o Case 1: when prs=1 -> Q = 1 and Qnot = 0 (the flip-flop is set)
o Case 2: when clr=1 -> Q=0 and Qnot = 1 (the flip-flop is clear)
o Case 3: when J=1, K=0 and clk=1 – > Q = 1 and Qnot = 0
The T flip-flop with an enable and active high reset input circuit
o Write a VHDL program to build the T flip-flop circuit
o Verify the output waveform of the program (the digital circuit)
with the flip-flop’s truth table
Truth table
o Note 1: when T=1, the Q output toggles every time (from 0 to 1 and 1 to 0)
o Note 2: when T=0, the Q output retains its previous state
VHDL program for The T flip-flop with an enable and active high reset input
library ieee;
use ieee.std_logic_1164.all;
entity T_flip_flop is
port (clk,t,en,rst : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
end T_flip_flop;
architecture TFF_arch of T_flip_flop is
signal op: std_logic;
begin
process(clk, rst) is
begin
if(en=’0′) then op<=’Z’;
elsif (en=’1′ and rst=’1′) then
op <= ‘0’;
elsif (clk’event and clk=’1′ and en=’1′) then
if(t=’1′) then op <= not op;
else op <= op;
end if;
end if;
end process;
Q <= op;
Qnot <= not op;
end TFF_arch;
Simulation waveform
o As shown in this figure,
o three cases are highlighted in red, blue, and green.
o Case 1: when en=0 -> both outputs are at a high impedance
o Case 2: when en=1 and rst=1 -> Q=0 and Qnot = 1 (the flip-flop is reset)
o Case 3: when en=1, rst=0 and clk=1 and T=1 – > Q = 1 and Qnot = 0 (the
output toggles between 0-1)
