Module 5: ARM Microcontrollers – Complete Notes
1. CISC vs RISC Architecture
Feature CISC (Complex Instruction Set Computer) RISC (Reduced Instruction Set Computer)
Instruction Set Large and complex Small and simple
Instruction Length Variable Fixed (typically 32-bit)
Clock Cycles per Instruction Multiple Mostly one
Memory Access Instructions can access memory directly Only load/store instructions can access memory
Code Size Smaller Larger
Execution Time Slower due to complexity Faster due to simplicity
Hardware Complexity Complex Simple
Examples Intel x86, Motorola 68000 ARM, MIPS, RISC-V
2. RISC Deviation from CISC Architecture
RISC was developed to overcome the limitations of CISC by simplifying instruction sets for higher performance.
Key Deviation Points:
Fixed-Length Instructions Simpler decoding and pipelining
Load/Store Architecture Memory is accessed only through specific instructions
More Registers Reduces memory access and improves speed
No Microcode Layer Execution is direct through hardware
Efficient Pipelining Minimal dependencies between instructions
Advantage:
High speed, better power efficiency, ideal for embedded systems (like ARM microcontrollers)
3. Necessity of RISC Processor
Embedded systems need low power, high speed, small code footprint RISC is perfect.
Ideal for mobile, battery-powered, real-time systems
Enables faster instruction execution with less heat and power
Fits modern compact designs with limited memory/storage
4. ARM Processor Fundamentals
32-bit RISC architecture
Load/Store model
Unified memory (Von Neumann architecture)
Barrel shifter for inline shifting
Thumb mode for compressed 16-bit instruction execution
Large general-purpose register set
5. ARM7TDMI Features
Letter Meaning Role
T Thumb 16-bit compressed instructions
D Debug Embedded debug features
M Multiplier High-speed hardware multiplier
I ICE In-Circuit Emulator for testing
Supports both 32-bit ARM & 16-bit Thumb instructions
Used in embedded systems like calculators, mobile phones, smart devices
Uses Von Neumann architecture
3-stage pipeline: Fetch Decode Execute
6. Register Set
Register Name Use
R0–R12 General Purpose Data processing
R13 SP Stack Pointer
R14 LR Link Register (return address)
R15 PC Program Counter
CPSR Status Register Flags + Mode bits
SPSR Saved Status Register Holds old CPSR in interrupt modes
Banked Registers are used in special modes for faster context switching
7. Operational Modes
Mode Use
User Normal execution (unprivileged)
FIQ Fast Interrupt (high priority)
IRQ Normal Interrupt
SVC Supervisor Mode (after reset)
ABT Abort Mode (memory errors)
UND Undefined Instruction
SYS System Mode (privileged like User)
Modes allow ARM to handle different scenarios (interrupts, OS calls, etc.)
Each has access to its own banked registers (like LR, SP)
8. ARM Core Data Flow Model
Stages:
Instruction Fetch (PC IR)
Instruction Decode
Operand Fetch
Execute via ALU (with Barrel Shifter)
Write Back
Key Units:
ALU
Barrel Shifter
Control Unit
Register File (R0–R15)
Instruction Decoder
9. Pipelining in ARM
3-Stage Pipeline (used in ARM7TDMI):
Stage Description
Fetch Get instruction from memory
Decode Decode the instruction
Execute Perform operation in ALU
Improves throughput: 1 instruction finishes every cycle after pipeline is full
5-Stage Pipeline (used in ARM9):
Stage Description
Fetch Instruction fetched
Decode Instruction is decoded
Execute ALU processes
Memory Data memory accessed
Writeback Result stored to register
Faster, more complex – helps achieve high performance
10. Pipeline Hazards
Type Description Solution
Data Hazard When one instruction depends on result of another Forwarding, Stalling
Control Hazard Caused by branches and jumps Branch prediction
Structural Hazard When hardware resources are shared Resource duplication or pipeline stalls
Sample Numerical (Pipelining):
Q: In a 3-stage pipeline, how many clock cycles are needed to execute 6 instructions?
A:
First instruction takes 3 cycles to complete
From 4th cycle onwards, one instruction completes per cycle
Total Cycles = (Pipeline stages - 1) + Number of instructions
= (3 - 1) + 6 = 8 cycles
Final One-Line Summary
ARM Microcontrollers are built on the efficient RISC architecture, using pipelining, register banking, and compressed instructions to offer high
performance and low power — perfect for embedded and real-time systems.
