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ADSP-21000 Family Applications Handbook

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Analog-Digital Conversion Handbook
Digital Signal Processing in VLSI
DSP Applications Using the ADSP-2100 Family (Vols. 1 & 2)

Ask The Applications Engineer

© Analog Devices, Inc., 1997
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ii 30th Anniversary Reader Bonus Ask The Applications Engineer

 TABLE OF CONTENTS
Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
␣ 1. Multi troubles, Trouble from the start, About log compensation resistors . . . . . . . . . . . . . James Bryant ␣␣1
␣ 2. When it comes to trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣␣2
␣ 3. V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣␣4
␣ 5. Used correctly, high-speed comparators provide many useful circuit functions . . . . . . . . . . John Sylvan ␣␣6
␣ 6. Op-amp issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣␣8
␣ 7. Op-amp issues—Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣ 10
␣ 8. Op-amp issues—Noise (continued), How grainy is current flow? . . . . . . . . . . . . . . . . . . . James Bryant ␣ 12
␣ 9. Seminars and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chris Hyde ␣ 14
Supply decoupling, non-idealities of resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣ 14
10. PC-board tracks and ground planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣ 16
11. Voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣ 18
12. Grounding (again) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Walt Kester ␣ 20
Time references, More on Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . James Bryant ␣ 22
13. Confused about amplifier distortion specs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Walt Kester ␣ 23
14. High-frequency signal contamination . . . . . . . . . . . . . . . . . . . . . . James Bryant, with Herman Gelbach ␣ 26
A Reader Notes (re-High-frequency signal contamination) . . . . . . . . . . . . . . . . . . . . . . . . Leroy Cordill ␣ 28
15. Using sigma-delta converters, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oli Josefsson ␣ 29
16. Using sigma-delta converters, part II, and questions on noise in converters . . . . . . . . . . . Oli Josefsson ␣ 33
17. Must a “16-bit” converter be 16-bit monotonic and settle to 16 ppm? . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dave Robertson and Steve Ruscak ␣ 39
18. Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peter Checkovich ␣ 40
19. Interfacing to serial converters, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eamon Nash ␣ 42
20. Interfacing to serial converters, part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eamon Nash ␣ 44
21. Capacitance and capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Steve Guinta ␣ 46
22. Current-feedback amplifiers, part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erik Barnes ␣ 50
23. Current-feedback amplifiers, part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erik Barnes ␣ 52
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Ask The Applications Engineer 30th Anniversary Reader Bonus iii

 PREFACE AND INTRODUCTION

This special issue of Analog Dialogue is offered as a bonus to our faithful readers and an encouragement to new readers. We have
reprinted here the popular series, entitled “Ask The Applications Engineer”, from its inception in 1988 through Number 23* in
1996.

We are celebrating Analog Dialogue’s 30th sequential year in print, just concluded. During those years, Analog Dialogue has informed,
enlightened, and occasionally educated more than a generation of engineers, scientists, and technicians about Analog Devices’s
products, practice, and ideas for high-performance signal processing by analog, digital, and mixed means.
This 30th anniversary Selection, Ask The Applications Engineer, joins the collection of articles in our 25th anniversary bonus
edition, The Best of Analog Dialogue—1967 to 1991. Readers of that 224-page collection (still available upon request) will recall its
many articles relating to practice—as well as articles about landmark products. Our intent in originating the “Ask The Applications
Engineer” series has been to supplement that mine of information with a source of what has come to be called FAQ—frequently
asked questions (and answers). They are chronicled by a few of our Applications Engineers, but are based on the accumulated
wisdom and experience of our worldwide Applications Engineering staff, interacting with tens of thousands of customers worldwide.

Throughout the pages of this volume you will find references to Analog Devices products and publications, just as they appeared
in the original edition. If you are interested in receiving copies of publications available from Analog Devices or information about
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Help line or one of our local offices.

The articles in this publication appear in chronological order, starting with “Ask The Applications Engineer—1”. But in order for
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to a particular interest wherever it appears. We hope you will find this publication helpful and will welcome your suggestions of
questions to be answered in the future.

[email protected]

Editor, Analog Dialogue

*With one exception: We have not included “Ask The Applications Engineer—4”, which was devoted to a description of a 5.25" Component Selection
Guide diskette that was novel and useful in its time; however, it has long been obsolete—in this day of the Web site, the CD-ROM, and the selection tree
in print. Just about everything else has turned out to include information of timeless value.

iv 30th Anniversary Reader Bonus Ask The Applications Engineer

Ask The Applications Engineer—1 Busy signal is always present on power-up the problem is almost
certain to be recognized—and addressed—during the design
by James Bryant of the system; but if the Busy signal is only occasionally present
on power-up the system may latch unpredictably. As a rule,
MULTI TROUBLES
control signals to an ADC during start-up should not depend
Q. My multiplexed ADC system is misbehaving . . .
on the logical state of Busy. b
A. Before you go any further, have you grounded all unused
multiplexer channels? ABOUT LOG COMPENSATION RESISTORS
Q. Designs of logarithmic circuits*, including those using the AD538
Q. No. But how did you know?
Y[Z/X] m unit: (for example, Figure 6 from the AD538
A. Because the floating terminal is one of the commonest causes Multifunction Unit data sheet†) call for “kT/q compensation
of problems in systems containing CMOS multiplexers. resistors”. What are they and where do I get them?
Unused MUX inputs and outputs (whether integrated into a
A. The VBE difference across two opposed silicon junctions,
multiplexed ADC or part of a self-contained MUX chip) can
one carrying a current, I, and the other a current, IREF, is
pick up signals from stray fields and inject them into the
(kT/q) ln (I/IREF). Here, k/q is the ratio of Boltzmann’s constant
device’s substrate, turning on spurious substrate devices.
to the charge on an electron (about 1/11,605 K/V), and T is
Then, even when the unused channel is turned off, the
the absolute temperature in kelvins.
performance of the on-channel may be badly degraded (at the
unlikely extreme, the injection may turn on a spurious four- Although employing similar junctions in isothermal pairs
layer device and destroy some chips). eliminates the effects of temperature-sensitivity of reverse
saturation current, the kT/q term is still temperature-dependent.
Whenever a MUX is used, all its inputs and outputs must be
To eliminate this dependency in the application, the
connected to a potential between its supply rails. The best way to
logarithmic voltage must be used in a circuit whose gain is
deal with unused channels is to ground them, but they may be
inversely proportional to the absolute temperature of the
connected to a more-convenient potential within the rails. b
junctions. Over a reasonable range of temperatures near
TROUBLE FROM THE START 20°C, this may be arranged by the use of a gain-setting 1-kΩ
Q. To save power, my ADC is powered up only to make a measurement. resistor having a positive temperature coefficient of
The system is very accurate in continuous operation, but approximately 3,400ppm/°C—and keeping it at the same
unpredictable when power is strobed. Why? temperature as the junctions.
A. When an ADC’s power is switched on only to perform a A 3,500 ppm/°C resistor is available from Tel Laboratories,
conversion, it may misbehave for three reasons: slow reference 154G Harvey Road, Londonderry, New Hampshire 03053
turn-on, random initial logic states, and system latch-up. (603)-625-8994, Telex: (710)-220-1844, designated Q-81, and
from the Precision Resistor Co. Inc., 10601, 75th. St., Largo,
For various reasons—thermal stabilization, capacitance
Florida 33543 [(813)-541-5771 Telex: 821788], as the PT146.
charging, slow starting of regenerative current mirrors using
Analog Devices offices in most European countries are aware
PNP transistors in band-gap references— it is not uncommon
of local suppliers of these resistors. b
for some voltage references to have relatively large errors for
many milliseconds after power-up. Such errors in an ADC’s
external or internal reference during conversion lead to
inaccurate results.
At turn-on, a typical ADC’s logic will be in a random state; for
a conversion triggered at that time, the ADC may not be able
to perform correctly. With one conversion triggered, the logic
should return to its correct pre-conversion state—but cases
exist where two conversion cycles are necessary before the ADC
is certain to perform a valid conversion. Hence, a good general
rule is to perform two “dummy” conversions after powerup
before relying on the results. (It is also well to recall that some
ADCs react badly to having a conversion triggered before the
previous conversion is complete; when this happens, one or
two “dummy” conversions may be needed to return the logic
to a known state.)
If an ADC’s external logic is arranged so that the end of the
ADC “Busy” signal starts a delay which ends with the start of
the next conversion, it is important to realize that if the *Much useful information about logarithmic and other analog function
converter powers up in the Busy state, the Busy signal may circuits can be found in the Nonlinear Circuits Handbook, published by
remain latched up until a conversion Start pulse has been Analog Devices ($5.95), P.O. Box 9902, Norwood MA 02062.
†See The Best of Analog Dialogue 1967–1991, pp. 164-167.
received. In this case, such a system cannot self-start. If the

Analog Dialogue 22-2 (1988) 1

Ask The Applications Engineer—2 of full-scale range). Depending on the architecture used, this
bipolar offset (BOS) may or may not be affected by the gain
by James Bryant trim. If it is so affected, equation (1) becomes:
WHEN IT COMES TO TRIMMING . . . OP = K × (IP – BOS) (4)
Q. I need some advice about trimming offsets and gains. In this case offset is trimmed at analog zero, after which gain is
A. Don’t!—unless you must. Good alternatives include (a) using trimmed near FS—positive or negative, but usually positive.
headache-free devices, components, and circuits that meet the This is normally the method used for DACs where the bipolar
specs without trimming; (b) taking advantage of digital offset is within the DAC.
technology in system applications to make trim corrections in If the bipolar offset is not affected by the gain trim:
software. Savings provided on occasion by trim potentiometers,
OP = K × IP – BOS (5)
in conjunction with loosely spec’d devices, can turn out to be
illusory when you consider the effects of circuit design, Here offset is trimmed at FS negative and gain is trimmed at
temperature, vibration, and life on performance and stability— (or very near to—see below) FS positive. This method is used
as well as additional paperwork and complexity trimming for most ADCs and for DACs where bipolar offset is obtained
entails. by the use of op amps and resistors external to the DAC.
Q. Nevertheless, how do I trim the offset and gain errors in analog Naturally, the method suggested on the data sheet should
circuitry? always be followed, but where a data sheet is unobtainable, in
general, offset should be trimmed at analog zero for DACs
A. In the correct order and with the correct inputs. If you consider
and FS negative for ADCs—and near FS positive for both.
the transfer characteristic of the circuit being trimmed the
method to use is generally straightforward. Q. Why do you keep saying “near” to full scale?
The simplified ideal transfer characteristic of a linear analog A. Amplifiers and DACs may be trimmed at zero and full scale.
circuit (such as an amplifier, ADC or DAC) is given by the In the case of a DAC, all-1’s—the largest digital input
equation: possible—should produce an output 1 LSB below “full scale,”
where “full scale” is considered as some constant times the
OP = K × IP (1)
reference; this follows since the output of a DAC is the
where OP is output, IP is input, and K is a scale factor (Note normalized product of the reference and the digital input.
that this simplification hides an enormous number of issues:
ADCs are not trimmed at zero and FS. The output of an
quantization error in an ADC; dimensionality of K if the input
ideal ADC is quantized, and the first output transition (from
and output are in different forms [e.g. voltage in / current out];
00 . . . 00 to 00 . . . 01) takes place 1/2 LSB above the nominal
intentional offsets; and many others.)
value of all 0’s. Thereafter transitions take place every 1-LSB
In a real (non-ideal) circuit, offset and gain errors, OS (referred increase in analog input until the final transition takes place
to the input) and ∆K, respectively, also appear in the equation, 1 1/2 LSB below FS. A non-ideal ADC is trimmed by setting
which becomes: its input to the nominal value of a desired transition and then
OP = (K + ∆K) × (IP + OS) (2) adjusting until the ADC output flickers between the two values
equally.
OP = (K × IP) + [(K × OS) + (∆K × IP) + (∆K × OS)] (3)
The offset of an ADC is therefore trimmed with an input
Equations (2) and (3) are incomplete in that they assume only
corresponding to the first transition (i.e., 1/2 LSB above zero
one offset—at the input—but this is the most-common case.
or above FS negative—which is “near” zero or “near” FS
Systems with separate input and output offsets will be
negative); and the gain is then trimmed at the last transition
considered later.
(i.e. 1 1/2 LSB below FS positive—which is “near” FS positive).
From (3) we see that it not possible to trim gain directly when This procedure results in an interaction between the gain and
an unknown offset is present. Offset must be trimmed first. offset errors during offset trim but it should be too slight to be
With IP set at 0, the offset trim is adjusted until OP is also 0. significant.
Gain may then be trimmed: with an input near to full scale
Q. Are there any other anomalies resulting in a need to trim “near”,
(FS), the gain trim is adjusted to make the output obey
rather than at full scale?
equation (1).
A. Synchronous voltage-to-frequency converters (SVFCs) are
Q. But what about bipolar ADCs and DACs?
liable to injection locking phenomena when their output
A. Many ADCs and DACs may be switched between unipolar frequency is harmonically related to their clock frequency,
and bipolar operation; such devices, wherever possible, should i.e., when their output is very close to 1/2, 1/3 or 1/4 of
have their offset and gain trimmed in the unipolar mode.Where clock frequency. FS for an SVFC is 1/2 clock frequency.
it is not possible, or where the converter is to operate only in The presence of a trim tool can exacerbate the problem. It
the bipolar mode, other considerations apply. is therefore advisable to trim the gain of an SVFC at around
A bipolar converter may be considered as a unipolar converter 95% of FS.
with a large offset (to be precise, an offset of 1 MSB—one-half

2 Analog Dialogue 23-1 (1989)

 Ask The Applications Engineer – 2

Q. What about circuits requiring both “input” and “output” offset very large value of summing resistance, compared to the
trim? signal-input resistances, in order to (i) avoid loading the
A. Circuits such as instrumentation and isolation amplifiers often summing point excessively, (ii) scale the correction voltage
have two stages of dc gain, and the gain of the input stages can properly and produce enough attenuation to minimize the
be variable. Thus a two stage amplifier, with an input offset, effects of differential supply-voltage drifts. It is often helpful
IOS, an output offset, OOS, a first stage gain of K, and a to use resistances between the supplies and the potentiometer
unity-gain output stage, has (for zero input) an output, OP, to increase trim resolution and reduce dissipation.
of: Where gain trim is provided for in a circuit, it will generally
OP = OOS + K × IOS (6) consist of a variable resistor. Details of its value and connection
will appear on the data sheet of the device. Where gain trim is
From (6) it is evident that if the gain is constant we need only not required, this resistor may be replaced by a fixed resistor
adjust either IOS or OOS to null the total offset (although if having half the resistance of the maximum value of the
the input uses a long-tailed pair of bipolar transistors we will recommended trim potentiometer.
get a better offset temperature coefficient if we trim both—for
FET long-tailed pairs this is not necessarily the case). If the Where gain trim is not provided it is not always achievable
first stage gain is to be varied, both offsets must be trimmed. externally without an additional variable-gain stage. For
example, consider a DAC using a ladder network. If the ladder
This is done by an iterative procedure. With zero input, and network is used in the current mode (Figure 2a), the input
gain set to maximum, the input offset is adjusted until the impedance at the reference terminal does not vary with digital
output is also zero. The gain is then reduced to its minimum code, and the gain of the DAC may be trimmed with a small
value and the output offset adjusted until the output is zero variable resistor in series with either the reference input or the
again. The two steps are repeated until no further adjustment feedback resistor. However, if the DAC is used in the voltage
is necessary. Gain trimming should not be done until both mode (Fig 2b), then the reference input impedance is code
IOS and OOS are pulled; the actual values of the high and low dependent, and gain may only be trimmed by varying the
gains used in offset trim are unimportant. reference voltage—which is not always possible—or the gain
Q. What circuitry should I use for gain and offset trims? of the buffer amplifier.
A. Many amplifiers (and a few converters) have terminals for The possibility of trimming gain in circuits not furnished with
trimming gain and offset. Many more do not. gain-trim circuitry, therefore, will depend on individual cases;
Offset trim is normally performed with a potentiometer each must be assessed on its own merits. b
connected between two assigned terminals, and its wiper is
connected (sometimes via a resistor) to one of the supplies.
The correct connections and component values will be given
on the device data sheet. One of the commonest differences
between op-amps is the value of offset correction potentiometer
and which supply it should be connected to.
Where separate terminals are not provided for offset trim, an
offset-adjusting constant can usually be added to the input
signal. Two basic possibilities are shown in Figures 1a and 1b.
Where the correction is being made to a system where a
differential input op amp is used as an inverter (the commonest
case) the method of la is best to correct for device offsets—but
not system offsets. In the single-ended connection, method 1b
will work for system offsets but should be avoided where a. CMOS DAC connected for current steering. Input imped-
possible for small device offsets, because it often requires a ance is constant.

a. Voltage applied to non-inverting input.

b. Current summed at inver ting input. b. The same DAC connected for voltage output.
Figure 1. Two connections for offset adjustment. Figure 2. Comparing basic DAC circuits.

Analog Dialogue 23-1 (1989) 3

Ask The Applications Engineer—3
by James Bryant
V/F CONVERTERS
Q. How do I send an analog signal a long distance without losing
accuracy?
A. An excellent solution to this common problem is to ship the
signal as frequency using a voltage-to-frequency converter (VFC),
Q. What are the advantages and disadvantages of the two types?
a circuit whose output is a frequency proportional to its input.
It is relatively easy to send a frequency signal over a long A. The multivibrator is simple and cheap, demands little power,
transmission path without interference via optical isolators, and has unity mark-space (M-S) output—very convenient with
optical fibre links, twisted-pair or co-axial lines, or radio links. some transmission media. But it is less accurate than the
charge-balance type and cannot integrate negative input
If the data must be digital, the receiver will consist of a
transients.
frequency counter, easily implemented in a single-chip micro-
computer. Frequency is reconverted to analog voltage by a The charge-balance type is more accurate, and negative input
“frequency-to-voltage converter” (FVC)—generally a VFC transients are integrated to contribute to the output. It has
configured to perform its inverse function, often using a more-demanding supply requirements and a lower input
phase-locked loop. impedance, and its output is a pulse train, not a unity M-S
square wave.
Q. What are the important types of error in a VFC?
A. The same three as in most precision circuitry: offset errors,
gain errors and linearity errors—and their variation with
Q. How does a VFC work? temperature. As with most precision circuitry, offset and gain
can be trimmed by the user, but linearity cannot. However,
A. There are two common types: multivibrator-(AD537) and the linearity of VFCs is normally very good (if the capacitors
charge-balance (AD650) VFCs.* are properly chosen—see below).
In the multivibrator type, the input voltage is converted to a Q. How do you trim gain and offset in a VFC?
current which charges and discharges a capacitor. The switching
thresholds are set by a stable reference, and the output, which A. The procedure suggested by theory is to trim offset first at
has unity mark-space ratio, is a frequency proportional to the zero frequency and then gain at full scale (FS). But this can
input. give rise to problems in recognizing “zero frequency,” which is
the state when the VFC is just not oscillating. It is therefore
The charge-balance VFC uses an integrator, a comparator and better to trim offset with a small input (say 0-1% FS) and
a precision charge source. The input is applied to the integrator, adjust for a nominal frequency, then trim gain at FS, and then
which charges. When the integrator output reaches the repeat the procedure once or twice.
comparator threshold, the charge source is triggered and a fixed
charge is removed from the integrator. The rate at which charge For example, suppose a VFC is being used with FS of 100 kHz
is removed must balance the rate at which it is being supplied, at 10-volt input. Ideally, 10 V should give 100-kHz output and
so the frequency at which the charge source is triggered will 10-mV input should give 100 Hz. Offset is, therefore, trimmed
be proportional to the input to the integrator. for 100 Hz with 10 mV applied; gain is then trimmed to give
100 kHz at 10 V. But gain error affects the 10-mV offset trim
slightly, so the procedure may have to be repeated to reduce
the residual error.
If a VFC is used with software calibration a deliberate offset is
often introduced so that the VFC has a definite frequency for
zero input voltage. The microcomputer measures the VFC
outputs at 0 V and FS inputs and computes the offset and
scale factor. It may also be necessary to reduce the gain so that
the VFC cannot try to exceed its maximum rated frequency.

*Data sheets are available for any of the Analog Devices products mentioned
here. An Application Note: “Operation and Applications of the AD654 V-to-F
Converter,” is also available without charge.

4 Analog Dialogue 23-2 (1989)

 Ask The Applications Engineer – 3

Q. What circuit precautions are necessary when using a VFC? The phase-locked-loop FVC illustrated differs from any other
A. Apart from the usual precautions necessary with any precision PLL in only one respect: the voltage-controlled oscillator of
analog circuitry (grounding, decoupling, current routing, the normal PLL, which must be monotonic but not necessarily
isolation of noise, etc., a subject for a book, not a paragraph) linear, has been replaced by a VFC with a linear control law.
the main precautions necessary when using a VFC are the In the servo system, negative feedback keeps the VFC’s output
choice of capacitor and separation of the input and output. frequency equal to the input frequency. The output voltage,
The critical capacitors in a precision VFC (the multivibrator’s the VFC’s input, is accurately proportional to the input
timing capacitor, and the monostable timing capacitor in a frequency.
charge-balance type) must be stable with temperature variation. Designing PLL systems is beyond the scope of this discussion,1
Furthermore, if they suffer from dielectric absorption, the VFC but if a 4000-series CMOS PLL, the 4046, is used just as a
will be nonlinear and may have poor settling time. phase detector (its VCO’s transfer characteristic is not sufficiently
If a capacitor is charged, discharged and then open-circuited linear), we can build the FVC shown here, with an AD654
it may recover some charge. This effect, known as dielectric VFC.
absorption (DA), can reduce the precision of VFCs or sample-
hold amplifiers using such capacitors. VFCs and SHAs should
therefore use Teflon or polypropylene, or zero- temperature-
coefficient (NPO, COG) ceramic capacitors with low DA.
Coupling between output and input of a VFC can also affect
its linearity. To prevent problems, decoupling practices and
the usual layout precautions should be observed. This is
critically important with opto couplers, which require high Q. What is a synchronous VFC?
current drive (10-30 mA).
A. A charge-balance VFC with improved linearity and stability,
Q. How do you make a frequency-to-voltage converter? where the monostable is replaced by a bistable, driven by an
A. There are two popular methods: the input frequency triggers external clock. The fixed time during which the precision
the monostable of a charge-balance VFC that has a resistor in current discharges the integrator is one clock period of the
parallel with its integration capacitor; or the input frequency external clock.
can be applied to the phase/frequency comparator of a phase- A further advantage of the SVFC is that the discharge does
locked loop (PLL), which uses a VFC (of either type) as its not start when the integrator passes the comparator threshold
oscillator. The basic principle of the first type is illustrated (at a non-critical rate), but on the next clock cycle. The SVFC
below. output is synchronous with a clock, so it is easier to interface
with counters, µPs, etc.; it is especially useful in multichannel
systems: it eliminates problems of interference from multiple
asynchronous frequency sources.
There are two disadvantages. Since the output pulses are
synchronized to a clock they are not equally spaced but have
substantial jitter. This need not affect the user of a SVFC for
For each cycle of the input frequency, a charge, ∆Q, is delivered a/d conversion, but it does prevent its use as a precision
to the leaky integrator formed by R and C. At equilibrium, an oscillator. Also, capacitive coupling of the clock into the
equal charge must leak away during each period, T (= 1/f), of the comparator causes injection-lock effects when the SVFC is at
input, at an average rate, I = V/R. Thus, V = ∆Q?f?R. 2/3 or 1/2 FS, causing a small (4-6 bit at 18-bit resolution at
1-MHz clock) dead zone in its response. Poor layout or device
Though the mean voltage is independent of C, the output ripple design can worsen this effect.
is inversely dependent on C. The peak-to-peak ripple voltage,
∆V, is given by the equation, ∆V= ∆Q/C. This indicates that Despite these difficulties the improvement in performance
ripple is independent of frequency (assuming that the charge, produced by the abolition of the timing monostable makes the
Q, is delivered in a short time relative to the period of the SVFC ideal for the majority of high-resolution VFC
input). The settling time of this type of FVC is determined by applications.
the exponential time constant, RC, from which the time to Q. Can you have a synchronized FVC?
settle within a particular error band may be calculated. A. Yes, and with very good performance; it is best done with an
From these equations, we see that the characteristics of this FVC- connected SVFC and a clock that is common to both
type of FVC are interdependent, and it is not possible to ends of the transmission path. If the input signal to a
optimize ripple and settling time separately. To do this we synchronized FVC is not phase related to the clock, severe
must use a PLL. timing problems can arise, which can only be solved by the
use of additional logic (two D flip-flops) to establish the correct
phase relationship. b
1
See Gardner, F. M, Phase-lock Techniques, 2nd ed., New York: Wiley, 1979, for
more detail; also Analog Devices’ Analog-Digital Conversion Handbook.

Analog Dialogue 23-2 (1989) 5

Ask The Applications Engineer—5 For example, after a high-to-low transition on the AD790, its
built-in hysteresis requires the input voltage (positive input) to
High-speed comparators provide many useful circuit
increase by 500 µV to produce a low-to-high transition.
functions when used correctly.
If my comparator does not have internal hysteresis, can I add it
by John Sylvan
externally?
Question: Why can’t I just use a standard op amp in a high-gain or
open-loop configuration as a voltage comparator? Yes, with external positive feedback. This is done by feeding a
small fraction of the output of the comparator back to the positive
You can—if you are willing to accept response times in the tens of
input. This simple technique is shown in Figure 1. The hysteresis
microseconds. Indeed, if in addition you require low bias-currents,
voltage from the lower transition point to the upper transition point
high-precision and low offset voltages, then an op amp might be a
will depend on the value of the feedback resistor, RF, the source
better choice than most standard voltage comparators. But since
resistance, RS, low output level, Vlow and high output level, Vhigh.
most op amps have internal phase/frequency compensation for
The low and high transition points are set by:
stability with feedback, it’s difficult to get them to respond in
nanoseconds. On the other hand, a low-cost popular comparator, RS RS
V low × and V high ×
the LM311, has a response time of 200 ns. RS + RF RS + RF
Also the output of an operational amplifier is not readily matched
to standard logic levels. Without external clamping or level-shifting,
an op amp operating as a comparator will swing to within a few
volts of the positive and negative supplies, which is incompatible
with standard TTL or CMOS logic levels.
My comparator oscillates uncontrollably.Why does this happen?
Examine the power-supply bypassing. Even a few inches of PC
trace on the supply lines can add unacceptable dc resistance and
inductance. As a result, transient currents while the output is Figure 1. Applying external hysteresis to a comparator.
switching may cause supply-voltage fluctuations, which are fed Figure 2 shows how adding external hysteresis can “clean up” a
back to the input through the ground and supply lines. Install comparator’s response. Figure 2a shows the response of a
low-loss capacitors (0.1µF ceramic capacitors) as close as possible comparator with bipolar output swing without hysteresis. As the
to the supply pins of the comparator to serve as a low-impedance triangular-wave input (trace A) passes through the transition point
reservoir of energy during high-speed switching.1 (ground), the device oscillates vigorously (and couples a portion
I’ve installed bypass capacitors, but I still can’t keep my high-speed of the oscillation into ground and the signal-source). Figure 2b
comparator from oscillating. Now what’s the problem? depicts the response of the same comparator with 5 mV of external
hysteresis applied; it shows a much cleaner transition.
It could be the comparator’s ground connection. Make sure that
the ground lead is as short as possible and connected to a low-
impedance ground point to minimize coupling through lead
inductance. Use a ground plane if possible and avoid sockets. ±5V
COMPARATOR
Another cause of the oscillation may be a high source impedance OUTPUT

and stray capacitance to the input. Even a few thousand ohms of

source impedance and picofarads of stray capacitance can cause
unruly oscillations. Keep leads short, including the ground clip of 14Hz 1V pk-pk
TRIWAVE
your scope probe. For best measurement results use the shortest
possible ground lead to minimize its inductance (< 1").
With a slowly moving input signal, my comparator seems to “chatter”
as it passes through the transition voltage.Why can’t I obtain a single No external hysteresis
clean transition from the device?
A comparator’s high gain and wide bandwidth are typically the
source of this problem. Any noise is amplified, and as the signal
±5V
passes through the transition region, the noise can cause a fast- COMPARATOR
responding amplifier’s output to bounce back and forth. Also, OUTPUT

since the device’s sensitivity (i.e., gain) is higher during a transition,

the tendency to oscillate due to feedback increases. If possible,
filter the signal to minimize noise accompanying it. Then try 14Hz 1V pk-pk
TRIWAVE
using hysteresis which, like backlash in gear trains, requires the
input to change by a certain amount before a reversal occurs.

1 5 mV external hysteresis
A useful discussion of comparator foibles can be found in Troubleshooting
Techniques Quash Spurious Oscillations, by Bob Pease, EDN, September 14, Figure 2. Hysteresis helps clean up comparator response.
1989, pp. 152-6

6 Analog Dialogue 23-4 (1989)

 Ask The Applications Engineer – 5

A problem encountered with external hysteresis is that output Can you suggest a circuit that performs autozeroing when the comparator
voltage depends on supply voltage and loading. This means the is off-line to minimize drift?
hysteresis voltage can vary from application to application; though Try the circuit shown in Figures 3 and 4. In the Calibrate mode,
this affects resolution, it need not be a serious problem, since the the input is disconnected and the positive input of the comparator
hysteresis is usually a very small fraction of the range and can is switched to ground. The comparator is connected in a loop with
tolerate a safety margin of two or three (or more) times what one a pair of low-voltage sources of opposing polarity charging a
might calculate. Swapping in a few comparators can help buffered capacitor in response to the comparator’s output state.
confidence in the safety margin. Don’t use wirewound resistors
for feedback; their inductance can make matters worse. If the comparator’s minus input terminal is above ground, then
the comparator output will be low, the 1-µF capacitor will be
What’s the difference between propagation delay and prop-delay connected to the negative voltage (–365 mV) and the voltage from
dispersion? Which of the two specifications is of most concern? the buffer amplifier will ramp down until it is below the plus input
Propagation delay is the time from when the input signal crosses (ground)—plus hysteresis and any offsets—at which point the
the transition point to when the output of the comparator actually comparator switches. If it is below ground, the comparator’s output
switches. Propagation-delay dispersion is the variation in prop delay will be high, the capacitor will be connected to the positive voltage
as a function of overdrive level. If you’re using a comparator in (+365 mV), the output from the buffer amplifier ramps up. In the
pin-drive electronics in an automatic test system, then prop-delay final state, each time the comparator switches (when the ramped
dispersion will determine the maximum edge resolution. In change exceeds the hysteresis voltage), the polarity of the current
contrast, propagation delay can be considered as a fixed time offset is reversed; thus the capacitor voltage averages out the offsets of
and therefore compensated for by other techniques. the buffer and comparator.
I have a +5-volt system and don’t want to add an additional supply At the end of the Calibrate cycle, the JFET switch is opened, with
voltage; can I use my comparator with a single supply? the capacitor charged to a voltage equal to the offsets of the
Yes, but to establish the threshold use an adequately bypassed comparator and buffer ± the hysteresis voltage. At the same time,
stable reference source well within the common-mode range of the Calibrate signal goes low, disabling the feedback to the polarity
the device. The signal level is also to be referenced to this source. switch and connecting the input signal to the comparator. b

I sometimes see unexpected behavior in my comparator.What could be

the cause of this problem? COMPARATOR
OUTPUT
Examine the common-mode range of the input signal. Unlike 0-VLOGIC

operational amplifiers, that usually operate with the input voltages

VOLTAGE AT
at the same level, comparators typically see a large differential AD790 –INPUT
voltage swings at their inputs. If the inputs exceed the device’s TERMINAL

specified common-mode range (even though within the specified –5V ph-ph
signal range), the comparator may respond erroneously. For proper TRIWAVE (5kHz)
(AD790 +INPUT)
operation, ensure that both input signals do not exceed the
common-mode range of the specific comparator. For example,
the AD790 has a +VS differential input range, but its common- Figure 4. Comparator output, buffer output, and comparator
mode range is from – VS to 2 volts below +VS. input.

Figure 3. Autozeroed comparator integrates out offsets during calibration cycle.

Analog Dialogue 23-4 (1989) 7

Ask The Applications Engineer—6
by James Bryant
OP-AMP ISSUES
Q. Why are there so many different types of operational amplifier?
A. Because there are so many parameters that are important in
different applications, and because it is impossible to optimize The bias currents in the inverting and non-inverting inputs
all of them at once. Op amps may be selected for speed, for are unipolar and well matched (their difference is called offset
noise (voltage, current or both), for input offset voltage and current), and they decrease in a minor way with increasing
drift, for bias current and its drift, and for common-mode temperature. In many applications, the accurate matching may
range. Other factors might include power: output, dissipation, be used to compensate for their high absolute value. This figure
or supply, ambient temperature ranges, and packaging. shows a bias compensation circuit where the bias current in
Different circuit architectures and manufacturing processes the non-inverting input flows in Rc (known as the bias
optimize different performance parameters. compensation resistor); this compensates for the voltage drop
as the bias current in the inverting input flows through R2. Rc
Q. Is there any common factor in the design of op-amps? is made nominally equal to the parallel combination of R1 and
A. Yes—most classical (voltage input) op-amps are three-stage R2.—it can be trimmed to minimize error due to non-zero
devices, consisting of an input stage with differential input and offset current).
differential output—with good common-mode rejection—
followed by a differential-input, single-ended output stage
having high voltage-gain and (generally) a single-pole frequency
response; and, finally, an output stage, which usually has unity
voltage gain.

Such bias compensation is only useful when the bias currents

Q. So where are the differences? are well-matched. If they are not well-matched, a bias
compensation resistor may actually introduce error.
A. There are many possible variations on this basic design. One
of the most fundamental is the structure of the input stage. If a bipolar input stage is required without the drawback of
This stage is almost always a long-tailed pair—that is to say, a such a high bias current, a different form of bias compensation
pair of amplifying devices connected as in the figure—but the may be used by the chip designer (next figure). The same
choice of devices has a profound effect on the input parameters long-tailed pair is used, but the major portion of the current
of the op amp. The figure was drawn with thermionic tubes to required by each base is supplied by a current generator on
avoid any suggestion of partiality in favour of any particular the chip. This can reduce the external bias current to 10 nA or
semiconductor device. Since thermionic devices at present are less without affecting the offset, temperature drift, bandwidth
not generally available in IC chip form, a monolithic op-amp or voltage noise. Bias current variation with temperature is
will have an input stage built with bipolar or field-effect quite low.
transistors.

There are two disadvantages to such an architecture: the

current noise is increased and the external bias currents are
not well matched (indeed, they may actually flow in opposite
A long-tailed pair built with bipolar transistors is shown in the directions, or change polarity as chip temperature changes).
next figure. Its strong features are its low noise and, with For many applications these features are no drawback; indeed,
suitable trimming, low voltage offset. Furthermore, if such a one of the most popular low-offset op-amp architectures, the
stage is trimmed for minimum offset voltage it will inherently OP-07, uses just such an architecture, as do the OP-27, OP-37
have minimum offset drift. Its main disadvantage stems from and the AD707, which has a guaranteed offset voltage of only
the proportionality of the emitter and base currents of the 15 µV. Bias-compensated amplifiers of this type are often
transistors; if the emitter current is large enough for the stage recognizable when their data sheets explicitly specify bipolar
to have a reasonable bandwidth, the base current—and hence bias current, for example, ± 4.0 nA.
the bias current—will be relatively large (50 to 1,000 nA in Where bias currents of even a few nanoamps are intolerable,
general-purpose op-amps, as much as 10 µA in high-speed bipolar transistors are usually replaced by field-effect devices.
ones). In the past, MOSFETs have been somewhat noisy for op-amp

8 Analog Dialogue 24-1 (1990)

 Ask The Applications Engineer – 6

input stages, although modern processing techniques are inverting and non-inverting input terminals reverse functions.
overcoming this drawback. Since MOSFETS also tend to have Negative feedback becomes positive feedback and the circuit
relatively high offset voltages, junction FETs (JFETs) are used may latch up. This latchup is unlikely to be destructive, but
for high-performance low-bias-current op amps. A typical JFET power may have to be switched off to correct it. This figure
op-amp input stage is shown in this figure. shows the effect of such phase inversion in a circuit where
latch-up does not occur. The problem may be avoided by using
bipolar amplifiers, or by restricting the common-mode range
of the signal in some way.

The bias current of a JFET bears no relationship to the current

flowing in the device, so even a wideband JFET amplifier may
have a very low bias current—values of a few tens of
picoamperes are commonplace, and the AD549 has a
guaranteed bias current of less than 60 fA (one electron per
three microseconds!) at room temperature.
A more serious form of latchup can occur in both bipolar and
The qualification “at room temperature” is critical—the bias JFET op-amps if the input signal becomes more positive or
current of a JFET is the reverse leakage current of its gate negative than the respective op-amp power supplies. If the input
diode, and the reverse leakage current of silicon diodes terminals go more positive than +Vs + 0.7 V or more negative
approximately doubles with every 10°C temperature rise. The than –Vs – 0.7 V, current may flow in diodes which are normally
bias current of a JFET op-amp is thus not stable with biased off. This in turn may turn on thyristors (SCRs) formed
temperature. Indeed, between 25°C and 125°C, the bias by some of the diffusions in the op- amp, short-circuiting the
current of a JFET op-amp increases by a factor of over 1,000. power supplies and destroying the device.
(The same law applies to MOSFET amplifiers, because the
To avoid such destructive latch-up it is important to prevent
bias current of most MOSFET amplifiers is the leakage current
the input terminals of op-amps from ever exceeding the power
of their gate-protection diodes.)
supplies. This can have important implications during device
The offset voltage of a JFET amplifier may be trimmed during turn-on: if a signal is applied to an op-amp before it is powered
manufacture, but minimum offset does not necessarily it may be destroyed at once when power is applied. Whenever
correspond to minimum temperature drift. It has therefore been there is a risk, either of signals exceeding the voltages on the
necessary to trim offset and drift separately in JFET op-amps, supplies, or of signals being present prior to power-up of the
which results in somewhat larger values of voltage offset and op-amp, the terminals at risk should be clamped with diodes
drift than are available from the best bipolar amplifiers (values (preferably fast low-forward-voltage Schottky diodes) to
of 250 µV and 5 µV/°C are typical of the best JFET op-amps). prevent latchup from occurring. Current-limiting resistors may
Recent studies at Analog Devices, however, have resulted in a also be needed to prevent the diode current from becoming
patented trimming method which is expected to yield much excessive (see the figure).
better values in the next generation of JFET op-amps.
We thus see that there are trade-offs between offset voltage,
offset drift, bias current, bias current temperature variation,
and noise in operational amplifiers—and that different
architectures optimize different features. The table compares
the features of the three commonest op-amp architectures. We
should note one more category, typified by the new AD705,
using bipolar superbeta input transistors; it combines low offset This protection circuitry can cause problems of its own.
voltage and drift with low bias current and drift. Leakage current in the diode(s) may affect the error budget of
the circuit (and if glass-encapsulated diodes are used, their
CHARACTERISTICS OF OP-AMP INPUT STAGES leakage current may be modulated at 100 or 120 Hz due to
SIMPLE BIAS-COMPENSATED photoelectric effects if exposed to fluorescent ambient lighting,
BIPOLAR BIPOLAR FET
OFFSET VOLTAGE LOW LOW MEDIUM
thus contributing hum as well as dc leakage current); Johnson
OFFSETDRIFT
BIAS CURRENT
LOW
HIGH
LOW
MEDIUM
MEDIUM
LOW-VERY LOW
noise in the current-limiting resistor may worsen the circuit’s
BIAS MATCH EXCELLENT POOR (CURRENT CAN
BE IN OPPOSITE
FAIR noise performance; and bias current flowing in the resistor may
DIRECTIONS produce an apparent increase in offset voltage. All these effects
BIAS/TEMP VARIATION LOW LOW BIAS DOUBLES FOR
EVERY 10°C RISE must be considered when designing such protection.
NOISE LOW LOW FAIR
The important subjects of noise, interference, bypassing, and
Q. What other features of op amps should the user know about?
grounding demand discussion—but we’re out of space! We’ll come
A. A common problem encountered with JFET op-amps is phase back to them again in future chats; meanwhile you may want to
inversion. If the input common-mode voltage of a JFET take a look at some of the references in the footnotes on pages 193-4 of
op-amp approaches the negative supply too closely, the The Best of Analog Dialogue, 1967-1991. b

Analog Dialogue 24-1 (1990) 9

Ask The Applications Engineer—7 Gaussian noise has the property that when the rms values of
noise from two or more such sources are added, provided that
by James Bryant and Lew Counts the noise sources are uncorrelated (i.e., one noise signal cannot
be transformed into the other), the resulting noise is not their
OP-AMP ISSUES—NOISE arithmetic sum but the root of the sum-of-their-squares (RSS).*
Q. What should I know about op-amp noise? The RSS sum of three noise sources, V1, V2, and V3, is
A. First, we must note the distinction between noise generated in
the op amp and its circuit components and interference, or V O = V 12 +V 22 +V 32
unwanted signals and noise arriving as voltage or current at any
Since the different frequency components of a noise signal are
of the amplifier’s terminals or induced in its associated circuitry.
uncorrelated, a consequence of RSS summation is that if the
Interference can appear as spikes, steps, sine waves, or random white noise in a brick-wall bandwidth of ∆ f is V, then the noise
noise, and it can come from anywhere: machinery, nearby
in a bandwidth of 2 ∆f is V 2 +V 2 = 2V . More generally, if
power lines, r-f transmitters and receivers, computers, or even
circuitry within the same equipment (for example, digital we multiply the bandwidth by a factor K, then we multiply the
circuits or switching-type power supplies). Understanding it, noise by a factor √K. The function defining the rms value of
preventing its appearance in your circuit’s neighborhood, noise in a ∆f = 1 Hz bandwidth anywhere in the frequency
finding how it got in, and rooting it out, or finding a way to range is called the (voltage or current) spectral density function,
live with it is a big subject. It’s been treated in these pages in specified in nV/√Hz or pA/√Hz. For white noise, the spectral
the past; those, and a few additional references, are mentioned density is constant; it is multiplied by the square root of the
in the Bibliography. bandwidth to obtain the total rms noise.
If all interference could be eliminated, there would still be A useful consequence of RSS summation is that if two noise
random noise associated with the operational amplifier and its sources are contributing to the noise of a system, and one is more
resistive circuits. It constitutes the ultimate limitation on the than 3 or 4 times the other, the smaller is often ignored, since
amplifier’s resolution. That’s the topic we’ll begin to discuss
here. 42 = 16 = 4, while 42 +12 = 17 = 4.12
Q. O.K.Tell me about random noise in op amps.Where does it come from? [difference less than 3%, or 0.26 dB]
A. Noise appearing at the amplifier’s output is usually measured
as a voltage. But it is generated by both voltage- and current 32 = 9 = 3, while 32 +12 = 10 = 3.16
sources. All internal sources are generally referred to the input, [difference less than 6%, or 0.5 dB]
i.e., treated as uncorrelated—or independent—random noise
generators (see next question) in series or parallel with the The source of the higher noise has become the dominant source.
inputs of an ideal noisefree amplifier: We consider 3 primary Q. O.K. How about current noise?
contributors to noise: A. The current noise of simple (i.e. not bias-current-compensated)
• a noise voltage generator (like offset voltage, usually shown in bipolar and JFET op-amps is usually within 1 or 2 dB of the
series with the noninverting input) Schottky noise (sometimes called the “shot noise”) of the bias
current; it is not always specified on data sheets. Schottky noise
• two noise-current generators pumping currents out through the is current noise due to random distribution of charge carriers
two differential-input terminals (like bias current). in the current flow through a junction. The Schottky noise
• If there are any resistors in the op-amp circuit, they too generate current, In, in a bandwidth, B, when a current, I, is flowing is
noise; it can be considered as coming from either current obtained from the formula
sources or voltage sources (whichever is more convenient to
deal with in a given circuit). I n = 2I qB
Op-amp voltage noise may be lower than 1 nV/√Hz for the Where q is the electron charge (1.6 × 10–19 C). Note that 2I q
best types. Voltage noise is the noise specification that is more is the spectral density, and that the noise is white.
usually emphasized, but, if impedance levels are high, current
noise is often the limiting factor in system noise performance. This tells us that the current noise spectral density of simple
That is analogous to offsets, where offset voltage often bears bipolar transistor op-amps will be of the order of 250 fA/√Hz,
the blame for output offset, but bias current is the actual guilty for Ib = 200 nA, and does not vary much with temperature—
party. Bipolar op-amps have traditionally had less voltage noise and that the current noise of JFET input op-amps, while lower
than FET ones, but have paid for this advantage with (4 fA/√Hz at Ib, = 50 pA), will double for every 20°C chip
substantially greater current noise—today, FET op-amps, while temperature increase, since JFET op-amps’ bias currents
retaining their low current noise, can approach bipolar double for every 10°C increase.
voltage-noise performance. Bias-compensated op-amps have much higher current noise
than one can predict from their input currents. The reason is
Q. Hold it! 1 nV/√Hz? Where does √Hz come from? What does it
that their net bias current is the difference between the base
mean?
current of the input transistor and the compensating current
A. Let’s talk about random noise. Many noise sources are, for source, while the noise current is derived from the RSS sum of
practical purposes (i.e., within the bandwidths with which the the noise currents.
designer is concerned), both white and Gaussian. White noise
is noise whose power within a given bandwidth is independent Traditional voltage-feedback op-amps with balanced inputs almost
of frequency. Gaussian noise is noise where the probability of always have equal (though uncorrelated) current noise on both
a particular amplitude, X, follows a Gaussian distribution. [*Note the implication that noise power adds linearly (sum of squares).]

10 Analog Dialogue 24-2 (1990)

 Ask The Applications Engineer – 7

their inverting and non-inverting inputs. Current-feedback, or on the horizontal scale. Let’s read the chart for the ADOP27:
transimpedance, op-amps, which have different input structures The horizontal line indicates the ADOP27’s voltage noise level
at these two inputs, do not. Their data sheets must be consulted of about 3 nV/√Hz is equivalent to a source resistance of less
for details of the noise on the two inputs. than about 500 Ω. Noise will not be reduced by (say) a 100-Ω
The noise of op-amps is Gaussian with constant spectral source impedance, but it will be increased by a 2-kΩ source
density, or “white”, over a wide range of frequencies, but as impedance. The vertical line for the ADOP27 indicates that,
frequency decreases the spectral density starts to rise at about for source resistances above about 100 kΩ, the noise voltage
3 dB/octave. This low-frequency noise characteristic is known produced by amplifier’s current noise will exceed that contributed
as “1/f noise” since the noise power spectral density goes by the source resistance; it has become the dominant source.
inversely with frequency (actually 1/f g). It has a –1 slope on a
log plot (the noise voltage (or current) 1/√f spectral density
slopes at –1/2). The frequency at which an extrapolated –3 dB/
octave spectral density line intersects the midfrequency
constant spectral density value is known as the “l/f corner
frequency” and is a figure of merit for the amplifier. Early
monolithic IC op-amps had 1/f corners at over 500 Hz, but
today values of 20–50 Hz are usual, and the best amplifiers
(such as the AD-OP27 and the AD-OP37) have corner
frequencies as low as 2.7 Hz. 1/f noise has equal increments
for frequency intervals having equal ratios, i.e., per octave or
per decade.
Remember that any resistance in the non-inverting input will
Q. Why don’t you publish a noise figure? have Johnson noise and will also convert current noise to a
A. The noise figure (NF) of an amplifier (expressed in dB) is a noise voltage; and Johnson noise in feedback resistors can be
measure of the ratio of the amplifier noise to the thermal noise significant in high-resistance circuits. All potential noise sources
of the source resistance. must be considered when evaluating op amp performance.
Vn = 20 log { [Vn(amp)+Vn(source)]/Vn(source)} Q. You were going to tell me about Johnson noise.
It is a useful concept for r-f amplifiers, which are almost always A. At temperatures above absolute zero, all resistances have noise
used with the same source resistance driving them (usually due to thermal movement of charge carriers. This is called
50 Ω or 75 Ω), but it would be misleading when applied to op Johnson noise. The phenomenon is sometimes used to measure
amps, since they are used in many different applications with cryogenic temperatures. The voltage and current noise in a
widely varying source impedances (which may or may not be resistance of R ohms, for a bandwidth of B Hz, at a temperature
resistive). of T kelvins, are given by:
Q. What difference does the source impedance make?
V n = 4kTRB and I n = 4kTB / R
A. At temperatures above absolute zero all resistances are noise
sources; their noise increases with resistance, temperature, and Where k is Boltzmann’s Constant (1.38 × 10–23 J/K). A handy
bandwidth (we’ll discuss basic resistance noise, or Johnson noise, rule of thumb is that a 1-kΩ resistor has noise of 4 nV/√Hz at
in a moment). Reactances don’t generate noise, but noise room temperature.
currents through them will develop noise voltages. All resistors in a circuit generate noise, and its effect must always
If we drive an op-amp from a source resistance, the equivalent be considered. In practice, only resistors in the input(s) and,
noise input will be the RSS sum of the amplifier’s noise voltage, perhaps, feedback, of high-gain, front-end circuitry are likely
the voltage generated by the source resistance, and the voltage to have an appreciable effect on total circuit noise.
caused by the amplifier’s I n flowing through the source Noise can be reduced by reducing resistance or bandwidth,
impedance. For very low source resistance, the noise generated but temperature reduction is generally not very helpful unless
by the source resistance and amplifier current noise would a resistor can be made very cold—since noise power is
contribute insignificantly to the total. In this case, the noise at proportional to the absolute temperature, T = °C + 273°. b
the input will effectively be just the voltage noise of the op-amp. (to be continued)
If the source resistance is higher, the Johnson noise of the source REFERENCES
resistance may dominate both the op-amp voltage noise and Barrow, J., and A. Paul Brokaw, “Grounding for Low- and High-Frequency
the voltage due to the current noise; but it’s worth noting that, Circuits,” Analog Dialogue 23-3, 1989.
since the Johnson noise only increases with the square root of Bennett, W. R., Electrical Noise. New York: McGraw-Hill, 1960.
Freeman, J. J., Principles of Noise. New York: John Wiley & Sons, Inc., 1958.
the resistance, while the noise voltage due to the current noise Gupta, Madhu S., ed., Electrical Noise: Fundamentals & Sources. New York: IEEE
is directly proportional to the input impedance, the amplifier’s Press, 1977. Collection of classical reprints.
current noise will always dominate for a high enough value of Motchenbacher, C. D., and F. C. Fitchen, Low-Noise Electronic Design. New
input impedance.When an amplifier’s voltage and current noise York: John Wiley & Sons, Inc., 1973.
are high enough, there may be no value of input resistance for Rice, S.O., “Math Analysis for Random Noise” Bell System Technical Journal 23
July, 1944 (pp 282–332).
which Johnson noise dominates. Rich, Alan, “Understanding Interference-Type Noise,” Analog Dialogue 16-3,
This is demonstrated by the figure nearby, which compares 1982.
- - - , “Shielding and Guarding,” Analog Dialogue 17-1, 1983.
voltage and current noise noise for several Analog Devices op Ryan, Al, and Tim Scranton, “DC Amplifier Noise Revisited,” Analog Dialogue
amp types, for a range of source-resistance values. The diagonal 18-1, 1984.
line plots vertically the Johnson noise associated with resistances van der Ziel, A. Noise. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1954. b

Analog Dialogue 24-2 (1990) 11

Ask The Applications Engineer—8 A. Because noise is generally Gaussian, as we pointed out in the
last issue. For a Gaussian distribution it is meaningless to speak
by James Bryant of a maximum value of noise: if you wait long enough any
value will, in theory, be exceeded. Instead it is more practical
OP-AMP ISSUES
to speak of the rms noise, which is more or less invariant—and
(Noise, continued from the last issue, 24-2)
by applying the Gaussian curve to this we may predict the
Q. What is “noise gain”?
probability of the noise exceeding any particular value. Given
A. So far we have considered noise sources but not the gain of the a noise source of V rms, since the probability of any particular
circuits where they occur. It is tempting to imagine that if the value of noise voltage follows a Gaussian distribution, the noise
noise voltage at the input of an amplifier is Vn and the circuit’s voltage will exceed a pk-pk value of 2 V for 32% of the time,
signal gain is G, the noise voltage at the output will be GVn; 3 V for 13% of the time, and so on:
but this is not always the case. % of time pk-pk
Consider the basic op-amp gain circuit in the diagram. If it is Pk-pk value value is exceeded
being used as an inverting amplifier (B), the non-inverting input 2 × rms 32%
will be grounded, the signal will be applied to the free end of 4 × rms 4.6%
R i and the gain will be –R f/R i . On the other hand, in a 6 × rms 0.27%
non-inverting amplifier (A) the signal is applied to the
6.6 × rms 0.10%
non-inverting input and the free end of Ri is grounded; the
8 × rms 60 ppm
gain is (1 + Rf/Ri)
10 × rms 0.6 ppm
A Ri Rf SIGNAL AMPLIFIER
VOUT GAIN NOISE GAIN 12 × rms 2 × 10–9 ppm
B
V1
A A: (1 + Rf
) (1 + Rf
) 14 × rms 2.6 × 10–12 ppm
Ri Ri

B So if we define a peak value in terms of the probability of its

Vn B: –
Rf
(1 + Rf
)
Ri Ri
occurrence, we may use a peak specification—but it is more
The amplifier’s own voltage noise is always amplified in the desirable to use the rms value, which is generally easier to
non-inverting mode; thus when an op-amp is used as an measure. When a peak noise voltage is specified, it is frequently
inverting amplifier at a gain of G, its voltage noise will be 6.6 × rms, which occurs no more than 0.1% of the time.
amplified by the noise gain of (G+ 1). For the precision Q. How do you measure the rms value of low-frequency noise in the
attenuation cases, where G<1, this may present problems. (A usually specified band, 0.1 to 10 Hz? It must take a long time to
common example of this is an active filter circuit where integrate. Isn’t this expensive in production?
stopband gain may be very small but stop-band noise gain is
at least unity.) A. Yes, it is expensive, but—Although it’s necessary to make many
careful measurements during characterization, and at intervals
Only the amplifier voltage noise—and any noise developed by thereafter, we cannot afford the time it would take in production
the noninverting-input current noise flowing in any impedance to make an rms measurement. Instead, at very low frequencies
present in that input (for example, a bias-current compensation in the 1/f region (as low as 0.1 to 10 Hz), the peak value is
resistor)—is amplified by the noise gain. Noise in Ri, either measured during from one to three 30-second intervals and
Johnson noise or arising from inverting input noise current, is must be less than some specified value. Theoretically this is
amplified by G in the same way as the input signal, and Johnson unsatisfactory, since some good devices will be rejected and
noise voltage in the feedback resistor is not amplified but is some noisy ones escape detection, but in practice it is the best
buffered to the output at unity gain. test possible within a practicable test time and is acceptable if
Q. What’s “popcorn” noise? a suitable threshold limit is chosen. With conservative
A. Twenty years ago this column would have spent a great deal of weightings applied, this is a reliable test of noise. Devices that
space discussing popcorn noise, which is a type of low frequency do not meet the arbitrary criteria for the highest grades can
noise manifesting itself as low level (but random amplitude) still be sold in grades for which they meet the spec.
step changes in offset voltage occurring at random intervals. Q. What other op-amp noise effects do you encounter?
When played through a loudspeaker it sounds like cooking A. There is a common effect, which often appears to be caused
popcorn—hence the name. by a noisy op amp, resulting in missing codes. This potentially
While no integrated circuit process is entirely free from the serious problem is caused by ADC input-impedance
problem, high levels of popcorn noise result from inadequate modulation. Here’s how it happens:
processing techniques. Today its causes are sufficiently well Many successive-approximation ADCs have an input
understood that no reputable op-amp manufacturer is likely impedance which is modulated by the device’s conversion clock.
to produce op-amps where popcorn noise is a major concern If such an ADC is driven by a precision op amp whose
to the user. {Oat-bran noise is more likely to be an issue in bandwidth is much lower than the clock frequency, the op amp
situations where cereal data is concerned[:-)]} cannot develop sufficient feedback to provide a stiff voltage
Q. Pk-pk noise voltage is the most convenient way to know whether source to the ADC input port, and missing codes are likely to
noise will ever be a problem for me. Why are amplifier manufacturers occur. Typically, this effect appears when amplifiers like the
reluctant to specify noise in this way? OP-07 are used to drive AD574s.

12 Analog Dialogue 24-3 (1990)

 Ask The Applications Engineer – 8

It may be cured by using an op amp with sufficient bandwidth that any current, I, is a flow of electrons or holes, which carry
to have a low output impedance at the ADC’s clock frequency, discrete charges, and the noise given in the formula is just an
or by choosing an ADC containing an input buffer or one whose expression of the graininess of the flow.
input impedance is not modulated by its internal clock (many He concludes that the omission of this noise component in
sampling ADCs are free of this problem). In cases where the any circuit carrying current, including purely resistive circuits,
op amp can drive a capacitive load without instability, and the can lead to serious design problems. And he illustrates its
reduction of system bandwidth is unimportant, a shunt significance by pointing out that this noise current, calculated
capacitor decoupling the ADC input may be sufficient to effect from the flow of dc through any ideal resistor, becomes equal
a cure. to the thermal Johnson noise current at room temperature when
Q. Are there any other interesting noise phenomena in high-precision only 52 mV is applied to the resistor—and it would become
analog circuits? the dominant current noise source for applied voltages higher
A. The tendency of high-precision circuitry to drift with time is a than about 200 mV.
noise-like phenomenon (in fact, it might be argued that, at a A. Since designers of low-noise op amps have blithely ignored
minimum, it is identical to the lower end of 1/f noise). When this putative phenomenon, what’s wrong? The assumption that
we specify long-term stability, we normally do so in terms of the above shot noise equation is valid for conductors.
µV/1,000 hr or ppm/1,000 hr. Many users assume that, since Actually, the shot noise equation is developed under the
there are, on the average, 8,766 hours in a year, an instability assumption that the carriers are independent of one another.
of x/1,000 hr is equal to 8.8 x/yr. While this is indeed the case for currents made up of discrete
This is not the case. Long-term instability (assuming no long- charges crossing a barrier, as in a junction diode (or a vacuum
term steady deterioration of some damaged component within tube), it is not true for metallic conductors. Currents in
the device), is a “drunkard’s walk” function; what a device did conductors are made up of very much larger numbers of
during its last 1,000 hours is no guide to its behavior during carriers (individually flowing much more slowly), and the noise
the next thousand. The long-term error mounts as the square- associated with the flow of current is accordingly very much
root of the elapsed time, which implies that, for a figure of smaller—and generally lost in the circuit’s Johnson noise.
x/l,000 hr, the drift will actually be multiplied by √8.766, or Here’s what Horowitz and Hill2 have to say on the subject:
about 3× per year, or 9× per 10 years. Perhaps the spec should
be in µV/1,000 √hr. “An electric current is the flow of discrete electric charges,
not a smooth fluidlike flow. The finiteness of the charge
In fact, for many devices, things are a bit better even than this. quantum results in statistical fluctuations of the current. If the
The “drunkard’s walk” model, as noted above, assumes that charges act independently of each other,* the fluctuating current
the properties of the device don’t change. In fact, as the device is . . .
gets older, the stresses of manufacture tend to diminish and
the device becomes more stable (except for incipient failure I noise (rms) = InR = (2 qIdc B)1/2
sources). While this is hard to quantify, it is safe to say that— where q is the electron charge (1.60 × 10–19 C) and B is the
provided that a device is operated in a low-stress environment— measurement bandwidth. For example, a “steady” current of
its rate of long-term drift will tend to reduce during its lifetime. 1 A actually has an rms fluctuation of 57 nA, measured in a
The limiting value is probably the 1/f noise, which builds up as 10-kHz bandwidth; i.e., it fluctuates by about 0.000006%.
the square-root of the natural logarithm of the ratio, i.e., √1n 8.8 The relative fluctuations are larger for smaller currents: A
for time ratios of 8.8, or 1.47 × for 1 year, 2.94 × for 8.8 years, “steady” current of 1 µA actually has an rms current-noise
4.4 × for 77 years, etc. fluctuation, over 10 kHz, of 0.006%, i.e., –85 dB. At 1 pA dc,
the rms current fluctuation (same bandwidth) is 56 fA, i.e., a
A READER’S CHALLENGE: 5.6% variation! Shot noise is ‘rain on a tin roof.’ This noise,
Q. A reader sent us a letter that is just a wee bit too long to quote like resistor Johnson noise, is Gaussian and white.
directly, so we’ll summarize it here. He was responding to the
mention in these columns (Analog Dialogue 24-2, pp. 20-21) “The shot noise formula given earlier assumes that the charge
of the shot effect, or Schottky noise (Schottky was the first to carriers making up the current act independently. That is
note and correctly interpret shot effect—originally in vacuum indeed the case for charges crossing a barrier, as for example
tubes1). Our reader particularly objected to the designation of the current in a junction diode, where the charges move by
shot noise as solely a junction phenomenon, and commented diffusion; but it is not true for the important case of metallic
that we have joined the rest of the semiconductor and op-amp conductors, where there are long-range correlations between charge
engineering fraternity in disseminating misinformation. carriers. Thus the current in a simple resistive circuit has far less
noise than is predicted by the shot noise formula.* Another
In particular, he pointed out that the shot noise formula— important exception to the shot-noise formula is provided by
In = √2q IB amperes, our standard transistor current-source circuit, in which negative
where In is the rms shot-noise current, I is the current flowing feedback acts to quiet the shot noise.”
through a region, q is the charge of an electron, and B is the *Italics ours
1
Goldman, Stanford, Frequency Analysis, Modulation, and Noise. New York:
bandwidth—does not seem to contain any terms that depend McGraw-Hill Book Company, 1948, p. 352.
on the physical properties of the region. Hence (he goes on) 2
Horowitz, Paul and Winfield Hill, The Art of Electronics, 2nd edition. Cam-
shot noise is a universal phenomenon associated with the fact bridge (UK): Cambridge University Press, 1989, pp. 431-2. b

Analog Dialogue 24-3 (1990) 13

Ask The Applications Engineer—9 position to help engineers from both analog and “mixed”
signal-processing technology.
SEMINARS AND SUPPORT Q. I’d love to go to a real nuts-and-bolts seminar on this topic. Are you
by Chris Hyde planning one?
Q. Are performance, quality, reliability, price, and availability the only A. You read our mind. Every year, Analog Devices sponsors a
important considerations in selecting products for use in the critical full-day technical course entitled, “[. . . subject . . .] Seminar.”
portions of my designs? Presented by Analog Devices applications engineers, it is
A. There is one more—support. A manufacturer’s support can be designed to assist both analog and digital designers with many
an important factor in shortening the design cycle and of the trickier aspects of both analog and digital signal
approaching optimal part selection—but only if you take processing. The seminar combines fundamental concepts,
advantage of it. Using it can make the difference between advanced theory, and practical application. Readers who have
getting your product to market on time or losing the edge and attended Analog Devices seminars—know that it will not be a
market window to your competitors. “product pitch” (but naturally our discussions of practical
application will unabashedly take into account the character-
Q. What do you mean by support?
istics of the devices we know best).
A. At Analog Devices, it basically means help for the designer. Its
Q. When? Where? How much?
constituents include:
• (mostly) free literature and software [for example, accurate and A. The widely advertised seminars are given in a variety of
comprehensive data sheets, data books, selection guides, locations throughout the United States and elsewhere in the
tutorial and technical reference books, application notes and World, and portions thereafter to other groups as the
guides, SPICE models and other useful disk-based material, opportunity arises. The minimal cost includes lunch and all
and serial publications such as Analog Dialogue and DSPatch] materials—including a fresh and typically 500-page book of
Notes. These books form a library that is available for sale. To
• advice and information from our applications engineers, on the
register or obtain more information, consult the analog.com
phone and in the field, to discuss the technical pros, cons,
web site. It’s an excellent opportunity to get a taste of Analog
advantages and pitfalls in using our products to solve your
Devices support.
design problems and selecting the right product from among
the many choices available Q. What seminar books are available?
• samples and evaluation boards from our sales and applications A. I thought you’d never ask. Here are the most recent thru 1996:
engineers, to try out new products—especially those at the • High-speed design techniques (1996)
edges of the technology—and • Practical analog design techniques (1995)
• seminars, practical tutorials in various aspects of analog-, • Linear design seminar (1994)
digital-, and mixed-signal processing.
• System applications guide (1993)
Q. That sounds like a rather full plate.What’s in it for you? • Amplifier applications guide (1992)
A. We’re really quite pragmatic. The products that we manufacture • Mixed-signal design seminar (1991) b
are—more often than not—state of the art and often pace the
knowledge of the engineers who will benefit by applying them. VARIOUS TOPICS
It is in Analog Devices’ best interest to assist these engineers by James Bryant
in learning how and why to apply these products. Q. Tell me something about supply decoupling.
Today, designers are at a crossroads and in need of new forms A. All precision analog integrated circuits, even low-frequency
of guidance. Analog Devices’ unique combination of abilities ones, contain transistors having cutoff frequencies of hundreds
in component design, processes, and functional integration, of MHz; their supplies must therefore be decoupled to the
our long-cultivated capability of combining analog and digital ground return at high frequency—as close to the IC as feasible
functions on a single chip, our 25 years of experience in helping to prevent possible instability at very high frequencies. The
designers deal with the unique problems of transitioning capacitors used for such decoupling must have low self-
between the analog and digital worlds—and now our unique inductance, and their leads should be as short as possible
contributions in digital signal processing—combine to put us (surface-mounted chip ceramic capacitors of 10- to 100 nF
in the forefront of a revolution in system design. are ideal, but leaded chip ceramics are generally quite effective
The integration of these capabilities shows up in both the if the lead length is kept to less than 2 mm (see nearby figure).
products and the ability to provide support for customers using Low-frequency decoupling is also important, since the PSR
them to deal with the signal-conditioning chain in its entirety. (power-supply rejection) is normally specified at dc and will
The chain starts and ends with the analog signal—to condition deteriorate appreciably with increasing power-supply ripple
it, convert it, process it in the digital domain, and convert the frequencies. In some high-gain applications, feedback through
result back to analog. The physical and electrical environment the common power-supply impedance can lead to low
is often hostile to signals, and there are many (often quite frequency instability (“motorboating”). However, low-
subtle) things for the designer to consider. We are in a unique frequency decoupling at each IC is not often necessary.

14 Analog Dialogue 25-1 (1991)

 Ask The Applications Engineer – 9

C IDEAL HF DECOUPLING HAS These reactances must be considered carefully when designing
1. LOW INDUCTANCE CAPACITOR (MONOLITHIC CERAMIC)
GROUND 2. MOUNTED VERY CLOSE TO THE IC
3. WITH SHORT LEADS
high frequency circuits which contain resistors.
IC PLANE
4. AND SHORT, WIDE PC TRACKS
Q. But many of the circuits you describe are for making precision
IT MAY BE SHUNTED WITH A TANTALUM BEAD ELECTROLYTIC
TO PROVIDE GOOD LF DECOUPLING AS WELL. measurements at DC or very low frequencies. Stray inductance and
capacitance don’t matter in such applications, do they?
C
A. They actually do. Since transistors (either discrete or within
ICs) have very wide bandwidths, if such circuits are terminated
with reactive loads, they may sometimes oscillate at frequencies
of hundreds or thousands of MHz; bias shifts and rectification
THIS SORT OF THING IS USELESS! associated with the oscillations can have devastating effects on
low-frequency precision and stability.
Supply decoupling does more than prevent instability. An op-
amp is a four-terminal device (at least), since there must be a Even worse, this oscillation may not appear on an oscilloscope,
return path for both input signals and the output circuit. It is either because the oscilloscope bandwidth is too low for such
customary to consider the common terminal of both op-amp a high frequency to be displayed, or because the scope probe’s
supplies (for op-amps using + supplies) as the output signal capacitance is sufficient to stop the oscillation. It is always wise
return path, but in fact, one of the supplies will be the de facto to use a wideband (LF to 1.5 GHz or more) spectrum analyzer
return path at higher frequencies, and the decoupling of the to verify the absence of parasitic oscillations in a system. Such
amplifier’s supply terminal for this supply must take into checks should be made while the input is varied throughout
consideration both the necessity of normal high-frequency its whole dynamic range, since parasitic oscillations may
decoupling and the routing of the output ground.* sometimes occur over a narrow range of inputs.

Q. In “Ask the Application Engineer,” you’re always describing Q. Are there any problems with the resistance of resistors?
non-ideal behavior of integrated circuits. It must be a relief to use a A. The resistance of a resistor is not fixed but varies with
simple component like a resistor and know that you have a near-ideal temperature. The temperature coefficient (TC) varies from a
component. few parts per million per degree Celsius (ppm/°C) to thousands
A. I only wish that a resistor was an ideal component, and that of ppm/°C. The resistors with the best stability are wirewound
that little cylinder with wire ends behaved just like a pure or metal film types, and the worst are carbon composition.
resistance. Real resistors also contain imaginary resistance Large temperature coefficients are sometimes useful (an
components—in other words they’re reactive. Most resistors earlier “Ask the Applications Engineer”† mentioned how a
have a small capacitance, typically 1-3 pF, in parallel with their +3,500-ppm/°C resistor can be used to compensate for the
resistance, although some types of film resistors, which have a kT/q term in the equation for the behavior of a junction diode).
spiral groove cut in their resistive film, may be inductive, with But in general, the variation of resistance with temperature is
inductances of a few tens or hundreds of nH. likely to be a source of error in precision circuits.

RESISTORS ARE REACTIVE:

If the accuracy of a circuit depends on the matching of two
resistors having different TCs, then, no matter how well-
matched at one temperature, they will not match at another;
“ ” and even if the TCs of two resistors match, there is no guarantee
≅ OR OR that they will remain at the same temperature. Self-heating by
internal dissipation, or external heating from a warm part of
the system, will result in a mismatch of temperature, hence
resistance. Even with high quality wirewound or metal-film
resistors these effects can result in matching errors of several
Of course, wirewound resistors are generally inductive rather
hundred (or even thousand) ppm. The obvious solution is to
than capacitive (at least, at the lower frequencies). After all,
use resistors which are fabricated in close proximity on the
they consist of a coil of wire. It is commonplace for wirewound
same substrate whenever good matching is necessary for system
resistors to have inductances of several microhenrys or tens of
accuracy. The substrate may be the silicon of a precision analog
microhenrys, and even so-called “non-inductive” wirewound
IC or a glass or metal thin-film substrate. In either case, the
resistors, which consist of N/2 turns wound clockwise and N/2
resistors will be well-matched during manufacture, will have
turns wound anticlockwise, so that the inductances of the two
well-matched TCs, and will be at nearly the same temperature
half windings cancel out, have a residual inductance of a
because of their proximity.
microhenry or even more. (For higher-resistance-value types,
above 10 kΩ or so, the residual reactance may be capacitive (This discussion will be continued in a future issue.) b
rather than inductive, and the capacitance will be higher—by †Analog Dialogue 22-2, 1988. p.29.
up to 10 pF—than a standard film or composition resistor.)

*This issue is developed in detail in the free application note, “An IC amplifier
user’s guide to decoupling, grounding, and making things go right for a change,”
by Paul Brokaw. [AN-202]

Analog Dialogue 25-1 (1991) 15

Ask The Applications Engineer—10 C=
0.00885 Er A
pF
d
by James Bryant A d
A = plate area in mm2
Q. In the last issue of Analog Dialogue you told us about some of the
d = plate separation in mm
problems of a simple resistor. [More will appear in a future issue.] Er = dielectric constant relative to air
Surely there must be some component that behaves exactly as I
expected it to. How about a piece of wire? ● Commonest type of PCB uses 1.5mm
glass-fiber epoxy material with Er = 4.7
A. Not even that. You presumably expect your piece of wire or
length of PC track to act as a conductor. But room-temperature ● Capacity of PC track over ground plane
is roughly 2.8pF/cm2
superconductors have not yet been invented, so any piece of
metal will act as a low-valued resistor (with capacitance and
inductance, too) and its effect on your circuit must be Q. Hold it! What’s a ground plane?
considered.
A. If one entire side of a PCB (or one entire layer, in the case of
Q. Surely the resistance of a short length of copper in small-signal circuits a multi-layer PCB) consists of continuous copper which is used
is unimportant? as ground this is known as a “ground plane.” It will have the
A. Consider a 16-bit a/d converter with 5-kΩ input impedance. least possible resistance and inductance of any ground
Suppose that the signal conductor to its input consists of configuration. If a system uses a ground plane, it is less likely
10 cm of typical PC track—0.25 mm (0.010") wide and to suffer ground noise problems.
0.038 mm (0.0015") thick. This will have a resistance of Q. I have heard that ground planes are hard to manufacture.
approximately 0.18 Ω at room temperature, which is slightly
less than 2 × 2–16 of 5 kΩ; this introduces a gain error of A. Twenty years ago there was some truth in this. Today
2 LSB of full scale. improvements in PC adhesives, solder resists and wave-
soldering techniques make the manufacture of ground-plane
OHM'S LAW PREDICTS 1 LSB DROP IN 5cm OF STANDARD
PCB TRACK – BUT WHO BELIEVES OHM'S LAW?
PCB’s a routine operation.
≈ 0.18Ω Q. You say that a system using a ground plane is “less likely” to suffer
10cm
16-BIT ground noise problems.What remaining ground noise problems does
ADC
SIGNAL
SOURCE
it not cure?
0.25mm 0.038mm
5k
A. The basic circuit of a system having ground noise is shown in
WIDE THICK
the diagram. Even with a ground plane the resistance and
inductance will not be zero—and if the external current source
R
FOR 1oz COPPER is strong enough it will corrupt the precision signal.
ρ = 1.724 × 10 –6 ohm-cm
Y X
and
Y = 0.0038cm
SIGNAL
ρ ADC
Z ≈ 0.45mΩ/ SIGNAL
Y SOURCE
ρZ 100
R= ρ = RESISTIVITY R ≈ 0.45
YX 0.25
ρ Z
= (OHMS/SQUARE) (# OF SQUARES)
Y X
VOLTAGE DUE TO SIGNAL CURRENT
AND (PERHAPS) EXTERNAL CURRENT
FLOWING IN GROUND IMPEDANCE
One might argue that the problem would be reduced if PC
tracks were made wider—and indeed, in analog circuitry it’s
almost always better to use wide tracks; but many layout drafters EXTERNAL
CURRENT
(and PC Design programs) prefer minimum-width tracks for SOURCE

signal conductor. In any case it’s especially important to

calculate the track resistance and its effect in every location
where it might cause a problem. The problem is minimized by arranging the PCB so that high
currents do not flow in regions where ground voltages can
Q. Doesn’t the capacitance of the extra width of track to metal on the
corrupt precision signals. Sometimes a break or slot in a ground
board’s underside cause a problem?
plane can divert a large ground current from a sensitive area—
A. Rarely. Although the capacitance of PC tracks is important but breaks in a ground plane can also reroute signals into
(even in circuits designed for low frequencies, since LF circuits sensitive areas, so the technique must be used with care.
can oscillate parasitically at HF) and should always be
Q. How do I know what voltage drops are present in a ground plane?
evaluated, the extra capacitance of a wider track is unlikely to
cause a problem if none existed previously. If it is a problem, A. They should generally be measured; however, it is sometimes
small areas of ground plane can be removed to reduce ground possible to calculate them from the resistance of the
capacitance.

16 Analog Dialogue 25-2 (1991)

 Ask The Applications Engineer – 10

ground plane material (standard 1 oz copper has resistance of For example, 1 cm of 0.25-mm track has an inductance of
0.45 mΩ/square) and the length through which currents flow, 10 nH.
but the calculation can be complicated. At DC and low
frequencies (dc-50 kHz), voltage drops can be measured 2R L, R in mm
with an instrumentation amplifier such as the AMP-02 or
L
the AD620.
2L
WIRE INDUCTANCE = 0.0002L In – 0.75 µH
R

EXAMPLE: 1cm of 0.5mm o.d. wire has an inductance of 7.26nH

(2R = 0.5mm, L = 1cm)
TO IN–
PROBES AMP L
OSCILLOSCOPE
H
5mV/div W
×1000

The amplifier is set to a gain of 1,000 and connected to an

2L W+H
oscilloscope with a gain of 5 mV/div. The amplifier may be STRIP INDUCTANCE = 0.0002L In + 0.2235 + 0.5 µH
W+H L

powered from the same supply as the circuit being tested—or EXAMPLE: 1cm of 0.25mm PC track has an inductance of 9.59 nH
from its own supply—but the grounds of the amplifier, its (H = 0.038mm, W = 0.25mm, L = 1cm)

supply if separate, and the oscilloscope must be connected to But inductive reactance is generally much less of a problem
the power ground of the circuit under test at the power supply. than stray flux cutting inductive loops and inducing voltages;
The voltage between any two points on the ground plane may loop area must be minimized, since voltage is proportional to
then be measured by applying the probes to those points. The it. In wired circuits this is easily done using twisted pairs.
combination of the amplifier gain and oscilloscope sensitivity REDUCING LOOP INDUCTANCE
give a measurement sensitivity of 5 µV/div. Amplifier noise
will swell the oscilloscope trace to a band about 3 µV wide but
LOAD
it is still possible to make measurements with about 1-µV SOURCE LOAD
resolution—sufficient to identify most low-frequency ground SOURCE

noise problems; and identification is 80% of a cure.

Q. Are there any cautions about performing this test? In boards, leads and return paths should be close together;
A. Any alternating magnetic fields which thread the probe leads quite small changes in layout will often minimize the effect.
will induce voltages in them. This can be tested by short-
circuiting the probes together (and resistively to ground to
A
provide a bias current path) and observing the oscilloscope
trace; ac waveforms observed that result from inductive pickup
may be minimized by repositioning the leads or taking steps to
eliminate the magnetic field. It is also essential to ensure that B
the ground of the amplifier is connected to the system ground;
without this connection the amplifier, with no return path for
bias current cannot work; grounding also ensures that this In this circuit, mutual inductance will couple energy from high-
connection does not disturb the current distribution that is level source A into low-level circuit B.
being measured.
Q. What about measuring HF ground noise? A

A. It is hard to make a suitable instrumentation amplifier with

wide bandwidth, so at HF and VHF a passive probe is more
suitable. This consists of a ferrite toroid (6-8 mm OD) wound B

with two coils of 6-10 turns each. One coil is connected to the
input of a spectrum analyzer, the other to the probes, to make
a high-frequency isolating transformer. Reducing area and increasing separation will minimize the
effect.
The test is similar to the LF one but the spectrum analyzer
displays noise as an amplitude-frequency plot.While this differs Usually, all that is necessary is to minimize loop area and
from time-domain information, sources of noise may be easier maximize the distance between potentially interfering loops.
to identify by their frequency signatures; in addition, the use Occasionally magnetic shielding is required, but it is expensive
of a spectrum analyzer provides at least 60 dB more sensitivity and liable to mechanical damage; avoid it whenever possible.
than is possible with a broadband oscilloscope. REFERENCES
Q. What about the inductance of wires? The Best of Analog Dialogue 1967-1991. Norwood MA: Analog
A. The inductance of wire- and PC-track leads should not Devices (1991), pp. 120-129, 193-195. Contains many additional
be overlooked at higher frequencies. Here are some references.
approximations for calculating the inductance of straight wires Mixed-Signal Design Seminar Notes. Norwood MA: Analog Devices
and runs. (1991). Contains additional References. b

Analog Dialogue 25-2 (1991) 17

Ask The Applications Engineer—11 At the surface of a silicon chip there are more impurities,
mechanical stresses and crystal-lattice dislocations than within
by James Bryant the chip. Since these contribute to noise and long-term
All analog-to-digital converters (ADCs) and digital-to-analog instability, the buried breakdown diode is less noisy and much
converters (DACs) require a reference signal, usually a voltage. more stable than surface Zeners—it is the preferred on-chip
The digital output of the ADC represents the ratio of the input to reference source for accurate IC devices.
the reference, the digital input to a DAC defines the ratio of its
However, its breakdown voltage is normally about 5 V or more
analog output to its reference. Some converters have their
and it must draw several hundred microamperes for optimum
references built-in, some require an external reference, but all must
operation, so the technique is not suitable for references which
have a voltage (or current) reference of some sort.
must run from low voltage and have low power consumption.
Most early applications of data converters were in “dc” For such applications, the “bandgap” reference is preferred. It
measurements of slowly varying signals, where the exact timing of develops a voltage with a positive temperature coefficient to
the measurement was unimportant. Today most data-converter compensate for the negative temperature coefficient of a
applications are in sampled data systems, where large numbers of transistor’s Vbe, maintaining a constant “bandgap” voltage. In
equally spaced analog samples must be processed and spectral the circuit shown,* Q2 has 8 times the emitter area of Ql; the
information is as important as amplitude information. Here the pair produces a current proportional to their absolute
quality of the frequency or time reference (the “sampling clock” temperature (PTAT) in R1, developing a PTAT voltage in series
or “reconstruction clock”) is comparable in importance to that of with the Vbe of Q1, resulting in a voltage, Vz, which does not
the voltage reference. vary with temperature and can be amplified, as shown. It is
equal to the silicon bandgap voltage (extrapolated to
VOLTAGE REFERENCES
absolute zero).
Q. How good must a voltage reference be?
Bandgap references are somewhat less accurate and stable than
A. It depends on the system. Where absolute measurements are
the best buried-Zener references, but temperature variation of
required, accuracy is limited by the accuracy with which the
better than 3 ppm/°C may be achieved.
reference value is known. In many systems, however, stability
or repeatability are more important than absolute accuracy; +V IN

and in some sampled-data systems the long-term accuracy of R8 R7

the voltage reference is scarcely important at all—but errors

R4
can be introduced by deriving reference from a noisy system I 2 > I1 VOUT = V Z 1 +
R5
supply. R4

Monolithic buried-Zener references (for example the AD588 Q2

8A
Q1
A
V Z = VBE + V1

and AD688) can have initial accuracy of 1 mV in 10 V (0.01% ∆VBE

∆VBE R5 = VBE + 2
R1
∆VBE
R2 (Q1) R2
or 100 ppm) and a temperature coefficient of 1.5 ppm/°C.
R 1 kT J1
They are accurate enough to use untrimmed in 12-bit systems = VBE + 2
R2 q
In
J2
R1
(1 LSB = 244 ppm) but not in 14- or 16-bit systems. With the 2I1 = I1 + I2 R1 V1 = 2 ∆VBE
R2 = 1.205V
initial error trimmed to zero, they can be used in 14- and 16-bit COM

systems over a limited temperature range. (1 LSB = 61 ppm, a

Q. What precautions should I take when using voltage references?
40°C temperature change in an AD588 or AD688).
A. Remember the basics of good analog circuit design: beware of
For higher absolute accuracy, the temperature of the reference
voltage drops in high impedance conductors, noise from
may need to be stabilized in a thermostatically controlled oven
common ground impedances, and noise from inadequately
and calibrated against a standard. In many systems, while 12-bit
decoupled supply rails. Consider in which direction the
absolute accuracy is unnecessary, 12-bit or higher resolution
reference current is flowing, and be careful of capacitive loads.
may be required; here, less accurate (and less costly) bandgap
references may be used. Q. I know about the effects of voltage drop and noise, but do references
have to supply large-enough currents for voltage drop in conductors
Q. What do you mean by “buried Zener” and “bandgap”?
to be significant?
A. These are the two commonest types of precision references
A. Generally, references are internally buffered; most will source
used in integrated circuits.
and sink 5-10 mA. Some applications may require currents of
The “buried” or subsurface Zener is the more stable and this order or greater; an example is where the reference serves
accurate. It consists of a diode with the correct value of as the system reference; another is in driving the reference input
reverse-breakdown voltage, formed below the surface level of of a high speed flash ADC which, has very low impedance. A
the integrated-circuit chip, then covered by a protective current of 10 mA flowing in 100 mΩ will experience a voltage
diffusion to keep the breakdown below the surface. drop of 1 mV, which may be significant. The highest-
TOP DIFFUSION
performance voltage references, such as the AD588 and
ZENER
BREAKDOWN DIFFUSION ZENER AD688, have Kelvin (force-sense) connections for both their
BURIED DIFFUSION
REGION BREAKDOWN output and output ground terminals. By closing a feedback
REGION

SIMPLE ZENER DIODE BURIED (OR SUBSURFACE) *From Analog Dialogue 9-1 (1975) also The Best of Analog Dialogue, 1967 to
ZENER DIODE 1991, p. 72.

18 Analog Dialogue 26-1 (1992)

 Ask The Applications Engineer – 11

loop around the sources of error, these connections avoid the RS (or a current source) must be chosen so that for all expected
effects of voltage drops; they also correct gain and offset errors values of negative supply and reference load current the ground-
when current-buffer amplifiers are used to drive substantial and output-terminal currents are within ratings.
loads or sink currents flowing in the wrong direction. The sense Q. What about capacitive loads?
terminal should be connected to the output side of the buffer
amplifier, preferably at the load. A. Many references have output amplifiers that become unstable
and may oscillate when operated with large capacitive loads;
so it is inadvisable to connect high capacitance (several µF or
more) to the output of a reference to reduce noise, but 1-10 nF
capacitors are often recommended—and some references (e.g.,
AD588) have noise-reduction terminals to which capacitance
can be safely connected. If force-sense terminals are available,
it may be possible to tailor loop dynamics under capacitive
load. Consult data sheets and manufacturers’ Application
Engineers to be sure. Even if the circuit is stable, it may not be
advisable to use large capacitive loads since they increase the
turn-on time of the reference.
Q. Don’t references turn on as soon as power is applied?
A. By no means. In many references the current that drives the
reference element (Zener or bandgap) is derived from the
Q. What do you mean by flow in the wrong direction”? stabilized output. This positive feedback increases dc stability
A. Consider a +5-V reference operated from a +10-V supply. If but leads to a stable “off ” state that resists startup. On-chip
its 5-volt output terminal is loaded by a resistor to ground, circuitry to deal with this and facilitate startup is normally
current will flow out of the terminal. If the resistor is instead designed to draw minimal current, so many references come
connected to the +10-V supply, current will flow into the up somewhat slowly (1-10 ms is typical). Some devices are
terminal. Most references will allow net current flow in either indeed specified for faster turn-on; but some are even slower.
direction; but some will source current but not sink it—or will If the designer needs reference voltage very quickly after power
sink much less than can be sourced. Such devices, identifiable is applied to the circuit, the reference chosen must have a
by the way their output current is specified on the data sheet, sufficiently fast turn-on specification; and noise reduction
may not be used in applications where substantial net current capacitance should be minimized. Reference turn-on delay may
must flow into the reference terminal. A common example is limit the opportunities for strobing the supplies of data
the use of a positive reference as a negative reference. conversion systems in order to conserve system power. The
+6V → +30V
problem must still be considered even if the reference is built
into the converter chip; it is also important in systems of this
2 type to consider the power-up characteristics of the converter
VIN as well [discussed in “Ask The Applications Engineer—1,”
VOUT 6 Analog Dialogue 22-2 (1988), p. 29].
AD586
High-precision references may require an additional period of
GND thermal stabilization after turn-on before the chip reaches
4 thermal stability and thermally induced offsets arrive at their
–5V final values. Such effects will be mentioned on the data sheet
RS
4kΩ
and are unlikely to exceed a few seconds.

–15V
Q. Does using these high precision references instead of its internal
Q. Why not just buy a negative reference? reference make a converter more accurate?

A. Because most single voltage-output references are positive A. Not necessarily. For example, the AD674B, a high-speed
references. Two-pin active references, of course, can be used descendant of the classical AD574, has a factory-trimmed
for either polarity; they are used in the same way as Zener calibration error of 0.25% (± l0 LSB) max, with an internal
diodes (and they are usually bandgap devices). reference guaranteed accurate to within +100 mV (1%). Since
0.25% of 10 V = 25 mV, full scale is 10.000 V + 25 mV. Suppose
For a three-terminal positive reference to be used as a negative that an AD674B with a 1% high internal reference (10.1 V)
reference, it must be able to sink current. Its output terminal had been factory-trimmed for 10.000 V full scale, by a 1%
is connected to ground and its ground terminal (which becomes gain increase. If an accurate 10.00-V AD588 system reference
the negative-reference terminal) is connected to the negative were to be connected to the device’s reference input, full scale
supply via a resistor (or a constant current source). The positive would become 10.100 V, at 4 times the specified max error.
supply pin must generally be connected to a positive supply at
least a few volts above ground. But some devices can provide Q. Please discuss the role of the clock as a system reference.
negative reference in the two-terminal mode: the positive and A. Oops, we’re out of space! This question introduces a topic that
output terminals are connected together to ground. merits thoughtful discussion. We’ll do it in a future issue. b

Analog Dialogue 26-1 (1992) 19

Ask The Applications Engineer—12 A. If you have only one data converter in your system, you could
actually do what the data sheet says and tie your analog and
GROUNDING (AGAIN) digital ground systems together at the converter. Your system
star ground point is now at the data converter. But this may be
by Walt Kester extremely undesirable, unless you initially planned your system
Q. I’ve read your data sheets and application notes and also attended
with this thought in mind. If you have several data converters
your seminars, but I’m still confused about how to deal with analog
located on different PCBs, the concept breaks down, because
(AGND) and digital (DGND) ground pins on an ADC.Your data
the analog and digital ground systems are joined at each
sheets usually say to tie the analog and digital grounds together at
converter on a number of PCBs. This is a perfect invitation for
the device, but I don’t want the ADC to become my system’s star
ground loops!
ground point. What do I do?
Q. I think I’ve figured it out! If I must join the AGND and DGND
A. First of all, don’t feel bad that you are confused about what to pins together at the device, and I want to maintain separate system
do with your analog and digital grounds. So are lots of folks! analog and digital grounds, I tie both AGND and DGND to either
Much of the confusion comes from the labeling of the ADC the analog ground plane or the digital ground plane on the PCB,
ground pins in the first place. The pin names, AGND and but not both. Right? Now, which one should it be, since the ADC is
DGND, refer to what’s going on inside the component itself both an analog and a digital device?
and do not necessarily imply what you should do with them A. Correct! Now, if you connect the AGND and DGND pins
externally. Let me explain. both to the digital ground plane, your analog input signal is
Inside an IC that has both analog and digital circuits, such as going to have digital noise summed with it, because it is
an ADC, the grounds are usually kept separate to avoid probably single-ended and referenced to the analog ground
coupling digital signals into the analog circuits. The diagram plane.
shows a simple model of an ADC. There is really nothing the Q. So the right answer is to connect both AGND and DGND pins to
IC designer can do about the wirebond inductance and the analog ground plane? But doesn’t this inject digital noise on my
resistance associated with connecting the pads on the chip to nice quiet analog ground plane? And isn’t the noise margin of the
the package pins. The rapidly changing digital currents produce output logic degraded because it now referenced to the analog ground
a voltage at point B which will inevitably couple into point A plane, and all the other logic is referenced to the digital ground plane?
of the analog circuits through the stray capacitance. It’s the IC I plan to run the ADC outputs to a backplane tristate data bus
designer’s job to make the chip work in spite of this. However, which is going to be pretty noisy to begin with so I think I need all
you can see that in order to prevent further coupling, the AGND the noise margin I can get.
and DGND pins should be joined together externally to the A. Well, nobody ever said life was easy or fair! You have reached
same low impedance ground plane with minimum lead lengths. the right conclusion by traveling a rocky road, but the problems
Any extra external impedance in the DGND connection will you suggest—digital noise on your analog ground plane and
cause more digital noise to be developed at point B; it will, in reduced noise margin on your ADC outputs—really aren’t as
turn, couple more digital noise into the analog circuit through bad as they seem; they can be overcome. It is clearly better to
the stray capacitance. Though an extremely simple model, this let a few hundred millivolts corrupt the digital interface than
serves to illustrate the point. to apply the same corrupting signal to the analog input where
VA V D1 VD2 the least-significant-bit for a 16-bit, 10-V-input-range ADC is
only 150 µV! First of all, the digital ground currents on DGND
A A D
pins can’t really be that bad, or they would have degraded the
ADC internal analog parts of the ADC in the first place! If you bypass
IC
the power pins of the ADC to the analog ground plane, using
DIGITAL
C STRAY LOGIC
a good-quality high-frequency ceramic capacitor for high
ICs frequency noise (say 0.1 µF), you will isolate these currents to
V IN
ANALOG DIGITAL a very small region around the IC, and they will have minimal
CIRCUITS CIRCUITS
effect on the rest of your system.
A B

IA
CSTRAY
ID
You will incur some reduction in digital noise margin, but it is
A usually acceptable with TTL or CMOS logic if it’s less than a
few hundred millivolts or so. If your ADC has single-ended
AGND DGND
GND ECL outputs, you may want to put a push-pull gate on each
digital output—i.e., one with both true and complementary
A A ∆V D
outputs. Tie the grounds of this gate package to the analog
ground plane and connect the logic signals differentially across
= ANALOG = DIGITAL
A
GROUND PLANE
D
GROUND PLANE the interface. Use a differential line receiver at the other end
Q. O.K., you’ve told me to join the AGND and DGND pins of the IC which is grounded to the digital ground plane. The noise
together to the same ground plane—but I am maintaining separate between the analog and digital ground planes is now common-
analog and digital ground planes in my system. I want them tied mode—most of it will be rejected at the output of the differential
together only at one point: the common point where the power supply line receiver. You could use the same technique with TTL or
returns are all joined together and connected to chassis ground. Now CMOS, but there is usually enough noise margin not to require
what do I do? differential transmission techniques.

20 Analog Dialogue 26-2 (1992)

 Ask The Applications Engineer – 12

However, one thing you said troubles me greatly. In general, it analog ground plane to prevent digital noise from coupling
is unwise to connect the ADC outputs directly to a noisy data into the analog output.
bus. The bus noise may couple back into the ADC analog input Q. What about mixed-signal chips which contain ADCs, DACs, and
through the stray internal capacitance—which may range from DSPs such as your ADSP-21msp5O voiceband processor?
0.1 to 0.5 pF. It is much better to connect the ADC outputs
directly to an intermediate buffer latch located close to the A. The same philosophy applies. You should never think of a
ADC. The buffer latch is grounded to your digital ground plane, complex mixed-signal chip, such as the ADSP-21msp50, as
so its output logic levels are now compatible with those of the being only a digital chip! The same guidelines we’ve just been
rest of your system. discussing should be applied. Even though the effective
sampling rate of the 16-bit sigma-delta ADC and DAC is only
VA VD1 V D2
0.1µF 0.1µF 0.1µF 8 ksps, the converters operate at an oversampling frequency of
1 MHz. The device requires an external 13-MHz clock, and
A A D
an internal 52- MHz processor clock is generated from it with
a phase-locked loop. So you see, successful application of this
device requires an understanding of design techniques for both
BUFFER
ADC
LATCH precision- and high-speed circuits.
TO NOISY
DATA BUS
Q. What about the analog and digital power-supply requirements of
A these devices? Should I buy separate analog and digital power supplies
A D or use the same supply?
Q. I think I understand now, but why on earth didn’t you just call all A. This really depends on how much noise is on your digital
the ground pins of your ADC AGND in the first place; then none of supply. The ADSP-21msp50, for example, has separate pins
this would have come up in the first place? for the +5- V analog supply and the +5-V digital supply. If you
have a relatively quiet digital supply, you can probably get away
A. Perhaps. But what if the incoming-inspection person connects
with using it for the analog supply too. Be sure to properly
an ohmmeter between these pins and finds out that they are
decouple each supply pin at the device with a 0.1-µF ceramic
not actually connected together inside the package? The whole
capacitor. Remember to decouple to the analog ground plane,
lot will probably be rejected—and the IC may be blown!
not the digital ground plane! You may also want to use ferrite
Furthermore, there is a tradition associated with ADC data
beads for further isolation. The diagram below shows the proper
sheets which says we must label the pins to indicate their true
arrangement. A much safer solution is to use a separate +5-V
function, not what we would like them to be.
analog supply. You can generate the +5 V from a quiet +15-V
Q. O. K. Now, here comes a question I’ve been saving as your ultimate or +12-V supply using a three-terminal regulator, if you can
test! I have a colleague who designed a system with separate analog tolerate the extra power dissipation. b
and digital ground systems. My colleague says that, with the ADC’s
AGND pin connected to the analog ground plane and the DGND REFERENCES [not available from Analog Devices unless noted]
pin connected to the digital ground plane, the system is working 1. Ralph Morrison, Grounding and Shielding Techniques in Instrumentation, Third
Edition. New York: Wiley-lnterscience, 1986.
fine! How do you explain this? 2. Henry W. Ott, Noise Reduction Techniques in Electronic Systems, Second
A. First of all, just because a practice is not recommended doesn’t
necessarily mean you can’t get away with it some of the time 0.1µF 0.1µF

and thereby be lulled into a false sense of security. (This is one

DIGITAL A A
of the lesser-known of Murphy’s Laws). Some ADCs are less SUPPLY

sensitive to external noise between the AGND and DGND L L

pins, and it may be that your colleague picked one of those by VD VA

L = FERRITE
accident. There could be other explanations—which would BEAD MIXED SIGNAL
DEVICE
require that we explore your colleague’s definition of “working
fine”—but the point is that the ADC’s specifications are not AGND DGND

guaranteed by the manufacturer under those operating

A A
conditions. With a complex component like an ADC, it is
impossible to test the device under all possible operating
circumstances, especially those which aren’t recommended in Edition. New York: Wiley-Interscience, 1988.
the first place! Your friend got lucky this time, but you can be 3. High-Speed Design Seminar, 1996. Norwood MA: Analog Devices, Inc.
sure that Murphy’s law will ultimately catch up with him (or 4. Mixed-Signal Design Seminar, 1991. Norwood MA: Analog Devices, Inc.
5. Paul Brokaw, “An I.C. Amplifier User’s Guide to Decoupling, Grounding
her) if this practice is continued in future system designs.
and Making Things Go Right for a Change.” AN-202. Free from Analog
Q. I think I understand the ADC grounding philosophy now, but what Devices.
about DACs? 6. Jeff Barrow, “Avoiding Ground Problems in High Speed Circuits,” R.F.
Design, July, 1989.
A. The same philosophy applies. The DAC’s AGND and DGND 7. Paul Brokaw and Jeff Barrow, “Grounding for Low- and High-Frequency
pins should be tied together and connected to the analog Circuits,” Analog Dialogue 23-3, 1989. Free from Analog Devices.
ground plane. If the DAC has no input latches, the registers 8. The Best of Analog Dialogue—1967-1991. Norwood MA: Analog Devices,
driving the DAC should be referenced and grounded to the Inc. Free from Analog Devices.

Analog Dialogue 26-2 (1992) 21

Ask The Applications Engineer – 12

ODDS ‘N’ ENDS (Continued from earlier issues) A. The phase noise of the sampling clock is often ignored, because
by James Bryant the limiting factor on system performance used to be the
aperture jitter of the of the sample-hold—but if we consider
TIME REFERENCES (continued from 26-1—AA-11) the system as a whole, aperture jitter is just one component of
Q. Why do you say that the clock of a system is a reference? the total phase noise in the sampling clock chain.With modern
A. This comment does not necessarily apply to the conversion sampling ADCs the aperture jitter may be less important than
clock of an ADC; it applies principally to the sampling clock other components of phase noise.
of a sampled-data system. In these systems, the signal is
required to be sampled repeatedly at predictable (usually equal) 1
SNR = 20 log 10
intervals for storage, communication, computational analysis, 90
2πfta
tph = 2ps
or other types of processing. The quality of the sampling clock 14
80
is a system-performance-limiting factor. tph = 10ps
70 12
Q. But crystal oscillators are very stable, aren’t they? 60 10
tph = 50ps

ENOB
SNR – dB
A. They have good long-term stability, but they are often used in 50 8
ways which introduce short-term phase noise. Phase noise is 40
tph = 250ps
6
also introduced by designers who, instead of using crystal 30 tph = 1250ps 4
oscillators, use R-C relaxation oscillators (such as the 555 or 20
the 4046)—which have a great deal of phase noise. 10

Q. How can I ensure that my sampling clock has low phase noise? 0
1 2 3 5 7 10 20 30 50 70 100
A. Don’t use the crystal oscillator circuitry in your microprocessor FREQUENCY OF FULLSCALE SINEWAVE INPUT – MHz
or DSP processor as the source of your sampling clock. If at all
The diagram shows the effect of the total phase jitter of the
possible, do not use a logic gate in a crystal oscillator. Crystal
sampling clock on signal-to-noise ratio (SNR) or effective
oscillators made with logic gates generally overdrive the crystal;
number of bits (ENOB). This jitter has the rms value of tph,
this is bad for its long term stability, and usually introduces
which is made up of the root-sum-of-squares of the phase jitter
worse phase noise than would a simple transistor oscillator. In
on the sampling clock oscillator, the phase jitter introduced by
addition, digital noise from the processor—or from other gates
pickup during transmission of the sampling clock through the
in the package if a logic gate is used as an oscillator—will appear
system, and the aperture jitter of the SHA in the sampling
as phase noise on the oscillator output.
ADC. This diagram may be somewhat unsettling, as it shows
Q. But crystal oscillators are very stable, aren’t they? just how little phase noise is required to corrupt a
A. Ideally, use a single transistor or FET as your crystal oscillator high-resolution sampled-data system.
and buffer it with a logic gate. This logic gate, and the oscillator
itself, should have a well-decoupled supply; the other gates in MORE ON TRIMMING
the package should not be used because logic noise from them Q. I don’t have enough range to adjust the offset of my circuit—and it
will phase-modulate the signal. (They may be used for dc seems to have rather more drift than I’d expected.
applications but not for fast-switching operations.) A. I’ll bet the amplifier is a bipolar type and you are using its
If there is a divider between the crystal oscillator and the offset-trim terminals to trim other circuit voltages.
sampling clock input of the various ADCs, the divider power Q. How did you guess?
supply should be decoupled separately from the system logic
A. The range of offset adjustment of an op amp is normally 2 to
to keep power supply noise from phase-modulating the clock.
5 times the maximum expected offset of the lowest grade of
The sampling clock line should be kept away from all logic the device (in some early op amps, it was much larger, but
signals to prevent pickup from introducing phase noise. Equally, such a wide range is not ideal). If the lowest grade has a VOS
it should be kept away from low-level analog signals lest it (max) of ± 1 mV, then the likely adjustment range with the
corrupt them. recommended circuit is ± 2 to ± 5 mV.
Q. You have told me not to use the clock oscillator of my processor as If the external voltage you are attempting to compensate for is
the sampling clock source.Why not? Isn’t it sensible to use the same larger than this (referred to the op amp’s input), you will not
oscillator for both, since there will then be a constant phase be able to do so with the amplifier’s offset-trim terminals.
relationship between the signals?
Furthermore, if you are using a bipolar-input op amp, it is
A. True. But in such cases, it is often better to use a single discrete
inadvisable to use these terminals for external offset correction
low-noise oscillator to drive the processor clock input and the
because drift will be increased. Here’s why: the input stage
sampling clock divider through separate buffers (though they may
thermal drift is proportional to the internal offset; if this
share a package) than to use the oscillator in the processor. In
has been trimmed to a minimum, the drift will also be a
medium-accuracy systems with low sampling rates it may be
minimum. If you then trim the amplifier to compensate for an
possible to use the processor’s internal oscillator—but check
external offset, drift will no longer be minimized. However,
with the diagram below).
FET-input op amps have separately trimmed offset and drift,
Q. Just how serious is this problem of noise on a sampling clock? I their offset adjustment terminals may thus be used for small
hardly ever see it mentioned in articles on sampled data systems. system adjustments. b

22 Analog Dialogue 26-2 (1992)

Ask The Applications Engineer—13 The expression for THD+N is similar; simply add the noise in
root-sum-square fashion (Vnoise = rms value of noise voltage
CONFUSED ABOUT AMPLIFIER DISTORTION SPECS? over the measurement bandwidth).
by Walt Kester V 22 + V 32 + V 42 + L + V n2 + Vnoise 2
Q. I’ve been looking at your amplifier data sheets and am confused THD =
Vs
about distortion specifications. Some amplifiers are specified in terms
of second- and third-harmonic distortion, others in terms of total It should be evident that THD+N ≈ THD if the rms noise
harmonic distortion (THD) or total harmonic distortion plus over the measurement bandwidth is several times less than the
noise (THD+N), still others have some of these specifications as THD, or even the worst harmonic. It is worth noting that if
well as two-tone intermodulation distortion and third-order you know only the THD, you can calculate THD+N fairly
intercept. Can you please clarify? accurately using the amplifier’s voltage- and current-noise
specifics. (Thermal noise associated with the source resistance
A. Because the amplifier is fundamental to a wide range of uses,
and the feedback network may also need to be computed).
it is natural that many application-specific specifications have
But if your rms noise level is significantly higher than the level
evolved as new amplifiers have been developed to meet those
of the harmonics, and you are only given the THD+N
needs. So—as you so rightly pointed out—distortion may be
specification, you cannot compute the THD.
specified in various ways; the spec depends on how distortion
is defined by users for the particular application. Some distor- Special equipment is often used in audio applications for a
tion specifications are fairly universal, while others are prima- more-sensitive measurement of the noise and distortion. This
rily associated with specific frequency ranges and applications. is done by first using a bandstop filter to remove the
fundamental signal. The total rms value of all the other
But there is some standardization of the basic definitions, so
frequency components (harmonics and noise) is then measured
let’s talk about them first. Harmonic distortion is measured
over an appropriate bandwidth. The ratio to the fundamental
by applying a spectrally pure sine wave to an amplifier in a
is the THD + N spec.
defined circuit configuration and observing the output spec-
trum. The amount of distortion present in the output is usually Q. How are the distortion specs looked at over the various frequency
a function of several parameters: the small- and large-signal ranges and applications?
nonlinearity of the amplifier being tested, the amplitude and A. I think the best way is to start at the low frequency end of the
frequency of the input signal, the load applied to the output of spectrum and work our way up; that will make it easier to see
the amplifier, the amplifier’s power supply voltage, printed the underlying method.
circuit-board layout, grounding, power supply decoupling, etc.
Audio-frequency amplifiers are a good place to start. Types
So you can see that any distortion specification is relatively
used here (such as the OP-275*) are optimized for low noise
meaningless unless the exact test conditions are specified.
and low distortion within the audio bandwidth (20 Hz to
Harmonic distortion may be measured by looking at the out- 20 kHz). In audio applications, total harmonic distortion plus
put spectrum on a spectrum analyzer and observing the values noise (THD+N) is usually measured with specialized equip-
of the second, third, fourth, etc., harmonics with respect to ment such as the Audio Precision System One. The output
the amplitude of the fundamental signal. The value is usually signal amplitude is measured at a given frequency (e.g.,
expressed as a ratio in %, ppm, dB, or dBc. For instance, 1 kHz); then, as above, the fundamental signal is removed
0.0015% distortion corresponds to 15 ppm, or –96.5 dBc. The with a bandstop filter and the system measures the rms value
unit “dBc” simply means that the harmonic’s level is so many of the remaining frequency components, which contain both
dB below the value of the “carrier” frequency, i.e., the harmonics and noise. The noise and harmonics are measured
fundamental. over a bandwidth that will catch the highest harmonics, usu-
Harmonic distortion may be expressed individually for each ally about 100 kHz. The measurement is swept over the fre-
component (usually only the second and third are specified), quency range for various conditions. THD+N results for
or they all may be combined in a root-sum-square (RSS) OP-275 are plotted here as a function of frequency.
fashion to give the total harmonic distortion (THD).
V 22 + V 32 + V 42 + L + V n2
THD =
Vs
where
Vs = signal amplitude (rms volts)
V2 = second harmonic amplitude (rms volts)
Vn = nth harmonic amplitude (rms volts)
The number of harmonics included in the THD measurement
may vary, but usually the first five are enough. You see, the
RSS process causes the higher-order terms to have negligible
effect on the THD, if they are 3 to 5 times smaller than the
largest harmonic [ 0.10 2 + 0.032 = 0.0109 = 0.104 ≈ 0.10].

Analog Dialogue 27-1 (1993) 23

Ask The Applications Engineer – 13

The signal level is 3 V rms, and the amplifier is connected as a –40

unity-gain follower. Notice that a THD+N value of 0.0008%
corresponds to 8 ppm, or –102 dBc. The input voltage noise of –50 VOUT = 2V p–p
the OP-275 is typically 6 nV/√Hz @ 1 kHz and, integrated
over a 100-kHz bandwidth, yields an rms noise level of 1.9 µV 2nd

DISTORTION – dBc
–60
rms. For a 3-V rms signal level, the corresponding signal-to- RL = 50 or 100Ω

noise ratio is 124 dB. Because the THD is considerably greater

–70
than the noise level, the THD component is the primary
contributor. 3rd
–80
RL = 100Ω
Q. I noticed that Analog Devices recently introduced another low-noise,
low-distortion amplifier (AD797) and that it is specified in THD, –90
3rd
not THD+N. The actual specification quoted at 20 kHz is RL = 50Ω
–120 dB.What gives? –100
0.1 0.2 0.6 1 2 4 6 10 20 40 60 100
A. Actually, we are not trying to be misleading here.The distortion FREQUENCY – MHz
is at the limits of measurement of the available equipment,
Q. What are two-tone intermodulation products, and how do they differ
and the noise is even lower—by 20 dB! Here is the measured
from harmonic distortion?
THD of the AD797 as a function of frequency.
–90 A. When two tones are applied to an amplifier that is non-linear,
the nonlinearity causes them to modulate one another,
producing intermodulation distortion (IMD) in the form of
–100 0.001 frequencies known as intermodulation products. (For the
mathematical development of this concept, see Reference 1).
For two tones at frequencies, f1 and f2 (where f2 > f1), the
THD – dB

THD – %

–110 0.0003 second- and third-order IM products occur at the following

frequencies:
Second Order: f1 + f2, f2 – f1
–120 0.0001
Third Order: 2f1 + f2, 2f2 + f1, 2f2 – f1, 2f1 – f2
MEASUREMENT
LIMIT
If the two tones are fairly close together, the third-order IMD
products at the difference frequencies, 2f2 – f1 and 2f1 – f2, may
–130
100 300 1k 3k 10k 30k 100k 300k be especially troublesome because—as the figure shows —they
FREQUENCY – Hz
are hard to filter out. Notice that the other second- and
The measurement was made with a spectrum analyzer by first third-order IMD products—which occur at substantially
filtering out the fundamental sine-wave frequency ahead of higher or lower frequencies—can be filtered (if the only
the analyzer. This is to prevent overdrive distortion in the frequencies of interest are in the neighborhood of f1 and f2).
spectrum analyzer. The first five harmonics were then SECOND- AND THIRD-ORDER
measured and combined in a root-sum-square fashion to get INTERMODULATION PRODUCTS

the THD figure. The legend on the graph indicates that the f1 f2 2 = SECOND-ORDER IMD PRODUCTS
measurement-equipment “floor” is about –120 dB; hence at 3 = THIRD-ORDER IMD PRODUCTS
AMPLITUDE

frequencies below 10 kHz, the THD may be even less. NOTE: f 1 = 5MHz, f 2 = 6MHz

For noise, multiply the voltage noise spectral density of the

3
AD797 (1 nV/√Hz) by the square root of the measurement 2 2
3f 1 2f 2+f 1
f 2–f1 3 3 f2+f 1
bandwidth to yield the device’s rms noise floor. For a 100-kHz 2f1 –f2 2f 2–f 1 2f1 2f 2
3
2f1 +f 2 3f 2
bandwidth, the noise floor is 316 nV rms, corresponding to a
signal-to-noise ratio of 140 dB for a 3-V rms output signal.
1 4 5 6 7 10 11 12 15 16 17 18
Q. How is distortion specified for high frequency amplifiers? FREQUENCY – MHz

A. Because of the increasing need for wide dynamic range at high Two-tone intermodulation-distortion specifications are of
frequencies, most wideband amplifiers now have distortion especial interest in r-f applications and are a major concern in
specifications. The data sheet may give individual values for the design of communications receivers. IMD products can
the second and third harmonic components, or it may give mask out small signals in the presence of larger ones. Although
THD. If THD is specified, only the first few harmonics IMD has been rarely specified in op amps operating at
contribute significantly to the result. At high frequencies, it is frequencies less than 1 MHz, many of today’s dc op amps are
often useful to show the individual distortion components wideband types that can operate usefully at radio frequencies.
separately rather than specifying THD. The AD9620 is a For this reason, it is becoming common to see IMD
600-MHz (typical –3-dB bandwidth) low distortion unity-gain specifications on fast op amps.
buffer. Here are graphs of the AD9620’s second and third Q. What are the second- and third-order intercept points, and what is
harmonic distortion as a function of frequency for various their significance?
loading conditions.

24 Analog Dialogue 27-1 (1993)

 Ask The Applications Engineer – 13

A. Usually associated with r-f applications, these specs provide the IMD products with respect to the output power actually
figures of merit to characterize the IMD performance of the delivered into the 50-Ω load rather than the actual op-amp output
amplifier. The higher the intercept power, the higher the input power.
level at which IMD becomes significant—and the lower the Another parameter that may be of interest is the 1-dB
IMD at a given signal level. compression point, shown in the figure. This is the point at
Here’s how it is derived: Two spectrally pure tones are applied which the output signal has started to limit and is attenuated
to the amplifier. The output signal power in a single tone (in by l dB from the ideal input/output transfer function.
dBm) and the relative amplitudes of the second-order and third- The figure below is a plot of the third-order intercept power
order products (referenced to a single tone) are plotted (and values for the AD9620 buffer amplifier as a function of input
extrapolated) here as a function of input signal power. frequency. Its data can be used to approximate the actual value
INTERCEPT POINTS, GAIN COMPRESSION, IMD of the third order intermodulation products at various
SECOND-ORDER frequencies and signal levels.
INT 2 INTERCEPT
OUTPUT POWER (PER TONE) – dBm

THIRD-ORDER
INT 3 50
INTERCEPT

1dB 50Ω
1dB COMPRESSION
POINT
50Ω

INTERCEPT – +dBm
FUNDAMENTAL 40
(SLOPE = 1)
TEST CIRCUIT
SECOND-ORDER IMD
(SLOPE = 2)
THIRD-ORDER IMD 30
(SLOPE = 3)

INPUT POWER (PER TONE) – dBm

If you go through the mathematical analysis [1], you will find 20

that if device nonlinearity can be modeled by a simple power-

dc 50 100 150
series expansion, the second-order IMD amplitudes tend to FREQUENCY – MHz
increase by 2 dB for every l dB of signal increase. Similarly,
the third-order IMD amplitudes increase 3 dB for every 1 dB Assume the op amp output signal is at 20 MHz with 2 V
of signal increase. Starting with a low-level two-tone input signal peak-to-peak into a 100-Ω load (50-Ω source and load
and taking a few IMD data points, you can draw (and terminations). The voltage into the 50-Ω load is therefore 1 volt
extrapolate) the second- and third-order IMD lines shown on peak-to-peak, with a power of 2.5 mW, corresponding to
the diagram. +4 dBm. The value of the third-order intercept at 20 MHz—
from the graph—is +40 dBm.This permits a graphical solution,
Beyond a certain level, the output signal begins to soft-limit, as shown below. For an output level of +4 dBm, the third-order
or compress (coinciding with the increasing visibility of IMD IMD products, based on an extrapolation of the slope of 3
products). If you extend the second- and third-order IMD back from the intercept, amount to –68 dBm, or 72 dB below
lines, they will intersect the extension of the output/input line; the signal.
these intersections are called the second- and third-order
intercept points. The projected output power values +40
1dB/dB–UNITY THIRD-ORDER
corresponding to these intercepts are usually referenced to the SLOPE INTERCEPT

output power of the amplifier in dBm. +20 +4dBm

Since the slope of the third-order IMD amplitudes is known 0

+20 +40 OUTPUT POWER – dBm

THIRD-ORDER
POWER – dBm

(3 dB/dB), if the intercept is also known, the third-order IM PRODUCTS

–IMD N = INT N(N–1) – N•P OUT ,
products at any input (or output) level can be approximated. –20
WHERE: N = ORDER OF THE IMD

For a higher intercept, the line moves to the right (same slope), IMD N = N TH -ORDER IMD PRODUCT (dBm)
INT N = N TH -ORDER INTERCEPT POINT (dBm)
–40
showing lower 3rd-order products for a given input level. 3dB/dB P OUT = OUTPUT POWER INTO THE LOAD (dBm)
SLOPE 2ND ORDER IMD: –IMD 2 = INT 2 – 2•P OUT
Many r-f mixers and “gain blocks” have 50-Ω input and output –60 3RD ORDER IMD: –IMD 3 = 2•INT 3 – 3•P OUT
–68dBm IN THIS EXAMPLE:
impedances. The output power is simply the power that the –IMD 3 = 2 × 40dBm – 3 × 4dBm = 68dBm

device transfers to a 50-Ω load. The output power is calculated –80

by squaring the rms output voltage (Vo) and dividing by the load
resistance, RL. The power is converted into dBm as follows: This analysis assumes that the op-amp distortion can be
2 modeled with a simple power series expansion as described in
V0
Reference 1. Unfortunately, op amps don’t always follow simple
RL
Output power = 10 log 10 d Bm models (especially at high frequencies), so the third-order
1mW
intercept specification should primarily be used as a figure of
Since an op amp, on the other hand, is a low-output-impedance merit, rather than a substitute for measurements. b
device, for most r-f applications, the output of the op amp
must be source- and load-terminated. This means that the REFERENCES
1. Robert A. Witte, “Distortion Measurements Using a Spectrum Analyzer,”
actual op amp output power has to be 3 dB higher than the RF Design, September 1992, pp. 75-84. (not available from ADI)
power delivered to the load, as calculated from the above 2. High Speed Design Seminar, 1996. Norwood, MA: Analog Devices, Inc.
formula. In this type of application, it is customary to define 3. 1992 Amplifier Applications Guide. Norwood, MA: Analog Devices, Inc.

Analog Dialogue 27-1 (1993) 25

Ask The Applications Engineer—14 they are therefore far more vulnerable and are affected by
low-level RF, such as radiation from a personal computer (PC).
by James Bryant (ADI Europe) [This phenomenon is detailed in the Analog Devices
with Herman Gelbach (The Boeing Company) system-design seminar notes, available for sale as System
Application Guide (1993).]
HIGH-FREQUENCY SIGNAL-CONTAMINATION
An important factor is that, in instrumentation amplifiers,
Q. I’ve heard that RF can make low-frequency circuits do strange
common-mode rejection decreases with increasing frequency,
things. What’s that all about?
starting to roll off at quite low frequencies—and distortion
A. I was once summoned to France because an Analog Devices increases with frequency. Thus, not only are high-frequency
Voltage-Frequency Converter (VFC), the AD654, suffered common-mode signals not rejected; they are distorted,
from “unacceptable variation of accuracy.” I had measured the producing offsets. For some applications, where RF interference
offending parts in my own laboratory and found them to be is a strong possibility, the AD830 difference amplifier has
stable and within specification, but when I returned them to wideband common-mode rejection and is designed for
the customer with my test jig he was unable to reproduce my line-receiver applications; it may be a useful substitute for an
results. While considering a site visit to confirm my suspicions, instrumentation amplifier.
I discovered that the restaurant “La Cognette” in the town
Sensors are often connected to their signal-conditioning
where our customer was located had three stars in the Guide
electronics by long cables. Radio engineers have a term for
Michelin, and the chef was a “Maitre Cuisinier de France”—a
such long pieces of wire; they call them antennas. The long
title not lightly bestowed. The visit to the customer became
feeders from sensors to their electronics will behave in the
doubly necessary. Herman, who was in England to look at data
same way and will serve as antennas, even if we do not wish
offsets in a Boeing wind tunnel test, offered to come and help—
them to do so. It does not matter if the sensor case is
he said it was the interesting technical problem (but just before
grounded—at high frequencies the reactances of the case and
he offered I saw him earnestly consulting the Guide Michelin).
feeders will allow the system to behave as an antenna, and any
To drive from the Analog Devices office in Newbury in the high- frequency signals (E-field, M-field, or E-M-field) which
South of England to the centre of France involves six hours of it encounters will appear across any impedances. The most
driving, a six hour ferry crossing of the English Channel, and likely place for them to end up is at the amplifier input.
a change from the correct side to the right side of the road. Precision low-frequency amplifiers can rarely cope with large
Nevertheless, driving is better than flying, because one can HF signals, and the result is error—commonly a varying offset
take more test gear (and the portable ham-radio station as error.
well—we are both hams).
Q. But this couldn’t happen to me!
As we approached the customer’s works we passed an enormous
A. Never believe it won’t happen to you! An easy free lunch can
short-wave transmitting antenna, and then another, and yet
always be obtained by persuading an innocent to bet on his or
another. We began to guess what might be wrong, and when
her circuit being free of such problems. Using a ham radio HT
we entered the laboratory I was carrying a hand-portable
on the two-metre (144-148-MHz) band, one watt at a distance
two-metre ham transceiver (an HT or “handy-talky”) in my
of one meter for one second will win you your free lunch
jacket pocket.
almost every time. But a less-dramatic test can be equally
The AD654 was indeed behaving unstably, as the customer convincing.
had claimed. The VFC’s output frequency varied by an
Disconnect the sensor and its leads. Short-circuit the amplifier
equivalent offset of tens of mV over the space of a few minutes.
input terminals to each other and to the amplifier circuit
I quietly reached into my pocket and pressed the transmit
common (probably ground) with the shortest possible links
button of my HT. The output frequency jumped by an
and measure the amplifier output; observe its stability over a
equivalent of 150 mV, thus demonstrating the problem to be
few minutes. Now remove the short-circuit, replace the sensor
high-frequency pickup. More-formal measurements a little later
leads and place them in their normal operating environment.
showed that the local transmitters (of the French Overseas
Disable the excitation and short-circuit the signal leads at the
Broadcast organization) produced high-frequency (HF) field
sensor end. Again measure the amplifier output, and its
strengths within our customer’s works of tens or hundreds
variation with time. Weep quietly.
of mV/m.
It is often possible to see what is happening by using a high-
Many problems of instability in precision measurement cir-
frequency oscilloscope (or a spectrum analyzer, which is more
cuitry can be traced to high-frequency interference, but unless
sensitive but less easy to interpret) to measure the HF noise,
there is a loudspeaker in the system that might unexpectedly
both normal mode and common-mode, at the amplifier input;
burst into hard rock music from the nearby radio station, it is
but normal mode measurements must be treated with some
common for engineers to overlook this source of inaccuracy and
suspicion, because the oscilloscope itself—and its power- and
blame the manufacturer of the amplifiers or data converters.
probe leads—may themselves introduce signals and invalidate
Furthermore, this case was unusual in that it took a high- the measurement. The effect of the oscilloscope may be
powered signal to affect the AD654, which is single-ended and minimized by using a simple broadband transformer between
also relatively insensitive to RF—it is much more common to the measurement point and the oscilloscope input, as shown
see with a differential amplifier in-amp. Both inputs of these in the figure; but such a transformer has fairly low impedance
types of amplifier have high input impedances to common; and will load the circuit being measured.

26 Analog Dialogue 27-2 (1993)

 Ask The Applications Engineer – 14

FERRITE
TOROID
SIGNAL
TO MEASUREMENT TO OSCILLOSCOPE
POINT OR SPECTRUM ANALYSER
GUARD
PIN
GUARD
Common-mode signals can be observed quite easily by
disabling any sensor excitation and connecting the oscilloscope
ground to the ground at the board input and joining all the The guard line is connected to ground at the source end and
sensor leads together and to the oscilloscope input. All too at the other end to the amplifier’s guard pin (or a comparable
often this signal will have an amplitude of several hundred derived voltage), which represents what the amplifier “thinks”
millivolts and contain components from low frequencies to tens is common mode, via a capacitor. The high-frequency common-
or hundreds of MHz. mode signal will appear (by definition) across the bottom
The world is full of HF noise sources: ham radio operators, winding, and will induce an equal common-mode voltage in
police, people with portable phones, garage door openers, the the other two, subtracting the common-mode voltage in series
sun, supernovas, switching power-supply and logic signals with each line and effectively cancelling the HF common-mode
(e.g., PCs). Since we cannot eliminate HF noise in the signal at the amplifier inputs.
environment, we must filter it out of low-frequency signals There are, of course, potential problems. A capacitor in series
before they arrive at precision amplifiers. with the transformer is almost essential in the guard circuit to
The simplest type of protection can be used when the signal block DC and LF and prevent transformer core saturation by
bandwidth is only a few Hz. A simple RC low-pass filter low-frequency currents in the guard circuit. The impedance
inserted ahead of an amplifier will afford both normal-mode looking into the amplifier guard terminal must be much lower
and common-mode HF protection. A suitable circuit is shown than the impedance of the transformer windings; and at very
in the figure. There are two important issues to be considered high frequencies the capacitances of the transformer will allow
in the choice of components: the resistances R and R9 (shown signal leakage or may cause phase shift. These issues set
as 1 kΩ in the diagram, a value suitable for amplifier bias incompatible constraints on the design of the transformer, if it
currents of a few nA or less) must be chosen so that they do must deal with a very wide range of common-mode frequencies.
not increase the offset appreciably as the amplifier bias current In such a case double cancellation using two separate
flows in them. The normal-mode time constant, (R + R9)C2, transformers as shown might be considered—the one nearer
must be much larger than the common-mode time constants, the amplifier having high inductance (and correspondingly high
RC1 and R9C19, otherwise the common-mode time constants capacitance) and the other having good VHF efficiency.
would have to be very carefully matched to avoid an imbalance HF TRANSFORMER
that would convert the common-mode to a signal between the (LOW C) MF TRANSFORMER

differential inputs. SIGNAL

GUARD
R 1kΩ PIN
C1
GUARD
0.01µF C2
C1´ 0.1µF
0.01µF
R´ 1kΩ Other approaches are also possible: the amplifier can be sited
closer to the sensor and the long leads be replaced by leads (or
If the signal bandwidth is wider, such simple filters will not be optical fibre) carrying digital data, which is less vulnerable;
suitable because they remove the desired HF normal-mode more shielding is often (but not always) helpful; and sometimes
signals as well as the unwanted HF common-mode signals. (but rarely) it is possible to reduce the possibility of unexpected
Large HF common-mode signals are very likely to suffer HF signals (even if you keep away the hams and police, there
common-mode→normal mode conversion (as well as minor is always the possibility of the unexpected pizza delivery truck
rectification, producing low-frequency errors) if they get to radioing to its base . . .)
the amplifier, so it is necessary to use a filter which will reject The most important consideration, though, is awareness of
HF common-mode signals but will pass DC and HF the possibility of HF interference and readiness to tackle it. If
normal-mode signals. designs are always made in the expectation of unwanted HF,
Such a filter is shown below. It was devised many years ago by chances are excellent that precautions will be adequate—it’s
Bill Gunning of Astrodata and is related to the “phantom when you don’t expect it that the trouble starts.
circuit” used in long-distance telephone circuits. It uses a tightly Q. How did it work out with the French customer?
coupled “trifilar” transformer having three windings in an
A. His problem was cured with two resistors, three capacitors and
accurate 1:1:1 ratio. An AC voltage across any winding will
a piece of grounded copper foil. We went off to “La Cognette”
also be present on the others.
to celebrate. b

Analog Dialogue 27-2 (1993) 27

Ask The Applications Engineer

Regarding (c), a good RF ground to the chassis is important for

A Reader Notes the signal common; but I find the shielding/grounding aspects of
HIGH-FREQUENCY SIGNAL CONTAMINATION the equipment design relate more to the ESD requirements than
by Leroy D. Cordill* RF (continuous-wave) susceptibility problems. I also try not to
rely on these (shielding/grounding) to a great extent, since I find
I found your article on high-frequency signal contamination (“Ask
them very uncontrollable during the life of a piece of field-
The Application Engineer—14,” Analog Dialogue 27-2, 1993)
customizable equipment.
interesting and would like to offer some additional comments.
For (d), my best, most consistent prescription is placing a small
EMI/EMC requirements are becoming more important to
capacitor␣ directly␣ across the input pins on bipolar op amps.␣ I have
designers of industrial equipment as analog signal sensitivities are
used 100-1000␣ pF for this purpose in various circuits; it usually
increased while more “RF generators” (higher-frequency digital
significantly reduces or eliminates the problem up to the level of
circuits) are incorporated into the same equipment. Therefore, I
interference that I plan for. I have found that with this in place on
would like to see a good application note relating to the issue of RF
the critical parts of the circuit, the requirements for extreme care in
susceptibility produced by someone such as Analog Devices. By
grounding and shielding of cables are greatly reduced.
“good”, I feel it should cover:
Regarding (e), I agree that a small walkie-talkie is useful, but
a.␣ rules of thumb about the types of circuits where you will
primarily as a go/no-go test on the equipment when it is all
likely have trouble
assembled, in the enclosure, etc. However, for pc board or circuit-
b.␣ some explanation of the phenomenon level work, I have two problems with the walkie-talkie technique:
c.␣ general grounding/shielding approaches for equipment (1) you will get many unkind remarks from the guy on the next
d.␣ “fix” type approaches to minimizing the effects when items bench over if he’s trying to breadboard a low-level circuit and is not
from (c) can’t be implemented ready for EMI testing yet; and (2) if you start attaching leads to
e. bench-level testing techniques. various points in the circuit to determine where the problems are,
and then apply RF in a radiated fashion, you have so many antennae,
(At least I’m not aware of any such application note in existence;
both to your circuit and to the various test gear, that you will have
maybe one exists and I haven’t found it.) Based on my own no idea what is happening.
experience, I offer the following comments on the above five areas:
I prefer to use an RF signal generator and apply the interference in
Regarding (a), I generally see the problem with low-level input or a conducted fashion. This allows much better control of which items
preamp circuits involving a voltage gain of 50␣ V/V or more. In my get RF applied to them. I don’t use a lot of RF power, as I usually
case, the signals are usually from thermocouples, RTDs, pressure connect the output of the generator directly to some connector or
sensors, etc., and the required signal bandwidth is less than 100␣ Hz. cable supplying the low-level signal of interest, or in some cases the
And I’m trying to maintain signal integrity suitable for conversion body of a sensor. A few hundred millivolts of RF signal is generally
by a 10-to-14-bit A/D converter. sufficient to identify problem circuits. I manually sweep from about
For (b), my “model” of the effect is that the error gets created by 10␣ MHz to 100␣ MHz. While this is not a quantitative type of test, it
rectification of the rf at the base-emitter junctions at the inputs of the is a very useful qualitative technique.
op amp, and essentially becomes a large input offset voltage for the Some of the RF generators I have used for this are older model
op amp. This introduces errors into dc-coupled circuits that cannot units—usually acquired at garage sales for $5 to $20 each:
be corrected for by any usual low-pass filtering of the signal.
RCA WV-50B
One observation I have made regarding this susceptibility problem Advance Schools, Inc., Model IGB-102
is that it is primarily related to bipolar-type op amps (741, 5558, Heathkit Model IG-102 (same as above)
OP05, OP07, OP27, AD708, OP220, etc.) If I swap to a FET- Precise Model 630
input op amp (TL082, TL032, OP80, OP42, AD845) the error
I hope this may be useful, and, as I mentioned would like to see a
will largely disappear. (Due to other considerations, this is not usually
good application note put together on this subject by someone who
a permanent solution, but helps to identify error sources during
can add some additional information regarding performance
EMC testing.)
implications of adding a capacitor on the op-amp inputs for various
Also involved is the RF impedance at the two input nodes of the op circuit configurations.
amp. If (in a typical inverting configuration) the feedback path has
Thanks to Mr. Cordill for a useful contribution to the Dialogue, and for
a capacitor for low-pass filtering, it aggravates the problem as one throwing down the gauntlet to our Application Engineers. They have
input node of the op amp sees more of the RF than the other. If this accepted the challenge; so keep your eyes on the “Worth Reading” page
is the situation, I’m not sure a wide-bandwidth op amp would help in future issues. Having said that, we feel obliged to point out that the
(regarding suggestions for using an AD830). Even without an challenge is to get it together in one place; much of the material he
intentional discrete capacitor in the feedback loop, PC-board layout suggests already exists in the Analog Devices literature (and elsewhere).
makes it difficult to count on matched impedances at the two inputs. For example, the System Applications Guide devotes pages 1-13 thru
1-55 to remote sensor application problems—including an exhaustive
discussion of RFI rectification in high-accuracy circuits. Other good sources
*RR 3 Box 8910, Bartlesville OK 74003. Leroy Cordill, a design engineer with
include the Applications Reference Manual, Chapter 3 and Bibliography
Applied Automation, Inc., has been involved in designing process gas
chromatographs for about 20 years. His areas of design have included system of the Transducer Interfacing Handbook, and Part 5 and Bibliography of
architecture, analog, digital, and serial communication circuits, as well as GC the Analog-Digital Conversion Handbook. b
detectors and valves.

28 Analog Dialogue 28-2 (1994)

Ask The Applications Engineer—15 Q: How do I make sure that a one-pole RC filter will suffice for my
application—and establish the time constant of the filter?
by Oli Josefsson
A: Your application will typically specify a maximum allowable
USING SIGMA-DELTA CONVERTERS—PART 1 attenuation of an input signal that falls within the bandwidth
Q: I’d like to use sigma-delta A/Ds but have some questions because of interest. This in turn puts a minimum on the 3-dB point of
they seem markedly different from what I’ve been using. To start the RC filter. Let’s take a look at an example using the ADl877
with, what issues do I need to consider when designing my to illustrate this point further and to show how one might verify
antialiasing filter? that a single-pole filter will provide enough filtering.
A: A major benefit of oversampling converters is that the filtering Let’s assume that we have an application where the bandwidth
required to prevent aliases can be quite simple. To understand of interest is 0 to 20 kHz, and signals in this range must
why this is the case and what the filter constraints are, let’s not be attenuated more than 0.1 dB, or a ratio of 0.9886
look at the basic digital signal processing that takes place in [dB = 20 log10 (ratio) for voltage and 10 log10 (ratio) for power].
such a converter. For the purpose of anti-alias filter design we From the formula for attenuation of a single-pole filter,
can think of a sigma-delta converter as a conventional high-
resolution converter, sampling at a rate much faster than the 1
ratio = > 0.99 at f = 20 kHz
( )
Nyquist sampling rate, followed by a digital decimator/filter; 2
1+ 2π fRC
the fact that the input into the digital decimator is 1-bit serial
with a noise-shaping transfer function is irrelevant.
( )
2
The input signal is sampled at Fms, the modulator input 1− ratio
RC ≤ ≈ 1.21×10 –6 s
(2π f ) (ratio )
2 2
sampling rate, which is much faster than twice the maximum
input signal frequency (the Nyquist rate). The figure shows
what the frequency response of a decimation filter may look Choosing RC = 1.0 µs, to allow for component tolerances, the
like; frequency components between fb and Fms–fb are greatly –3-dB frequency will be 159 kHz. We can now calculate the
attenuated. Thus, the digital filter can be used to filter out all attenuation the filter will provide in the frequency bands,
energy from the converter within [0, Fms–fb] that does not fall kFms± fb, that alias down to the baseband. Assuming that the
within the bandwidth of interest [0, fb]. However, the converter AD1877 has a modulator sampling rate of 3.072 MHz (and
can not distinguish between signals appearing at the input that output sampling rate of 48 kHz), the first frequency band
are in the range [0,± fb] and those in the ranges, [kFms± fb], where occurs at 3.052 MHz to 3.092 MHz. The attenuation of
k is an integer. Any signals (or noise) in those ranges get aliased the RC filter at these frequencies is approximately 25.7 dB
down to the bandwidth of interest [0,fb] via the sampling (about 0.052) over the whole band. Over the second band
process; the decimation filter, which works only on the digitized (6.124 MHz to 6.164 MHz), the attenuation is 31.8 dB
samples, cannot be of any help attenuating these signals. (0.026). We know that the noise in these two bands (and all
higher bands up the scale) that escapes through the filter to
the A/D input will be aliased down to the baseband and get
REPEATS AT INTEGER added as root sum-of-the-squares (rss) of their rms values,
MULTIPLES OF Fms
MAGNITUDE – dB

i.e., n12 + n22 + . . . + ni 2 . For values given in dB, the formulas

shown the Appendix can provide results directly in dB, avoiding
the intermediate step of computing the ratios.
For white noise, the noise spectral density is constant as a
function of frequency, and each frequency range has the same
bandwidth, so each band contributes an equal amount of noise
0 fb Fms Fms – fb Fms f to the input of the filter. We can therefore find the effective
2 attenuation of the RC filter by adding the attenuation of the
different frequency bands in rss fashion. The noise contribution
Thus it is the input noise energy in these bands [kFms± fb] that
from the first two bands, for example, is the same as the
must be removed by the antialiasing filter before the input signal
contribution from a single frequency band with attenuation of
is sampled by the converter.
Q: So if I were to use the AD1877, which has a dynamic range of 0.052 2 + 0.026 2 = 0.058, or 24.7 dB, compared with
90 dB, the antialiasing filter will need attenuation well above 90 dB 25.7 dB for the first band. How many bands do we need to
at Fms – fb (≈ 3 MHz)? consider when calculating the total aliased noise? For this case,
A: Not quite. You are assuming that the A/D has full-scale input the rss sums of the first 3, 4, 5, and 6 bands are, respectively,
at frequencies close to the modulator sampling rate; this is –24.2, –24.0, –23.9, –23.8 dB. The first band is therefore quite
simply not the case in most systems. The only signal input of dominant; its attenuation is within 2 dB of the attenuation for
concern for aliasing is normally just noise from sensors and all bands. It is usually sufficient to take only the first band into
circuitry preceding the converter. The noise is usually low account unless the noise is exceptionally large or has a
enough for a simple RC filter to suffice as an antialias filter. non-white spectrum; in addition, the A/D itself, though fast,
has limited bandwidth; it tends to reject high-order bands.

Analog Dialogue 28-1 (1994) 29

Ask The Applications Engineer – 15

Now that the attenuation is in hand, we can consider the noise MODULATOR
magnitude itself: Let’s be conservative (by about 50%) and OUTPUT
SPECTRUM

MAGNITUDE – dB
take the effective filter attenuation to be 20 dB (i.e., 0.1 V/V).
To be able to calculate the maximum allowed noise spectral INPUT SHAPED QUANTIZATION
density when using a single pole filter, an estimate should be SIGNAL NOISE
SPECTRUM
made of the maximum performance degradation that aliased
noise can contribute. From the dynamic specs of the AD1877
we find that the total noise power internal to the converter is
90 dB below (32 ppm of) full-scale input. If the whole system 0 fi fb Fms Fms – fb Fms – fi Fms f
is to be within, say, 0.5 dB of this spec, the total aliased noise 2
power can’t exceed the rss difference between –90 dB and
–89.5 dB or –99.1 dB (11.1 × 10–6). Using this information, As shown, the spectral “sticks” (single frequencies) at fi and
and the fact that the input scale of the AD1877 is 3 V p-p, we Fms – fi correspond to an input signal, while the shaded area
find that aliased noise must not exceed 3/(2√2) V × 11.1 × 10–6 shows how the quantization noise has been pushed (shaped)
= 11.8 µV rms. If all this noise were assumed lumped in a single beyond the bandwidth of interest, fb.
aliased band, and noting that rms noise = noise spectral density The digital filter, which is often an n-tap FIR filter, takes the
(N.S.D.) × √BW, high-speed low-resolution (1-bit) modulator output and
11.8 µ V performs a weighted average of n modulator outputs in a
N.S.D. < = 59 nV / Hz manner dictated by the desired filter characteristics. The output
3.092 MHz– 3.052 MHz
of the filter is a high-resolution word, which becomes the A/D
This is the maximum post-filter spectral density allowed. To output. The digital filter is designed to filter out “everything”
find the maximum prefilter spectral density (MPSD), with the between fb and Fms–fb, where Fms is the sampling rate of the
effective filter attenuation of 20 dB (i.e., × 0.1) established modulator. Cleaning out all the noise in between fb and Fms–fb
previously, M.P.S.D. = 10 × 59 nV/√Hz = 0.59 µV/√Hz. makes it possible to reduce the sampling rate to values between
Clearly your system has to be pretty noisy in the 3-6-9-12-MHz Fms and 2fb without causing any spectra to overlap (i.e., aliasing).
regions in order for a simple RC filter not to suffice; however, Conceptually, reducing the sample rate, i.e., decimation, can
as always, one must be careful of ambient rf pickup. be thought of as only sending every dth digital filter output to
Q: As I understand it, the noise floor of sigma-delta converters may the A/D output, where d is the decimation factor. This will
exhibit some irregularities. Any thoughts on that? bring the spectral images close together, as shown in the figure,
which makes the output look like an output from a non
A: Most sigma-delta converters exhibit some spikes in the noise
oversampled converter. The upper figure shows the output of
floor, called idle tones. In general, these spikes have low energy,
the modulator after digital filtering but prior to decimation.
not enough to substantially affect the S/N of the converter.
The lower figure shows the spectral output after decimation—
Despite that, however, many applications cannot tolerate spikes
the final A/D output.
in the frequency spectrum that extend much beyond the white
noise floor. In audio applications, the human ear, for example, In real converters, digital filtering and decimation are intimately
does an excellent job of detecting tones in the absence of large combined for economy in design and manufacture. Thus, the
input signals even though the tones are well below the terms “digital filter” and “decimator” are used interchangeably
integrated (0-20-kHz) noise of the system. to describe the digital circuitry processing the modulator output
to produce the output of the converter.
There are two sources of idle tones. Their most common cause
is voltage-reference modulation.To understand this mechanism
a basic understanding of sigma-delta converters is needed. Here DIGITAL FILTER OUTPUT
MAGNITUDE

is a one minute crash course on sigma-delta converters (to BEFORE DECIMATION

probe further please consult[1]).
As the block diagram shows, a basic sigma-delta A/D converter
consists of an oversampling modulator, followed by a digital Fi Fb Fms Fms – Fi Fms f
filter and a decimator. The modulator output swings between 2

two states (high and low, or 0 and 1, or +1 and –1), and the
MAGNITUDE

average output is proportional to the magnitude of the input

signal. Since the modulator output always swings full-scale FINAL CONVERTER OUTPUT
(1 bit), it will have large quantization errors. The modulator,
however, is constructed so as to confine most of the
quantization noise to the portion of the spectrum beyond fb, Fi Fs Fs– Fi Fs f
the bandwidth of interest. F ms
2
MODULATOR

+
INTEGRATION COMPARATOR O.K., now back to “idle tones”. Let’s start by looking at the
ANALOG ∑
INPUT
–
1/s DIGITAL
FILTERING
output of the modulator when a dc signal is applied to the input.
1-BIT AND n-BIT DIGITAL
AT F ms DECIMATION OUTPUT For an exact mid-scale dc input level, the output of the mod-
1-BIT AT F s << F ms
± V REF DAC ulator is equally likely to be high (1) or low (0), in other words,

30 Analog Dialogue 28-1 (1994)

 Ask The Applications Engineer – 15

the pulse density is 0.5, very likely to result in bitstream patterns Q: So what can I do to minimize the chances of idle tones interfering
like 010101. These regular patterns mean that the output spec- with my A/D conversion?
trum will have a spike at Fms/2 (upper figure). If the dc input A: Follow the layout recommendations and bypassing schemes
now moves somewhat off midscale, the modulator output bit recommended by the manufacturer of the converter. This
pattern will change accordingly. The spectrum of the modulator applies not only to the voltage reference, but to power supplies
output will now show spikes at Fms/2– ∂F and Fms/2 + ∂F, with and grounding as well. It is the manufacturer’s responsibility
∂F proportional to the dc change from midscale (lower figure). to minimize the voltage-reference corruption that takes place
inside the converter, but it is up to the system designer to
minimize the external coupling. By following those guidelines,
CONCENTRATION OF the user should be able to reduce the coupling to a negligible
MAGNITUDE

ENERGY AT Fms /2
level. If, despite the proper design precautions, idle tones are
still an issue, there is yet another option that can be pursued.
As I explained previously, frequency of the idle tones is a
function of the dc input. This opens up the possibility of
introducing enough dc offset on the A/D input to move the
Fms Fms f idle tones out of the bandwidth of interest to where they will
2 be filtered out by the decimation filter. If the user does not
want the dc offset to propagate through the system it can be
Fms
– ∂f
subtracted out by the processor that handles the data from the
2 A/D.
MAGNITUDE

Fms
+ ∂f
2
Q: What kind of a load does the input of sigma-delta converters present
to my signal conditioning circuitry?
A: It depends on the converter. Some sigma-delta converters have
a buffer at the input, in which case the input impedance is very
Fms Fms f high and loading is negligible. But in many cases the input is
2 connected directly to the modulator of the converter. A
With effective digital filtering, how can such tones possibly switched-capacitor sigma-delta modulator will have a simplified
find their way down to baseband? The answer is via the voltage equivalent circuit like that shown in the figure.
reference. The digital output is a measure of the ratio of the
S1 S2
analog input to the voltage reference. An x% change in the
magnitude of the voltage reference will result in a –x% change
C
in the magnitude of the digital output word. Voltage-reference
change will, in effect, amplitude modulate the A/D output. Now,
we have clocks internal to the converter, and possibly also Switches S1 and S2 are controlled by the two phases of a clock
externally, running at Fms/2. If small amounts of these clock to produce alternating closures. While S1 is closed, the input
pulses get coupled onto the voltage reference line, they will capacitor samples the input voltage. When S1 is opened, S2 is
change it slightly and, in effect, modulate the tones at Fms/2 – ∂F closed and the charge on C is dumped into the integrator,
and Fms/2 + ∂F. One of the difference frequencies created by this thus discharging the capacitor. The input impedance can be
modulation is at ∂F, and it is clearly in the bandwidth of interest. computed by calculating the average charge that gets drawn
Nonlinearities may also create tones at multiples of ∂F. by C from the external circuitry. It can be shown that if C is
Q: From your explanation it seems that if I apply an ac signal to the allowed to fully charge up to the input voltage before S1 is
converter I do not have to worry about idle tones? opened then the average current into the input is the same as
if there were a resistor of 1/(FswC) ohms connected between
A: Well, any ac signal generally has a dc component associated the input and ground, where Fsw is the rate at which the input
with it, which will have to be represented by the modulator capacitor is sampling the input voltage. F sw is directly
output, so the explanation above still applies. But if the total proportional to the frequency of the clock applied to the
dc input offset (i.e., internal converter offset plus external converter. This means that the input impedance is inversely
offsets) in your system is exactly 0, the tones will be at dc (0 Hz). proportional to the converter output sample rate.
There is another source of idle tones in lower-order (<3rd- Sometimes other factors, such as gain, can influence the input
order) modulators. The order of the modulator (number of impedance. This is the case for the 16/24-bit AD771x family
integrations) is a measure of how much quantization-noise of signal conditioning A/Ds. The inputs of these converters
shaping takes place. Second-order modulators can actually can be programmed for gains of 1 to 128 V/V. The gain is
exhibit bit patterns that show up directly in the baseband, even adjusted using a patented technique that effectively increases
if voltage-reference modulation is not occurring. This is one of Fsw (but keeps the converter output sample rate constant) and
the reasons why sigma-delta converters from Analog Devices combines the charges from multiple samples. The input
that are designed for ac applications use higher-order (≥3) impedance of these converters is, for example, 2.3 MΩ when
sigma-delta modulators. the device’s external clock is 10 MHz and the input gain is 1.
With input gain of 8, the input impedance is reduced to 288 kΩ.

Analog Dialogue 28-1 (1994) 31

Ask The Applications Engineer – 15

These impedances, as noted earlier, represent the average For converters that have a differential input, a differential
current flow into or out of the converters. However, they are version of this circuit may be used, as shown in the figure below.
not the impedances to consider when determining the Since one input is positive with respect to ground while the
maximum allowable output impedance of the A/D driver other is negative, one input (the negative one) needs to be
circuitry. Instead, one needs to consider the charging time of supplied negative charge while the other needs to get rid of
the capacitor, C, when S1 is closed. For dc applications the negative charge when the input capacitors are switched on line.
driver circuit impedance has only to be low enough so that the Connecting a capacitor between the two inputs enables most
capacitor, C, will be charged to a value within the required of the charge that is needed by one input to be effectively
accuracy before S1 is opened.The impedance will be a function supplied by the other input. This minimizes undesirable charge
of how long S1 is closed (proportional to the sampling rate), transfers to and from the analog ground.
the capacitance, C and CEXT in parallel with the input (unless
CEXT >> C).The table shows allowable values of external series
resistance with fCLKIN = 10 MHz which will avoid gain error of
1 LSB of 20 bits—for various values of gain and external
capacitance on the AD7710. VIN +
∆∑ A/D CONVERTER
DIFFERENTIAL WITH A DIFFERENTIAL
Typical external series resistance which will not INPUT SWITCHED CAPACITOR
INPUT
introduce 20-bit gain error VIN –

External Capacitance (pF)

Gain 0 50 100 100 500 5000
1 145 kΩ 34.5 kΩ 20.4 kΩ 5.2 kΩ 2.8 kΩ 700 Ω
To be continued. Topics to be covered in the next installment include
2 70.5 kΩ 16.9 kΩ 10 kΩ 2.5 kΩ 1.4 kΩ 350 Ω
multiplexing, clock signals, noise, dither, averaging, spec clarifications
4 31.8 kΩ 8.0 kΩ 4.8 kΩ 1.2 kΩ 670 Ω 170 Ω
8-128 13.4 kΩ 3.6 kΩ 2.2 kΩ 550 Ω 300 Ω 80 Ω
APPENDIX
RSS addition of logarithmic quantities: The root-sum square
For ac applications, such as audio, where the modulator sample
rate is around 3 MHz for 64× oversampling, the input capacitor of two rms signals, S1 and S2, has an rms value of S12 + S22 .
voltage may not have enough time to settle within the accuracy One often needs to calculate the rss sum of two numbers that are
indicated by the resolution of the converter before the capacitor expressed in dB relative a given reference. To do this one has to
is switched to discharging. It actually turns out that as long as take the antilogs, perform the rss addition, then convert the result
the input capacitor charging follows the exponential curve of back to dB. These three operations can be combined into one
RC circuits, only the gain accuracy suffers if the input capacitor convenient formula: If D1 and D2 are ratios expressed in dB
is switched away too early. [negative or positive] their sum, expressed in dB, is

The requirement of exponential charging means that an op 10 log10 10D1/10 + 10D2/10

amp can not drive the switched capacitor input directly. When
a capacitive load is switched onto the output of an op amp, the Similarly, to find the difference between two rms quantities,
amplitude will momentarily drop. The op amp will try to correct x = S22 – S12
the situation and in the process hits its slew rate limit (non
the result, x, expressed in dB, is
linear response), which can cause the output to ring excessively.
To remedy the situation, an RC filter with a short time constant 10 log10 10D2/10 – 10D1/10 b
can be interposed between the amplifier and the A/D input as
shown in the figure. The (low) resistance isolates the amplifier References (not available from Analog Devices):
1
from the switched capacitor, and the capacitance between the Oversampling Delta-Sigma Data Converters—Theory, Design, and
input and ground supplies or sinks most of the charge needed Simulation, edited by J.C. Candy and G.C. Temes, IEEE Press,
to charge up the switched capacitor. This ensures that the op Piscataway, NJ, 1991.
amp will never see the transient nature of the load. This 2
J. Vanderkooy and S.P. Lipshitz, “Resolution Below the Least
additional filter can also provide antialiasing. Significant Bit in Digital Systems with Dither,” J. Audio Eng.
Soc., vol. 32, pp. 106-113 (1984 Mar.); correction ibid., p.889
∑∆ ADC (1984 Nov.).
AMPLIFIER
3
A.H. Bowker and G.J. Lieberman, Engineering Statistics, Prentice
VIN
Hall, Englewood Cliffs, NJ, 1972.

32 Analog Dialogue 28-1 (1994)

Ask The Applications Engineer—16 the new data. The AD1879, for example, an 18-bit audio A/D
converter, has a 4096-tap FIR filter which, when running at
by Oli Josefsson 3.072␣ MHz, has a 1.33-ms settling time.

USING SIGMA-DELTA CONVERTERS—PART 2 X [n] Z

–1
Z
–1
Z –1 Z –1

This is a continuation of a discussion of sigma-delta converters begun in

a4
the last issue.We covered antialiasing requirements, idle tones, and loading a2
a3
a1 ak
on the signal source.
Q:␣ What happens if my input signal is beyond the input range of the
sigma-delta converter? I remember hearing something about the
∑ y [n]
converter becoming unstable?
y(n) = a1 x(n) + a2 x(n–1) + a3 x(n–2) +... + ak x(n–k+1)
A:␣ The modulator can become temporarily unstable if it is driven
with inputs outside the recommended range. However, this
instability is invisible to the user, since decimators are generally The effective sampling rate for sigma-delta converters in
designed to simply clip the digital output and show either multiplexed applications is quite low because of this need to
negative or positive full scale, just as one would expect with a wait for the old signal to be flushed out before capturing a
conventional converter. valid data point for the new input.Traditional converters, which
convert directly, or in a small number of stages, are therefore a
Q:␣ The specifications for sigma-delta converters assume a certain input
much better choice in applications requiring the capture of
clock rate and therefore a specific sampling rate. Can I safely use
multiple ac channels.
the converter with a higher or lower clock frequency?
For a multichannel dc application where time is available to
A:␣ While the specs are measured at a particular sampling frequency,
wait after switching between channels, or if the application
we often specify a range of input clock frequencies that the
does not require frequent changes between channels, the use
device can be operated with. This translates into a range of
of a sigma-delta converter can be very feasible. In fact, Analog
possible sampling rates. If you plan to go much beyond that
Devices offers 16-24-bit converters with multiplexers on the
range you can expect some performance degradation. If you
input (AD771x family) specifically for such applications.
sample at higher rates than specified, the internal switched-
capacitor circuits may not be able to settle to the required Q: Does this also explain why sigma-delta converters are not suitable
accuracy before a new clock edge comes along. With too slow for some control applications?
a sampling rate, capacitor leakage will degrade performance. A:␣ Yes. Since delays in control loops must be minimized for
The digital filter characteristics of the converter (group delay, stability, sigma-delta converters are not suitable for control
cutoff frequency, etc.) scale with sampling rate; so too do the applications where they add a relatively long time delay.
input impedance (unless the input is buffered) and power However, the actual delay is predictable; in applications that
consumption. involve relatively slow signals, the converter phase delay, and
therefore the effect on pole and zero locations of the control
Q:␣ I am planning to use a sigma-delta converter to digitize several signals
loop, may be negligible. However, even if this is the case, a
by using a multiplexer at the input of the converter. Is that a problem?
traditional non-oversampling converter may still be a much
A:␣ While sigma-delta converters have a certain appeal due to their better choice for the application, because a sigma-delta
ease of antialiasing, they do not lend themselves well to converter would need to run at a much faster sampling rate
applications for multiplexed ac signals. The reason for this is than a traditional converter in order to have the same phase
that the output of a sigma-delta converter is a function not delay. This will unnecessarily burden the circuitry that
only of the latest analog input but also of previous inputs. This processes the A/D data.
is mostly due to the memory that the digital filter has of previous
Q: Are there any other issues I should be aware of when using sigma-
inputs, but the modulator has some memory as well. In a
delta converters?
multiplexing application, after switching from one input to
another, all information the filter has about the old input needs A:␣ In addition to the general guidelines on grounding, power supply
to be flushed out before the converter output word represents bypassing, etc., that apply to all converters, there are a couple
the new input. of points worth remembering when designing with sigma-delta
converters. The first issue involves their input. As mentioned
Most decimation filters in sigma-delta converters intended for
earlier, some sigma-delta converters (such as the AD1877) have
ac applications are FIR filters, principally because of their linear
buffers on the input; others (such as the AD1879), without a
phase-response. For FIR filters, it is easy to calculate the time
buffer, present a switched-capacitor load, which needs periodic
it takes to rid the filter of any information about the old input.
current transients to charge the input capacitor. It is important
The figure shows the structure of a FIR filter; the number of
that the circuitry driving the converter be as close to the
clock cycles required to clock all old data points out (i.e., the
converter as possible to minimize the inductance in the leads
filter settling time) is equal to k, the number of taps in the
between the external circuitry and the switched-capacitor node.
filter. While data corresponding to a new input is propagating
This reduces the settling time of the input and minimizes
through the filter and replacing the earlier data, the output of
radiation from the input to other parts of the circuit board.
the filter is calculated from a combination of the old data and

Analog Dialogue 28-2 (1994) 33

Ask The Applications Engineer – 16

Another issue has to do with interference from clock signals If Nrms is the rms value of the converter noise and VLSB is the
affecting the A/D conversion. As I noted earlier, the digital size of the LSB in volts (=␣ Vspan/2b, where b is the number of
decimation filter can’t provide any filtering of signals whose bits in the output word) the peak to peak noise in terms of
frequencies are close to multiples of the modulator sampling LSBs, NB, is
rate. To be precise, the passbands are [kFms ± fb]s where k is an
6 × Nrms 6 × 2b × Nrms
integer, Fms is the modulator sampling rate, and fb is the NB = =
VLSB Vspan
decimator cutoff frequency.
Besides the consequences for anti-aliasing discussed earlier, If the signal-to-noise ratio of a converter expresses noise power
the decimator cutoff frequencies have a bearing on the selection relative to full scale, rms signal V span / (2 2) , we have
of clock frequencies for devices that operate in the same system
as the converter. These frequency bands (i.e., the passbands) NB = 3 × 2b × 10–SNR/20
embody the converter’s greatest vulnerability to interference 2
(inductive or capacitive coupling, power supply noise, etc.), How many codes show up at the output depends where the
because any signals in these frequency bands that manage to mean of the input, i.e., the dc input value, is with respect to
get into the modulator will not be subjected to attenuation in code transitions. If the mean is close to the boundary between
the filter. Therefore one is wise to avoid using clock frequencies two output codes, more codes are likely to appear than if the
that fall in these bands to minimize the possibility of interfering mean is half way between two output codes. It can easily be
with the conversion—unless they are synchronous with the shown that NC, the number of codes appearing for a particular
converter clock. value of NB, is either INT(NB)+1 or INT(NB)+2, depending
on the dc input value [INT(NB) is the integer portion of NB].
QUESTIONS ON NOISE IN CONVERTERS And don’t be surprised to see even more codes from the less-
Q:␣ I recently evaluated a dual-supply A/D converter; one of the tests I probable noise amplitudes >± 3␣ standard deviations.
did was to ground the input and look at the output codes on a LED How many bits will NC cause to toggle on the output? The
register. To my big surprise I got a range of output codes instead of a number of bits needed to represent NC codes is
single code output as I expected?
log NC
A:␣ The cause is circuit noise. When the dc input is at the transition INT + 0.5
log 2
between two output codes, just a little circuit noise in even the
finest dc converters will ensure that two codes will appear at We can, however, see many more bits toggle, since the number
the output. This is a fact of life in the converter world. In many of bits toggling is a function of the actual value of the converter’s
instances, as in your case, the internal noise may be large dc input. Consider, for example, that a one-code transition
enough to cause several output codes to appear. Consider, for from an output word of –1 to 0 on a 2s-complement-coded
example, a converter with peak-to-peak noise of just over converter involves inverting all the output bits.
2␣ LSB. When the input of this converter is grounded, or a Lets look at an example using the AD1879, an 18-bit sigma-
clean dc source is connected to the input, we will always see delta converter with dynamic range of 103␣ dB. From the
three—and sometimes even four—codes appear at the output. definition of dynamic range we have
The circuit noise prevents the voltage being sampled from being
confined to a voltage bin that corresponds to one digital code. 103 = 20 log S
Nrms
Any external noise on the A/D input (including a noisy signal),
From the AD1879 data sheet, we find that the rms value of a
on the power supplies, or on the control lines will add to the
full-scale input signal, S, is 6/√2␣ V rms. This allows us to solve
internal circuit noise—and possibly result in more bits toggling.
for Nrms which turns out to be 30␣ µV. We next find the LSB
Q: Is there a way to determine how many codes I can expect to appear size by dividing the full input range by the number of possible
when I apply a dc signal to a converter? output codes:
A: It would not be hard in the ideal case where you knew the VLSB = 12 = 45.8 µV
noise distribution, the exact size of the codes where the dc 218
input is at and where within a code quantum the input lies (in Thus NB is 3.9. We can therefore expect either 4 or 5 different
the center, on the edge of two codes, etc.). But in reality you codes to appear at the AD1879 output when the input is
don’t have this information. However, knowing some of the ac grounded (ground corresponds to a midscale input for the
specifications (S/N, dynamic range, etc.) of the converter, you AD1879).
can make an estimate. From these specs you can find the
magnitude of the rms converter noise relative to full scale. The
noise will in all likelihood have a Gaussian amplitude
PROBABILITY

distribution, so the standard deviation (sd) of the distribution

equals the rms value. This also means that the codes that appear
will not have equal probability of occurring. Using the fact
that 99.7% of a Gaussian distribution occurs within ± 3 VDC
standard deviations from the mean, we can estimate the peak-
n n+1 n+2 n+3 n+4 n+5 n+6
to-peak noise voltage at six times the standard deviation. INPUT

34 Analog Dialogue 28-2 (1994)

 Ask The Applications Engineer – 16

One can take this estimation one step further: If the standard actual applied dc input is slightly above the border between
deviation (the rms value) of a Gaussian distribution and the the two codes, whereas the calculations assume it is exactly on
mean (the mean of the noise is 0 in this case) are known, one the border.
can use standard tables for the Gaussian distribution to The biggest weakness of this estimating technique is the fact
calculate what percent of the time the noise will fall into a that in conventional converters the code width (the amount
voltage interval corresponding to a specific output code. A the dc input has to be increased to increase the digital output
histogram can be estimated, showing the distribution of codes by one bit) varies from code to code. This means that if the dc
at the output. Also the process can be reversed: a histogram input is in an area where codes are narrow, we can expect more
showing the distribution of noise codes at a given value of dc bits to be toggling than in an area where the codes are wide.
output permits one to estimate the S/N ratio for a converter. This method also assumes that the circuit noise within the
To make all this real, let’s continue our example involving the converter stays constant, whether the applied signal is ac or
AD1879. Consider two cases, one where the input lies midway dc. This is not exactly true in many cases.
between two output codes and one when the input is on the The estimate will probably be more accurate when used with
transition between two codes. From the calculations above, sigma-delta converters (except for “dead bands”), because
we found that the standard deviation (sd) of the noise (the neither of the two factors mentioned above is an issue in such
rms value) was 30␣ µV. The size of one LSB in terms of sd is converters.
45.78 µV Q: Ah, now I understand why there are multiple codes at the output.
= 1.524
30.0 µV But why not discard the bits that toggle and only bring out the bits
that stay steady, since the others are really indeterminate? Isn’t that
In the case where the dc input is midway between code
the real resolution of the converter?
transitions, as shown below, it is clear that any noise that falls
within –0.5␣ LSBs to +0.5␣ LSBs from the input will result in A: Many converters are designed for ac or dynamic applications
the correct code at the A/D output. This corresponds to the where THD (total harmonic distortion) and THD+N (total
noise being confined to a range of (–0.5␣ ×␣ 1.524)␣ sd to harmonic distortion+noise) are the most important specs. The
(+0.5␣ ×␣ 1.524)␣ sd from its mean (0). From standard tables one design therefore focuses on minimizing harmonic distortion
can find that the noise will fall in this range 55.4% of the time. for high- and low-level input signals, while keeping the noise
If the noise falls within 0.5␣ LSBs to 1.5␣ LSBs, the output will to acceptable levels. As it turns out, these requirements
be one code too high. Again from standard tables one can find somewhat contradict the requirements for a good dc converter,
that this will occur 21.2% of the time. Continuing in this which is optimized for precision conversion of slow moving
manner one can calculate the whole histogram showing the signals where harmonic distortion is not an issue. It is actually
distribution of output codes. desirable to have some noise (called dither) superimposed on
57.4% the input signal to minimize distortion at very low input signal
(55.4%)
600 levels; dither can also be used to improve dc accuracy where
NUMBER OF INSTANTS

500 repeated measurements can be made.

400
To understand how this may be, let’s start by looking at
300 20.3% 20.7%
(21.2%) (21.2%) quantization noise. The output of an ideal A/D converter has
200
finite accuracy because of the finite number of bits available to
100 0.7% 0.9%
(1.1%) (1.1%) represent the input voltage. Each one of the 2b quanta
0
–28 –27 –26 –25
OUTPUT CODE
–24 –23 –22 represents with one single value all values in the analog range
from –0.5␣ LSB to +0.5␣ LSB of its nominal input value. The
500
43.9% 46.0%
(43.6%)
A/D output can therefore be thought of as a discrete version of
(43.6%)
NUMBER OF INSTANTS

the analog input plus an error signal (quantization noise).When

400
a large and varying input signal (dozens, hundreds, or
300
thousands of LSBs in amplitude) is applied to a converter, the
200
quantization noise has very little correlation with the input
4.4% 5.6%
100 (6.4%) (6.4%) 0.1% signal. It is, in other words, approximately white noise. The
(0%)
0
–26 –25 –24 –23 –22 –21 –20
figure shows the quantization noise of a perfect A/D converter
OUTPUT CODE at various instants of time when the input signal is a sinusoid
The upper figure shows an actual measurement where the dc of about 100␣ LSBs in amplitude.
0.5
input happened to be –25␣ LSBs. Five output codes, ranging
0.4
from –27 to –23, appeared. 1024 measurements were taken 0.3
and the percentage distribution of each code is shown on top 0.2
ERROR IN LSBs

of each column. The calculated distribution is listed in brackets 0.1

on top of each column. As can be seen, the experimental results 0

agree well with the calculated values. The lower figure shows –0.1
–0.2
a case where the dc input is close to the boundary between
–0.3
two codes. By following a similar procedure, one can calculate
–0.4
how the histogram should look. Again the experimental and –0.5
calculated values are in excellent agreement. Note that the

Analog Dialogue 28-2 (1994) 35

Ask The Applications Engineer – 16

When the A/D input is very low in amplitude, so that the signal is often about 1/3␣ LSB rms (2␣ LSBs peak-to-peak if the
amplitude does not change more than a fraction of a LSB noise is Gaussian). Clearly, this will result in a converter that
between samples, the samples stay in the same quantum, and will have more than two codes at the output when the input is
are therefore constant for a few sample periods. This is depicted grounded. We saw an example earlier involving the AD1879
in the figure below, which shows a sinusoidal input signal that which had either four or five codes appear on the output
has an amplitude of only 1.5␣ LSBs, the A/D output and the depending on the dc input level.
quantization noise. Note that the quantization error follows The figure below shows the simulated output of an A/D
the input waveform exactly while the samples are staying converter with an undithered low level input signal. The
constant. The longer the samples stay constant, the more the quantization noise is a function of the input signal magnitude
quantization noise looks like the input waveform, i.e., the at the sample instant.This correlation between the quantization
correlation between the input signal and the quantization noise noise and the input signal shows up as a cluster of harmonically
increases. While the rms of the quantization error may not have related sticks in the A/D output spectrum. Note that the
changed, the quantization error will take on a non-uniform magnitude scale in the figure is referenced to the input signal
spectral shape. In fact, the correlated quantization noise shows (not full scale input).
up as harmonics in the A/D spectrum. 0

1.5 –5

–10
INPUT VOLTAGE IN LSBs

1.0
–15

0.5 –20

–25
0
–30

–0.5 –35

–40
–1.0
–45
–1.5 –50

1.5 –55

–60
1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0.5 The right-hand figure shows the A/D output after a dither signal
OUTPUT CODE

0
that is 4␣ dB above the quantization noise floor is added to the
input. In this case the quantization noise depends on the
–0.5
magnitude of the dither signal at the instant when a sample is
–1.0 taken. Since the value of the dither doesn’t depend on the input
–1.5
signal, the quantization noise becomes uncorrelated to the input
1.5 and the harmonics in the A/D spectrum are eliminated, but at
INPUT SIGNAL
the cost of an overall increase in the noise floor.
1.0
QUANTIZATION Instead of actually adding noise to the A/D input, dithering
0.5 ERROR
can be accomplished by using the thermal noise of the converter
LSBs

0 as the dither signal and calculating enough output bits to ensure

–0.5 a decorrelated quantization noise.
–1.0 Though I have used A/D converters in my examples, the idea
of using dither also applies to D/A converters as well. Dither is
–1.5
applied to D/A converters by adding the output of a digital
noise generator to the digital word sent to the D/A.
Another way to look at this phenomenon is to consider the
case when the (sinusoidal) input signal is only around 1␣ LSB Q: But in dc applications, I want to make an accurate measurement
in size and the digital output resembles a square wave. Square each time and may not be able to tolerate the uncertainty of having
waves are rich in harmonics! The harmonics, or noise a few LSBs of error in a particular measurement.
modulation products, are very objectionable in many converter A: If you need n-bit dc accuracy in each conversion and you have
applications, especially audio. problems finding a suitable n-bit converter, you have two
To get around this problem, a technique called dithering is options. One is to use an (n+2)-bit converter and simply ignore
used to trade correlated quantization noise for white noise, the two LSBs. However, if your hardware has the capability
which is less offensive to the human ear than correlated noise. (and time) to do some signal processing, you can enhance the
Dithering is done by using circuit elements to add random resolution of a noisy (dithered) dc converter and, in fact, get
noise to the input signal. While this will result in an increase of more than n-bit accuracy out of an n-bit converter if the
the total converter noise, the added noise breaks up the simple accuracy is limited by noise.
square wave patterns in the output code.The quantization error To understand why this may be so, think of an ideal n-bit
will not be a function of the input signal but of the instantaneous converter. For a particular value of dc input, you will get one
value of the dither noise. Thus the dither decorrelates the digital code at the output. However, you do not know where
quantization noise and the input signal. The size of the dither the input lies within the code quantum (i.e., in the middle,

36 Analog Dialogue 28-2 (1994)

 Ask The Applications Engineer – 16

close to the upper transition, etc.). That may be sufficiently the actual imperfections suffices, but these can only suggest ac
accurate for your application, but if you add noise to the input performance. For example, integral nonlinearity is a major
of the converter—so that several codes can appear at the factor in determining large-signal distortion (along with glitch
output—you will find that the code distribution contains energy for D/As) while differential nonlinearity governs small-
information to place the dc value of the input more exactly. signal distortion. To accurately determine the ac performance,
In the earlier examples involving the AD1879, we saw how the at least two types of tests are performed in the case of A/Ds.
code distribution looks when the input is in the vicinity of a The tests are as follows:
code transition; the two most-frequent output codes are the a) Full-scale sine
ones on either side of the transition. Their average is therefore A sinusoidal signal approaching full-scale is applied to the
a good estimate of where the input lies. In fact, taking the converter. The signal is large enough so that converter’s
average of a lot of conversions, while the input stays put, is an imperfections cause significant harmonic components to occur
excellent way of enhancing the resolution of the converter. One at multiples of the input signal frequency. The harmonics will
has to be careful, when processing the converter output, to show up in the output spectrum, along with noise. A common
allow the output word length to grow without introducing performance measure is the relative magnitude of the harmonic
roundoff errors. Otherwise one actually injects unwanted components, usually expressed in dB. Relative to what? Two
noise—called requantization noise—into the final output. Note possibilities are the applied input signal and the full scale of
that filtering out the noise is only just that; it will have no effect the converter (which in most cases is different from the applied
on other error sources of the converter, such as integral and input signal). Referring the harmonics to full scale will clearly
differential nonlinearity. yield a lower (more attractive) number than referring them to
This concept of resolution enhancement is an interesting one the rms value of the actual input signal. This reference issue
and is not restricted to the dc domain. One can actually trade causes a lot of confusion when dynamic specifications are
resolution for bandwidth in the ac domain and combine the evaluated, because there is no universally accepted standard
outputs of several converters or to construct a more-accurate for what each performance measure should be referred to. The
output. The basic principle is that signal repetitions (which best advice I can give you is: never assume anything; read
are self-correlated) add linearly, while repetitions of random manufacturers’ data sheets very carefully.
noise produce root-square increases. Thus, a fourfold increase Sometimes the magnitudes of the individual harmonics are
in number of samples increases S/N by 6␣ dB. specified, but most often only the total harmonic distortion
Q:␣ You mentioned a couple of converter ac specifications above. I am (THD) is specified. The THD measures the total power of the
somewhat confused about how S/N, THD+N,THD, S/THD, harmonics and is found by adding the individual harmonics in
S/THD+N, and dynamic range are measured on A/D and D/A rss fashion. The formula then for THD when referred to the
converters and how they relate to each other. Can you shed any light input signal is
on this?
Σ H (i) Σ H (i)
m m
2 2
A:␣ Your confusion is quite understandable. There is unfortunately rms rms
i=2 i=2
no industry standard on exactly how these quantities are 20 log10 or 10 log10
S S2
measured and therefore, what exactly they mean. Sometimes
manufacturers are guilty of choosing the definition that portrays where H(i)rms refers to the rms value of ith harmonic component
their part favorably. and S to the rms value of the input signal. Usually, harmonics
Most often data sheets include a note on the testing conditions 2 through 5 are sufficient. Note that the input-frequency, or
and how the different specs were calculated. The best advice I fundamental, component is the first harmonic. To refer any
can give is to read these very carefully. By simple calculations harmonic to full scale, add x␣ dB to the formula above, where x
you can often convert a specification for one part to a number is the magnitude of the input signal relative to full scale. This
that allows a fair comparison to a specification for another part. simple conversion formula can be applied to other
specifications, but take care to observe proper polarity of the
Most specifications are not expressed in absolute units, but as
log quantities.
relative measurements or ratios. Noise, for example, is not
specified in rms volts, but as SNR, or the ratio between signal Nowadays, clear distinction is usually made between total
power and noise power under particular test conditions. These harmonic distortion plus noise (THD+N) and THD. This has
ratios are usually expressed in decibels, dB, and occasionally not always been the case. THD+N includes not only the
as percentages (%). A power ratio, x, expressed in bels, is harmonics that are generated in the conversion, but also the
defined as log10x; multiply by 10 if expressed in decibels (one noise. The formula for THD+N when referred to the input
tenth of a bel): 10␣ log 10 x. SNR is therefore equal to signal is:
10␣ log10␣ (signal power/noise power)␣ dB. Evaluated in terms of
Σ H (i)
m
rms voltage quantities, SNR␣ =␣ 20␣ log10(Vsignal/Vnoise). N 2rms + 2
rms
i=2
Armed with this knowledge, let’s see whether we can make 20 log10
S
sense out of the multiple specifications you mentioned above
or
(many of which are redundant). Those specifications seek to

Σ H (i)
describe how the imperfections of the converter affect the m

characteristics of an ac signal that gets processed by the N 2rms + 2

rms
i=2
converter. For dc applications, a listing of the magnitude of 10 log10 2
S

Analog Dialogue 28-2 (1994) 37

Ask The Applications Engineer – 16

where Nrms is the rms value of the integrated noise in the It’s important to note that the performance measures above
bandwidth specified for the measurement. are affected by: bandwidth of the measurement, the sampling
Another commonly used specification is signal to noise-plus- frequency, and the input signal frequency. For a fair comparison
distortion (S/[N+D], or S/[THD+N]), also called sinad. of two converters, one has to make sure that these test
This is essentially the inverse of THD+N, when referred to the conditions are similar for both.
signal; its dB number is the same, but with opposite polarity. Image Filtering Question
Another performance measure describing the test results is Q: I intend to use Analog’s AD1800 family of audio D/A converters
the signal to noise ratio, S/N or SNR, which is a measure of for a digital audio playback application. I understand that using an
the relative noise power, most useful for estimating response interpolator ahead of the D/A will make it easier to filter the
to small signals in the absence of harmonics. If S/N is not D/A output, assuming I want to get rid of all the images at the D/A
specified, but THD and THD+N are provided, relative to the output. But is it really necessary to filter the output, since all the
input signal, THD can be rss-subtracted from THD+N to obtain images will be above the audible range as long as sampling is at
the noise to signal ratio [=␣ 1/(S/N]. If the numbers are given >40␣ kHz?
in dB, the rss subtraction formula for logarithmic quantities in A: Good question. The audio equipment (audio amplifiers,
the Appendix can be used as follows equalizers, power amplifiers, etc.) that may eventually receive
the output of your D/As are typically built to handle 20-Hz to
20-kHz signals. Since they are not intended to respond at
SNR = –10 log10 10 THD+N /10 – 10THD/10 frequencies much beyond 20␣ kHz—and in effect themselves
function as filters—they may not have the necessary slew rate
to yield the input signal power relative to noise power expressed
and gain to handle incoming signals from an unfiltered D/A
in dB.
output having significant energy well above 20␣ kHz. With their
b) Low-level sine slew-rate and gain limitations, the amplifiers are driven into
The second test usually performed is to apply a sinusoidal signal nonlinear regions, generating distortion. These distortion
well below full scale to the converter (usually –60␣ dB). At this products are not limited to high frequencies but can affect the
input level, sigma-delta converters usually exhibit negligible 20-Hz to 20-kHz range as well. Attenuating the high frequency
nonlinearities, so only noise (no harmonic components) signals at the DAC will therefore reduce the possibility of
appears in the spectrum. At this level, S/N␣ =␣ S/N+D distortion. CD players often include filters steep enough to
= –THD+N␣ =␣ –THD, when all are referred to the same level. reduce the total out-of-band energy to >80␣ dB below full scale.
As a result, one specification indicating the noise level suffices APPENDIX
to describe the result of this test. This specification called RSS addition of logarithmic quantities: The root-square sum
dynamic range (inversely, dynamic-range distortion), specifies
the magnitude of the integrated noise (and harmonics if they of two rms signals, S1 and S2, has an rms value of S12+ S22 .
exist) over a specific bandwidth relative to full scale, when a One often needs to calculate the rss sum of two numbers that are
–60-dB input signal is applied to the converter. expressed in dB relative a given reference. To do this one has to
Conventional (i.e. not sigma-delta) converters can exhibit take the antilogs, perform the rss addition, then convert the result
harmonics in their output spectrum even with low-level input back to dB. These three operations can be combined into one
signals because all the codes may not have equal width convenient formula: If D1 and D2 are ratios expressed in dB, their
(differential nonlinearity). In some such instances, the S/N, sum, expressed in dB, is
which ignores harmonics, measured with a –60-dB input signal, 10 log10 10D1/10 + 10D2/10
is different from dynamic range.
Frequently one sees THD+N at –60-dB and dynamic range Similarly, to find the difference between two rms quantities,
specified for the same converter. These really are, as explained x = S22 – S12
above, redundant since they only differ in the reference used.
the result, x, expressed in dB, is
The only twist on dynamic range is that sometimes, when audio
converters are specified, a filter that mimics the frequency 10 log10 10D2/10 – 10D1/10 b
response of the human ear is applied to the converter output.
References:
This processing of the converter output is called A-weighting
[1] Oversampling Delta-Sigma Data Converters—Theory, Design, and
(because an A-weighting filter is used); it will effectively
Simulation, edited by J.C. Candy and G.C. Temes, IEEE Press,
decrease the noise floor, and therefore increase the signal-to-
Piscataway, NJ, 1991.
noise ratio, if the noise is white.
[2] J. Vanderkooy and S.P. Lipshitz, “Resolution Below the Least
Everything discussed above applies to both A/D and D/A Significant Bit in Digital Systems with Dither,” J.Audio Eng.
converters, with the possible exception of signal to noise ratio. Soc., vol. 32, pp. 106-113 (1984 Mar.); correction ibid., p.889
Sometimes (particularly for audio D/A converters) S/N is a (1984 Nov.).
measure of how “quiet” the D/A output is when zero (midscale) [3] A.H. Bowker and G.J. Lieberman, Engineering Statistics,
code is sent to the converter. Under these conditions, the S/N Prentice␣ Hall, Englewood Cliffs, NJ, 1972.
expresses the analog noise power at the D/A output relative to
full scale output.

38 Analog Dialogue 28-2 (1994)

 A.␣ That’s true, but whether to worry about it depends on the
Ask The Applications Engineer—17 application. If you have an instrumentation application that really
MUST A “16-BIT” CONVERTER BE 16-BIT MONOTONIC AND requires 16-bit resolution, 1/2-LSB accuracy for all codes, and
SETTLE TO 16␣ PPM? 1-LSB full-scale settling in 31.25 ns (we’ll get to that discussion
shortly), this isn’t the right converter. But perhaps you really
by Dave Robertson and Steve Ruscak need 16-bit dynamic range to handle fine structure over small
Q. I recently saw a data sheet for a low-cost 16-bit, 30 MSPS D/A ranges, as in the above example, while high overall accuracy is
converter. On examination, its differential nonlinearity (DNL) was not needed—and is actually a burden if cost is critical.
only at the 14 bit level, and it took 35 ns (1/28.6 MHz) to settle to What you need to consider in regard to DNL in signal-processing
0.025% (12 bits) of a full scale step. Isn’t this at best a 14 bit, 28 applications is 1) the noise power generated by the DNL errors
MHz converter? And if the converter is only 14-bit monotonic, the and 2) the types of signals that the D/A will be generating. Let’s
last two bits don’t seem very effective; why bother to keep them? consider how these might affect performance.
Can I be sure they’re even connected?
In many cases, DNL errors occur only at specific places along
A. That’s a lot of questions. Let’s take them one at a time, starting the converter’s transfer function.These errors appear as spurious
with the last one.␣ You can verify that the 15th and 16th bits are components in the converter’s output spectrum and degrade
connected by exercising them and observing that 0..00, 0..01, the signal-to-noise ratio. If the power in these spurs makes it
0..10, and 0..11 give a very nice 4-level output staircase, with impossible to distinguish the desired signal, the DNL errors are
each step of the order of 1/65,536 of full scale.␣ You can see that too large. Another way to think about it is as a ratio of the quantity
they would be especially useful in following a waveform that of good codes to bad codes (those having large DNL errors).
spent some of its time swinging between 0..00 and 0..11, or This is where the type of signal is important.
providing important detail to one swinging through a somewhat
The various applications may concentrate in differing portions of
wider range. This is the crux of the resolution spec, the ability of
the converter’s transfer function. For example, assume that the
the DAC to output 216 individual voltage levels in response to
D/A converter must be able to produce very large signals and
the 65,536 codes possible with a 16-bit digital word.
very small signals. When the signals are large, there is a high
Systems that must handle both strong and weak signals require proportion of DNL errors. But, in many applications, the signal-
large dynamic range. A notable example of this is the DACs to-noise ratio will be acceptable because the signal is large.
used in early CD player designs. These converters offered 16-
Now consider the case where the signal is very small. The
20 bits of dynamic range but only about 14 bits of differential
proportion of DNL errors that occur in the region of the transfer
linearity. The somewhat inaccurate representation of the digital
function exercised by the signal may be quite small.␣ In fact, in
input was far less important than the fact that the dynamic range
this particular region, the spurs produced by the DNL errors
was much wider than that of LP records and allowed both loud
could be at a level comparable to the converter’s quantization
and soft sounds to be reproduced with barely audible noise—
noise.␣ When the quantization noise becomes the limiting factor
and that the converters’ low cost made CD players affordable.
in determining signal-to-noise ratio, 16 bits of resolution will
The resolution is what makes a 16-bit DAC a “16-bit DAC”. really make a difference (12␣ dB!) when compared to 14 bits.
Resolution is closely associated with dynamic range, the ratio of
Q. OK, I understand. That’s why there’s such a variety of converters out
the largest signal to the smallest that can be resolved. So dynamic
there, and why I have to be careful to interpret the specs in terms of my
range also depends on the noise level; the irreducible “noise”
application. In fact, maybe data sheets that have a great number of
level in ideal ADCs or DACs is quantization noise.
“typical” plots of parameters that are hard to spec are providing really
Q.␣ What is quantization noise? useful information. Now, how about the settling-time question?
A.␣ The sawtooth-wave-shaped quantization noise of an ideal n-bit A.␣ Update rate for a D/A converter refers to the rate at which the
converter is the difference between a linearly increasing analog digital input circuitry can accept new inputs, while settling time
value and the stepwise-increasing digital value. It has an rms is the time the analog output requires to achieve a specified
value of 1/(2n+1√3) of span, or –(6.02␣ n␣ + 10.79)␣ dB (below p-p level of accuracy, usually with full-scale steps.
full scale). For a sine wave, with peak-to-peak amplitude
As with accuracy, time-domain performance requirements differ
equal to the converter’s span, rms is √2/4, or
widely between applications. If full accuracy and full-scale steps
–9.03␣ dB, of span, so the full-scale signal-to-noise ratio of an ideal
are required between conversions, the settling requirements will
n-bit converter, expressed in dB, becomes the classical
be quite demanding (as in the case of offset correction with
6.02␣ n␣ +␣ 1.76␣ dB. (1) CCD image digitizers). On the other hand, waveform synthesis
As the analog signal varies through a number of quantization typically requires relatively small steps from sample to sample.
levels, the associated quantization noise resembles super- The solid practical ground is that full-scale steps in consecutive
imposed “white” noise. In a real converter, the circuit noise samples mean operation at the Nyquist rate (half the sampling
produced by the devices that constitute it adds to quantization frequency), which makes it extremely difficult (how about
noise in root-sum-of-squares fashion, to set a limit on the “impossible”?) to design an effective anti-imaging filter.
amplitude of the minimum detectable signal. Thus, DACs used for waveform reconstruction and many other
Q. But I still worry about that differential nonlinearity spec. Doesn’t applications* inevitably oversample. For such operation, full-scale
14-bit differential nonlinearity mean that the converter may be non- settling is not required; and in general, smaller transitions require
monotonic at the 16-bit level, i.e., that those last two bits have little less time to settle to a given accuracy. Oversampled waveforms,
influence on overall accuracy? taking advantage of this fact, achieve accuracy and speed greater
*The AD768 is an example of such a DAC. than are implied by the full-scale specification. b

Analog Dialogue 29-1 (1995) 39

 Such generators are in practice very difficult to develop. A rather
Ask The Applications Engineer—18 “low-tech” device has served for quite some time as a means
for generating a flat-top transition; the contact opening of a
SETTLING TIME
mercury-wetted-contact relay connected to a stable low-
by Peter Checkovich impedance voltage source can be used to produce a rather clean
Q. Why is settling time important? (and surprisingly fast) flat-topped pulse.␣ The figure shows a
simple circuit that performs this function. For a negative-going
A. Op amp settling time is a key parameter for guaranteeing the transition, with the relay closed, a dc voltage, VSTEP, is applied
performance of data acquisition systems. For accurate data to the input of the DUT and a 50-Ω resistor to ground. When
acquisition, the op amp output must settle before the A/D the relay opens, the input node rapidly discharges to ground,
converter can accurately digitize the data. However, settling creating the input transition. The open relay contact ensures
time is generally not an easy parameter to measure. that all other elements are totally isolated from the amplifier
Over the years, the techniques and equipment used to measure input; the input level is held constant (grounded through 50␣ Ω)
the settling time of op amps have been barely able to keep up for as long as the relay remains open.
with the performance of the devices themselves. As each new VSTEP
MERCURY-WETTED-CONTACT
generation of op amps settles to better accuracy in shorter time, RELAY

greater demands have been placed on test equipment, its DUT

designers, and its users. A major dilemma, often causing dis- 50Ω

agreement among engineers, is whether some combination of

techniques and equipment actually measures the device under
test (DUT) or just some limiting property of the test setup. So
there is continual development of new test equipment and tech-
niques in an effort to specify this ever-demanding parameter. Next problem: directly measuring the output requires handling
In a data-acquisition system, the output of an op amp should a large dynamic range. If the DUT is configured as an inverter,
settle to within 1 LSB [i.e., 2-nFS] of final value of the A/D a subtractor circuit can be created that only looks at the error
that it drives within a time period dictated by the sampling signal and does not have to handle the entire dynamic range of
rate of the system. To settle within 1 LSB of full scale implies the output. This figure shows a circuit used for measuring the
the settling accuracy of the A/D is ± 1/2 LSB. Thus, a 10-bit 16-bit settling time of the AD797—800 ns typical to 0.0015%.
system will require the op amp to settle to half of one part in 226Ω 4.26kΩ

1024, or approximately 0.05%. A 12-bit system will require

settling to half of one part in 4096 (0.01%). The requirements 2
A2 VERROR × 5
for 14-bits and greater are yet more demanding. Settling-time 250Ω
AD829 6
values such as 0.1% and 0.01% are the most widely specified. 7
3 2x
4 HP2835
Although a larger full-scale signal range will increase the size 2x 0.47µF
HP2835
of the LSB, easing the problem somewhat, it is not a feasible
0.47µF
approach for high-frequency systems. Most high frequency A/Ds +VS
have a full-scale span of 1␣ V or, at most, 2␣ V.␣ For a 10-bit system –VS
with a 1-V full scale signal, an LSB is about 1␣ mV.␣ For a 12-bit 1kΩ 1kΩ
system, an LSB is approximately 250␣ µV.␣ To resolve the settling NOTE:
100Ω 1kΩ
characteristics for a full-scale transition, dynamic ranges USE CIRCUIT
BOARD
approaching four orders of magnitude must be handled. With FLAT-TOP WITH GROUND
VIN 20pF
settling times of new op amps [e.g., the AD9631 and AD9632] GENERATOR 1kΩ PLANE
2
dropping to the 20␣ ns to 10␣ ns range, the measurement of settling A1
AD797 6
time presents quite a challenge. DUT
51pF
7
3
Q. How is settling time measured? 4

1µF 0.1µF
A. A key requirement over the years has been the need to drive the
1µF 0.1µF
input of the op amp with a fast, precise signal source, often +VS
referred to as a flat-top generator.␣ As the name implies, such a –VS
generator would have a sharp transition between two levels of
known amplitude at time, t0, should have minimal overshoot A1, the DUT in this circuit, is configured for a gain of –1. The
(or undershoot) and then remain flat for the remainder of the voltage divider from input to output forms a second “false”
measurement time.␣ In this case “flat” means significantly flatter summing node that will replicate the signal at the amplifier’s
than the error to be measured in the amplifier. summing node. The 100-Ω potentiometer is used to null the dc
voltage.The wiper of the potentiometer is clamped by the diodes
The great accuracy is required to be certain that any output
at the input of A2 to limit saturation effects in this amplifier.
signal from the op amp is entirely due to its settling response
The output is also similarly clamped.
and not its response to a signal that is present at the input after
the step transition.␣ Any active device in the path of this signal Since the pre- and post-transition voltages at the output of A2
would require better settling characteristics than the DUT. will be the same (i.e., the difference will be zero), the settling

40 Analog Dialogue 29-2 (1995)

 Ask The Applications Engineer – 18

characteristics of this amplifier due to a step change are not strategies to produce thermal symmetry, but this is easier for low-
important for measuring A1. Thus, the output of A2 can be level high-precision devices than those designed for high-speed,
measured to find the settling time of A1. because of the large, rapid swings of power that occur.
This technique requires that the DUT be configured as an In particular, the new dielectrically isolated processes (like
inverting amplifier. The circuit can be made to work at other XFCB) that have worked wonders for improving the raw speed
gains, but the resistor values and setting of the dc balance of the op amps can have some difficulty in minimizing the
potentiometer will have more influence on the measurement. presence of thermal tails.␣ This is because the process provides
Q. Any other techniques? each transistor a separate dielectric “tub.”␣ While this dielectric
isolation reduces the parasitic capacitance and greatly speeds
A. Another technique for measuring settling time uses the up electrical performance, it also provides thermal insulation
computing power of a digital oscilloscope. It calculates a that slows the dissipation of heat to the substrate.
waveform that represents the settling error as the instantaneous
difference between the acquired input and output signals of the The seriousness of long tails depends on the application. For
DUT and compares them with the values for an ideally settling example, some systems sample at rates compatible with the initial
device. The resulting waveform is the error of the DUT. short-term settling time and are not seriously affected by longer
term drifts. Communication systems and others, where the
If there is a gain error in this system, it will show up as a dc frequency domain properties of the converted signal are most
offset in the error waveform. The calculation can be adapted for important, are examples of such systems. Although long-term
a DUT with any gain, either inverting or non inverting. It also settling errors can produce variations in gain and offset, the
can compensate for a signal generator that itself has a low long-term thermal tails will have minimal contribution to the
frequency settling tail. The DUT response to a low frequency distortion products of the digitized signal. For these systems,
input will not be influenced by that settling time. frequency domain measurements—such as distortion
Because such oscilloscopes are designed primarily for speed, in products—are more important than time domain measurements,
order to determine errors at higher resolutions, averaging must such as settling time.
be used. For example, if the A/D used in the oscilloscope has On the other hand, systems such as video and scanners might
only 8␣ bit resolution, but accuracy better than 8␣ bits, a number produce a step input, followed by a long-duration plateau of
of cycles can be averaged to increase the effective resolution of constant value. During this time, repetitive A/D conversions of
the measurement. the op amp output signal will track the long-term settling
Q. Any more? characteristic. For these systems it is important to understand
A. Yet a third way to measure settling time is to look at the output the long term settling characteristics of the op amp.
directly.␣ A Data Precision Data 6000 can directly digitize signals The figures below illustrate the long- and short-term settling
of up to 5␣ V with 16-bit accuracy and 10-ps resolution. The patterns for the AD8036, a unity-gain-stable high-speed clamp
only fly in the ointment is that the instrument relies on repetitive amp that is a good candidate for an A/D driver in high speed
sampling with a comparator probe. The waveform is built up systems. The figure at left shows that after the initial large
one bit at a time for each of the sample points. As a result, transition, the output is still about 0.09% from its long-term
obtaining a settling characteristic can be very time consuming. final value. However, the right-hand figure shows, on a 300×
This is especially so when using a relay-type flat top generator faster scale, that after about 16␣ ns the output has entered a local
with a 1-kHz upper frequency. 0.01% short-term settling region which can be usefully sampled
Q. Why do data sheets sometimes define short term and long term settling by some systems. The distortion of the AD8036 is extremely
characteristics? low (2nd and 3rd harmonics down by more than 65␣ dB with
500-Ω load) so it would be a good candidate in systems where
A. The traditional definition of settling time is the time from the this kind of performance is critical. b
input transition to the time when the amplifier output enters
0.4
the specified error zone and does not leave again. This concept 0.05

0.3 0.04
is relatively uncomplicated and straightforward. However, there 0.2 0.03

are some cases where the initial settling is fast, followed by an 0.1 0.02

extended period of settling to the final value. Single-supply

ERROR – %

0
ERROR – %

0.01

–0.1 0
amplifiers may exhibit this characteristic in the vicinity of the –0.2 –0.01
lower rail. Of greater prevalence for large transients, a “thermal –0.3 –0.02

tail” is a slow drift that continues for a relatively long time after –0.4 –0.03

–0.5
rapid settling to apparently excellent initial accuracy. –0.6
–0.04

–0.05
0 2 4 6 8 10 12 14 16 18 0 5 10 15 20 25 30 35 40 45
Thermal tails are produced when voltage level changes within SETTLING TIME - s SETTLING TIME – ns

the op amp caused by a step transition create temperature

Reference: Demrow, Robert, “Settling time of operational
gradients among the transistors. Matched transistors will not
amplifiers,” in The Best of Analog Dialogue, 1967 to 1991, pages
track well while they are at temporarily different temperatures.
32-42.
The thermal time constant of the chip determines how long it
takes for equilibrium to return. Op amps are designed to prevent Analog-Digital Conversion Handbook. Norwood, MA; Analog Devices,
or reduce these effects by careful placement of devices and 1986, pp. 312-317 and 436-439 (DAC settling time).

Analog Dialogue 29-2 (1995) 41

 The key difference between serial and parallel data converters
Ask The Applications Engineer—19 lies in the number of interface lines required. From a space
saving point of view, serial converters offer a clear advantage
INTERFACING TO SERIAL CONVERTERS—I
because of reduced device pin-count. This makes it possible to
by Eamon Nash package a 12-bit serial ADC or DAC in an 8-pin DIP or SO
Q. I need data converters to fit in a tight space, and I suspect that a package. More significantly, board space is saved because serial
serial interface will help. What do I need to know to choose and use interface connections require fewer PCB tracks.
one? Q. My digital-to-analog converters have to be physically remote from
A. Let’s start by looking at how a serial interface works and then the central processor and from one another. What is the best way to
compare it to a parallel interface. In doing this we will dispel approach this?
some myths about serial data converters. A. Initially, you must decide whether to use serial or parallel DACs.
RFS1 With parallel DACs, you could map each one into a memory
TFS1
mapped I/O location, as shown in the figure. You would then
SCLK1
DSP ADC
ADSP-2105 AD7890 program each DAC by simply doing a Write command to the
DR1 appropriate I/O location. However, this configuration has a
DT1
significant disadvantage. It requires a parallel data bus, along
with some control signals, to all of the remote locations. Clearly,
SLCK a serial interface, that can have as few as two wires, is much
DATA OUT
LEADING
ZERO A2 A1 A0 DB11 DB10 DB0 more economical.
DATA IN A2 A1 A0 CONV STBY DON’T
CARE
DON’T
CARE
ADDRESS BUS

DECODE LOGIC
The figure shows an AD7890 8-Channel multiplexed 12-bit
CS 0 CS 1 CS “N”
serial A/D converter (ADC) connected to the serial port of an
DAC 0 DAC 1 ... DAC “N”
ADSP-2105 digital signal processor (DSP). Also shown is the
timing sequence that the DSP uses to communicate with the DATA BUS
ADC. The 12 bits that constitute the conversion result are
transmitted as a serial data stream over a single line. The data Serial converters cannot in general be mapped into a processor’s
stream also includes three additional bits that identify the input memory. But a number of serial DACs could be connected to
channel that the AD7890’s multiplexer is currently selecting. the serial I/O port of the processor. Then, other ports on the
To distinguish the bits of the serial data stream from one processor could be used to generate Chip Select signals to
another, a clock signal (SCLK) must be provided, usually by enable the DACs individually. The Chip Select signals will
the DSP; However, sometimes the ADC supplies this clock as require a line from each device to the interface. But there may
an output. The DSP usually (but not always) supplies an be a limit to the number of lines on the processor that can be
additional framing pulse that is active either for one cycle at configured to transmit Chip Select signals.
the beginning of the communication or, as shown (TFS/RFS), One way of getting around this problem is to use serial DACs
for the duration of the transmission. that can be daisy-chained together. The figure shows how to
In this example, the DSP’s serial port is used to program an connect multiple DACs to a single I/O port. Each DAC has a
internal 5-bit register in the ADC. The register’s bits control Serial Data Out (SDO) pin that connects to the Serial Data In
such functions as selecting the channel to be converted, putting (SDI) pin of the next DAC in the chain. LDAC and SCLK are
the device in power-down mode, and starting a conversion. It fed in parallel to all the DACs in the chain. Because the data
should be evident that the serial interface, in this case, must clocked into SDI eventually appears at SDO (N clock cycles
be bi-directional. later), a single I/O port can address multiple DACs. However,
the port must output a long data stream (N bits per DAC times
A parallel ADC, on the other hand, connects directly (or
the number of devices in the chain). The great advantage of
possibly through buffers) to the data bus of the processor it is
this configuration is that device decoding is not needed. All
interfaced with. The figure shows the AD7892 interfaced to
devices are effectively at the same I/O location. The main
an ADSP-2101. When a conversion is complete, the AD7892
drawback of daisy chaining is accessibility (or latency). To
interrupts the DSP, which responds by doing a single read of
change the state of even a single DAC, the processor must still
the ADC’s decoded memory address.
TIMER
output a complete data stream from the I/O port.
DMA13–DMA0

ADDRESS DAC 0 DAC 1

DECODE
LOGIC
TO
DAC DAC LDAC
LDAC
REGISTER LDAC REGISTER DAC 3
DMD15–DMD0 DB11–DB0
ADSP-2101 AD7892
SDO SDI SDO TO
INPUT INPUT
SDI SDI
REGISTER REGISTER
tCONV
DAC 3
TO
tACCESS tHOLD CLOCK CLK
DATA OUT
3-STATE
VALID DATA
3-STATE DAC 3

42 Analog Dialogue 29-3 (1995)

 Ask The Applications Engineer – 19

Q. If serial data converters save so much space and wire, why aren’t (less than 10 effective bits of resolution).There is also an additional
they used in every space-sensitive application? danger that overshoot and noise on the sampling signal will further
A. A major disadvantage of serial interfacing is the tradeoff of degrade the integrity of the analog to digital conversion.
speed for space. For example, to program a parallel DAC, just Q. When should I choose a converter with an asynchronous serial
place the data on the data bus and clock it into the DAC with interface?
a single pulse. However, when writing to a serial DAC, the bits A. An asynchronous link allows devices to exchange unclocked
must be clocked in sequentially (N␣ ␣ clock pulses for an N-bit data with each other. The devices must initially be programmed
converter) and followed by a Load pulse. The processor’s I/O to use the identical data formats. This involves setting a
port spends a relatively large amount of time communicating particular data rate (usually expressed in baud, or bits per
with a serial converter. Consequently, serial converters with second). A convention, that defines how to initiate and end
throughput rates above 500␣ ␣ ksps are uncommon. transmissions, is also necessary. We do this using identifiable
Q. My 8-bit processor doesn’t have a serial port. Is there a way to interface data sequences called start and stop bits. The transmission may
a serial 12-bit ADC like the AD7893 to the processor’s parallel bus? also include parity bits that facilitate error detection.
A. It can of course be done using an external shift register, which RXD RXD
is loaded serially (and asynchronously), then clocked into the TXD TXD
processor’s parallel port. However, if the sense of the question COM PORT

is “without external logic”, the serial ADC can be interfaced AD1B60 ADM232 PC

as if it were a 1-bit parallel ADC. Connect the converter’s

SDATA pin to one of the processor’s data bus lines (it is The figure shows how the AD1B60 Digitizing Signal
connected to D0 in the diagram). Using some decode logic, Conditioner interfaces to a PC’s asynchronous COM Port. This
the converter can be mapped into one of the processor’s is a 3-wire bidirectional interface (the ground lines have been
memory locations so that the result of the conversion can be omitted for clarity). Notice that the receive and transmit lines
read with 12 successive Read commands. Then additional exchange roles at the other end of the line.
software commands integrate the LSBs of the 12 bytes that An asynchronous data link is useful in applications in which
were read into a single 12-bit parallel word. devices communicate only sporadically. Since start and stop
MICRO-
bits are included in every transmission, a device can initiate
ADDRESS BUS
PROCESSOR
communication at any time by simply outputting its data. The
ADDRESS
number of connections between devices is reduced because
DECODER
AD7893 clocking and control signals are no longer necessary.
WR
RD
Q. The data sheet of an ADC I am considering recommends using a
D7
SCLK
non-continuous clock on the serial interface. Why?
D6
D5
DATA BUS D4
(1 BIT USED) D3 A. The specification probably requires that the clock be kept
D2
D1 inactive while the conversion is in progress. Some ADCs require
D0 SDATA
this because a continuous data clock can feed through to the
analog section of the device and adversely affect the integrity
This technique, which is sometimes referred to as “bit banging”,
of the conversion. A continuous clock signal can be
is very inefficient from a software perspective. But it may be
discontinued during conversion if the I/O port has a framing
acceptable in applications in which the processor runs much
pulse; it is used as a gating signal that enables the serial clock
faster than the converter.
to the converter only during data transfer.
Q. In the last example, a gated version of the processor’s write signal
Q. What makes a device SPI or MICROWIRE compatible?
was used to start conversions on the AD7893. Are there problems
with that approach? A. SPI (Serial Peripheral Interface) and MICROWIRE are serial
interface standards developed by Motorola and National
A. I am glad you spotted that. In this example, a conversion can
Semiconductor, respectively. Most synchronous serial
be initiated by doing a dummy write to the AD7893’s mapped
converters can be easily interfaced to these ports; but in some
memory location. No data is exchanged, but the processor
cases additional “glue” logic may be necessary.
provides the write pulse needed to begin the conversion. From
a hardware perspective, this configuration is very simple Q. O.K. I decided to put prejudice aside and use a serial ADC in my
because it avoids the need to generate a conversion signal. current design. I have just wired it up as the data sheet specifies.
When my micro reads the conversion result, the ADC always seems
However, the technique is not recommended in ac data-
to output FFFHEX. What’s happening?
acquisition applications, in which signals must be sampled
periodically. Even if the processor is programmed to do periodic A. Perhaps you are having a communications problem. We need
writes to the ADC, phase jitter on the Write pulse will seriously to look at the connections between the ADC and the
degrade the attainable signal-to-noise ratio (SNR). The gating processor—and at how the timing and control signals have been
process may make the Write signal jitter even worse. A sampling set up. We also need to look at the Interrupt structure. The
clock phase jitter level of as little as 1␣ ns, for example, would next installment will return to this issue, discussing the
degrade the SNR of an ideal 100-kHz sine wave to about 60 dB problems encountered when designing serial interfaces. b
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.

Analog Dialogue 29-3 (1995) 43

 A. Once again there are a number of possible error sources. The
Ask The Applications Engineer—20 ADC will be outputting its conversion result either in straight
binary or in twos complement format (BCD data converters
INTERFACING TO SERIAL CONVERTERS—II
are no longer widely used). Check that your micro is configured
by Eamon Nash to accept the appropriate format. If the micro can’t be
Q. At the end of our discussion in the last issue,␣ I was having a problem configured to accept twos complement directly, you can convert
establishing communication between my ADC and my the data to straight binary by exclusive-or’ing the number with
microcontroller. If you recall, the microcontroller always seemed to 100␣ .␣ .␣ .␣ 00 binary.
be reading a conversion result of FFFHEX regardless of the voltage Normally the leading edge of the serial clock (either rising or
on the analog input.What could be causing this? falling) will enable the data out of the ADC and onto the data
A. There are a number of possible timing-related error sources. bus. The trailing edge then clocks the data into the micro. Make
You could start trouble-shooting this problem by connecting sure that both micro and ADC are operating under the same
all of the timing signals either to a logic analyzer or to a multi- convention and that all Setup and Hold times are being met. A
channel oscilloscope (at least three channels are needed to look conversion result that is exactly half or double what one would
at all signals simultaneously).What you would see on the screen expect is a tell-tale sign that the data (especially the MSB) is
would look similar to the timing diagram in the figure below. being clocked on the wrong edge. The same problem would
First make sure that a Start Conversion command (CONVST) manifest itself in a serial DAC as an output voltage that is half
is being generated (coming either from the micro or from an or double the expected value.
independent oscillator). A frequent mistake is to apply a
CONVST signal with the wrong polarity. The conversion is
still performed, but not when you expect it to be. It is also
important to remember that there is usually a minimum pulse 0V
UNDERSHOOT > 0.3V
B E C
P P
width requirement on the CONVST signal (typically about N
50␣ ns). The standard Write or Read pulse from fast P

microprocessors may not satisfy this requirement. If too short,

the pulse width can be extended by inserting software Wait
states. The digital signals driving the converter should be clean. In
t1
addition to causing possible long-term damage to the device,
tCONV overshoot or undershoot can cause conversion and
communication errors. The figure shows a signal with a large
overshoot spike driving the clock input of a single-supply
converter. In this case, the clock input drives the base of an
PNP transistor. As is usual practice, the P-type substrate of
SCLK
the device is internally connected to the most negative potential
available—in this case, ground. An excursion of more than 0.3
DATA OUT DB11 DB10 DB0
volts below ground on the SCLK line is sufficient to begin
turning on a parasitic diode between the N-type base and the
P-type substrate. If this happens frequently, over the long term,
Make certain that the micro is waiting for the conversion to be it may lead to damage to the device.
completed before the Read cycle begins. Your software should
In the short term, though not causing damage, energizing the
either be taking note of the time required to convert or be
normally inert substrate affects other transistors in the device
waiting for an End of Conversion (EOC) indicator from the
and can lead to multiple clock pulses being detected for each
ADC to generate an interrupt in the micro. Make sure that the
pulse applied.␣ The resulting jitter is a serious matter in serial
polarity of the EOC signal is correct, otherwise the ADC will
converters—but is less of a problem in parallel converters,
cause an interrupt while the conversion is in progress. If the
because the Read and Write cycles generally depend upon the
micro is not responding to the interrupt, you should examine
first applied pulse; subsequent pulses are ignored. However,
the configuration of the interrupt in your software.
the noise performance on both serial and parallel converters
It is also important to consider the state of the serial clock line can suffer if signals of this kind are present during conversion.
(SCLK) while it is not addressing the converter. As I mentioned
The figure shows how overshoot can be easily reduced. A small
in our previous discussion, some DACs and ADCs do not
resistor is placed in series on the digital line that is causing the
operate correctly with continuous serial clocks. In addition to
problem. This resistance will combine with Cpar, the parasitic
this, some devices require that the SCLK signal always idles in
capacitance of the digital input, to form a low-pass filter which
one particular state.
should eliminate any ringing on the received signal. Typically
Q. O.K. I’ve found and corrected some bugs in my software and things a 50-Ω resistor is recommended, but some experimentation
seem to be improving. The data from the converter are changing as may be necessary. It may also be necessary to add an external
I vary the input voltage but the conversion results seem to have no capacitance from the input to ground if the internal capacitance
recognizable format.

44 Analog Dialogue 30-1 (1996)

 Ask The Applications Engineer – 20

of the digital input is insufficient. Here again, experimentation The figure also shows how to deal with the increasingly
is necessary—but a good starting point would be about 10␣ pF. common challenge of powering a mixed-signal system with a
single power supply. As in the grounding case, we run separate
ADC/DAC power lines (preferably power planes) to the analog and digital
TO INTERNAL portions of the circuit. We treat the digital power pin of the
DIGITAL 50Ω CIRCUITRY
INPUT converter as analog. But some isolation from the analog power
SIGNAL
CEXT CPAR pin, in the form of an inductor, is appropriate. Remember that
both power pins of the converter should have separate
decoupling capacitors. The data sheet will recommend
appropriate capacitors, but a good rule of thumb is 0.1␣ µF. If
space permits, a single 10-µF capacitor per device should also
Q. You mentioned that clock overshoot can degrade the noise be included.
performance of a converter. Is there anything else I can do from an Q. I want to design an isolated serial interface between an ADC and a
interfacing point of view to get a good signal to noise ratio? microcontroller using opto-isolators.What should I be aware of when
A.␣ Because your system is operating in a mixed-signal environment using these devices?
(i.e., analog and digital), the grounding scheme is critical. You A. Opto-isolators (also known as opto-couplers) can be used to
probably know that—because digital circuitry is noisy—analog create a simple and inexpensive high-voltage isolation barrier.
and digital grounds should be kept separate, joined at only The presence of a galvanic isolation barrier between converter
one point. This connection is usually made at the power supply. and micro also means that analog and digital system grounds
In fact, if the analog and digital devices are powered from a no longer need to be connected. As shown in the figure, an
common supply, as might be the case in a +5␣ V or +3.3␣ V isolated serial interface between the AD7714 precision ADC
single-supply system, there is no choice but to connect the and the popular 68HC11 microcontroller can be implemented
grounds back at the supply. But the data sheet for the converter with as few as three optoisolators.
probably has an instruction to connect the pins AGND and +5V +5V
DGND at the device! So how can one avoid creating a ground
loop that can result if the grounds are connected in two places? 68HC11 10kΩ
AD7714
425Ω
MISO 4N25
The figure below shows how to resolve this apparent dilemma.
The key is that the AGND and DGND labels on the converter’s DATA OUT
pins refer to the parts of the converter to which those pins are 10kΩ
425Ω
connected. The device as a whole should be treated as analog. 4N25 DATA IN
So after the AGND and DGND pins have been connected
together, there should be a single connection to the system’s MOSI

analog ground. True, this will cause the converter’s digital 10kΩ
currents to flow in the analog ground plane, but this is generally 425Ω
4N25 SCLK
a lesser evil than exposing the converter’s DGND pin to a noisy
digital ground plane. This example also shows a digital buffer, SCLK AGND DGND
referred to digital ground, to isolate the converter’s serial data
pins from a noisy serial bus. If the converter is making a point-
to-point connection to a micro, this buffer may be unnecessary.
The designer should be aware, though, that the use of
optoisolators having relatively slow rise and fall times with
TO OTHER
DIGITAL CIRCUITS CMOS converters can cause problems, even when the serial
communication is running at a slow speed.
“QUIET” NOISY SERIAL
VD VA VD
SYSTEM DIGITAL DATA BUS CMOS logic inputs are designed to be driven by a definite
POWER
ADC/DAC BUFFER logic zero or logic one. In these states, they source and sink
LATCH
SYSTEM
GROUND
a minimal amount of current. However, when the input
voltage is in transition between logic zero and logic one (0.8␣ V
AGND DGND
to 2.0␣ V), the gate will consume an increased amount of
current. If the opto-isolators used have relatively slow rise
A D
and fall times, the excessive amount of time spent in the
TO OTHER
DIGITAL GROUND/POWER PLANE
DIGITAL CIRCUITS dead-band will cause self-heating in the gate. This self-heating
ANALOG GROUND/POWER PLANE tends to shift the threshold voltage of the logic gate upwards,
which can lead to a single clock edge being interpreted by
the converter as multiple clock pulses. To prevent this
threshold jitter, the lines coming from the optoisolators
should be buffered using Schmitt trigger circuits, to deliver
fast, sharp edges to the converter. b

Analog Dialogue 30-1 (1996) 45

 Capacitor Leakage, RP: Leakage is an important parameter
Ask The Applications Engineer—21 in ac coupling applications, in storage applications, such as
by Steve Guinta analog integrators and sample-holds, and when capacitors are
used in high-impedance circuits.
CAPACITANCE AND CAPACITORS
IL
I. Understanding the Parasitic Effects In Capacitors: C C RP

Q. I need to understand how to select the right capacitor for my

application, but I’m not clear on the advantages and disadvantages (a) IDEAL MODEL (b) LEAKAGE MODEL

of the many different types.

In an ideal capacitor, the charge, Q, varies only in response to
A. Selecting the right capacitor type for a particular application
current flowing externally. In a real capacitor, however, the
really isn’t that difficult. Generally, you’ll find that most
leakage resistance allows the charge to trickle off at a rate
capacitors fall into one of four application categories:
determined by the R-C time constant.
•AC coupling, including bypassing (passing ac signals while
Electrolytic-type capacitors (tantalum and aluminum),
blocking dc)
distinguished for their high capacitance, have very high leakage
•decoupling (filtering ac or high frequencies superimposed on current (typically of the order of about 5-20 nA per µF) due to
dc or low frequencies in power, reference, and signal circuitry) poor isolation resistance, and are not suited for storage or
•active/passive RC filters or frequency-selective networks coupling applications.
•analog integrators and sample-and-hold circuits (acquiring and The best choices for coupling and/or storage applications are
storing charge) Teflon (polytetrafluorethylene) and the other “poly” types
+
(polyproplene, polystyrene, etc).
Equivalent Series Resistance (ESR), RS:␣ The equivalent
+
series resistance (ESR) of a capacitor is the resistance of the
AC COUPLING DECOUPLING capacitor leads in series with the equivalent resistance of the
capacitor plates. ESR causes the capacitor to dissipate power
FILTERS SAMPLE-HOLD
(and hence produce loss) when high ac currents are flowing.
This can have serious consequences at RF and in supply
“1” decoupling capacitors carrying high ripple currents, but is
“0”
unlikely to have much effect in precision high-impedance, low-
Even though there are more than a dozen or so popular level analog circuitry.
capacitor types—including poly, film, ceramic, electrolytic, Capacitors with the lowest ESR include both the mica and
etc.—you’ll find that, in general, only one or two types will be film types.
best suited for a particular application, because the salient
Equivalent Series Inductance (ESL), LS:␣ The equivalent
imperfections, or “parasitic effects” on system performance
series inductance (ESL) of a capacitor models the inductance
associated with other types of capacitors will cause them to be
of the capacitor leads in series with the equivalent inductance
eliminated.
of the capacitor plates. Like ESR, ESL can also be a serious
Q. What are these “parasitic effects” you’re talking about? problem at high (RF) frequencies, even though the precision
A. Unlike an “ideal” capacitor, a “real” capacitor is typified by circuitry itself may be operating at DC or low frequencies. The
additional “parasitic” or “non-ideal” components or behavior, reason is that the transistors used in precision analog circuits
in the form of resistive and inductive elements, nonlinearity, may have gain extending up to transition frequencies (Ft) of
and dielectric memory. The resulting characteristics due to hundreds of MHz, or even several GHz, and can amplify
these components are generally specified on the capacitor resonances involving low values of inductance. This makes it
manufacturer’s data sheet . Understanding the effects of these essential that the power supply terminals of such circuits be
parasitics in each application will help you select the right decoupled properly at high frequency.
capacitor type. Electrolytic, paper, or plastic film capacitors are a poor choice
RL for decoupling at high frequencies; they basically consist of
two sheets of metal foil separated by sheets of plastic or paper
C
RESR LESL
dielectric and formed into a roll. This kind of structure has
considerable self inductance and acts more like an inductor
RDA CDA
than a capacitor at frequencies exceeding just a few MHz.
A more appropriate choice for HF decoupling is a monolithic,
Model of a “Real” Capacitor
ceramic-type capacitor, which has very low series inductance.
Q. OK, so what are the most important parameters describing non- It consists of a multilayer sandwich of metal films and ceramic
ideal capacitor behavior? dielectric, and the films are joined in parallel to bus-bars, rather
A. The four most common effects are leakage (parallel resistance), than rolled in series.
equivalent series resistance (ESR), equivalent series inductance A minor tradeoff is that monolithic ceramic capacitors can be
(ESL), and dielectric absorption (memory). microphonic (i.e., sensitive to vibration), and some types may

46 Analog Dialogue 30-2 (1996)

 Ask The Applications Engineer – 21

even be self-resonant, with comparatively high Q, because of Another thing to remember about high frequency decoupling
the low series resistance accompanying their low inductance. is the actual physical placement of the capacitor. Even short
Disc ceramic capacitors, on the other hand, are sometime quite lengths of wire have considerable inductance, so mount the
inductive, although less expensive. HF decoupling capacitors as close as possible to the IC, and
Q. I’ve seen the term “dissipation factor” used in capacitor selection ensure that leads consist of short, wide PC tracks.
charts.What is it? Ideally, HF decoupling capacitors should be surface-mount
A. Good question. Since leakage, ESR, and ESL are almost always parts to eliminate lead inductance, but wire-ended capacitors
difficult to spec separately, many manufacturers will lump are ok, providing the device leads are no longer than 1.5␣ mm.
leakage, ESR and ESL into a single specification known as G
CAP
G
CAP
dissipation factor, or DF, which basically describes the R
O
R
O
U U
inefficiency of the capacitor. DF is defined as the ratio of energy IC N IC N
D D
dissipated per cycle to energy stored per cycle. In practice, this P P
L L
is equal to the power factor for the dielectric, or the cosine of A A
N N
the phase angle. If the dissipation at high frequencies is E E

principally modeled as series resistance, at a critical frequency RIGHT WAY WRONG WAY

of interest, the ratio of equivalent series resistance, ESR, to

• USE LOW INDUCTANCE CAPACITORS (MONOLITHIC CERAMIC)
total capacitive reactance is a good estimate of DF, • MOUNT CAPACITOR CLOSE TO IC
• USE SURFACE MOUNT TYPE
DF ≈ ωRSC . • USE SHORT, WIDE PC TRACKS

Dissipation factor also turns out to be the equivalent to the II. Stray Capacitance:
reciprocal of the capacitor’s figure of merit, or Q, which is also
sometimes included on the manufacturer’s data sheet. A. Now that we’ve talked about the parasitic effects of capacitors
as components, let’s talk about another form of parasitic known
Dielectric Absorption, RDA, CDA: Monolithic ceramic as “stray” capacitance.
capacitors are excellent for HF decoupling, but they have
considerable dielectric absorption, which makes them unsuitable Q. What’s that?
for use as the hold capacitor of a sample-hold amplifier (SHA). A. Well, just like a parallel-plate capacitor, stray capacitors are
Dielectric absorption is a hysteresis-like internal charge formed whenever two conductors are in close proximity to each
distribution that causes a capacitor which is quickly discharged other (especially if they’re running in parallel), and are not
and then open-circuited to appear to recover some of its charge. shorted together or screened by a conductor serving as a
Since the amount of charge recovered is a function of its Faraday shield.
previous charge, this is, in effect, a charge memory and will
cause errors in any SHA where such a capacitor is used as the A
C = 0.0085 ER
d d
hold capacitor.
C = CAPACITANCE IN pF
AREA “A”
ER = DIELECTRIC CONSTANT RELATIVE TO AIR
A = AREA OF PARALLEL CONDUCTORS IN mm2
A
d = DISTANCE BETWEEN CONDUCTORS IN mm
B
C (NC)

Capacitor Model
A B C
TIME Stray or “parasitic” capacitance commonly occurs between
parallel traces on a PC board or between traces/planes on
Capacitors that are recommended for this type of application
opposite sides of a PC board. The occurrence and effects of
include the “poly” type capacitors we spoke about earlier, i.e.,
stray capacitance—especially at very high frequencies—are
polystyrene, polypropylene, or Teflon. These capacitor types
unfortunately often overlooked during circuit modelling and
have very low dielectric absorption (typically <0.01%).
can lead to serious performance problems when the system
The characteristics of capacitors in general are summarized in circuit board is constructed and assembled; examples include
the capacitor comparison chart (page 21). greater noise, reduced frequency response, even instability.
A note about high-frequency decoupling in general: The
PARASITIC CAPACITANCE
best way to insure that an analog circuit is adequately decoupled PC TRACES PC TRACES
at both high and low frequencies is to use an electrolytic-type
capacitor, such as a tantalum bead, in parallel with a monolithic
1.5 mm
ceramic one. The combination will have high capacitance at TYPICAL

low frequency, and will remain capacitive up to quite high GROUND PLANE
frequencies. It’s generally not necessary to have a tantalum
ADJACENT BETWEEN TRACES AND/OR
capacitor on each individual IC, except in critical cases; if there BETWEEN TRACES PLANES ON OPPOSITE SIDES

is less than 10␣ cm of reasonably wide PC track between each (a) (b)
PC BOARD PC BOARD
IC and the tantalum capacitor, it’s possible to share one TOP VIEW CROSS SECTIONAL VIEW
tantalum capacitor among several ICs.

Analog Dialogue 30-2 (1996) 47

Ask The Applications Engineer – 21

For instance, if the capacitance formula is applied to the case KOVAR® LID
of traces on opposite sides of a board, then for general purpose
CERAMIC
PCB material (ER␣ =␣ 4.7, d␣ =␣ 1.5␣ mm), the capacitance between
conductors on opposite sides of the board is just under
3␣ pF/cm2. At a frequency of 250␣ MHz, 3␣ pF corresponds to a
reactance of 212.2␣ ohms! Whatever the environmental noise level, it is good practice for
Q. So how can I eliminate stray capacitance? the user to ground the lid of any side brazed ceramic IC where
the lid is not grounded by the manufacturer. This can be done
A. You can never actually “eliminate” stray capacitance; the best
with a wire soldered to the lid (this will not damage the device,
you can do is take steps to minimize its effects in the circuit.
as the chip is thermally and electrically isolated from the lid).
Q. How do I do that? If soldering to the lid is unacceptable, a grounded phosphor-
A. Well, one way to minimize the effects of stray coupling is to bronze clip may be used to make the ground connection, or
use a Faraday shield, which is simply a grounded conductor conductive paint can be used to connect the lid to the ground
between the coupling source and the affected circuit. pin. Never attempt to ground such a lid without verifying that it is,
in fact, unconnected; there do exist device types with the lid
Q. How does it work? connected to a supply rail rather than to ground!
A. Look at the Figure; it is an equivalent circuit showing how a One case where a Faraday shield is impracticable is between
high-frequency noise source, VN, is coupled into a system the bond wires of an integrated circuit chip. This has important
impedance, Z, through a stray capacitance, C. If we have little consequences. The stray capacitance between two chip bond
or no control over Vn or the location of Z1, the next best solution wires and their associated leadframes is of the order of 0.2␣ pF;
is to interpose a Faraday shield: observed values generally lie between 0.05 and 0.6␣ pF.
CAPACITANCE, C

Z2 = 1/j C ≈ 0.2pF

VN Z1 VCOUPLED
CIRCUIT IMPEDANCE

Z1 VOLTAGE NOISE
VCOUPLED = VN ( –––––– ) COUPLED THROUGH
Z1 + Z2 STRAY CAPACITANCE
Consider a high-resolution converter (ADC or DAC), which
is connected to a high-speed data bus. Each line of the data
As shown, below, the Faraday shield interrupts the coupling bus, (which will be switching at around 2 to 5␣ V/ns),will be
electric field. Notice how the shield causes the noise and able to influence the converter’s analog port via this stray
coupling currents to return to their source without flowing capacitance; the consequent coupling of digital edges will
through Z1. degrade the performance of the converter.
FARADAY
SHIELD

Z1 VCOUPLED
VN
CIRCUIT HIGH SPEED ANALOG
IMPEDANCE DATA BUS SECTION

CAPACITIVE NOISE
AND FARADAY SHIELDS
PARASITIC (STRAY)
CAPACITANCE

Z1 VCOUPLED
VN
CIRCUIT
IMPEDANCE
This problem may be avoided by isolating the data bus,
interposing a latched buffer as an interface. Although this
solution involves an additional component that occupies board
Another example of capacitive coupling is in side-brazed area, consumes power, and adds cost, it can significantly
ceramic IC packages. These DIP packages have a small, square, improve the converter’s signal-to-noise. b
conducting Kovar lid soldered onto a metallized rim on the
ceramic package top. Package manufacturers offer only two
options: the metallized rim may be connected to one of the BUFFER/
DATA LATCH
D-A
CONVERTER
corner pins of the package, or it may be left unconnected. Most HIGH SPEED ANALOG
logic circuits have a ground pin at one of the package corners, DATA BUS SECTION

and therefore the lid is grounded. But many analog circuits do BUFFER/
DATA LATCH
A-D
CONVERTER
not have a ground pin at a package corner, and the lid is left
floating. Such circuits turn out to be far more vulnerable to
electric field noise than the same chip in a plastic DIP package,
where the chip is unshielded.

48 Analog Dialogue 30-2 (1996)

 Ask The Applications Engineer – 21

CAPACITOR COMPARISON CHART

TYPE TYPICAL ADVANTAGES DISADVANTAGES

DIELECTRIC
ABSORPTION
NPO ceramic <0.1% Small case size DA generally low, but may not be specified
Inexpensive Limited to small values (10␣ nF)
Good stability
Wide range of values
Many vendors
Low inductance
Polystyrene 0.001% Inexpensive Damaged by temperature > +85°C
to 0.02% Low DA available Large case size
Wide range of values High inductance
Good stability
Polypropylene 0.001% Inexpensive Damaged by temperature > +105°C
to 0.02% Low DA available Large case size
Wide range of values High inductance

Teflon 0.003% Low DA available Relatively expensive

to 0.02% Good stability Large size
Operational above +125°C High inductance
Wide range of values
MOS 0.01% Good DA Limited availability
Small Available only in small capacitance values
Operational above +125°C
Low inductance
Polycarbonate 0.1% Good stability Large size
Low cost DA limits to 8-bit applications
Wide temperature range High inductance
Polyester 0.3% Moderate stability Large size
to 0.5% Low cost DA limits to 8-bit applications
Wide temperature range High inductance
Low inductance (stacked film)

Monolithic ceramic >0.2% Low inductance Poor stability

(High K) Wide range of values Poor DA
High voltage coefficient
Mica >0.003% Low loss at HF Quite large
Low inductance Low values (<10␣ nF)
Very stable Expensive
Available in 1% values or better

Aluminum electrolytic High Large values High leakage

High currents Usually polarized
High voltages Poor stability
Small size Poor accuracy
Inductive
Tantalum electrolytic High Small size Quite high leakage
Large values Usually polarized
Medium inductance Expensive
Poor stability
Poor accuracy

Analog Dialogue 30-2 (1996) 49

Ask The Applications Engineer—22 that no current flows into the op amp (infinite input
impedance); both inputs will be at about the same potential
by Erik Barnes (negative feedback and high open-loop gain)).
CURRENT FEEDBACK AMPLIFIERS—I With Vo␣ =␣ (VIN+␣ –␣ VIN–)A(s)
Q. I’m not sure I understand how current-feedback amplifiers work as RG
and V IN – = V
compared with regular op amps. I’ve heard that their bandwidth is RG + RF o
constant regardless of gain. How does that work? Are they the same substitute and simplify to get:
as transimpedance amplifiers?
A. Before looking at any circuits, let’s define voltage feedback, Vo  R  1 A(s)
= 1 + F  where LG =
current feedback, and transimpedance amplifier. Voltage VIN  RG 1 R
1+ 1+ F
feedback, as the name implies, refers to a closed-loop LG RG
configuration in which the error signal is in the form of a The closed-loop bandwidth is the frequency at which the loop
voltage. Traditional op amps use voltage feedback, that is, their gain, LG, magnitude drops to unity (0␣ dB). The term,
inputs will respond to voltage changes and produce a 1␣ +␣ R F/R G, is called the noise gain of the circuit; for the
corresponding output voltage. Current feedback refers to any noninverting case, it is also the signal gain. Graphically, the
closed-loop configuration in which the error signal used for closed-loop bandwidth is found at the intersection of the open-
feedback is in the form of a current. A current feedback op loop gain, A(s), and the noise gain, NG, in the Bodé plot.
amp responds to an error current at one of its input terminals, High noise gains will reduce the loop gain, and thereby the
rather than an error voltage, and produces a corresponding closed-loop bandwidth. If A(s) rolls off at 20␣ dB/decade, the
output voltage. Notice that both open-loop architectures gain-bandwidth product of the amplifier will be constant. Thus,
achieve the same closed-loop result: zero differential input an increase in closed-loop gain of 20 dB will reduce the closed-
voltage, and zero input current. The ideal voltage feedback loop bandwidth by one decade.
amplifier has high-impedance inputs, resulting in zero input
current, and uses voltage feedback to maintain zero input Z(s)
voltage. Conversely, the current feedback op amp has a low VIN+

LOG – Ω
+1 VO
impedance input, resulting in zero input voltage, and uses Z(s)
LG
RO
BODE PLOT
current feedback to maintain zero input current. VIN–
I ERR R F+R O NG
The transfer function of a transimpedance amplifier is expressed
RF
RG LOG f
as a voltage output with respect to a current input. As the CURRENT FEEDBACK RF O fCL
AMPLIFIER, NONINVERTING
function implies, the open-loop “gain”, vO/iIN, is expressed in GAIN CONNECTION
ohms. Hence a current-feedback op amp can be referred to as
a transimpedance amplifier. It’s interesting to note that the Consider now a simplified model for a current-feedback
closed-loop relationship of a voltage-feedback op amp circuit amplifier. The noninverting input is the high-impedance input
can also be configured as a transimpedance, by driving its of a unity gain buffer, and the inverting input is its low-
dynamically low-impedance summing node with current (e.g., impedance output terminal. The buffer allows an error current
from a photodiode), and thus generating a voltage output equal to flow in or out of the inverting input, and the unity gain
to that input current multiplied by the feedback resistance. forces the inverting input to track the noninverting input. The
Even more interesting, since ideally any op amp application error current is mirrored to a high impedance node, where it is
can be implemented with either voltage or current feedback, converted to a voltage and buffered at the output. The high-
this same I-V converter can be implemented with a current impedance node is a frequency-dependent impedance, Z(s),
feedback op amp. When using the term transimpedance amplifier, analogous to the open-loop gain of a voltage feedback amplifier;
understand the difference between the specific current- it has a high dc value and rolls off at 20␣ dB/decade.
feedback op amp architecture, and any closed-loop I-V
converter circuit that acts like transimpedance. The closed-loop transfer function is found by summing the
currents at the V IN– node, while the buffer maintains
Let’s take a look at the simplified model of a voltage feedback VIN+␣ =␣ VIN–. If we assume, for the moment, that the buffer has
amplifier. The noninverting gain configuration amplifies the zero output resistance, then Ro␣ =␣ 0Ω
difference voltage, (VIN+␣ –␣ VIN–), by the open loop gain A(s)
Vo − V IN − −V IN −
+ Ierr = 0 and Ierr =V 0 / Z (s )
and feeds a portion of the output back to the inverting input
+
through the voltage divider consisting of RF and RG. To derive RF RG
the closed-loop transfer function of this circuit, Vo/VIN+, assume Substituting, and solving for Vo/VIN+

Z (s)
A(s)
Vo  R  1
= 1+ F  , where LG =
V IN + 
VIN+ VO
A(s)
RG  1 RF
GAIN – dB

VIN– LG
BODE PLOT 1+
LG
RF
RG
VOLTAGE FEEDBACK
NG The closed-loop transfer function for the current feedback
LOG f
AMPLIFIER, NONINVERTING fCL amplifier is the same as for the voltage feedback amplifier, but
GAIN CONNECTION
the loop gain (1/LG) expression now depends only on RF, the

50 Analog Dialogue 30-3 (1996)

 Ask The Applications Engineer – 22

feedback transresistance—and not (1␣ +␣ RF/RG). Thus, the

Q5 Q6
closed-loop bandwidth of a current feedback amplifier will vary
with the value of RF, but not with the noise gain, 1␣ +␣ RF/RG. Q1 Q3
VIN– Z(S)
VIN+ VO
The intersection of RF and Z(s) determines the loop gain, and +1
Q2 Q4
thus the closed-loop bandwidth of the circuit (see Bodé plot). SIMPLIFIED CURRENT FEEDBACK
AMPLIFIER, ILLUSTRATING INPUT
Clearly the gain-bandwidth product is not constant—an Q7 Q8 STAGE AND CURRENT MIRRORS.

advantage of current feedback.

In practice, the input buffer’s non-ideal output resistance will Q. What about dc accuracy?
be typically about 20 to 40 Ω, which will modify the feedback A. The dc gain accuracy of a current feedback amplifier can be
transresistance. The two input voltages will not be exactly equal. calculated from its transfer function, just as with a voltage
Making the substitution into the previous equations with feedback amplifier; it is essentially the ratio of the internal
VIN–␣ =␣ VIN+␣ – IerrRo, and solving for Vo/VIN+ yields: transresistance to the feedback transresistance. Using a typical
Vo  R  1 Z (s) transresistance of 1␣ MΩ, a feedback resistor of 1␣ kΩ, and an
= 1+ F  , where LG =
V IN 
Ro of 40␣ ohms, the gain error at unity gain is about 0.1%. At
RG  1  R 
1+ RF + Ro 1+ F  higher gains, it degrades significantly. Current-feedback
LG  RG 
amplifiers are rarely used for high gains, particularly when
The additional term in the feedback transresistance means that absolute gain accuracy is required.
the loop gain will actually depend somewhat on the closed- For many applications, though, the settling characteristics are
loop gain of the circuit. At low gains, RF dominates, but at of more importance than gain accuracy. Although current
higher gains, the second term will increase and reduce the loop feedback amplifiers have very fast rise times, many data sheets
gain, thus reducing the closed-loop bandwidth. will only show settling times to 0.1%, because of thermal
It should be clear that shorting the output back to the inverting settling tails— a major contributor to lack of settling precision.
input with RG open (as in a voltage follower) will force the Consider the complementary input buffer above, in which the
loop gain to get very large. With a voltage feedback amplifier, VIN– terminal is offset from the VIN+ terminal by the difference
maximum feedback occurs when feeding back the entire output in VBE between Q1 and Q3. When the input is at zero, the two
voltage, but the current feedback’s limit is a short-circuit VBEs should be matched, and the offset will be small from VIN+
current. The lower the resistance, the higher the current will to VIN–. A positive step input applied to VIN+ will cause a
be. Graphically, RF␣ =␣ 0 will give a higher-frequency intersection reduction in the VCE of Q3, decreasing its power dissipation,
of Z(s) and the feedback transresistance—in the region of thus increasing its VBE. Diode-connected Q1 does not exhibit
higher-order poles. As with a voltage feedback amplifier, higher- a VCE change, so its VBE will not change. Now a different offset
order poles of Z(s) will cause greater phase shift at higher exists between the two inputs, reducing the accuracy. The same
frequencies, resulting in instability with phase shifts > 180 effect can occur in the current mirror, where a step change at
degrees. Because the optimum value of RF will vary with closed- the high-impedance node changes the VCE, and thus the VBE,
loop gain, the Bode plot is useful in determining the bandwidth of Q6, but not of Q5. The change in VBE causes a current error
and phase margin for various gains. A higher closed-loop referred back to VIN–, which—multiplied by RF—will result in
bandwidth can be obtained at the expense of a lower phase an output offset error. Power dissipation of each transistor
margin, resulting in peaking in the frequency domain, and occurs in an area that is too small to achieve thermal coupling
overshoot and ringing in the time domain. Current-feedback between devices. Thermal errors in the input stage can be
device data sheets will list specific optimum values of RF for reduced in applications that use the amplifier in the inverting
various gain settings. configuration, eliminating the common-mode input voltage.
Current feedback amplifiers have excellent slew-rate Q. In what conditions are thermal tails a problem?
capabilities. While it is possible to design a voltage-feedback A. It depends on the frequencies and waveforms involved.
amplifier with high slew rate, the current-feedback architecture Thermal tails do not occur instantaneously; the thermal
is inherently faster. A traditional voltage-feedback amplifier, coefficient of the transistors (which is process dependent) will
lightly loaded, has a slew rate limited by the current available determine the time it takes for the temperature change to occur
to charge and discharge the internal compensation capacitance. and alter parameters—and then recover. Amplifiers fabricated
When the input is subjected to a large transient, the input stage on the Analog Devices high-speed complementary bipolar (CB)
will saturate and only its tail current is available to charge or process, for example, don’t exhibit significant thermal tails for
discharge the compensation node. With a current-feedback input frequencies above a few kHz, because the input signal is
amplifier, the low-impedance input allows higher transient changing too fast. Communications systems are generally more
currents to flow into the amplifier as needed. The internal concerned with spectral performance, so additional gain errors
current mirrors convey this input current to the compensation that might be introduced by thermal tails are not important.
node, allowing fast charging and discharging—theoretically, Step waveforms, such as those found in imaging applications,
in proportion to input step size. A faster slew rate will result in can be adversely affected by thermal tails when dc levels change.
a quicker rise time, lower slew-induced distortion and For these applications, current-feedback amplifiers may not
nonlinearity, and a wider large-signal frequency response. The offer adequate settling accuracy.
actual slew rate will be limited by saturation of the current
mirrors, which can occur at 10 to 15␣ mA, and the slew-rate Part II will consider common application circuits using current-feedback
limit of the input and output buffers. amplifiers and view their operation in more detail. b

Analog Dialogue 30-3 (1996) 51

Ask The Applications Engineer—23 when referred to the input; added to the input voltage noise of
the amplifier in RSS fashion, this gives an input-referred
by Erik Barnes noise voltage of only 2.5␣ nV/√Hz (neglecting resistor
noise). Used thus, the CF op amp becomes attractive for a low
CURRENT FEEDBACK AMPLIFIERS—II
noise application.
Part I (Analog Dialogue 30-3) covers basic operation of the
current-feedback (CF) op-amp. This second part addresses Q. What about using the classic four-resistor differential
frequently asked questions about common applications. configuration? Aren’t the two inputs unbalanced and
therefore not suitable for this type of circuit?
Q. I now have better understanding of how a current feedback
A. I’m glad you asked; this is a common misconception of CF op-
op-amp works, but I’m still confused when it comes to
amps. True, the inputs are not matched, but the transfer
applying one in a circuit. Does the low inverting input
function for the ideal difference amplifier will still work out
impedance mean I can’t use the inverting gain configuration?
the same. What about the unbalanced inputs? At lower
A. Remember that the inverting mode of operation works frequencies, the four-resistor differential amplifier’s CMR is
because of the low-impedance node created at the inverting limited by the matching of the external resistor ratios, with
input. The summing junction of a voltage-feedback (VF) 0.1% matching yielding about 66␣ dB. At higher frequencies,
amplifier is characterized by a low input impedance after the what matters is the matching of time constants formed by the
feedback loop has settled. A current feedback op amp will, in input impedances. High-speed voltage-feedback op amps
fact, operate very well in the inverting configuration because usually have pretty well matched input capacitances,
of its inherently low inverting-input impedance, holding the achieving CMR of about 60␣ dB at 1␣ MHz. Because the CF
summing node at “ground,” even before the feedback loop has amplifier’s input stage is unbalanced, the capacitances may
settled. CF types don’t have the voltage spikes that occur at not be well matched. This means that small external resistors
the summing node of voltage feedback op amps in high- (100 to 200␣ Ω) must be used on the noninverting input of
speed applications. You may also recall that advantages of some amplifiers to minimize the mismatch in time constants.
the inverting configuration include maximizing input slew If careful attention is given to resistor selection, a CF op-amp
rate and reducing thermal settling errors. can yield high frequency CMR comparable to a VF op amp. If
Q. So this means I can use a current feedback op-amp as a higher performance is needed, the best choice would be a
current-to-voltage converter, right? monolithic high speed difference amplifier, such as the
A. Yes, they can be configured as I-to-V converters. But there are AD830. Requiring no resistor matching , it has a
limitations: the amplifier’s bandwidth varies directly with the CMR > 75␣ dB at 1␣ MHz and about 53␣ dB at 10␣ MHz.
value of feedback resistance, and the inverting input current Q. What about trimming the amplifier’s bandwidth with a
noise tends to be quite high. When amplifying low level feedback capacitor? Will the low impedance at the inverting
currents, higher feedback resistance means higher signal-to- input make the current feedback op amp less sensitive to
(resistor-) noise ratio, because signal gain will increase shunt capacitance at this node? How about capacitive loads?
proportionally, while resistor noise goes as √R. Doubling the A. First consider a capacitor in the feedback path. With a voltage
feedback resistance doubles the signal gain and increases feedback op amp, a pole is created in the noise gain, but a
resistor noise by a only factor of 1.4; unfortunately the pole and a zero occur in the feedback transresistance of a
contribution from current noise is doubled, and, with a current current feedback op amp, as shown in the figure below.
feedback op amp, the signal bandwidth is halved. Thus the Remember that the phase margin at the intersection of the
higher current noise of CF op amps may preclude their use in feedback transresistance and the open loop transimpedance
many photodiode-type applications. When noise is less critical, will determine closed-loop stability. Feedback
select the feedback resistor based on bandwidth requirements; transresistance for a capacitance, CF, in parallel with RF, is
use a second stage to add gain. given by
Q. I did notice the current noise is rather high in current feedback sCF RF RG RO
amplifiers. So will this limit the applications in which I can use  1+
 RF   RF RG + RF RO + RG RO
them? Z F (s) =  RF + RO 1+  
  RG   1+ sCF RF
A. Yes, the inverting input current noise tends to be higher in CF
The pole occurs at 1/2πRFCF, and the zero occurs higher in
op amps, around 20 to 30␣ pA/√Hz. However, the input voltage
frequency at 1/[2π(RF||RG||RO)CF]. If the intersection of ZF
noise tends to be quite low when compared with similar
and ZOL occurs too high in frequency, instability may result
voltage feedback parts, typically less than 2␣ nV/√Hz, and
from excessive open loop phase shift. If RF␣ →␣ ∞, as with an
the feedback resistance will also be low, usually under 1␣ kΩ.
integrator circuit, the pole occurs at a low frequency and very
At a gain of 1, the dominant source of noise will be the
little resistance exists at higher frequencies to limit the loop
inverting-input noise current flowing through the feedback
gain. A CF integrator can be stabilized by a resistor in series
resistor. An input noise current of 20␣ pA/√Hz and an RF of
with the integrating capacitor to limit loop gain at higher
750␣ Ω yields 15␣ nV/√Hz as the dominant noise source at the
frequencies. Filter topologies that use reactive feedback, such
output. But as the gain of the circuit is increased (by reducing
as multiple feedback types, are not suitable for CF op amps;
input resistance), the output noise due to input current noise
but Sallen-Key filters, where the op amp is used as a fixed-
will not increase, and the amplifier’s input voltage noise
gain block, are feasible. In general, it is not desirable to add
will become the dominant factor. At a gain, of say, 10, the
capacitance across RF of a CF op amp.
contribution from the input noise current is only 1.5␣ nV/√Hz
52 Analog Dialogue 30-4 (1996)
 Ask The Applications Engineer – 23

LOG Ω
VIN+
+ With the resistor outside the feedback loop, but in series with
ZOL(S)
+1 VO the load capacitance, the amplifier doesn’t directly drive a
RO purely capacitive load. A CF op amp also gives the option of
–
increasing R F to reduce the loop gain. Regardless of the
RF RF
ZF(S) RF + RO 1 +
RG approach taken, there will always be a penalty in bandwidth,
RG slew rate, and settling time. It’s best to experimentally optimize
CF LOG f
fP fZ a particular amplifier circuit, depending on the desired
characteristics, e.g., fastest rise time, fastest settling to a
Another issue to consider is the effect of shunt capacitance at specified accuracy, minimum overshoot, or passband flatness.
the inverting input. Recall that with a voltage feedback VIN+ RS

amplifier, such capacitance creates a zero in the noise gain, CL RL

increasing the rate of closure between the noise gain and open RG
RF

loop gain, generating excessive phase shift that can lead to

instability if not compensated for. The same effect occurs with
Q. Why don’t any of your current feedback amplifiers offer true single-
a current feedback op amp, but the problem may be less
supply operation, allowing signal swings to one or both rails?
pronounced. Writing the expression for the feedback
transresistance with the addition of CIN: A. This is one area where the VF topology is still favored for
several reasons. Amplifiers designed to deliver good current
  R   sCIN RF RG RO  drive and to swing close to the rails usually use common-
Z F (s) =  RF + RO 1+ F   1+ 
  R 
G  R R
F G + R R
F O + R R
G O emitter output stages, rather than the usual emitter followers.
Common emitters allow the output to swing to the supply
A zero occurs at 1/[2π(RF||RG||RO)CIN], shown in the next rail minus the output transistors’ V CE saturation voltage.
figure (fZ1). This zero will cause the same trouble as with a VF With a given fabrication process, this type of output stage
amplifier, but the corner frequency of the zero tends to be does not offer as much speed as emitter followers, due in
higher in frequency because of the inherently low input part to the increased circuit complexity and inherently higher
impedance at the inverting input. Consider a wideband voltage output impedance. Because CF op amps are specifically
feedback op amp with R F ␣ =␣ 750␣ Ω, R G ␣ =␣ 750␣ Ω, and developed for the highest speed and output current, they
CIN␣ =␣ 10␣ pF. The zero occurs at 1/[2π(RFiRG)CIN], roughly feature emitter follower output stages.
40␣ MHz, while a current feedback op-amp in the same
With higher speed processes, such as ADI’s XFCB (extra-fast
configuration with an RO of 40␣ Ω will push the zero out to
complementary bipolar), it has been possible to design a
about 400␣ MHz. Assuming a unity gain bandwidth of 500␣ MHz
common-emitter output stage with 160-MHz bandwidth and
for both amplifiers, the VF amplifier will require a feedback
160-V/µs slew rate, powered from a single 5-volt supply
capacitor for compensation, reducing the effect of CIN, but also
(AD8041). The amplifier uses voltage feedback, but even if,
reducing the signal bandwidth. The CF device will certainly
somehow, current feedback had been used, speed would still
see some additional phase shift from the zero, but not as much
be limited by the output stage. Other XFCB amplifiers, with
because the break point is a decade higher in frequency. Signal
emitter-follower output stages (VF or CF), are much faster
bandwidth will be greater, and compensation may only be
than the AD8041. In addition, single-supply input stages use
necessary if in-band flatness or optimum pulse response is
PNP differential pairs to allow the common-mode input range
required. The response can be tweaked by adding a small
to extend down to the lower supply rail (usually ground). To
capacitor in parallel with RF to reduce the rate of closure
design such an input stage for CF is a major challenge, not yet
between ZF and ZOL. To ensure at least 45° of phase margin,
met at this writing.
the feedback capacitor should be chosen to place a pole in the
feedback transresistance where the intersection of ZF and ZOL Nevertheless, CF op amps can be used in single-supply
occurs, shown here (fP). Don’t forget the effects of the higher applications. Analog Devices offers many amplifiers that are
frequency zero due to the feedback capacitor (fZ2). specified for +5- or even +3-volt operation. What must be kept
+
LOG Ω in mind is that the parts operate well off a single supply if the
VIN+
+1 VO
ZOL(S)
WITH WITH application remains within the allowable input and output voltage
CIN CIN AND CF

RO
ranges. This calls for level shifting or ac coupling and biasing to
–
the proper range, but this is already a requirement in most
RF
RF ZF(S) RF + RO 1 +
RG
single-supply systems. If the system must operate to one or
CIN RG
both rails, or if the maximum amount of headroom is demanded
CF LOG f
fZ1 fP fZ2 in ac-coupled applications, a current feedback op amp may
simply not be the best choice. Another factor is the rail-to-rail
Load capacitance presents the same problem with a current output swing specifications when driving heavy loads. Many
feedback amplifier as it does with a voltage feedback amplifier: so-called rail-to-rail parts don’t even come close to the rails
increased phase shift of the error signal, resulting in degradation when driving back- terminated 50- or 75-Ω cables, because of
of phase margin and possible instability. There are several well- the increase in VCESAT as output current increases. If you really
documented circuit techniques for dealing with capacitive need true rail-to-rail performance, you don’t want or need a
loads, but the most popular for high speed amplifiers is a resistor current feedback op amp; if you need highest speed and output
in series with the output of the amplifier (as shown below). current, this is where CF op amps excel. b

Analog Dialogue 30-4 (1996) 53

 INDEX
Accuracy enhancement . . . . . . . . . . . . . . . . . . . . . . . . 36, 37 phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 38, 39 serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
A/D converters sigma delta converters . . . . . . . . . . . . . . . . . . . . . . . . . . 33
buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Comparators
grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 21 autozeroed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 hysteresis to stabilize . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
noise and missing codes . . . . . . . . . . . . . . . . . . . . . . . . 12 oscillation in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38 propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-53
references, internal vs. external . . . . . . . . . . . . . . . . . . . 19 and single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
serial, interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
sigma-delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38 D/A converters
trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 accuracy vs. resolution . . . . . . . . . . . . . . . . . . . . . . . . . 39
Amplifiers current-steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
bias and offset current . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
differential, long-tailed pair . . . . . . . . . . . . . . . . . . . . . . . 8 serial interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-45
distortion specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
drift, long-term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 update rate vs. settling time . . . . . . . . . . . . . . . . . . . . . . 39
feedback, voltage vs. current . . . . . . . . . . . . . . . . . . 50, 51 voltage-switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
JFET input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 34
latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Decoupling, supply . . . . . . . . . . . . . . . . . . . . . . 6, 14, 15, 47
multiplicity of types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Delta-sigma (see Sigma-delta)
noise (see Noise) . . . . . . . . . . . . . . . . . . . . . 10, 11, 12, 13 Distortion
phase inversion error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 harmonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 24
rectification in input stage . . . . . . . . . . . . . . . . . . . . 26, 27 intercept points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 25
signal contamination . . . . . . . . . . . . . . . . . . . . . . . . 26, 27 intermodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 25
superbeta input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 reduction with dither . . . . . . . . . . . . . . . . . . . . . . . 35, 36
trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 root sum-of-squares . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
local vs. system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25

Bias current, Faraday shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

and offset current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Feedback, voltage vs. current . . . . . . . . . . . . . . . . . . . . 50-53
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Feedback capacitors, in current-feedback amplifiers . . 52-53
Filters
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-49 antialiasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
comparators, bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . 6 digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
decoupling, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14, 15 FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 33
loading on references . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Floating inputs, need to tie . . . . . . . . . . . . . . . . . . . . . . . . . 1
parasitic effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-47 F/V converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
dielectric absorption . . . . . . . . . . . . . . . . . . . . . . . . . 47
dissipation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Gain-bandwidth, in voltage- and current-feedback
equivalent series inductance, (ESL) . . . . . . . . . . . . . . 46 amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 51
equivalent series resistance, (ESR) . . . . . . . . . . . . . . 46 Gain, trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Grounding
strays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-48 analog vs. digital grounds . . . . . . . . . . . . . . . . . 20, 21, 45
IC packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 factor in comparator oscillations . . . . . . . . . . . . . . . . . . . 6
PC boards . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 47, 48 mixed-signal chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
switched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 32
types, comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Hysteresis, comparators . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 7
V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Idle tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 31
conversion clock vs. sample clock . . . . . . . . . . . . . . . . . 22 Inductance, PC boards . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ask The Applications Engineer 30th Anniversary Reader Bonus v

Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
low-frequency effects of . . . . . . . . . . . . . . . . . . 26, 27, 28 sink currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
testing for susceptibility to . . . . . . . . . . . . . . . . 26, 27, 28 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19, 22
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19
Log circuits, compensation resistors . . . . . . . . . . . . . . . . . . 1 Resistors
ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mixed-signal circuits log temperature compensation . . . . . . . . . . . . . . . . . . . . 1
grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20, 21, 45 non-ideal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 45 PC tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 temperature coefficients . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
sigma delta converter input . . . . . . . . . . . . . . . . . . . . . . 33 Root sum-of-squares (RSS)
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11, 12, 13 distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1/f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 13 log quantities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32, 38
and dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 29
and long term drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
and missing codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Seminars and support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial converter interfacing . . . . . . . . . . . . . . . . . . . . . 42-45
figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
gain, noise- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 50 Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39, 40, 41
Gaussian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11, 12 thermal tails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 51
in sigma-delta ADCs . . . . . . . . . . . . . . . . . . 29, 30, 35-38 Sigma-delta converters . . . . . . . . . . . . . . . . . . . . . . . . . 29-38
interference . . . . . . . . . . . . . . . . . . . . . . . . . 10, 26, 27, 28 antialiasing filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 34
Johnson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 idle tones in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 31
measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 37, 38 multiple output codes . . . . . . . . . . . . . . . . . . . . . . . 34, 35
phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 practice issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 34
popcorn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal-to-noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 38
quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 36, 39 Slew rate, in current-feedback amplifiers, . . . . . . . . . . . . . 51
random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 11
root sum-of-squares (RSS) . . . . . . . . . . . . . . . . . . . 10, 29 Thermal tails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 51
Schottky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transimpedance amplifiers . . . . . . . . . . . . . . . . . . . . . 50-53
vs. conductor noise . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trim circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
source impedance effects . . . . . . . . . . . . . . . . . . . . . . . . 11 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
temperature effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 vs. system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Nonlinearity, differential . . . . . . . . . . . . . . . . . . . . . . . . . . 39 D/A converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
V/F converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Offset trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Optoisolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Unused channel, grounding . . . . . . . . . . . . . . . . . . . . . . . . . 1
Oscillations, parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 15 Update rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38, 39
VBE, logarithmic relationship . . . . . . . . . . . . . . . . . . . . . . . . 1
Powerup problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V/F converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Printed circuit boards capacitors for . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 47, 48 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 17 frequency to voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 interference effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
track resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 synchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-53
References
bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Wire, non-ideal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 16
buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 19
buried Zener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

vi 30th Anniversary Reader Bonus Ask The Applications Engineer