keeps changing from one quasi stable state to another quasi stable state on its own the moment

it is connected to the supply.

A bistable multivibrator is the basic memory element. It is used to perform many digital
operations such as counting and storing of binary data. It also finds extensive applications in the
generation and processing of pulse type waveforms. The monostable multivibrator finds
extensive applications in pulse circuits. Mostly it is used as a gating circuit or a delay circuit.
The astable circuit is used as a master oscillator to generate square waves. It is often a basic
source of fast waveforms. It is a free running oscillator. It is called a square wave generator. It is
also termed a relaxation oscillator.
BISTABLE MULTIVIBRATOR
A bistable multivibrator is a multivibrator which can exist indefinitely in either of its two
stable states and which can be induced to make an abrupt transition from one state to the other
by means of external excitation. In a bistable multivibrator both the coupling elements are
resistors (dc coupling). The bistable multivibrator is also called a multi, Eccles-Jordan circuit
(after its inventors), trigger circuit, scale-of-two toggle circuit, flip-flop, and binary. There are
two types of bistable multivibrators:
1. Collector coupled bistable multivibrator
2. Emitter coupled bistable multivibrator
There are two types of collector-coupled bistable multivibrators:
1. Fixed-bias bistable multivibrator
2. Self-bias bistable multivibrator
A FIXED-BIAS BISTABLE MULTIVIBRATOR
Figure 4.1 shows the circuit diagram of a fixed-bias bistable multivibrator using
transistors (inverters). Note, that the output of each amplifier is direct coupled to the input of the
other amplifier. In one of the stable states, transistor Q[ is ON (i.e. in saturation) and Q 2 is OFF

(i.e. in cut-off), and in the other stable state Qj is OFF and Q2 is ON. Even though the circuit is
symmetrical, it is not possible for the circuit to remain in a stable state with both the transistors
conducting (i.e. both operating in the active region) simultaneously and carrying equal currents.
The reason is that if we assume that both the transistors are biased equally and are carrying equal
currents /[ and 72 and suppose there is a minute fluctuation in the current 1\~—let us say it
increases by a small amount—then the voltage at the collector of Qi decreases. This will result in
a decrease in voltage at the base of Q2. So Q2 conducts less and /2 decreases and hence the
potential at the collector of Q2 increases. This results in an increase in the base potential of Qi.

So, Qi conducts still more and /[ is further increased and the potential at the collector of Q t is

further reduced, and so on. So, the current I\ keeps on increasing and the current /2 keeps on

decreasing till Q( goes into saturation and Q2 goes into cut-off. This action takes place because
of the regenerative feedback incorporated into the circuit and will occur only if the loop gain is
greater than one.A stable state of a binary is one in which the voltages and currents satisfy the
Kirchhoff's laws and are consistent with the device characteristics and in which, in addition, the
condition of the loop gain being less than unity is satisfied.
The condition with respect to loop gain will certainly be satisfied, if either of the two devices is
below cut-off or if either device is in saturation. But normally the circuit is designed such that in
a stable state one transistor is in saturation and the other one is ir cut-off, because if one
transistor is biased to be in cut-off and the other one to be in active region, as the temperature
changes or the devices age and the device parameters vary, the quiescent point changes and the
quiescent output voltage may also change appreciably Sometimes the drift may be so much that
the device operating in the active region may gc into cut-off, and with both the devices in cut-off
the circuit will be useless.

Selection of components in the fixed-bias bistable multivibrator

In the fixed-bias binary shown in Figure 4.1., nearly the full supply voltage V cc will

appear across the transistor that is OFF. Since this supply voltage Vcc is to be reasonably smaller

than the collector breakdown voltage SVce. Vcc *s restricted to a maximum of a few tens of

volts. Under saturation conditions the collector current Ic is maximum. Hence RC must be

chosen so that this value of 7C (= VCC/^G) does not exceed the maximum permissible limit. The
values of R\, /?2 and VBB must be selected such that in one stat>le state the base current is large
enough to drive the transistor into saturation whereas in the second stable state the emitter

junction must be below cut-off. The signal at a collector called the output swing V w is the

change in collector voltage resulting from a transistor going from one state to the other, i.e. V w

= VCi - ^C2- If the loading caused by RI can be neglected, then the collector voltage of the OFF

transistor is Vcc. Since the collector saturation voltage is few tenths of a volt, then the swing V w

= Vcc, independently of RQ- The component values, the supply voltages and the values of /CBO,

h^, VBE(sat), and VCE(sat) are sufficient for the analysis of transistor binary circuits.
Loading
The bistable multivibrator may be used to drive other circuits and hence at one or both
the collectors there are shunting loads, which are not shown in Figure 4.1. These loads reduce the
magnitude of the collector voltage VC1 of the OFF transistor. This will result in reduction of the

output voltage swing. A reduced VC[ will decrease 7B2 and it is possible that Q2 may not be
driven into saturation- Hence the flip-flop circuit components must be chosen such that under the
heaviest load, which the binary drives, one- transistor remains in saturation while the other is in
cut-off. Since the resistor Rl also loads the OFF transistor, to reduce loading, the value of R]

should be as large as possible compared to the value of Rc. But to ensure a loop gain in excess of
unity during the transition between the states, R^ should be selected such that For some
applications, the loading varies with the operation being performed. In such cases, the extent to
which a transistor is driven into saturation is variable. A constant output swing V\v = V, arid a

constant base saturation current IB2 can be obtained by clamping the collectors to an auxiliary

voltage V < Vcc through the diodes DI and D2 as indicated in Figure 4.2. As Qi cuts OFF, its
collector voltage rises and when it reaches V, the "collector catching diode" D| conducts and
clamps the output to V.
Transistor as an ON-OFF switch
In digital circuits transistors operate either in the cut-off region or in the saturation
region. Specially designed transistors called switching transistors with negligible active region
are used. In the cut-off region the transistor does not conduct and acts as a open switch. In the
saturation region the transistor conducts heavily and acts as a closed switch-In a binary which
uses two cross-coupled transistors, each of the transistors is alternately cut-off and driven into
saturation. Because of regenerative feedback provided both the transistors cannot be.ON or both
cannot be OFF simultaneously. When one transistor is ON, the other is OFF and vice versa.
THE EMITTER-COUPLED BINARY (THE SCHMITT TRIGGER CIRCUIT)

Figure 4.29 shows the circuit diagram of an emitter-coupled bistable multivibrator using n-p-n
transistors. Quite commonly it is called Schmin trigger after the inventor of its vacuum-tube
version. It differs from the basic collector-coupled binary in that the coupling from the output of the
second stage to the input of the first stage is missing and the feedback is obtained now through a
common emitter resistor RE. It is a bistable circuit and the existence of only two stable states results
form the fact that positive feedback is incorporated into the circuit, and from the further fact that the loop
gain of the circuit is greater than unity. There are several ways to adjust the loop gain. One way of
adjusting the loop gain is.by varying /?C1. Suppose RC] is selected such that the loop gain is less than

unity. When fl cl is small, regeneration is not possible.

For the circuit of Figure 4.29, under quiescent conditions Qi is OFF and Q 2 is ON because it gets

the required base drive from VCc through RCi and /?j. So the output voltage

is at its lower level. With Q2 conducting, there will be a voltage drop across RE -7B2)/?E> and this will
elevate the emitter of Q\. As the input v is increased from zero, the circuit will not respond until Qi
reaches the cut-in point (at v = Vt). Until then the output remains at its lower level. With Oj

conducting (for v > V|) the circuit will amplify because Q2 is already conducting and since the gain

Av</Av is positive, the output will rise in response to the rise in input. As v continues to rise, C t and

hence B2 continue to fall and E2 continues to rise. Therefore a value of v will be reached at which Qa

is turned OFF. At this point v0 = VCc and the output remains constant at this value of Vcc, even if the

input is further increased. A plot of va versus v is shown in Figure 4.30(a) for loop gain < 1.
Suppose the loop gain is increased by increasing the resistance Rci. Such a change will have negligible
effect on the cut-in point V| of Qj. However in the region of amplification (i.e. for v > V{) the amplifier
gain Av</Av will increase and so the slope of the rising portion of the plot in Figure 4.30(a) will be
steeper. This increase in slope with increase in loop gain continues until at a loop gain of unity where the
circuit has just become regenerative the slope will become infinite. And finally when the loop gain
becomes greater than unity, the- slope becomes negative and the plot of va versus v assumes the S shape
shown in Figure 4.30(b).

Figure 4.30 Response of emitter-coupled binary for (a) loop gain < 1 and (b) loop gain > 1.
The behaviour of the circuit may be described by using this S curve. As v rises from zero voltage, v0 will

remain at its lower level (= VCc ~ 'c2 ^ca) unt*l v reaches V\. (This value of v = V, at which the transistor

Qi just enters into conduction is called the upper triggering point, UTP.) As v exceeds V} the output will

make an abrupt .transition to its higher level (= Vcc). For v > Vh Qj is ON and Q2 is OFF. Similarly if v
is initially greater than V], then as v is decreased, the output will remain at its upper level until v attains a
definite level V2 at which point the circuit makes an abrupt transition to its lower level. For v < ^2> Qi is

OFF and Q2 is ON. (This value of v = V2 at which the transistor Q2 resumes conduction is called the
lower triggering point, LTP.) This circuit exhibits hysteresis, that is, to effect a transition in one direction
we must first pass beyond the voltage at which the reverse transition took place.
A vertical line drawn at v = V which lies between V2 and Vi intersects the S curve at three points a, b
and c. The upper and lower points a and c are points of stable equilibrium.
The S curve is a plot of values which satisfy Kirchhoff's laws and which are consistent with the transistor
characteristics. At v = V, the circuit will be at a or c, depending on the direction of approach of v towards
V. When v = V in the range between V2 and V|, the Schmitt circuit is in one of its two possible stable
states and hence is a bistable circuit.
Applications of Schmitt trigger circuit
Schmitt trigger is also a bistable multivibrator. Hence it can be used in applications where a normal binary
is used. However for applications where the circuit is to be triggered back-and-forth between stable states,
the normal binary is preferred because of its symmetry. Since the base of Q] is not involved in
regenerative switching, the Schmitt trigger is preferred for applications in which the advantage of this free
terminal can be taken. The resistance KC2 m me output circuit of Q2 is not required for the operation of the
binary. Hence this resistance may be selected over a wide range to obtain different output signal
amplitudes.
A most important application of the Schmitt trigger is its use as an amplitude comparator to mark the
instant at which an arbitrary waveform attains a particular reference level. As input v rises to Vi or falls to
V2, the circuit makes a fast regenerative transfer to its other state.
Another important application of the Schmitt trigger is as a squaring circuit. It can convert a sine wave
into a square wave. In fact, any slowly varying input waveform can be converted into a square wave with
faster leading and trailing edges as shown in Figure 4.31, if the input has large enough excursions to
carry the input beyond the limits of the hysteresis range, VH = V\ - V2.

Figure 4.31 Response of the emitter-coupled binary to an arbitrary input waveform.

In another important application, the Schmitt trigger circuit is triggered between its two stable states by
alternate positive and negative pulses. If the input is biased at a voltage V between V2 and V\ and if a

positive pulse of amplitude greater than V\ - V is coupled to the input, then Qj will conduct and Q2 will

be OFF. If now a negative pulse of amplitude larger than V - V2 is coupled to the input, the circuit will be

triggered back to the state where Qj is OFF and Q2 is ON.

Hysteresis
If the amplitude of the periodic input signal is large compared with the hysteresis range V H, then the
hysteresis of the Schmitt trigger is not a matter of concern. In some applications, a large hysteresis
range will not allow the circuit to function properly.
Hysteresis may be eliminated by adjusting the loop gain of the circuit to unity. Such an adjustment
may be made in a number of ways:
(1) The loop gain may be increased or decreased by increasing or decreasing the resistance
^ci-
(2) The loop gain may be increased or decreased by adding a resistance /?E1 in series

with the emitter of Qi, or by adding a resistance 7?^ in series with the emitter of Q 2 and then decreasing

or increasing REl and RE2. Since /?C1 and RE] are in series with Qi, these resistors will have no effect on

the circuit when Qi is OFF. Therefore, these resistors will not change V\ but may be used to move V2

closer to or coincident with V\. Similarly, RE2 will affect V\ but not V2.

(3) The loop gain may also be varied by varying the ratio R[/(Ri + /?2). Such an adjustment

will change both V\ and V2.

(4) The loop gain may be increased by increasing the value of R$.
If /?E1 or RE2 is larger than the value required to give zero hysteresis, then the gain will be less than

unity and the circuit will not change state. So, usually RE\ or /?E2 is chosen so that a small amount of
hysteresis remains in order to ensure that the loop gain is greater than unity.
Vi is independent of Rs but V2 depends on R$ and increases with an increase in the value of Rs. So for a

large value of Rs it is possible for V2 to be equal to V\, Hysteresis is thus eliminated and the gain is unity.

If Rs exceeds this critical value, the loop gain falls below unity and the circuit cannot bs triggered. If Rs
is too small, the speed of operation of the circuit is reduced.
Derivation of expression for UTP
The upper triggering point UTP is defined as the input voltage Vl at which the transistor Qi just enters

into conduction. To calculate Vb we have to first find the current in Q2 when Q! just enters into
conduction. For this we have to find the Thevenin's equivalent voltage V and the Thevenin's equivalent
resistance tfB at the base of Q2, where

It is possible for Q2 to be in its active region or to be in saturation. Assuming that Q 2 is in its active region
In the circuit shown in Figure 4.32, to calculate V\, we replace Vcc, KCI> ^i anc* ^2 of Figure 4.29 by V

and RB at the base of Q2.

Figure 4.32 The equivalent circuit of Figure 4.29 with Q| just at cut-in.

Writing KVL around the base loop of Q2,

Since VyJ is the voltage from base to emitter at cut-in where the loop gain just exceeds unity, it

differs from VBE2 in the active region by only 0.1 V for either Ge or Si.

This indicates that V, may be made almost independent of h^, of the emitter resistance RE, of the
temperature and of whether or not a silicon or germanium transistor is used. Hence the discriminator
level Vt is stable with transistor replacement, ageing, temperature changes, provided that (/ IPE + l)/?E »

RB and that V" » 0.1. Since V depends on Vcc, RCI, R\ and R2, where stability is required it is necessary
that a stable supply and stable resistors are selected.
Derivation of expression for LTP
The lower triggering point LTP is defined as the input voltage V2 at which the transistor Q2 resumes

conduction. Vi can be calculated from the circuit shown in Figure 4.33 which is obtained by replacing V cc,

J?C1, RI and R2 of Figure 4.29 by Thevenin's equivalent voltage VTH and Thevenin's equivalent resistance

R at the collector of Q(, where

Figure 433 The equivalent circuit of Figure 4.29 when Q2 just resumes conduction.

The voltage ratio from the collector of Qi to the base of Q 2 is Figure 4.33, the

input signal to Qi is decreasing, and when it reaches V2 then Q2 comes out of cut-off.

Writing KVL around the base circuit of Q2,

Since VBE| is higher for silicon than germanium, the LTP Va is a few tenths of a volt higher for a
Schmitt trigger using silicon transistors than for one using germanium transistors.
MONOSTABLE MULTIVIBRATOR
As the name indicates, a monostable multivibrator has got only one permanent stable state, the other state
being quasi stable. Under quiescent conditions, the monostable multivibrator will be in its stable state
only. A triggering signal is required to induce a transition from the stable state to the quasi stable state.
Once triggered properly the circuit may remain in its quasi stable state for a time which is very long
compared with the time of transition between the states, and after that it will return to its original state. No
external triggering signal is required to induce this reverse transition. In a monostable multivibrator one
coupling element is a resistor and another coupling element is a capacitor.
When triggered, since the circuit returns to its original state by itself after a time T, it is known as a one-
shot, a single-step, or a univibrator. Since it generates a rectangular waveform which can be used to
gate other circuits, it is also called a gating circuit. Furthermore, since it generates a fast transition at a
predetermin6d time T after the input trigger, it is also referred to as a delay circuit. The monostable
multivibrator may be a collector-coupled one, or an emitter-coupled one.
THE COLLECTOR COUPLED MONOSTABLE MULTIVIBRATOR
Figure 4.41 shows the circuit diagram of a collector-to-base coupled (simply called collector-
coupled) monostable multivibrator using n-p-n transistors. The collector of Q2 is coupled to the base of

Qi by a resistor R} (dc coupling) and the collector of Qt is coupled to the base of Q2 by a capacitor C (ac
coupling). Ci is the commutating capacitor introduced to increase the speed of operation. The base of Qi
is connected to -VBB through a resistor R2, to ensure that Q! is cut off under quiescent conditions. The
base of Q2 is connected to VCc through R to ensure that Q2 is ON under quiescent conditions. In fact, R

may be returned to even a small positive voltage but connecting it to Vcc is advantageous.
The circuit parameters are selected such that under quiescent conditions, the monostable multivibrator
finds itself in its permanent stable state with Q2ON (i.e. in saturation) and Q! OFF (i.e. in cut-off)- The
multivibrator may be induced to make a transition out of its stable state by the application of a negative
trigger at the base of Q2 or at the collector of Q|. Since the triggering signal is applied to only one device
and not to both the devices simultaneously, unsymmetrical triggering is employed.
When a negative signal is applied at the base of Q2 at t ~ 0, due to regenerative action Q2 goes to

OFF state and Qi goes to ON state. When Q, is ON, a current /i flows through its Rc and hence its

collector voltage drops suddenly by I\RC This drop will be instantaneously

Figure 4.41 Circuit diagram of a collector-coupled monostable multivibrator.

transmitted through the coupling capacitor C to the base of Q 2. So at t = 0+, the base voltage of Q2 is

The circuit cannot remain in this state for a long time (it stays in this state only for a finite time T) because
when Qt conducts, the coupling capacitor C charges from Vcc through the conducting transistor Qi and

hence the potential at the base of Q2 rises exponentially with a time constant

where R0 is the conducting transistor output impedance including the resistance Rc. When it passes the

cut-in voltage Vy of Q2 (at a time t = T), a regenerative action takes place turning Q| OFF and
eventually returning the multivibrator to its initial stable state.
The transition from the stable state to the quasi-stable state takes place at t = 0, and the reverse transition
from the quasi-stable state to the stable state takes place at t = T. The time T for which the circuit is in its
quasi-stable state is also referred to as the delay time, and also as the gate width, pulse width, or pulse
duration. The delay time may be varied by varying the time constant t(= RC).
Expression for the gate width T of a monostable multivibrator neglecting the reverse
saturation current /CBO

Figure 4.42(a) shows the waveform at the base of transistor Q2 of the monostable multivibrator shown
in Figure 4.41.
For t < 0, Q2 is ON and so vB2 = VBE(sat). At t = 0, a negative signal applied brings Q2 to OFF state and

Q[ into saturation. A current /| flows through Rc of Qt and hence vci drops abruptly by /|7? c volts and so

vB2 also drops by I\RC instantaneously. So at t - 0, vB2 = VBE(sat) - I}RC. For t > 0, the capacitor charges

with a time constant RC, and hence the base voltage of Q2 rises exponentially towards VCc with the same

time constant. At t = T, when this base voltage rises to the cut-in voltage level Vy of the transistor, Q2
goes to ON state, and Qj to OFF state and the pulse ends.

In the interval 0 < t < 7", the base voltage of Q2, i.e. vB2 is given by

Figure 4.42(a) Voltage variation at the base of Q2 during the quasi-stable state (neglecting /cuoX
Normally for a transistor, at room temperature, the cut-in voltage is the average of the saturation junction

voltages for either Ge or Si transistors, i.e.

Neglecting the second term in the expression for T

but for a transistor in saturation Ra « R.

Gate width, T = 0.693KC

The larger the Vcc is, compared to the saturation junction voltages, the more accura the result is.
The gate width can be made very stable (almost independent of transistor characteristic supply
voltages, and resistance values) if Ql is driven into saturation during the quasi-stab state.

Expression for the gate width of a monostable multivibrator considering th

reverse saturation current /CBO
In the derivation of the expression for gate width T above, we neglected the effect of tt reverse
saturation current /CBO on the gate width T. In fact, as the temperature increases, tt reverse saturation
current increases and the gate width decreases.
In the quasi-stable state when Q2 is OFF, /CBO flows out of its base through R to th supply Vcc. Hence

the base of Q2 will be not at Vcc but at Vcc + /CBO^> ^ C *s disconnect from the junction of the base of

Q2 with the resistor R. It therefore appears that the capacitt C in effect charges through R from a source

Vcc + /CBO^- See Figure 4.42(b).

 Figure 4.42(b) Voltage variation at the base of Q2 during the quasirstable state (considering

Neglecting the junction voltages and the cut-in voltage of the transistor,

Since /CBO increases with temperature, we can conclude that the delay time T decreases
as temperature increases.
Waveforms of the collector-coupled monostable multivibrator
The waveforms at the collectors and bases of both the transistors Q] and Q2 of the
monostable multivibrator of Figure 4.41 are shown in Figure 4.44.

The triggering signal is applied at t = 0, and the reverse transition occurs at t = T.

The stable state. For t < 0, the monostable circuit is in its stable state with Q2 ON and Q, OFF. Since Q2

is ON, the^ase voltage of Q2 is vB2 = VBE2(sat) and the collector voltage of Q2 is vC2 = VCE2(sat). Since

Q, is OFF, there is no current in Rc of Q! and its base voltage must be negative. Hence the voltage at the

collector of Q| is, vC1 = VCC

and the voltage at the base of Q] using the superposition theorem is

The quasi-stable state. A negative triggering signal applied at t = 0 brings Q2 to OFF state and Qi to ON state.

A current /, flows in tfc of Q]. So, the collector voltage of Qj drops suddenly by I}RC volts. Since the

voltage across the coupling capacitor C cannot change instantaneously, the voltage at the base of Q 2

also drops by /itfc, where I{RC = Vcc -VcE2(sat)- Since Qi is ON,

In the interval 0 < t < T, the voltages VGI, VBI and Vc2 remain constant at their values at f = 0, but the
voltage at the base of. Q2, i.e. vB2 rises exponentially towards Vcc with a time constant, t - RC, until at t

= T, vB2 reaches the cut-in voltage Vx of the transistor.

Waveforms for t > T. At / = 7*1", reverse transition -takes place. Q2 conducts and Qi is cut-off. The

collector voltage of Q2 and the base voltage of Qi return to their voltage levels for / < 0. The voltage vcl

now rises abruptly since Qt is OFF. This increase in voltage is transmitted to the base of Q 2 and drives Q2

heavily into saturation. Hence an overshoot develops in vB2 at t = 7**", which decays as the capacitor
recharges because of the base current. The magnitude of the base current may be calculated as follows.
Replace the input circuit of Q2 by the base spreading resistance r BB in series with the voltage VsE(sat) as

shown in Figure 4.43. Let 7B be the base current at t = 1*. The current in R may be neglected compared

to /'B.
From Figure 4.43,
 Figure 4.43 Equivalent circuit for calculating the overshoot at base 62 of Q3.

The jumps in voltages at B2 and C| are, respectively, given by

Since C] and B2 are connected by a capacitor C and since the voltage across the capacitts cannot
change instantaneously, these two discontinuous voltage changes 5 and 5' must bl equal.
Equating them,

vB2 and vcl decay to their steady-state values with a time constant
Figure 4.44 Waveforms at the collectors and bases of the collector-coupled monostable multivibrator. (a) at the
base of Q2, (b) at the collector of Qt, (c) at the collector of Q2, and (d) at the base o

ASTABLE MULTIVIBRATOR
As the name indicates an astable multivibrator is a multivibrator with no permanent stable state. Both
of its states are quasi stable only. It cannot remain in any one of its states indefinitely and keeps on
oscillating between its two quasi stable states the moment it is connected to the supply. It remains in
each of its two quasi stable states for only a short designed interval of time and then goes to the other
quasi stable state. No triggering signal is required. Both the coupling elements are capacitors (ac
coupling) and hence both the states are quasi stable. It is a free running multivibrator. It generates
square waves. It is used as a master oscillator.
There are two types of astable multivibrators:
1. Collector-coupled astable multivibrator
2. Emitter-coupled astable multivibrator
THE COLLECTOR-COUPLED ASTABLE MULTIVIBRATOR
Figure 4.53 shows the circuit diagram of a collector-coupled astable multivibrator using n-p-n
transistors. The collectors of both the transistors Qj and Q2 are connected to the bases

Figure 4.53 A collector-coupled astable multivibrator.

of the other transistors through the coupling capacitors C s and C2. Since both are ac couplings, neither
transistor can remain permanently at cut-off. Instead, the circuit has two quasi-stable states, and it makes
periodic transitions between these states. Hence it is used as a master oscillator. No triggering signal is
required for this multivibrator. The component values are selected such that, the moment it is connected
to the supply, due to supply transients one transistor will go into saturation and the other into cut-off, and
also due to capacitive couplings it keeps on-oscillating between its two quasi stable states.
The waveforms at the bases and collectors for the astable multivibrator, are shown in Figure 4.54. Let us say
at t = 0, Q2 goes to ON state and Q] to OFF state. So, for t < 0, Q2 was OFF and Qi was ON. Hence
for t < 0, vB2 is negative, vC2 = Vcc, VB! = VBE(sat) and vcj = VCE(sat). The capacitor C2 charges from Vcc

through R2 and vB2 rises exponentially towards V cc. At t = 0, vB2 reaches the cut-in voltage Vy and Q2

conducts. As Q2 conducts, its collector voltage Vc2 drops by /2/?c - ^cc ~ VcE(saO- This drop in vc2 is

transmitted to the base of Qj through the coupling capacitor C2 and hence vB1 also falls by /2/?c- Qi goes

to OFF state. So, VB] = VBE(sat) - /2tfc, and its collector voltage vcl rises towards VCc- This rise in vc] is

coupled through the coupling capacitor C2 to the base of Q2, causing an overshoot § in vB2 and the

abrupt rise by the same amount 8 in VCL as shown in Figure 4.51(c). Now since Q2 is ON, C\ charges

from Vcc through Rlt and hence VB] rises exponentially. At t = 7"], when VB! rises to VY, Qi conducts and

due to regenerative action Qi goes into saturation and Q2 to cut-off. Now, for t > T\, the coupling

capacitor C2 charges from Vcc through R2 and at / = 7", + 7"2, when vB2 rises to the cut-in voltage Vr, Q2

conducts and due to regenerative feedback Q2 goes to ON state and Q| to OFF state. The cycle of events
repeats and the circuit keeps on oscillating between its two quasi-stable states. Hence the output is a
square wave. It is called a square wave generator or square wave oscillator or relaxation oscillator. It is a
free running oscillator.
Expression for the frequency of oscillation of an astable multivibrator
On similar lines considering the waveform of Figure 4.54(b), we can show that the time T2 for which Q2 is

OFF and Qj is ON is given by The period of the waveform, The frequency of

oscillation,
If R{ = R2 = R, and Cs = C2 = C, then TI = T2 = 772

The frequency of oscillation may be varied over the range from cycles to mega cycles by varying RC. It is
also possible to vary the frequency electrically by connecting R\ and R2 to an auxiliary voltage source V

(the collector supply remains +VCC) and then varying this voltage V.
THE EMITTER-COUPLED ASTABLE MULTIVIBRATOR
An emitter-coupled astable multivibrator may be obtained by using three power supplies or a
single power supply.
Figure 4.63 shows the circuit diagram of a free-running emitter coupled multivibrator using n-p-n
transistors. Figure 4.64 shows its waveforms. Three power supplies are indicated for the sake of
simplifying the analysis. A more practical circuit using a single supply is indicated in Figure 4.65. Let
us assume that the circuit operates in such a manner that Qi switches between cut-off and saturation and
Q2 switches between cut-off and its active region.

Figure 4.63 The astable emitter-coupled multivibrator.

During the interval preceding t = t\, the capacitor C charges from a fixed voltage ^ BB ~ V0 through the
resistor RE2. All circuit voltages remain constant except vEN2, which falls asymptotically towards zero.

The transistor Q2 will begin to conduct when vEN2 falls to

Calculations at f = tf
When Q2 conducts, vEN2 and vEN1 rise. As vENi rises, Q] comes out of saturation and vCN1 (= vBN2)

also increases, causing a further increase in the current in Q2. Because of this regenerative action, Qi is

driven OFF and Q2 is driven into its active region where its base-to-emitter voltage is VBE2, its base

current is /B2 and its collector current is /C2. From Figure 4.64, we see that after transition, at t = rf.
At t\ there is an abrupt change Vp in vEN2.
Because of the capacitive coupling between emitters there must also be the same discontinuity VD
in VENI. Hence,

Neglecting junction voltages and /B2^ci compared with VCCi

The period
The interval T\ when Q2 conducts and Qi is OFF ends at t = t2- The transistor Qt will turn ON when

the base-to-emitter voltage reaches the cut-in value Vy or when VENi reaches the voltage

Since the base voltage of Qi is fixed, then to carry the transistor from the cut-in point to
saturation the emitter must drop. However this drop S is small, since S = Va~ Vr= 0.2 V. Because the

emitters are capacitively coupled there will be an identical jump S in vEN2, After / = t2, in the interval

T2, conditions are the same as they were for t < t\.
Therefore, the cycle of events described above is repeated and the circuit behaves as
an astable multivibrator.
From Figure 4.64(a), we see that the voltage VENI starts at V\ at t = t\ and falls to
*^BB - Vj,at f = t2. Since this decay is exponential with a time constant # E|C and
approaches zero asymptotically,
Assuming that the supply voltages are large compared with the junction voltages and assuming also that

/B2^Ei « ^ccb we find

Subject to the same approximations, T 2 is given by

If VCC| and VBB are arranged to be proportional to one another, then the frequency is independent of
the supply voltages.
When QJ is OFF, its collector-to-ground voltage is approximately VCC1 and equals the base-to-ground voltage

of Q2. Since it is desired that Q2 be in its active region, then VBN2 should be less than VCN2 or VCC[

< VCC2. Since Qj is to be driven into saturation, then its base voltage may be almost as large as its
collector supply voltage. However, to avoid driving Q\ too deeply into saturation it is better to arrange that
VBB < VCC1, A circuit which uses a single supply and which satisfies the requirements that V BB be

proportional to Vca and that VBB < VCC1 < VCC2 is shown in Figure 4.65. Since C' is a bypass capacitor

intended to maintain VBB constant, it is not involved in the operation of the circuit. We assume that /?! and

RI are small enough so that the voltage VBB at the junction of R} and R2 remains normally constant
during the entire cycle of operations of the multivibrator. Using Thevenin's theorem we see that the
circuit of Figure 4.65 is of the same form as that of Figure 4.63 with VCc2 ~ ^cc a°d with

The advantages and disadvantages of the emitter-coupled astable multivibrator over the collector-coupled
astable multivibrator are given below:
Advantages
1. It is inherently self-starting.
2. The collector of Q2 where the output is taken may be loaded heavily even capacitively.
3. The output is free of recovery transients.
4. Because it has an isolated input at the base of Qi, synchronization is convenient.
5. Frequency adjustment is convenient because only one capacitor is used.

Figure 4.65 The emitter-coupled multivibrator.

Disadvantages
1. This circuit is more difficult to adjust for proper operating conditions.
2. This circuit cannot be operated with T\ and T2 widely different.
3. This circuit uses more components than does the collector-coupled circuit.
 UNIT – IV
TIME BASE GENERATORS
TIME BASE GENERATORS
A time-base generator is an electronic circuit which generates an output voltage or current
waveform, a portion of which varies linearly with time. Ideally the output waveform should be a ramp.
Time-base generators may be voltage time-base generators or current time-base generators. A voltage
time-base generator is one that provides an output voltage waveform, a portion of which exhibits a
linear variation with respect to time. A current time-base generator is one that provides an output current
waveform, a portion of which exhibits a linear variation with respect to time. There are many important
applications of time-base generators, such as in CROs, television and radar displays, in precise time
measurements, and in time modulation. The most important application of a time-base generator is in
CROs. To display the variation with respect to time of an arbitrary waveform on the screen of an
oscilloscope it is required to apply to one set of deflecting plates a voltage which varies linearly with
time. Since this waveform is used to sweep the electron beam horizontally across the screen it is called
the sweep voltage and the time-base generators are called the sweep circuits.
GENERAL FEATURES OF A TIME-BASE SIGNAL
Figure 5.1(a) shows the typical waveform of a time-base voltage. As seen the voltage starting
from some initial value increases linearly with time to a maximum value after which it returns again to
its initial value. The time during which the output increases is called the sweep time and the time taken
by the signal to return to its initial value is called the restoration time, the return time, or the flyback
time. In most cases the shape of the waveform during restoration time and the restoration time itself are
not of much consequence. However, in some cases a restoration time which is very small compared with
the sweep time is required. If the restoration time is almost zero and the next linear voltage is initiated
the moment the present one is terminated then a saw-tooth waveform shown in Figure 5.1(b) is
generated. The waveforms of the type shown in Figures 5.1 (a) and (b) are generally called sweep
waveforms even when they are used in applications not involving the deflection of an electron beam.
In fact, precisely linear sweep signals are difficult to generate by time-base generators and
moreover nominally linear sweep signals may be distorted when transmitted through a coupling
network.
 Figure 5.1 (a) General sweep voltage and (b) saw-tooth voltage waveforms.
The deviation from linearity is expressed in three most important ways:
1 . The slope or sweep speed error, es

2. The displacement error, ed

3. The transmission error, e,

The slope or sweep-speed error, es

An important requirement of a sweep is that it must increase linearly with time, i.e. the rate of change
of sweep voltage with time be constant. This deviation from linearity is defined as

The displacement error, ed

Another important criterion of linearity is the maximum difference between the actual sweep
voltage and the linear sweep which passes through the beginning and end points of the actual sweep.
The displacement error ed is defined as

As shown in Figure 5.2(a), vs is the actual sweep and v's is the linear sweep.

The transmission error, et

When a ramp signal is transmitted through a high-pass circuit, the output falls away from the input
as shown in Figure 5.2(b). This deviation is expressed as transmission error et, defined as the
difference between the input and the output divided by the input at the end of the sweep
where as shown in Figure 5.2(b), V's is the input and Vs is the output at the end of the sweep,

i.e. at t = TS

Figure 5.2 (a) Sweep for displacement error and (b) sweep for transmission error.
If the deviation from linearity is small so that the sweep voltage may be approximated by the sum
of linear and quadratic terms in t, then the above three errors are related as

which implies that the sweep speed error is the more dominant one and the displacement error is the least
severe one.
METHODS OF GENERATING A TIME-BASE WAVEFORM
In time-base circuits, sweep linearity is achieved by one of the following methods.
1. Exponential charging. In this method a capacitor is charged from a supply voltage through a
resistor to a voltage which is small compared with the supply voltage.
2. Constant current charging. In this method a capacitor is charged linearly from a constant current
source. Since the charging current is constant the voltage across the capacitor increases linearly.
3. The Miller circuit. In this method an operational integrator is used to convert an input step
voltage into a ramp waveform.
4. The Phantastron circuit. In this method a pulse input is converted into a ramp. This is a version of the
Miller circuit.
5. The bootstrap circuit. In this method a capacitor is charged linearly by a constant current which
is obtained by maintaining a constant voltage across a fixed resistor in series with the capacitor.
6. Compensating networks. In this method a compensating circuit is introduced to improve the
linearity of the basic Miller and bootstrap time-base generators.
7. An inductor circuit. In this method an RLC series circuit is used. Since an inductor does not allow
the current passing through it to change instantaneously, the current through the capacitor more or less
remains constant and hence a more linear sweep is obtained.
EXPONENTIAL SWEEP CIRCUIT
Figure 5.3(a) shows an exponential sweep circuit. The switch S is normally closed and is open at t = 0. So for t
> 0, the capacitor charges towards the supply voltage V with a time constant RC. The voltage across

the capacitor at any instant of time is given by After an interval of time Tx when

the sweep amplitude attains the value Vs, the switch again closes. The resultant sweep waveform is
shown in Figure 5.3(b).

Figure 5.3 (a) Charging a capacitor through a resistor from a fixed voltage and (b) the resultant exponential waveform
across the capacitor.

The relation between the three measures of linearity, namely the slope or sweep speed error es, the

displacement error ed , and the transmission error e, for an exponential sweep circuit is derived below.

Slope or sweep speed error, es

We know that for an exponential sweep circuit of Figure 5.3(a),

Rate of change of output or slope is

For small Ts, neglecting the second and higher order terms
Neglecting the second and higher order terms

So the smaller the sweep amplitude compared to the sweep voltage, the smaller will be the slope error.
The transmission error, e,
From Figure 5.2(b),

The displacement error, ed

From Figure 5.2(a), we can see that the maximum displacement between the actual sweep and the
linear sweep which passes through the beginning and end points of the actual sweep occurs at t =T S / 2

The actual sweep vs is given by

The displacement error ed is given by

If a capacitor C is charged by a constant current /, then the voltage across C is ft/C. Hence the rate
of change of voltage with time is given by
Sweep speed = I/C
UNIJUNCTION TRANSISTOR
 As the name implies a UJT has only one p-n junction, unlike a BJT which has two p-n junctions.
It has a p-type emitter alloyed to a lightly doped n-type material as shown in Figure 5.4(a). There are two
bases: base B| and base B2, base B] being closer to the emitter than base B2. The p-n junction is formed
between the p-type emitter and n-type silicon slab.
Originally this device was named as double base diode but now it is commercially known as UJT. The
equivalent circuit of the UJT is shown in Figure 5.4(b). /?B] is the resistance between base B! and the

emitter, and it is basically a variable resistance, its value being dependent upon the emitter current i'E.

/?B2 is the resistance between base 62 and the emitter, and its value is fixed.

Figure 5.4 (a) Construction of UJT, (b) equivalent circuit of UJT, and (c) circuit when iE = 0.

If IE = 0, due to the applied voltage VBB, a current i results as shown in Figure 5.4(c).

From the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltage

where Vy is the cut-in voltage of the diode.

This value of emitter voltage which makes the diode conduct is termed peak voltage and is denoted by VP.

It is obvious that if VE < VP, the UJT is OFF and if VE > VP, the UJT is ON.
The symbol of UJT is shown in Figure 5.5(a). The input characteristics of UJT (plot of VE versus /E)
are shown in Figure 5.5(b). The main application of UJT is in switching circuits wherein rapid
discharge of capacitors is very essential. UJT sweep circuit is called a relaxation oscillator.
SWEEP CIRCUIT USING UJT
Many devices are available to serve as the switch S. Figure 5.6(a) shows the exponential sweep circuit in
which the UJT serves the purpose of the switch. In fact, any current-controlled negative-resistance
device may be used to discharge the sweep capacitor.
The supply voltage VyY and the charging resistor R must be selected such that the load line intersects
the input characteristic in the negative-resistance region. Assume that the UJT is OFF. The capacitor C
charges from VYY through R. When it is charged to the peak value VP, the UJT turns ON and the

capacitor now discharges through the UJT. When the capacitor discharges to the valley voltage Vv» tne
UJT turns OFF, and again the capacitor starts charging and the cycle repeats. The capacitor voltage
appears as shown in Figure 5.6(b). The expression for the sweep time Ts can be obtained as follows.

Figure 5.6 (a) UJT sweep circuit and (b) output waveform across the capacitor.
MILLER AND BOOTSTRAP TIME-BASE GENERATORS—BASIC PRINCIPLES
The linearity of the time-base waveforms may be improved by using circuits involving feedback. Figure
5.10(a) shows the basic exponential sweep circuit in which S opens to form the sweep. A linear sweep
cannot be obtained from this circuit because as the capacitor charges, the charging current decreases and
hence the rate at which the capacitor charges, i.e. the slope of the output waveform decreases. A
perfectly linear output can be obtained if the initial charging current / = VIR is maintained constant. This
can be done by introducing an auxiliary variable generator v whose generated voltage v is always equal
to and opposite to the voltage across the capacitor as shown in Figure 5.10(b). Two methods of
simulating the fictitious generator are discussed below.

Figure 5.10 (a) The current decreases exponentially with time and (b) the current remains constant.
In the circuit of Figure 5.10(b) suppose the point Z is grounded as in Figure 5.11(a). A linear sweep will
appear between the point Y and ground and will increase in the negative direction. Let us now replace
the fictitious (imaginary) generator by an amplifier with output terminals YZ and input terminals XZ as
shown in Figure 5.11(b). Since we have assumed that the generated voltage is always equal and opposite
to the voltage across the capacitor,

Figure 5.11 (a) Figure 5.10(b) with Z grounded and (b) Miller integrator circuit.
the voltage between X and Z is equal to zero. Hence the point X acts as a virtual ground. Now for the
amplifier, the input is zero volts and the output is a finite negative value. This can be achieved by using an
operational integrator with a gain of infinity. This is normally referred to as the Miller integrator circuit or
the Miller sweep.
Suppose that the point Y in Figure 5.10(b) is grounded and the output is taken at Z. A linear sweep will
appear between Z and ground and will increase in the positive direction. Let us now replace the
fictitious generator by an amplifier with input terminals XY and output terminals ZY as shown in Figure
5.12. Since we have assumed that the generated voltage v at any instant is equal to the voltage across the
capacitor vc, then v0 must be equal to v,-, and the amplifier voltage gain must be equal to unity. The
circuit of Figure 5.12 is referred to as the Bootstrap sweep circuit.

Figure 5.12 Bootstrap sweep circuit.

The Miller sweep
The Miller integrating circuit of Figure 5.11(b) is redrawn in Figure 5.13(a). A switch S at the closing
of which the sweep starts is included. The basic amplifier has been replaced at the input side by its input
resistance and on the output side by its Thevenin's equivalent. R0 is the output resistance of the
amplifier and A its open circuit voltage gain. Figure 5.13(b) is obtained by replacing V, R and tf, on the
input side by a voltage source V in series with a resistance R' where

Neglecting the output resistance in the circuit of Figure 5.13{b), if the switch is closed at t = 0 and if the
initial voltage across the capacitor is zero, then v0 (f = 0+) = 0, because at / = 0~, V; ~ 0 and since the
voltage across the capacitor cannot change instantaneously.

This indicates that the sweep starts from zero.

At t = ∞, the capacitor acts as an open-circuit for dc. So no current flows and therefore
Figure 5.13 (a) A Miller integrator with switch S, input resistance Rf and Thevenin's equivalent on the output side
and (b) Figure 5.13(a) with input replaced by Thevenin's equivalent.
This indicates that the output is exponential and the sweep is negative-going since A is a negative number.

where Vs is the sweep amplitude and V is the peak-to-peak value of the output.

The deviation from linearity is times that of an RC circuit charging directly from a source V.

If R0 is taken into account, the final value attained by v0 remains as before, AV = - \A\V. The initial
value however is slightly different.
To find v0 at t = 0+, writing the KVL around the mesh in Figure 5.13(b), assuming zero voltage across
the capacitor, we have

From the above equations, we find

Therefore, if R0 is taken into account, v0(t = 0+) is a small positive value and still it will be a negative-
going sweep with the same terminal value. Thus the negative-going ramp is preceded by a small positive
jump. Usually this jump is/small compared to the excursion AV', Hence, improvement in linearity
because of the increase in total excursion is negligible.
The bootstrap sweep
Figure 5.14 shows the bootstrap circuit of Figure 5.12. The switch S at the opening of which the
sweep starts is in parallel with the capacitor C. Here, /?,- is the input resistance, A is the open-circuit
voltage gain, and R0 is the output resistance of the amplifier.

Figure 5.14 Bootstrap circuit of Figure 5.12 with switch S which opens at ( = 0, input resistance Rf, and
Thevenin's equivalent of the amplifier on the output side.
At t = 0~, the switch was closed and so vt - 0, Since the voltage across the capacitor cannot change

instantaneously, at t = 0* also, v(- = 0 and hence Av, = 0, and the circuit shown in Figure 5.15 results.

The output has the same value at t = 0 and hence there is no jump in the output voltage at t = 0.
 Figure 5.15 Equivalent circuit of Figure 5.14 aU = 0.
At t = <*>, the capacitor acts as an open-circuit and the equivalent circuit shown in Figure 5.16 results.

Writing KVL in the circuit of Figure 5.16,

Since A « 1, and if R0 is neglected, we get

Since R0 « /?, v0 at t = 0 can be neglected compared to the value of v0 at t - <». Then the total excursion
of the output is given by

and the slope error is

This shows that the slope error is [1 - A + (R/Rj)] times the slope error that would result if the capacitor
is charged directly from V through a resistor.
Comparing the expressions for the slope error of Miller and bootstrap circuits, we can see that it is
more important to keep R/Rj small in the bootstrap circuit than in the Miller circuit. Therefore, the
Miller integrator has some advantage over the bootstrap circuit in that in the Miller circuit a higher
input impedance is less important.
THE TRANSISTOR MILLER TIME-BASE GENERATOR
Figure 5.17 shows the circuit diagram of a transistor Miller time-base generator. It consists of a three-
stage amplifier. To have better linearity, it is essential that a high input impedance amplifier be used for
the Miller integrator circuit. Hence the first stage of the amplifier of Figure 5.17 is an emitter follower.
The second stage is a common-emitter amplifier and it provides the necessary voltage amplification.
The third stage (output stage) is also an emitter follower for two reasons. First, because of its low
output impedance R0 it can drive a load such as the horizontal amplifier. Second, because of its high
input
impedance it does not load the collector circuit of the second stage and hence the gain of the second
stage can be very high. The capacitor C placed between the base of Qi and the emitter of Q 3 is the
timing capacitor. The sweep speed is changed from range to range by switching R and C and may be
varied continuously by varying VBB.

Under quiescent condition, the output of the Schmitt gate is at its lower level. So transistor Q 4 is ON.

The emitter current of Q4 flows through RI and hence the emitter is at a negative potential. Therefore the

diode D conducts. The current through R flows through the diode D and the transistor Q4. The capacitor
C is bypassed and hence is prevented from charging. When a triggering signal is applied, the output of
the Schmitt gate goes to its higher level. So the base voltage of Q4 rises and hence the transistor Q4 goes

OFF. A current flows now from 10 V source through RI. The positive voltage at the emitter of Q4 now
makes the diode D reverse biased. At this time the upper terminal of C is connected to the collector of Q4

which is in cut-off. The capacitor gets charged from VBB and hence a run down sweep output is obtained

at the emitter of Q3. At the end of the sweep, the capacitor C discharges rapidly through D and Q4.
Considering the effect of the capacitance C\, the slope or sweep speed error is given by

THE TRANSISTOR BOOTSTRAP TIME-BASE GENERATOR

Figure 5.18 shows a transistor bootstrap time-base generator. The input to transistor Q] is the gating
waveform from a monostable multivibrator (it could be a repetitive waveform like a square wave).
Figure 5.19(a) shows the base voltage of Qj. Figure 5.19(b) shows the collector current waveform of Qj
and Figure 5.19(c) shows the output voltage waveform at the emitter of q2

Figure 5.18 A voltage time-base generator.

Quiescent conditions
Under quiescent conditions, i.e. before the application of the gating waveform at t - 0, Q| is in saturation
because it gets enough base drive from YCC through ^B- So the voltage across the capacitor which is
also the voltage at the collector of Qj and the base of Q2 is VCE (sat). Since Q2 is conducting and acting

as an emitter follower, the voltage at the emitter of Q2 which is also the output voltage is less than this
base

voltage by VBE2, i.e.

is a small negative voltage (a few tenths of a volt negative). If we neglect this small voltage as well as the
small drop across the diode D, then the voltage across C\ as well as across R is Vcc-Hence the current i>
through R i§ Vcc/R- Since the quiescent output voltage at the emitter of Q2 is close to zero, the emitter
current of Q2 is VEE/J?E. Hence the base current of Q2 is iB2 = VEE /

hFE RE iR = iC1 + iB2

Since the base current of Q2, i.e. /B2 is very small compared with the collector current iC1 of Q1

For Qj to be really in saturation under quiescent condition, its base current (( Bi = VCC/RB) t be at
least equal to I'CI#*FE> i.e. VCC//IFE^. so that

Formation of sweep
When the negative-going gating waveform is applied at t - 0, the transistor Q] is driven OFF. The current /Ci
now flows into the capacitor C and so the voltage across the capacitor rises according to the equation

Assuming unity gain for the emitter follower,

Since the voltage across C\ is constant and equal to VGO when the sweep starts, the diode is reverse
biased and the current through R is supplied by the capacitor C\ .
The equation, v0 ~ Vcct/RC is valid only if the gate duration Tg is small enough so that the calculated value of

v0 does not exceed Vcc- From Figure 5.18 it can be seen that when v0 approaches VCG, the voltage VCE of Q2

approaches zero and the transistor Q2 goes into saturation. Then it no longer acts as an emitter follower.

Hence v0 (also vc) remains constant at Vcc. The current Vcc/K through Ci and R now flows from base to

emitter of Q2.

If the output v0 reaches the voltage Vcc m a time Ts < Tg, then Vcc = Vcc TS / RC or TS = RC
Figure 5.19 Voltage time-base generator of Figure 5.18: (a) the base voltage of Q1% (b) the collector current of
Qi, and (c) the output voltage at the emitter of Q2-
whereas if the sweep amplitude Vs is less than Vcc> then the maximum ramp voltage is given by

Retrace interval
At t = Tg, when the gate terminates, the transistor Qi goes into conduction and a current r' Bi = VCC/R-Q
flows into the base of Qi. Hence a current/ci =/ IFE*BI flows into the collector of Qj. This current
remains constant till the transistor goes into saturation. Since Q] is ON the capacitor C discharges
through Qi. Because of emitter follower action, when vc falls, v0 also falls by the same amount and so

the voltage across R remains constant at Vcc. The constant current iR = Vcc/R also flows through Qi.

Applying KVL at the collector of Qi and neglecting /B2,

Since the discharging current of C, i.e. IA is constant, the voltage across C and hence the output
voltage falls linearly to its initial value.
If the retrace time is Tr, then the charge lost by the capacitor = IA Tr

where Vs is the sweep amplitude. That is,

After C is discharged, the collector current is now supplied completely through R and
becomes established at the value V^c/R- The retrace time can be reduced by choosing a small
value of Rs. However if RR is reduced greatly, then the collector current dissipation may be
excessive.

The recovery process

During the entire interval the capacitor C[ discharges at a constant rate because the

Current through it has remained constant. So it would have lost a charge

Hence at the time T when the voltage across C and at the base of Q2 returns to its value for t< 0, the
voltage across Ci is smaller than it was at the beginning of the sweep. The diode D starts conducting at t
- T, and the end of Ci, which is connected to D, returns to its initial voltage, i.e. Vcc- Therefore,.the
other terminal of Ci which is connected to the emitter of Ch is at a more positive potential than it was at
t = 0 and so Q2 goes to cut-off. So the capacitor Ci charges through the resistor RE with a current,

The maximum recovery time T\ for C\ can be calculated as follows.

Charge lost by capacitor Ci in time T is

Charge gained by capacitor Ci in minimum recovery time T\

is
This shows that T\ is independent of C\ and varies inversely with VEE. T\ can be reduced by increasing

VEE. However this modification will increase the quiescent current in Q2 and hence its dissipation.

CURRENT TIME-BASE GENERATORS

We have mentioned earlier that a linear current time-base generator is one that provides an output current
waveform a portion of which exhibits a linear variation with respect to time. This linearly varying
current waveform can be generated by applying a linearly varying voltage waveform generated by a
voltage time-base generator, across a resistor. Alternatively, a linearly varying current waveform can be
generated by applying a constant voltage across an inductor. Linearly varying currents are required for
magnetic deflection applications.
A SIMPLE CURRENT SWEEP
Figure 5.26(a) shows a simple transistor current sweep circuit. Here the transistor is used as a switch and the
inductor L in series with the transistor is bridged across the supply voltage. Rd represents the sum of the diode
forward resistance and the damping resistance. The gating waveform shown in Figure 5.26(b) applied to the
base of the transistor is in two levels. These levels are selected such that when the input, is at the lower level
the transistor is cut-off and when it is at the upper level the transistor Is in saturation. For t < 0, the input to
the base is at its lower level (negative). So the transistor is cut-off. Hence no currents flow in the transistor
and iL = 0 and VCE = Vcc- At f = 0, the gate signal goes to its upper level (positive). So the transistor conducts

and goes into saturation. Hence the collector voltage falls to v CE(sat) and the entire supply voltage Vcc is
applied across the inductor. So the current through the inductor

increases linearly with time. This continues till t = Tg, at which time the gating signal comes to its lower

level and so the transistor will be cut-off. During the sweep interval Ts (i.e. from t = 0 to t = Tg), the

diode D is reverse biased and hence it does not conduct. At t ~ Ts, when the transistor is cut-off and no
current flows through it, since the current through the inductor cannot change instantaneously it flows
through the diode and the diode conducts. Hence there will be a voltage drop of lLRd across the

resistance Rd. So at t = Tg, the potential at the collector terminal rises abruptly to Vcc + fiftd* i-e- there is

a voltage spike at the collector at t = Tg. The duration of the spike depends on the inductance of Z-^but
the amplitude of the spike does not. For t > Tg, the inductor current decays exponentially to zero with a

time constant T- LIRd. So the voltage at the collector also decays exponentially and settles at Vcc under

steady-state conditions. The inductance L normally represents a physical yoke and its resistance RL may

not be negligible. If RCs represents the collector saturation resistance of the transistor, the current
increases in accordance with the equation

If the current increases linearly to a maximum value IL, the slope error is given by

The inductor current waveform and the waveform at the collector of the transistor are shown in
Figures 5.26(c) and 5.26(d) respectively. To maintain linearity, the voltage (RL + /?csXt across the

total circuit resistance must be kept small compared with the supply voltage Vcc.
A TRANSISTOR CURRENT TIME-BASE GENERATOR

Figure 5.30 shows the circuit diagram of a transistor current time-base generator. Transistor Q! is a
switch which serves the function of S in Figure 5.29. Transistor Qi gets enough base drive from VCC1

through KB a°d hence is in saturation under quiescent conditions. At / = 0, when the gating signal is

applied it turns off Qi and a trapezoidal voltage waveform appears at the base of Q 2. Transistors Q2 and

Q3 are connected as darlington pair to increase the input impedance so that the trapezoidal waveform
source is not loaded. Such loading would cause nonlinearity in the ramp part of the trapezoid.
The emitter resistor RE introduces negative current feedback into the output stage and thereby improves the
linearity with which the collector current responds to the base voltage. For best linearity it is necessary
to make the emitter resistance as large as possible. RE is selected so that the voltage developed across
it will be comparable to the supply voltage
 UNIT – V
SAMPLING GATES AND LOGIC GATES

IC families:
comparison of the important characteristics of various IC logic families.

(i) CMOS inverter

(ii) Tristate logic
(i) CMOS Inverter: It is complementary MOSFET obtained by using P-channel MOSPET and
n-channel MOSFET simultaneously. The P and N channel are connected in series, their drains
are connected together, output is taken from common drain point. Input is applied at common
gate terminal. CMOS is very fast and consumes less power.
Case 1. When input Vi = 0. The (Gate source) voltage of Q1 will be 0 volt, it will be off.
But Q2 will be ON; Hence output will be equal to +VDD or logic 1.

Case 2. When input Vi = 1, The (Gate source) voltage of Q2 will be 0 volt, it will be
OFF, But Q1 will be ON. Hence output will be connected to•
ground or logic 0.
In this way, CMOS function as an inverter.
(ii) Tri-state logic: When there are three states i.e. state 0, state 1 and high impendence i.e.
called Tri-state logic. High impedance is considered as state when no current pass through
circuit. Although in state 0 and state 1 circuit functions and current flows through it.
 Propagation delay is the average transition delay time for a pulse to propagate from

input to output of a switching circuit.

 Fan-in is the number of inputs to the gate which it can handle. 
 Fan-out is the number of loads the output of a gate can drive without effecting its operation. 
 Power dissipation is the supply voltage required by the gate to operate with 50% duty
cycle at a given frequency
 RTL, DTL, DTL are the logic families which are now obsolete. 
 TTL is the most widely used logic family. 
 TTL gates may be: 
(a) Totem pole
(b) Open collector
(c) Tri-state .
 TTL is used in SSI and MSI Integrated circuits and is the fastest of all standard logic
families. 
 Totem pole TTL has the advantage of high speed and low power dissipation but its 
disadvantage is that it cannot be wired ANDed because of current spikes generation.
 Tri-state has three states : .
(a) High
 (b) Low
(c) High Impedance
 ECL is the fastest of all logic families because its propagation delay is very small i.e. of
about 2 nsec.
 ECL can be wired ORed. 
 MOS logic is the simplest to fabricate.
 MOS transistor can be connected as a resistor.
 MOSFET circuitry are normally constructed from NMOS devices because they are 3 times
faster than PMOS devices.
 CMOS uses both P-MOS and N-MOS.
 CMOS needs less power as compared to ECL as they need maximum power.
 Both NMOS and PMOS are more economical than CMOS because of their greater packing
densities.
 Speed of CMOS gates increases with increase in VDD. 
 CMOS has large fan-out because of its low output resistance. 
Schematic of RTL NOR gate and explain its operation.
RTL was the first to introduced. RTL NOR gate is as shown in fig.

Working:
Case I: When A = B = 0.
Both T1 and T2 transistors are in cut off state because the voltage is insufficient to drive the
transistors i.e. VBE < 0.6 V: Thus, output Y will be high, approximately equal to supply voltage
Vcc. As no current flows through Rc and drop across Rc is also zero.
Thus, Y = 1, when A = B = 0.
Case II : When A = 0 and B = 1 or A = 1 and B = 0.
The transistor whose input is high goes into saturation where as other will goes to off cut state.
This positive input to transistor increases the voltage drop across the collector resistor and
decreasing the positive output voltage.
Thus, Y = 0,when A= 0 and B = 1 or A = 1 and B = 0.

Case III : When A = B = 1. Both the transistors T1 and T2 goes into saturation and output
voltage is equal to saturation voltage.
Thus, Y = 0,when A = B = 1
Truth Table

Which is the output of NOR gate.

DCTL NAND gate with the help of suitable circuit diagram.
DCTL NAND gate circuit diagram is as shown:

Working
Case I: When A = B = 0. Both transistors T1 and T2 goes to cut off state. As the voltage is not
sufficient to drive the transistor into saturation. Thus, the output voltage equal to Vcc.
When A = B = 0, output Y = 1
Case II: When A = 0 and B = 1 or A = 1 and, B = 0. The corresponding transistor goes to cut
off state and the output voltage equals to Vcc.
Thus, When A = 0 and B = 1 or A = 1 and B = 0, Output Y = 1.
Case III: When A = B = 1. Both transistors T1 and T2 goes into saturation state and output
voltage is insufficient to consider as ‘1’
Thus when A B = 1, output Y = 0.
Truth Table

Which is the output of NAND gate.

Compare standard TTL, Low power TTL and high speed TTL logic families.

characteristics and specification of CMOS.

1 Power supply (VDD) = 3 — 15 Volts
2. Power dissipation (Pd) = 10 nW
3. Propagation delay (td) = 25 ns
4. Noise margine (NM) = 45% of
VDD 5, Fan out (FO) = >50
Two input ECL NOR gate
The circuit diagram of two input ECL NOR gate is as shown:
Working
Case I : When A = B = 0, the reference voltage of T3 is more forward biased then T1 and T2.
Thus, T3 is ON and T1, T2 remains OFF. The value of R1 is such-that the output of NOR gate is
high .i.e. ‘1’.

Case II: When A = 1 or B = 1 or A = B = 1, the corresponding transistors are ON, as they are
more forward biased that T3 and thus T3 is OFF. Which makes the NOR output to be low i.e.
‘0’.
This shows that the circuit works as a NOR gate.
TTL inverter.

Tristate TTL inverter utilizer the high-speed operation of totem-pole arrangement while
permitting outputs to be wired ANDed (connected together). It is called tristate TTL because it
allows three possible output stages. HIGH, LOW and High-Impedance. We know that transistor
T3 is ON when output is HIGH and T4 is ON when output is LOW. In the high impedance state
both transistors, transistor T3 and T4 in the totem pole arrangement are med OFF. As a result
the output is open or floating, it is neither LOW nor HIGH.
The above fig. shows the simplified tristate inverter. It has two inputs A and E. A is the normal
logic input whereas E is an ENABLE input. When ENABLE input is HIGH, the circuit works as
a normal inverter. Because when E is HIGH, the state-of the transistor T1 (either ON or OFF)
depends on the logic input A and the additional component diode is open circuited as cathode is
at logic HIGH. When ENABLE input is LOW, regardless of the state of logic input the base-
emitter junction of T is forward biased and as a result it turns ON. This shunts the current
through R1 away from T2 making it OFF. As T2 is OFF, there is no sufficient drive for T4
conduct and hence T4 turns OFF. The LOW at ENABLE input also forward biases diode D2,
which shunt the current away from the base of T3, making it OFF. In this way, when ENABLE
output is LOW, both transistors are OFF and output is at high impedance state.
ECL OR gate
ECL or gate : Emitter-coupled logic (ECL) is the fastest of all logic families and thus it is used
in applications where very high speed is essential. High speeds have become possible in ECL
because the transistors are used in difference amplifier configuration, in which they are never
driven into saturation and thereby the storage time is eliminated. Here, rather than switching the
transistors from ON to OFF and vice-versa, they are switched between cut-off and active
regions. Propagation delays of less than 1 ns per gate have become possible in ECL.
Basically, ECL is realized using difference amplifier in which the emitters of the two transistors
are connected and hence it referred to as emitter-coupled logic. A 3-input ECL gate is shown in
Fig. (A) which has three parts. The middle part is the difference amplifier which performs the
logic operation.
Emitter followers are used for d.c. level shifting of the outputs, so that V (0) and V (1) are same
for the inputs and the outputs. Note that two output Y1 and Y2 are available in this circuit which
are complementary. Y1. corresponds to OR logic and Y2 to NOR logic and hence it is named as
an OR/NOR gate.
Additional transistors are used in parallel to T1 to get the required fan-in. There is a fundamental
difference between all other logic families (including MOS logic) and ECL as far as the supply
voltage is concerned. In ECL, the positive end of the supply is connected to ground in contrast
to other logic families in which negative end of the supply is grounded. This is done to minimize
the effect of noise induced in the power supply and protection of the gate from an accidental
short circuit developing between the output of a gate and ground. The voltage corresponding to
V (0) and V (1) are both negative due to positive end of the supply being connected to ground.
The symbol of an ECL OR/NOR gate is shown in Fig. (B)

Open collector TTL NAND gate and explain its operation

The circuit diagram of 2-input NAND gate open-collector TTL gate is as shown:

Working:
Case.1 : When A = 0,B = 0
When both inputs A and B are low, both functions of Q1 are forward biased and Q2 remains off.
So no current flows through R4 and Q3 is also off and its collector voltage is equal to Vcc i.e. Y
=1
Case2 : When A = 0, B = 1 and
Case 3: When A = 1, B = 0
When one input is high and. other is low, then one junction is forward biased so Q2 is off and
Q3 is also off. So collector voltage is equal to Vcc i.e. Y = 1
Case 4: When A = 1, B = 1
When both inputs are high, Q1 is turned off and Q2 turned ‘ON’ Q3 goes into saturation and
hence Y = 0. The open-collector output has main advantage that wired ANDing is possible in it.
TTL NAND gate
Two input TTL NAND gate-is given in fig. (1). In this transistor T3 and T4 form a totem pole.
Such type of configuration is called-as totem-pole output or active pull up output.

So, when A = 0 and B = 1 or (+5V). T1 conducts and T2 switch off. Since T2 is like an open
switch, no current flows through it. But the current flows through the resistor R2 and into the
base of transistor T3 to turn it ON. T4 remains OFF because there is no path through which it
can receive base current. The output current flows through resistor R4 and diode D1. Thus, we
get high’ output.
When both inputs are high i.e. A = B = 1 or (+ 5V), T2 is ON and it drives T4 turning it ON. It
is noted that the voltage at the base of T3 equals the sum of the base to emitter drop of

T4 and of T2.
The diode D1 does not allow base-emitter junction of T3 to be forward-biased and hence, T3
remains OFF when T4 is ON. Thus, we get low output.
It works as TTL NAND gate.
Totem pole NAND gate
In TTL Totem pole NAND gate, multiple emitter transistor as input is used. The no. of inputs
may be from 2 to 8 emitters. The circuit diagram is as shown

Case 1:
When A = 0, B = 0
Now D1 and D2 both conduct, hence D3 will be off and make Q2 off. So its collector voltage
rises and make Q3 ‘ON’ and Q4 off; Hence output at Y = 1 (High)
Case 2 and Case 3:
If A = 0, B = 1 and A = 1, B=0
In both cases, the diode corresponding to low input will conduct and hence diode P3 will be
OFF making Q2 OFF. In a similar way its collector voltage rises Q3 ‘ON’ and Q4 ‘OFF’. Hence
output voltage Y = 1 (High).
Case 4: A = 1, B = 1
Both diodes D1 and D2 will be off. D3 will be ‘ON’ and Q2 will ‘ON’ making Q4 also ‘ON’.
But Q3 will be ‘OFF’. So output voltage Y = 0.
All the four cases shows that circuit operates as a NAND gate.
Totem pole can’t be Wired ANDed due to current spike problem. The transistors used in circuits
may get damaged over a period of time though not immediately. Sometimes voltage level rises
high than the allowable.