Tutorial 6: Sequential circuits

Design
Q1) [5 point] Design the T flip flop

A T flip-flop is a device which swaps or "toggles" state every time it is triggered if the T input is equal to
1, otherwise it holds the current output.

a) Design the T flip-flop by using the conventional D flip-flop. First, obtain the Moore
state diagram for the T flip-flop (T is the input variable).

b) Finish the state table below: d) Draw the sequential circuit using D flip-flop:
Current Input Next FF
state State input
Q(t) T Q(t+1) D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

c) Find the Boolean equation: D = Q(t+1) = = D = Q . T' + Q' . T = Q XOR T (Recall

that AB' + A'B = A XOR B)

e) Fill the following characteristic table and excitation table to describe the behavior of the
T flip-flop:

f) Finish the timing diagram:

Q2) [10 point] Design the JK flip flop

The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It
works just like a SR flip-flop where J is serving as set input and K serving as reset. The only difference is
that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its
state.

a) Design the JK flip-flop by using the conventional D flip-flop. First, obtain the Moore
state diagram for the JK flip-flop (Not this circuit has two input variable, namely J and
K).

b) Finish the state table below:

Current Next FF input

Input
state State Karnaugh map for
Q(t) J K Q(t+1) D Q(t+1)
0 0 0 0 0 Q(T)
0 0 1 0 0 J K 0 1
0 1 0 1 1 0 0 0 1
0 1 1 1 1
0 1 0 0
1 0 0 1 1
1 0 1 0 0 1 1 1 0
1 1 0 1 1 1 0 1 1
1 1 1 0 0

c) Find the Boolean equation: Q(t+1) and simplify using above K-map.

Q(t+1) = J . Q' + K' . Q

d) Draw the sequential circuit:

e) Fill the following characteristic table and excitation table to describe the behavior of the
JK flip-flop:

f) Finish the timing diagram:

Q3) [10 points] A reset-dominant flip-flop has set and reset inputs. It differs from a conventional SR
flip-flop in that, when both SD and RD are equal to 1, the flip-flop is reset.

a) Obtain the Moore state diagram and the state table for the reset-dominant flip-flop and

SD RD Q(t+1) Description
0 0 Q(t) Hold
0 1 0 Reset
1 0 1 Set
1 1 0 Reset

b) Design the reset-dominant flip-flop by using the conventional SR flip-flop.

Inputs Current Next Latch inputs

state state
SD RD Q(t) Q(t+1) S R Recall excitation table of SR latch:
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 X
1 1 1 0 0 1

c) Finish the timing diagram:

Q4) (10 points) State diagrams for Counters:

a) Design the state diagram of a counter that counts from 0 to 3 and repeats.

b) Design the state diagram of a counter that counts from 2 to 7 and repeats.

c) Design the state diagram of a counter that counts from 3 to 0 and repeats.

d) Design the state diagram of a counter that counts from 15 to 10 and repeats.

e) Design the state diagram of a counter that counts in the following order 4, 0, 7, 2, 1,6 and repeats.
f) Design the state diagram of a counter that counts from 0 to 3 and repeats. The conter has one
external input X. If X =1 , the counter works, and if X = 0, the counter resets, i.e. goes back to 0.

g) Design the state diagram of a counter that counts 0, 7, 3, 2, 5, 1 and repeats. The conter has one
external input X. If X =1 , the counter works, and if X = 0, the counter resets (i.e. goes back to 0).
Q6) [10 points] state diagrams for sequence recognizers:

a) Design a synchronous circuit with input X and one output Z that recognizes the input string 111 (Use
a moore type diagram.). For example:

X 1 1 0 1 1 1 1 1 1 1 0 1 1 1
Z 0 0 0 0 0 1 1 1 1 1 0 0 0 1

b) Redo the diagram this time using a mealy type:

c) Design a synchronous circuit with input X and one output Z that recognizes the input string 011. Use
a moore type diagram.

d) Design a synchronous circuit with input X and one output Z that recognizes the input string 101. It
should also recognize overlapping sequences. Use a moore type diagram.

e) Design a synchronous circuit with input X and one output Z that recognizes the input string 100. Use
a moore type diagram.
f) Design a synchronous circuit with input X and one output Z that recognizes the input string 1010. It
should also recognize overlapping sequences. Use a moore type diagram.

g) Design a synchronous circuit with input X and one output Z that recognizes the input string 0101. It
should also recognize overlapping sequences. Use a mealy type diagram.

h) Design a synchronous circuit with input X and one output Z that recognizes the input string 1001. It
should also recognize overlapping sequences. Use a mealy type diagram.

i) Design a synchronous circuit with input X and one output Z that recognizes the input string 0100. It
should also recognize overlapping sequences (Use a moore type diagram). For example:
j) Design a sequence detector for ‘11011’ (Use a moore type diagram). Overlap is allowed between
neighboring bit sequences. For instance, let X denote the input and Z denote the output. Assume
X=’11011011011’ and the detector will output Z=’00001001001’.

Q1) [20 points] The following is the state diagram for a sequential circuit:

a) [1 points] is this a mealy or moor type diagram? Moore type

b) [9 points] Find the state table for the circuit.

Present state Next state Output

X=0 X=1 Z
A B D 0
B D C 0
C A F 0
D F C 1
E C E 1
F E F 1
 a) [10 points] Make a state assignment for the circuit using 3-bit codes for the six states;
make one of the code bits equal to the output to save logic, and find the encoded state
table. The next states and outputs are don’t cares for the two unused state codes. Assume
A=000, B=001, C=010, D=100, E=101, F=110.

Present state Next state Output

X=0 X=1 Z
Y2 Y1 Y0 Y2 (+) Y1 (+) Y0 (+) Y2 (+) Y1 (+) Y0 (+)
A = 000 0 0 1 1 0 0 0
B = 001 1 0 0 0 1 0 0
011 X X X X X X X
C = 010 0 0 0 1 1 0 0
D = 100 1 1 0 0 1 0 1
E = 101 0 1 0 1 0 1 1
111 X X X X X X X
F = 110 1 0 1 1 1 0 1

b) Find an optimized cicuit implementation using D flip-flops, NAND gates, and inverters.

Y1Y0 00 01 11 01 Y1Y0 00 01 11 01
XY2 XY2
00 0 0 X 0 00 1 0 X 0
01 1 1 X 0 01 0 0 X 1
11 1 0 X 1 11 0 1 X 0
10 0 1 X 1 10 0 0 X 0

D1 = XY1 + XY2'Y0+X'Y2Y1'+Y2Y1'Y0' D0 = X Y2'Y1'Y0' + X'Y2'Y1+X'Y2Y0

Y1Y0 00 01 11 01 Y1Y0 00 01 11 01
XY2 Y2
00 0 1 X 0 0 0 0 X 0
01 1 0 X 1 1 1 1 X 1
11 0 1 X 1
10 0 0 X 1

D2 = X'Y2'Y0 + X'Y2Y0' + Y1Y2+ XY2Y0 + Z = Y2

XY2'Y0'

To use Nand gates, use Demorgans law:

D0 = X Y2'Y1'Y0' + X'Y2'Y1+X'Y2Y0
= ( (X Y2'Y1'Y0')' . (X'Y2'Y1)' . (X'Y2Y0)' )'
D1 = XY1 + XY2'Y0+X'Y2Y1'+Y2Y1'Y0'
= ( (XY1)' . (XY2'Y0)' . (X'Y2Y1')' . (Y2Y1'Y0')' )'

D2 = X'Y2'Y0 + X'Y2Y0' + Y1Y2+ XY2Y0 + XY2'Y0'

= ( (X'Y2'Y0)' . (X'Y2Y0')' . (Y1Y2)' . (XY2Y0)' . (XY2'Y0')' )
Q2) [20 points] A sequential circuit has 3 flip-flops, A, B, C; one input x; one output y. The state
diagram is shown below. The circuit is to be designed by treating the unused states as don’t care
conditions..

a) Derive state table assuming T flip-flops to be used in the implementation.

Current State Input Next State Output FF 2 FF 1 FF 0

Q2 Q1 Q0 X Q2(t+1) Q1(t+1) Q0(t+1) Y T2 T1 T0
0 0 0 0 0 1 1 0 0 1 1
0 0 0 1 1 0 0 1 1 0 0
0 0 1 0 0 0 1 0 0 0 0
0 0 1 1 1 0 0 1 1 0 1
0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 1 0 1 0
0 1 1 0 0 0 1 0 0 1 0
0 1 1 1 0 1 0 1 0 0 1
1 0 0 0 0 1 0 0 1 1 0
1 0 0 1 0 1 1 0 1 1 1
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
 a) Derive the Boolean equations for T2, T1, T0, and Y. Use k-maps and reduce them.

Q0X
Q2Q1 00 01 11 10
00 1 0 1 0
01 0 0 1 0
11 X X X X
10 0 1 X X

T2 = Q2 + Q1' . X T1 = Q1' . Q0' . X ' + Q2 + Q1 T0 = Q2' . Q1' . Q0' . X' + Q0

. Q0' . X + Q1 . Q0 . X ' . X + Q2 . X

Q0X
Q2Q1 00 01 11 10
00 0 1 1 0
01 0 1 1 0
11 X X X X
10 0 0 X X

Y = Q2' . X

b) Draw the circuit:

Q3) [20 points] Design a synchronous circuit with input X and one output Z that recognizes the input
string 1001. It should recognize overlapping sequences also. For example:
X 1 1 0 1 1 1 1 1 1 1 0 1 0 1
Z 0 0 0 0 0 0 1 1 1 1 0 0 0 0

(a) draw a Moore model state diagram:

(b) Asume: S0 = 000, S1 = 001, S2 = 010, S3 = 011, S4 = 100, build the state tables. Assume we will use
J-K flip-flops.

(c) Derive the boolean equations for J0,K0,J1,K1,J2, K2, and Z. Use k-maps and reduce them.
 J2 = Q1 . Q0 . X K2 = 1 Z = Q2

J1 = Q2 . X’ + Q0 . X’ K1 = Q0 + X

J0 = Q1 + X K0 = Q1 + X’

(d) Implement the circuit with J-K flip-flops

Q4) [20 points] Design a sequence detector for ‘11011’ using D flip-flops. Overlap is allowed between
neighboring bit sequences. For instance, let X denote the input and Z denote the output. Assume
X=’11011011011’ and the detector will output Z=’00001001001’.

a) Draw the state diagram:

b) Asume: A = 000, B = 001, C = 010, D = 011, E = 100, and F = 111. Build the state table.

Input Current State Next State Output FF 2 FF 1 FF 0

X Q2 Q1 Q0 Q2(t+1) Q1(t+1) Q0(t+1) Z D2 D1 D0
0 A 0 0 0 0 0 0 0 0 0 0
0 B 0 0 1 0 0 0 0 0 0 0
0 D 0 1 1 0 0 0 0 0 0 0
0 C 0 1 0 0 1 1 0 0 1 1
0 E 1 0 0 0 0 0 0 0 0 0
0 1 0 1 X X X X X X X
0 F 1 1 1 0 1 1 0 0 1 1
0 1 1 0 X X X X X X X
1 A 0 0 0 0 0 1 0 0 0 1
1 B 0 0 1 0 1 0 0 0 1 0
1 D 0 1 1 1 0 0 0 1 0 0
1 C 0 1 0 0 1 0 0 0 1 0
1 E 1 0 0 1 1 1 0 1 1 1
1 1 0 1 X X X X X X X
1 F 1 1 1 0 1 0 1 0 1 0
1 1 1 0 X X X X X X X
 c) Derive the Boolean equations for D2, D1, D0, and Z. Use k-maps and reduce them.

Q1Q0 Q1Q0 Q1Q0

XQ2 00 01 11 10 XQ2 00 01 11 10 XQ2 00 01 11 10
00 0 0 0 0 00 0 0 0 1 00 0 0 0 1
01 0 X 0 X 01 0 X 1 X 01 0 X 1 X
11 1 X 0 X 11 1 X 1 X 11 1 X 0 X
10 0 0 1 0 10 0 1 0 1 10 1 0 0 0

D2 = X . Q2 . Q1' + X . Q2' . D1 = X . Q2 + X . Q0 . Q1'+ D0 = X' . Q2 . Q1 + X' . Q1 .

Q1 . Q0 Q1 . Q0' + Q2 . Q1 Q0' + X . Q1' . Q0' + X . Q2 .
Q1'

Q1Q0
XQ2 00 01 11 10
00 0 0 0 0
01 0 X 0 X
11 0 X 1 X
10 0 0 0 0

Z = X . Q2 . Q1

Q5) [20 points] Design a sequential circuit that counts from 0 to 3, restarting from 0 after reaching 3. The
circuit has an input X. When X=1, the circuit increments. When X = 0, the circuit stops at the last
number. Use J-K flip flops.

c) [5 points] Draw the state diagram:

 c) [10 points] Find the state table for the circuit.

Current State Input Next State J K values

Y1 Y0 X Y1+ Y0+ J1 K1 J0 K0
00 0 0 0 0 X 0 X
00 1 0 1 0 X 1 X
01 0 0 1 0 X X 0
01 1 1 0 1 X X 1
10 0 1 0 X 0 0 X
10 1 1 1 X 0 1 X
11 0 1 1 X 0 X 0
11 1 0 0 X 1 X 1

d) [10 points] Use k-maps to find and reduce the Boolean functions for J1, K1, J0, K0

Y0X Y0X
Y1 00 01 11 10 Y1 00 01 11 10
0 0 0 1 0 0 X X X X
1 X X X X 1 0 0 1 0
J1 = Y0 X K1 = Y0 X
Y0X Y0X
Y1 00 01 11 10 Y1 00 01 11 10
0 0 1 X X 0 X X 1 0
1 0 1 X X 1 X X 1 0
J0 = X K0 = X

a) [5 points] Draw the sequential circuit.

Q6) [[10 points] Find the response for the following state machine diagram to the following sequence of
inputs (assume the initial state is STA).

W 0 1 1 0 1 1 0 1
X 1 1 0 1 0 1 0 1
Y 0 1 0 1 0 1 0 1
State STA STA STB STC STA STB STC STA STB
Z 0 0 0 1 0 0 1 0

Q7) [10 points] Find the state table for the following state machine diagram.

Transition Next state Output

condition
STA
W' STA
W STB
STB
X'Y STA
X STC
X'Y' STC Z
STC STA Z
Q8) [5 points] Complete the following state machine diagram for a circuit that detects a difference in
value in an input signal X at two successive positive clock edges. If X has different values at two
successive positive clock edges, then output Z is equal to 1 for the next clock cycle. Otherwise output Z is
0.

Default: Z = 0

a) [3 points] Convert to a moore type state diagram

b) Fill in the state table:

Q9) [5 points] Find the state machine diagram corresponding to the following description:
There are two states, A and B. If in state A and input X is 1, then the next state is A. If in state A and
input X is 0, then the next state is B. If in state B and input Y is 0, then the next state is B. If in state B
and input Y is 1, then the next state is A. Output Z is equal to 1 while the circuit is in state B.

Default: Z = 0
Q10) [10 points] Recall the State Machine Diagram (SMD) that we designed together in class:

a) Finish the state table in the next page and find the next state equations and output equations :

Hd_A+ = 𝑄 = 𝑄 . 𝐷𝑂. (𝐹1. (𝐶2 + 𝐺2) + 𝐹2. (𝐶1 + 𝐺1)) + 𝑄 . 𝐹2 + 𝑄 𝐹1

Hd_B+ = 𝑄 = 𝑄 . 𝐷𝑂. 𝐹1. (𝐶2 + 𝐺2) + 𝐹2. (𝐶1 + 𝐺1) + 𝑄 . 𝑇𝑂

Hd_C+= 𝑄 = 𝑄 . 𝑇𝑂 + 𝑄 . 𝐷𝐶. (𝐹1 + 𝐹2) +

U+ = 𝑄 = 𝑄 . 𝐷𝐶 . 𝐹1 + 𝑄 . 𝐹2

Dn+ = 𝑄 = 𝑄 . 𝐷𝐶 . 𝐹2 + 𝑄 . 𝐹1

Up = 𝑄 = U
Down = 𝑄 = Dn

TS = 𝑄 . 𝐷𝑂. 𝐹1. (𝐶2 + 𝐺2) + 𝐹2. (𝐶1 + 𝐺1) = 𝐻𝑑_𝐴 . 𝐷𝑂. 𝐹1. (𝐶2 + 𝐺2) +
𝐹2. (𝐶1 + 𝐺1)

SD = 𝑄 . 𝑆2 + 𝑄 . 𝑆1 = 𝑈 . 𝑆2 + 𝐷𝑛 . 𝑆1

CD = 𝑄 . 𝐷𝐶. (𝐹1 + 𝐹2) = 𝐻𝑑_𝐶+ . 𝐷𝐶. (𝐹1 + 𝐹2)

OD = 𝑄 . 𝐷𝑂 = 𝐻𝑑_𝐴 . 𝐷𝑂
State Assigned Transition Condition Next Next State Code OC
code State
𝑄 𝑄 𝑄 𝑄 𝑄
Q Q Q Q
Hd_A 𝐷𝑂 / 𝑂𝐷

0 0 0 0 1 𝐷𝑂. (𝐹1. (𝐶2 + 𝐺2) + 𝐹2. (𝐶1 + 𝐺1)) Hd_A 0 0 0 0 1

𝐷𝑂. 𝐹1. (𝐶2 + 𝐺2) + 𝐹2. (𝐶1 + 𝐺1) Hd_B 0 0 0 1 0 𝑇𝑆

Hd_B

0 0 0 1 0 𝑇𝑂 Hd_B 0 0 0 1 0

𝑇𝑂 Hd_C 0 0 1 0 0
Hd_C

𝐷𝐶. (𝐹1 + 𝐹2) Hd_C 0 0 1 0 0 𝐶𝐷

0 0 1 0 0
𝐷𝐶 . 𝐹1 U 0 1 0 0 0

𝐷𝐶 . 𝐹2 Dn 1 0 0 0 0
U Up, S2/SD

0 1 0 0 0 𝐹2 U 0 1 0 0 0

𝐹2 Hd_A 0 0 0 0 1
Dn Down, S1/SD

1 0 0 0 0 𝐹1 Dn 1 0 0 0 0

𝐹1 Hd_A 0 0 0 0 1
 b) Draw the circuit using D Flip-Flops

Q11) [10 points] Design of an SMD for a mixing machine as described below:
Build the state table for the SMD above:
State Assigned Transition Condition Next Next State Output
code State Code Actions
(OCs)
INIT
𝑆𝑇𝐴𝑅𝑇 + 𝑆𝑇𝑂𝑃 INIT
𝑆𝑇𝐴𝑅𝑇 + 𝑆𝑇𝑂𝑃
FILL_1 V1
𝑆𝑇𝑂𝑃 INIT
𝐿1 . 𝑆𝑇𝑂𝑃 FILL_1
𝐿1 . 𝑆𝑇𝑂𝑃 FILL_2
FILL_2 V2
𝑆𝑇𝑂𝑃 INIT
𝐿2 . 𝑆𝑇𝑂𝑃 FILL_2
𝐿2 . 𝑁𝐼. 𝑆𝑇𝑂𝑃 FILL_3
𝐿2 . 𝑁𝐼 . 𝑆𝑇𝑂𝑃 MIX
FILL_3 V3
𝑆𝑇𝑂𝑃 INIT
𝐿3 . 𝑆𝑇𝑂𝑃 FILL_3
𝐿3 . 𝑆𝑇𝑂𝑃 MIX PST
MIX MX
𝑆𝑇𝑂𝑃 INIT
𝑇𝑍 . 𝑆𝑇𝑂𝑃 MIX TM
𝑇𝑍 . 𝑆𝑇𝑂𝑃 EMPTY
EMPTY
𝐿0 + 𝑆𝑇𝑂𝑃 INIT
Draw the sequential circuit:
Q12) [10 points] Design a machine that outputs a 1 when exactly two of the last three inputs are 1.

The output Z = 1 if we have the following sequences: 011, 101, or 110, so the state diagram is in some
way is "the combination of three sequence recognizers":