Chapter 6 Combinational CMOS ombinational MOS Circuit and Logic Design g g
Jin Fu Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory p g g Department of Electrical Engineering National Central University Jhongli, Taiwan
Outline
Advanced CMOS Logic Design I/O St uctu s Structures
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Jin-Fu Li, EE, NCU
Pseudo-NMOS Logic
A pseudo-NMOS inverter
p
VDD F
VL Time
The low output voltage can be calculated as p g
n (V DD V tn )V L =
for Vtn = Vtp = Vt
P
2
(V DD | V tp |) 2
VL =
P (V DD V T ) 2n
Thus VL depends strongly on the ratio p / n The logic is also called ratioed logic g g
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Pseudo-NMOS Logic
An N-input pseudo-NMOS gate
Vout inputs NMOS network
Features of pseudo-NMOS logic
Advantages
Low area cost only N+1 transistors are needed for an Ninput gate Low input gate-load capacitance Cgn Non zero Non-zero static power dissipation
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Disadvantage
Pseudo-NMOS XOR Gate
An example of XOR gate realized with pseudoNMOS logic
The XOR is defined by
Y = X1 X 2 = X1 X 2 + X1 X 2 = X1 X 2 + X1 X 2 = X1 X 2 + X1 + X 2
Y
X1 X2
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Choosing Transistor Sizes
Goals
Noise margin Power consumption Speed
Noise margin Speed
It is affected by the low output voltage (VL) VL is determined by p / n The larger the W/L of the load transistor, the faster the gate will be, particularly when driving many other gates Unfortunately, this increases the power dissipation and the area of the driver network
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Choosing Transistor Sizes
Power dissipation
A pseudo-NMOS logic gate having a 1 output has no p g g g p static (DC) power dissipation. However, a pseudo-NMOS gate having a 0 output has a static p er dissipation power dissipati n
The static power dissipation is equal to the current of the PMOS load transistor multiplied by the power supply p y p pp y voltage. Thus, the power is given by p C ox W Pdc = ( ) P (V gs V tp ) 2 V dd 2 L
The large PMOS results in large power dissipation
Power-reduction Power reduction methods
Select an appropriate PMOS Increase the bias voltage of PMOS
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A simple procedure for choosing transistor sizes of pseudo-NMOS logic gates
The l ti Th relative size (W/L) of th PMOS load t i f the l d transistor i i t is chosen as a compromise between speed and size versus power dissipation Once the size of the load transistor has been chosen, then a simple procedure can be used to choose the W/Ls of the NMOS transistors in the NMOS network Let (W/L)eq be equal to one-half of the W/L of the ( ) q PMOS load transistor For each transistor Qi, determine the maximum number of drive transistors it will be in series, for all possible inputs. Denote this number ni. Take T k (W/L)i=ni(W/L) (W/L)eq
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Choosing Transistor Sizes
An Example
Choose appropriate sizes for the pseudoNMOS logic gate shown below
(W/L)8 is 5 um/0.8 um (W/L)eq is (5/0.8)/2=3.125 Gate lengths of drive transistors are taken at their minimum 0.8um Q8 5/0.8 Thus we can obtain
Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Size 2.5um/0.8um 2 5um/0 8um 5.0um/0.8um 5.0um/0.8um 10um/0.8um 10um/0 8um 10um/0.8um 10um/0.8um 10um/0.8um 10um/0 8um
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Y X1
Q1 X2 Q2
X4 X5
Q4 Q5 Q6 Q7
9
X3
Q3
X6 X7
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Dynamic Logic
To eliminate the static power dissipation of p pseudo-NMOS logic g
An alternative technique is to use dynamic precharging called dynamic logic as shown below
PR Vout t inputs NMOS network
Normally, Normally during the time the output is being precharged precharged, the NMOS network should not be conducting
This is usually not possible
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Dynamic Logic
Another dynamic logic technique
Vout inputs NMOS network Evaluate CLK Precharge
CLK
Two-phase Two phase operation: precharge & evaluate This can fully eliminate static power dissipation di i i
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Examples of Dynamic Logic
Two examples
clk A B B clk C clk Y=ABC
clk lk C A Z (A B).C Z=(A+B).C
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Problems of Dynamic Logic
Two major problems of dynamic logic
Charge sharing shar ng Simple single-phase dynamic logic can not be cascaded
Charge sharing
clk=1 1 B 1 C 0 clk=1 C1 C2 charge sharing model A C C2 C1 A C
CVDD = (C + C1 + C2 )VA VA = C VDD C + C1 + C2
E.g., if C1 = C2 = 0.5C then output voltage is VDD/2
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Problems of Dynamic Logic
Simple single-phase dynamic logic can not be cascaded
clock N1 inputs N Logic N Logic T d1 clock N2 T d2
Erroneous State
N2 N1
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CMOS Domino Logic
Domino logic can be cascaded The basic structure of domino logic
Vout inputs NMOS network
CLK
Some limitations of this structure
Each gate must be buffered Only noninverting structures are possible
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A Domino Cascade
An example of cascaded domino logics
Stage 1 Stage 2 Stage 3
Vout
NMOS network NMOS network NMOS network
CLK
precharge
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evaluate
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Charge-Keeper Circuits
The domino cascade must have an evaluation interval that is long enough to allow every stage time to discharge
This means that charge sharing and charge h h h h d h leakage processes that reduce the internal voltage may be limiting factors l b l f
Two types of modified domino logics can yp fm f m g cope with this problem
Static version Latched version
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Charge-Keeper Circuits
Modified domino logics
Weak W k PMOS Weak W k PMOS
Z Inputs
N-logic g Block
Z Inputs
N-logic Block
Clk Static version
Clk Latched version
The aspect ratio of th charge-keeper MOS must be h asp ct rat o the charg p r small so that it does not interfere with discharge event
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Complex Domino Gate
In a complex domino gate, intermediate nodes have been provided with their own p precharge transistor
F
N logic N-logic
N logic N-logic
N logic N-logic
N logic N-logic
CLK
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Multiple-Output Domino Logic
Multiple-output domino logic (MODL) allows two or more outputs from a single logic gate The basic structure of MODL
F1 A F2 B
CLK
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A Multiple-Output Domino Logic Gate
F1 A B C D F2 A B C
C C C C
B A
B A
F3 A B
CLK
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NP Domino Logic
A further refinement of the domino logic is shown below
The domino buffer is removed, while cascaded logic blocks are alternately composed of P- and N-transistors
CLK -CLK CLK
N-logic
P-logic
N-logic
Other P blocks
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Other blocks Oth N bl k
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NP Domino Logic
NP domino logic with multiple fanouts
Other N blocks Other P blocks
CLK
-CLK
CLK
N logic N-logic
P logic P-logic
N logic N-logic
Other P blocks
Other N blocks
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Advanced CMOS Logic Design
Pass Transistor Pass-Transistor Logic
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Pass-Transistor Logic
Model for pass transistor logic
Control signals Pi
Pass signals Vi
Product term (F)
The product term
F=P1V1+P2V2++PnVn The pass variables can take the values {0 1 Xi,{0,1,X Xi,Z}, where Xi and Xi are the true and complement of the ith input variable and Z is the mp m f p high-impedance
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Pass-Transistor Logics
Different types of pass-transistor logics for two input two-input XNOR gate implementation
A -A -B -A B A OUT B -B A OUT OUT B A
Complementary
Single-polarity
Cross-coupled
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Full-Swing Pass-Transistor Logic
Modifying NMOS pass-transistor logic so full level full-level swings are realized
B A
Adding the additional PMOS has another advantages
It adds hysteresis to the inverter, which makes it less likely to have glitches
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Differential Logic Design
Features of the differential logic design
Log c nvers ons Logic inversions are trivially obtained by s mply tr v ally obta ned simply interchanging wires without incurring a time delay The load networks will often consist of two crosscoupled P l d PMOS only. This minimizes both area and the l h b h d h number of series PMOS transistors
Disadvantage Dis d nt
Two wires must be used to represent every signal, the interconnect area can be significantly greater In greater. applications in which only a few close gates are being driven, this disadvantage is often not as significant as the advantages
Thus differential logic circuits are often a preferable consideration
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A Fully Differential Logic Circuit
One simple and popular approach for realizing differential logic circuit is shown below
The inputs to the drive network come in pairs, a singleended signal and its inverse The Th NMOS network can be divided i t t t k b di id d into two separate t networks, one between the inverting output and ground, and a complementary network between the noninverting p y g output and ground
VoutV1 + V1 Vn+ VnAdvanced Reliable Systems (ARES) Lab.
Vout+ Fully Differential NMOS Network
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Examples
Differential CMOS realizations of AND and OR functions
AB A A B B
AB
A+B A A B B
A+B
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Examples
Differential CMOS realization of the function Vout=(A+B)C+AE =(A+B )C+A E
Vout C A B E A A B A E C
Vout
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Differential Split-Level Logic
Differential split-level (DSL) logic
A variation of fully differential logic y g A compromise between a cross-coupled load with no d.c. power dissipation and a continuously-on load with d.c. power dissipation d c p er dissipati n
VoutVref VV1+ V1Vn+ VnAdvanced Reliable Systems (ARES) Lab.
Vout+ Vref V+ Differential NMOS Network
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Differential Split-Level Logic
Features of DSL logic
The loads have some of the features of both continuous loads and cross-coupled load
Both outputs begin to change immediately The l ds d h Th loads do have d.c. power dissipation, but normally d dissi ti b t ll much less than pseudo-NMOS gates and dynamic power dissipation
The nodes V+, V-, and all internal nodes of the NMOS network have voltage changes between greater th 0V and Vref-Vtn t than d V
This reduced voltage swing increases the speed of the logic gates
The maximum drain-source voltage across the NMOS transistors is reduced by about one-half y
This greatly minimizes the short-channel effects
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Differential Pass-Transistor Logic
It is not necessary to wait until one side goes to low before the other side goes high
Pass-transistor networks for most required logic functions exist in which both sides of the crosscoupled loads are d i l dl d driven simultaneously i lt l This minimizes the time from when the inputs changes to when the low to high transition occurs low-to-high
VoutV1+ V1Vn+ VnAdvanced Reliable Systems (ARES) Lab.
Vout+ Pass-Transistor Network
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Differential Pass-Transistor Logic
Other features of pass-transistor logic
It removes the ratio requirements on the logic and has guaranteed functionality The cross-coupled loads restore signal levels to full f ll Vdd l levels, thereby eliminating th voltage l th b li i ti the lt drop
Examples: E l
AB ABA+ AB+
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AB A+
A+B A+ BAA+
A+B AB+
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Dynamic Differential Logic
A differential Domino logic gate
CLK
VoutV1+ V1Vn+ Vn-
Vout+
Differential NMOS Net o k Network
CLK
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Dynamic Differential Logic
Features of dynamic Domino logic
Its d.c. power dissipation is very small, dc small whereas its its speed still quite good Because of the buffers at the output its output, output drive capability is also very good One f O of major li it ti j limitations of D i l i f Domino logic, the difficulty in realizing inverting functions, is eliminated because of th f ti i li i t d b f the differential nature of the circuits
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Dynamic Differential Logic
When the fan-out is small, the inverters at the output can be eliminated and the inputs to the charge-keeper transistors can be taken from the opposite output
CLK
VoutV1+ V1Vn+ Vn-
Vout+
Differential NMOS Network
CLK
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Clocked CMOS (C2MOS)
Structure of a C2MOS gate
Ideally, clocks are non-overlapping CLK X CLK=0 CLK=1, f is valid CLK=0, the output is in a high-impedance state. During this time interval, the output voltage is held on Cout interval
PMOS Network
CLK f CLK NMOS Network Cout + Vout
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Examples of C2MOS Logic Gates
A CLK CLK A B Cout B
B A AB CLK CLK Cout A A+B
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f M Gates
L g
The problem of charge leakage The basics of charge leakage are shown g g V(t) V below
dd
Cause that the output node cannot hold the p charge on Vout very long
CLK=1
ip
CLK=0
iout
i n Cout
+ Vout
V1
VX 0
V (t)
th
t
iout = in i p = C out
dV dt
dV =
iout dt Cout
Assume iout is a constant IL
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IL I dt V ( t ) = V1 L t V1 0 C C out out I V ( t h ) = V1 L t h = V X C out C t h = out (V 1 V X ) IL dV =
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I/O Pads
Types of pads
Vdd, Vss pad p Input pad (ESD) Output pad (driver) I/O pad (ESD+driver)
All pads need guard ring for latch-up p g g p protection ore l m ted pad l m ted Core-limited pad & pad-limited pad
Core-limited pad Pad-limited pad PAD PAD
I/O circuitry
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I/O circuitry
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ESD Protection
Input pad without electrostatic discharge (ESD) protection
PAD
Assume I=10uA, Cg=0.03pF, and t=1us The voltage that appears on the gate is about 330volts
Input pad with ESD protection
PAD
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Tristate & Bidirectional Pads
Tristate pad
output-enable OE P OUT OE D N P OUT 0 X 0 1 0 1 1 0 Z 0 1
PAD
N data D
1 1
0 1
Bidirectional pad
PAD
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Schmitt Trigger Circuit
Voltage transfer curve of Schmitt circuit
Vout VDD
Vin VTVT+ VDD
Hysteresis voltage VH=VT+-VTWhen the input is rising, it switches when Vin=VT+ rising When the input is falling, it switches when Vin=VTAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45
Schmitt Trigger Circuit
Voltage waveform for slow input
Voutt VDD Vin
VT+ VTTime
Schmitt trigger turns a signal with a very slow transition into a signal with a sharp transition
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Schmitt Trigger Circuit
A CMOS version of the Schmitt trigger circuit
VDD
P1 P2 VFP P3
Vin
N2 VFN N1 N3
Vout
VGS2 = VTn Then VFN =VT+ VTn
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When the input is rising, the VGS of the transistor N2 is given rising by VGS2 =Vin VFN When Vin = VT + , N2 enters in conduction mode which means
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Summary
The following topics have been introduced in this chapter
CMOS Logic Gate Design Advanced CMOS Logic Design Clock ng Strateg es Clocking Strategies I/O Structures
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