5/14/2025

VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

VNU INFORMATION TECHNOLOGY INSTITUTE

Computer Architecture
Lecture 5: The processor - The Basic Structure

Duy-Hieu Bui, PhD

AIoT Laboratory
Email: [email protected]
https://duyhieubui.github.io

Copyright

Content adapted from “Computer Organization and Design RISC-V

Edition: The Hardware Software Interface, Second Edition” by David A.
Patterson, John L. Hennessy, published by Morgan Kaufmann. © 2020
Elsevier Inc. All rights reserved.

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Introduction

• CPU performance factors

– Instruction count
• Determined by ISA and compiler
– CPI and Cycle time
• Determined by CPU hardware
• We will examine two RISC-V implementations
– A simplified version
– A more realistic pipelined version
• Simple subset, shows most aspects
– Memory reference: ld, sd
– Arithmetic/logical: add, sub, and, or
– Control transfer: beq

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Instruction Execution

• PC → instruction memory, fetch instruction

• Register numbers → register file, read registers
• Depending on instruction class
– Use ALU to calculate
• Arithmetic result
• Memory address for load/store
• Branch comparison
– Access data memory for load/store
– PC  target address or PC + 4

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CPU Overview

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Multiplexers

◼ Can’t just join

wires together
◼ Use multiplexers

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Control

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Logic Design Basics

• Information encoded in binary

– Low voltage = 0, High voltage = 1
– One wire per bit
– Multi-bit data encoded on multi-wire buses
• Combinational element
– Operate on data
– Output is a function of input
• State (sequential) elements
– Store information

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Combinational Elements

• AND-gate • Adder A
– Y=A&B – Y=A+B + Y
A B
Y
B

• Multiplexer • Arithmetic/Logic
– Y = S ? I1 : I0 Unit
– Y =A F(A, B)
I0 M
u Y ALU Y
I1 x

B
S F

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Sequential Elements

• Register: stores data in a circuit

– Uses a clock signal to determine when to update the
stored value
– Edge-triggered: update when Clk changes from 0 to 1

Clk
D Q
D

Clk
Q

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Sequential Elements

• Register with write control

– Only updates on clock edge when write control input is 1
– Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

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Clocking Methodology

• Combinational logic transforms data during clock

cycles
– Between clock edges
– Input from state elements, output to state element
– Longest delay determines clock period

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Building a Datapath

• Datapath
– Elements that process data and addresses
in the CPU
• Registers, ALUs, mux’s, memories, …
• We will build a RISC-V datapath incrementally
– Refining the overview design

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Instruction Fetch

Increment by
4 for next
64-bit instruction
register

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R-Format Instructions

• Read two register operands

• Perform arithmetic/logical operation
• Write register result

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Load/Store Instructions

• Read register operands

• Calculate address using 12-bit offset
– Use ALU, but sign-extend offset
• Load: Read memory and update register
• Store: Write register value to memory

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Branch Instructions

• Read register operands

• Compare operands
– Use ALU, subtract and check Zero output
• Calculate target address
– Sign-extend displacement
– Shift left 1 place (halfword displacement)
– Add to PC value

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Branch Instructions

Just
re-routes
wires

Sign-bit wire
replicated

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Composing the Elements

• First-cut data path does an instruction in one

clock cycle
– Each datapath element can only do one function at a
time
– Hence, we need separate instruction and data
memories
• Use multiplexers where alternate data sources
are used for different instructions

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R-Type/Load/Store Datapath

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Full Datapath

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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ALU Control

• ALU used for

– Load/Store: F = add
– Branch: F = subtract
– R-type: F depends on opcode

ALU control Function

0000 AND
0001 OR
0010 add
0110 subtract

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ALU Control

• Assume 2-bit ALUOp derived from opcode

– Combinational logic derives ALU control

ALU
opcode ALUOp Operation Opcode field ALU function control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001

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The Main Control Unit

• Control signals derived from instruction

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Datapath With Control

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R-Type Instruction

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Load Instruction

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Branch-on-Equal Instruction

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Performance Issues

• Longest delay determines clock period

– Critical path: load instruction
– Instruction memory → register file → ALU → data
memory → register file
• Not feasible to vary period for different
instructions
• Violates design principle
– Making the common case fast
• We will improve performance by pipelining

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Pipelining Analogy

• Pipelined laundry: overlapping execution

– Parallelism improves performance

• Four loads:
– Speedup
= 8/3.5 = 2.3
• Non-stop:
– Speedup
= 2n/0.5n + 1.5 ≈ 4
= number of stages

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RISC-V Pipeline

• Five stages, one step per stage

1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

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Pipeline Performance

• Assume time for stages is

– 100ps for register read or write
– 200ps for other stages
• Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register ALU op Memory Register Total time

read access write
ld 200ps 100 ps 200ps 200ps 100 ps 800ps
sd 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

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Pipeline Performance

Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

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Pipeline Speedup

• If all stages are balanced

– i.e., all take the same time
– Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
• If not balanced, speedup is less
• Speedup due to increased throughput
– Latency (time for each instruction) does not decrease

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Pipelining and ISA Design

• RISC-V ISA designed for pipelining

– All instructions are 32-bits
• Easier to fetch and decode in one cycle
• c.f. x86: 1- to 17-byte instructions
– Few and regular instruction formats
• Can decode and read registers in one step
– Load/store addressing
• Can calculate address in 3rd stage, access memory in 4th
stage

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Hazards

• Situations that prevent starting the next

instruction in the next cycle
• Structure hazards
– A required resource is busy
• Data hazard
– Need to wait for previous instruction to complete its
data read/write
• Control hazard
– Deciding on control action depends on previous
instruction

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Structural Hazards

• Conflict for use of a resource

• In RISC-V pipeline with a single memory
– Load/store requires data access
– Instruction fetch would have to stall for that cycle
• Would cause a pipeline “bubble”
• Hence, pipelined datapaths require separate
instruction/data memories
– Or separate instruction/data caches

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Data Hazards

• An instruction depends on completion of data

access by a previous instruction
– add x19, x0, x1
sub x2, x19, x3

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Forwarding (aka Bypassing)

• Use result when it is computed

– Don’t wait for it to be stored in a register
– Requires extra connections in the datapath

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Load-Use Data Hazard

• Can’t always avoid stalls by forwarding

– If value not computed when needed
– Can’t forward backward in time!

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Code Scheduling to Avoid Stalls

• Reorder code to avoid use of load result in the
next instruction
• C code for a = b + e; c = b + f;

ld x1, 0(x0) ld x1, 0(x0)

ld x2, 8(x0) ld x2, 8(x0)
stall add x3, x1, x2 ld x4, 16(x0)
sd x3, 24(x0) add x3, x1, x2
ld x4, 16(x0) sd x3, 24(x0)
stall add x5, x1, x4 add x5, x1, x4
sd x5, 32(x0) sd x5, 32(x0)
13 cycles 11 cycles
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Control Hazards

• Branch determines flow of control

– Fetching next instruction depends on branch
outcome
– Pipeline can’t always fetch correct instruction
• Still working on ID stage of branch
• In RISC-V pipeline
– Need to compare registers and compute
target early in the pipeline
– Add hardware to do it in ID stage

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Stall on Branch

• Wait until branch outcome determined

before fetching next instruction

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Branch Prediction

• Longer pipelines can’t readily determine

branch outcome early
– Stall penalty becomes unacceptable
• Predict outcome of branch
– Only stall if prediction is wrong
• In RISC-V pipeline
– Can predict branches not taken
– Fetch instruction after branch, with no delay

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More-Realistic Branch Prediction

• Static branch prediction

– Based on typical branch behavior
– Example: loop and if-statement branches
• Predict backward branches taken
• Predict forward branches not taken
• Dynamic branch prediction
– Hardware measures actual branch behavior
• e.g., record recent history of each branch
– Assume future behavior will continue the trend
• When wrong, stall while re-fetching, and update
history

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Pipeline Summary The BIG Picture

• Pipelining improves performance by

increasing instruction throughput
– Executes multiple instructions in parallel
– Each instruction has the same latency
• Subject to hazards
– Structure, data, control
• Instruction set design affects complexity of
pipeline implementation

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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RISC-V Pipelined Datapath

MEM

Right-to-left WB
flow leads to
hazards

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Pipeline registers

• Need registers between stages

– To hold information produced in previous cycle

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Pipeline Operation

• Cycle-by-cycle flow of instructions through

the pipelined datapath
– “Single-clock-cycle” pipeline diagram
• Shows pipeline usage in a single cycle
• Highlight resources used
– c.f. “multi-clock-cycle” diagram
• Graph of operation over time
• We’ll look at “single-clock-cycle” diagrams
for load & store

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IF for Load, Store, …

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ID for Load, Store, …

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EX for Load

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MEM for Load

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WB for Load

Wrong
register
number

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Corrected Datapath for Load

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EX for Store

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MEM for Store

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WB for Store

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Multi-Cycle Pipeline Diagram

• Form showing resource usage

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Multi-Cycle Pipeline Diagram

• Traditional form

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Single-Cycle Pipeline Diagram

• State of pipeline in a given cycle

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Pipelined Control (Simplified)

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Pipelined Control

• Control signals derived from instruction

– As in single-cycle implementation

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Pipelined Control

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Outline

• Introduction
• Logic Design Conventions
• Building a Datapath
• A Simple Implementation Scheme
• An Overview of Pipelining
• Pipelined Datapath and Control
• Concluding Remarks

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Concluding Remarks

• ISA influences design of datapath and control

• Datapath and control influence design of ISA
• Pipelining improves instruction throughput
using parallelism
– More instructions completed per second
– Latency for each instruction not reduced
• Hazards: structural, data, control
• Multiple issue and dynamic scheduling (ILP)
– Dependencies limit achievable parallelism
– Complexity leads to the power wall

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