Datapath Functional Units

Contents

• Comparator

• Funnel Shifter

• Multi Input Adder

• Multiplier

• Divider

2
 Introduction
• Data path
• Consists of functional units where all computations are carried out
• Ex: Registers, multiplexers, bus, adders, multipliers, counter
• Control path
• Consists of FSM and provide control signals to the data path in proper sequence
• With the help of control signals various operations are carried out by the data
path
• Also takes inputs from the data path regarding status information

3
Multiplication by repeated addition
Start

• Illustrate (P × Q) by repeated addition

Read P, Q
• Assumption, Q is not zero
F=0
• Identify the functional blocks
F=F+P
• Design the FSM to implement the
algorithm with the help of data path Q=Q-1
No
Yes
Q = 0? Stop

5
Multiplication by repeated addition
• Data Path bus

loadQ loadF
decQ Q loadP P F clrF

Comparator Adder

zero Z

in_data

6
Multiplication by repeated addition
• Block Diagram
loadP
loadQ
in_data
start clrF

done Control loadF Data

Path decQ Path

zero

clock

7
Multiplication by repeated addition
Start S0
• Control Path !start
S0
start P = in_data S1
S1
Q = in_data
F=0 S2
S2

!zero
F=Z S3
Q=Q-1
S3
zero
No
Yes
S4 Q = 0? done = 1

S4 8
Multiplication by repeated addition
• Write HDLs and simulate
testbench

top_dut
shift_reg counter

testbench comparator

adder controller

9
Comparators

• 0’s detector: A = 00…000

• 1’s detector: A = 11…111

• Equality comparator: A=B

• Magnitude comparator: A<B

Datapath Slide 10
 1’s & 0’s Detectors
• 1’s detector: N-input AND gate
• 0’s detector: NOTs + 1’s detector (N-input NOR)
A7
A6
A5 A3
A4 A2
allones
A3 allzeros
A2 A1
A1 A0
A0

A7
A6
A5
A4
A3 allones
A2
A1
A0

Datapath Slide 11
Equality Comparator

• Check if each bit is equal (XNOR, an equality detector gate)

• 1’s detect on bitwise equality

B[3]
A[3]
B[2]
A[2] A=B
B[1]
A[1]
B[0]
A[0]

Datapath Slide 12
 Magnitude Comparator
• Compute B-A and look at sign
• B-A = B + ~A + 1
• For unsigned numbers, carry out is sign bit

Datapath Slide 13
 Detecting overflows
1) When the result of the operation is outside the representable range an
overflow occurs.
2) Overflows can only occur when the sign of the two operands is the same
and if the sign of the result is different from the sign of the operands.
 Recall that the MSB represents the sign.
 xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s respectively.
 Circuit to detect overflow can be implemented by the following logic
expression:

Datapath Slide 14
 Detecting overflows
3) It can also be shown that overflow occurs when the carry bits cn and
cn−1 are different.
Therefore, a simpler circuit for detecting overflow can be obtained by
implementing the expression cn ⊕ cn−1 with an XOR gate.

Datapath Slide 15
 Detecting overflows
Example indicating overflow is occurred
1) +5 + +6
0101 + 0110 = 1011 overflow is occurred
2) +3 – (-7)
0011 – 1001 = 0011 + 0111 = 1010 overflow is occurred

Datapath Slide 16
Shifters
• Logical Shift:
• Shifts number left or right and fills with 0’s
• 1011 LSR 1 = 0101 1011 LSL1 = 0110
• Arithmetic Shift:
• Shifts number left or right. Right shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110
• Rotate:
• Shifts number left or right and fills with lost bits
• 1011 ROR1 = 1101 1011 ROL1 = 0111

Datapath Slide 18
Funnel Shifter
• A funnel shifter can do all six types of shifts
• A funnel shifter creates a 2N – 1-bit input word Z from A then selects an N-bit
field from this input word
• Selects N-bit field Y from 2N-bit input
• Shift by k bits (0  k < N)

2N-1 N-1 0
B C

offset + N-1 offset

Datapath Slide 19
Funnel Shifter Design
• Log N stages of 2-input muxes
– No select decoding needed

Datapath Slide 20
Multi-input Adders
• Suppose we want to add k N-bit words
• Ex: 0001 + 0111 + 1101 + 0010 = 10111
• Straightforward solution: k-1 N-input CPAs
• Large and slow
0001 0111 1101 0010

+
10101

+
10111

Datapath Slide 21
 Carry Save Addition
• A full adder sums 3 inputs and produces 2 outputs
- Carry output has twice weight of sum output
• N full adders in parallel are called carry save adder
- Produce N sums and N carry outs
X4 Y4 Z4 X3 Y3 Z3 X2 Y2 Z2 X1 Y 1 Z1

C4 S4 C3 S3 C2 S2 C1 S1
XN...1 YN...1 ZN...1

n-bit CSA

CN...1 SN...1

Datapath Slide 22
 CSA Application
• Use k-2 stages of CSAs 0001 X
• Keep result in carry-save redundant form
0001 0111 1101 0010 0111 Y
• Final CPA computes actual result +1101 Z
4-bit CSA 1011 S
0101_ C
0101_ 1011
0101_ X
5-bit CSA 1011 Y
+0010 Z
01010_ 00011 00011 S
01010_ C
+
01010_ A
10111 + 00011 B
10111 S
Datapath Slide 23
Multiplication
1100 : 1210 multiplicand
• Example: 0101 : 510 multiplier
1100
0000 partial
1100 products
0000
00111100 : 6010 product

• M x N-bit multiplication
• Produce N M-bit partial products
• Sum these to produce M+N-bit product
Datapath Slide 24
General Form
• Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
• Multiplier: X = (xN-1, xN-2, …, x1, x0)
• Product:
 M 1 j 
N 1
i
N 1 M 1
P    y j 2    xi 2    xi y j 2i  j y5 y4 y3 y2 y1 y0 multiplicand
 j 0   i 0  i 0 j 0 x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product

Datapath Slide 25
 Array Multiplier y3 y2 y1 y0

x0

• Array multiplier using CSA

x1
and CPA CSA
Array

x2

x3

CPA

p7 p6 p5 p4 p3 p2 p1 p0

A B
Sin A Cin critical path A B
A B
B Sin
= Cout Cin = Cout Cin
Cout Cin
Sout
Datapath Cout Sout Sout
Sout
Divider

• Division algorithm – Two types

• Fast Division Algorithms
Ex.: Goldschmidt algorithm, Newton-Raphson algorithm

• Slow Division Algorithms

Ex.: STR algorithm, restoring algorithm, non-performing algorithm, and the
non-restoring algorithm

27
 Restoring Division Algorithm
• Division of an unsigned integer.
• ‘Restoring’ term because value of register
A will be restored after each iteration.

Divisor Dividend

No

Yes

Flow Chart 28
• Step 1: The corresponding value will be initialized to the registers
A ← 0, M ← Divisor, Q ← Dividend, and N ← number of bits in
dividend.

• Step 2: Register A and register Q will be treated as a single unit, and the
value of both the registers will be shifted left.

• Step 3: Value of M subtracted from A. The result of subtraction stored in

A.

• Step 4: Now, check the MSB of A. If this bit of A is 0, then the LSB of Q
set to 1. If the MSB of A is 1, then the LSB of Q set to 0, and restore the
value of A that means it will restore the value of A before subtraction with
M.

• Step 5: Value of N decremented. Here N is used as a counter.

• Step 6: If the value of N is 0, break the loop. Otherwise, go to step 2. 29

 N M A Q Operation
Example: 11 / 3 4 00011 00000 1011 Initialize
00011 00001 011_ Shift left AQ
• We should not forget to 00011 11110 011_ A=A-M
restore the value of the 00011 00001 0110 Q[0] = 0 & restore A
MSB of A, which is 1.
3 00011 00010 110_ Shift left AQ
• A contains the remainder 2.
00011 11111 110_ A=A-M
• Q contains the quotient 3
00011 00010 1100 Q[0] = 0
2 00011 00101 100_ Shift left AQ
00011 00010 100_ A=A-M
00011 00010 1001 Q[0] = 1
1 00011 00101 001_ Shift left AQ
00011 00010 001_ A=A-M
00011 00010 0011 Q[0] = 1 30
Non-Restoring Division Algorithm

• More complex as compared to the restoring division algorithm.

• But when we implement this algorithm in hardware, it has an

advantage, i.e., it contains only addition/subtraction per quotient bit.

• After subtraction, no restoring steps. Hence, the numbers of operations

basically cut down up to half. Because of the less operation, the
execution of this algorithm will be fast.

31
Flow Chart

32
• Step 1: The corresponding value will be initialized to the registers
A ← 0, M ← Divisor, Q ← Dividend, and N ← number of bits in dividend.
• Step 2: Check the sign bit of A
• Step 3: If this bit of A is 1, then shift the value of AQ through left, and perform A = A
+ M. If this bit is 0, then shift the value of AQ into left and perform A = A - M. That
means in case of 0, the 2's complement of M is added into register A, and the
result is stored into A.
• Step 4: Check the sign bit of A again.
• Step 5: If this bit of register A is 1, then Q[0] will become 0. If this bit is 0, then Q[0]
will become 1.
• Step 6: The value of N is decremented. Here N is used as a counter.
• Step 7: If the value of N = 0, then go to the next step. Otherwise, go to step 2.
• Step 8: A = A + M if the sign bit of register A is 1
• Step 9: This is the last step. Q contains quotient, and A contains remainder. 33
 N M A Q Action
Example: 11 / 3 4 00011 00000 1011 Begin
Dividend = 11 00011 00001 011_ Shift left AQ
Divisor = 3
00011 11110 011_ A=A-M
3 00011 11110 0110 Q[0] = 0
• If A = 0 Subtract else Add 00011 11100 110_ Shift left AQ
• A contains the remainder 2 00011 11111 110_ A=A+M
• Q contains the quotient 3 2 00011 11111 1100 Q[0] = 0
00011 11111 100_ Shift left AQ
00011 00010 100_ A = A +M
1 00011 00010 1001 Q[0] = 1
00011 00101 001_ Shift left AQ
00011 00010 001_ A=A-M
0 00011 00010 0011 Q[0] = 1 34