AN INTRODUCTION TO 8051

MICROCONTROLLER AND ITS

APPLICATION
Presented by
Sudipta Chakraborty
DIRECTOR
TECHNO INDIA GROUP

15/03/2023
 PART 1

THE 8051 ARCHITECTURE

 Microprocessor
• Microprocessor is an Central Processing Unit of
a Digital Computer, which contains an arithmetic
and logic unit (ALU), a Program Counter (PC), a
Stack Pointer (SP), some working Register, a
clock timing circuit, and interrupt circuits.
To make a digital computer ,one must add
memory usually RAM and ROM, parallel and
serial I/O lines. In addition with some special
purpose devices such as interrupt handlers and
counter. And also required some mass storage
devices usually floppy disk drive, hard disk
drive, and other I/O peripherals, such as
keyboard and CRT display.
 Microcontroller
• A Microcontroller which is also known as a
true computer on a single chip. It has a
CPU which contain ALU, PC, SP,
REGISTERS. In addition with a fixed
amount of RAM,ROM,I/O ports including
serial communication, and timer are all
embedded together on a single chip. In
some microcontroller an ADC and DAC
(PWM o/p) also embedded in a single
chip.
 Internal Organisation Of Computers

ADDRESS BUS

CPU
RAM ROM Printer Disk Monitor Keyboard

DATA BUS
Read/Write

CONTROL BUS
 CPU CPU RAM ROM

General-

Purpose Serial
RAM ROM I/O Timer COM
PORT Port
Microproc-
I/O Timer Serial
essor COM
Port

(a) General- Purpose Microprocessor System (b) Microcontroller

 DIFFERENCE BETWEEN MICROPROCESSOR &
MICROCONTROLLER
1. Microprocessor contains no 1. Micro controller has a C.P.U in
RAM, ROM, I/O ports on addition to a fixed amount of
the chip itself. RAM, ROM, I/O ports and timer
all on a single chip.
2. The addition of external 2. Because of embedded system
RAM, ROM & I/O ports there is no external RAM,
makes the whole system ROM,timer,I/O ports &
bulkier and much more external memory in a micro
expensive. controller system.So it is less
expensive.
3. It can’t use in a small 3. Micro controller is ideal for
circuitry system. many application in which cost
and space are critical.
4. Microprocessor have the
advantage of versatility, 4. It is not possible in a micro
such that the designer can controller system.
decide the amount of
RAM,ROM & I/O ports as
needed.
A MICROCONTROLLER SURVEY
• 4 bit microcontroller
Manufacturer Model Pins:I/o Counter RAM ROM Features

Hitachi HMCS40 24:10 ----- 32 512 10 bit ROM

National COP420 28:23 1 64 1K Serial bit I/O

OKI MSM6411 16:11 ---- 32 1K

TI TMS 1000 28:11 ---- 64 1K LED display

Toshiba TLCS47 42:35 2 128 2K Serial bit I/O

 Contd.
• 8 bit microcontroller
Manufacturer Model Pins:I/O Counter RAM ROM Features

TI TMS370 68:55 2 256 4K 112k EM,A/D, serial

C050 port
Intel 8051 40:32 2 128 4K 128K EM, serial port

Microchip PIC 18:12 0 25 1K RC oscillator, self

16C56 reset, low cost
National COP820 28:24 1 64 1K Serial bit I/O

Motorola 68HC11 52:40 2 256 8K Serial port, WDT, A/D

PHILIPS 87C552 68:48 3 256 8K Serial port, WDT, A/D

Rockwell 6500/1 40:32 1 64 2K

ZILOG Z86C83 28:22 2 256 4K Low cost, 124k EM,

A/D, serial port
 Contd.
• 16 bit microcontroller

Manufacturer Model Pins:I/O Counter RAM ROM Features

Hitachi H8/532 84:65 5 1K 32K 1M EM, A/D, serial

port, PWM
Intel 80C196 68:40 2 232 8K 64K EM, serial port,
A/D, PWM
National HPC161 68:52 4 512 16K 64K EM, serial port,
64 A/D, PWM
 MCUs Architecture
• Von Neumann – contains single memory for storing
control program & data, contains single bus for
transferring data to/from CPU. Most computers use
this.
• Harvard – separate memory for program & data, with
separate buses, increases speed since program &
data can be fetched simultaneously, buts needs twice
as many address & data pins. PIC MCUs use this
• Modified Harvard – Single data & address bus
externally, but two separate buses internally.
Program & data information is separated by
multiplexing method.
 MCUs Architecture

ADDRESS
DATA Memory
(program)
Memory DATA
(program CPU ADDRESS
CPU
+data)
Memory
ADDRESS (data)

DATA

Von Neumann Harvard

 INSTRUCTION SET
• Complex Instruction Set Computer – 8051
compatibles, Motorola 68HC11
• Reduced Instruction Set Computer – PIC series, AVR
series
• In CISC type MCUs, a no. of instructions are available.
RISC type MCUs have a min. set. Complex arithmetic,
logical instructions are omitted. This reduces the
complex instruction decoding process, thus making
them faster. RISC MCUs have fixed length instructions
to simplify the fetch & decoding cycle. Addresses &
data are directly embedded in the instruction, thus
allowing them to be fetched in a single cycle. For this
the data bus width needs to be same as the instruction
bus. Only 20% of most CISC type instructions are
used.
 Features of 8051
• 8 bit CPU with register A and B
• 16 bit Program Counter and Data Pointer
• 8 bit Program Status Word
• 8 bit Stack Pointer
• Internal ROM and Internal RAM
• 4 Ports of each 8 bit, P0-P3
• 2 timers of each 16 bit, T0 and T1
• Full Duplex serial data Transmitter/ Receiver
• Control Registers: TCON,TMOD,SCON,PCON,IE,IP
• 2 external and 3 internal interrupt sources
• Oscillator and Clock circuit
 8051 family micro controller
Arithmetic
And PSW Special
I/O
Logic Unit Function Latch
Register Port 0 A0-A7
RAM D0-D7
A B

DPTR Latch
Port 1 I/O
PC DPH
ROM Special
DPL
Function
16-Bit Address Bus Register

IE
EA Byte/Bit Latch I/O
ALE System IP Port 2
Address A8-A15
PSEN Timing PCON
XTAL 1 Register SBUF
XTAL 2 System Bank 3
SCON I/O
RESET Interrupts
Register Interrupt
TCON Latch
Bank 2 Port 3 Counter
Timer TMOD Serial Data
VCC Data Buffers Register TLO RD-WR
GND Memory Bank 1
THO
Controls
Register TL1
Bank 0 TH1
Internal RAM Structure
8051 ARCHITECTURE
 Features of the 8051

Feature Quantity
ROM 4K bytes
RAM 128 bytes
Timer 2
I/O pins 32
Serial port 1
Interrupt sources 6
 Comparison of 8051 Family Members

Feature 8051 8052 8031

ROM(on-chip program space in bytes) 4K 8K 0K
RAM 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

Various 8051 Micro controllers

• 8751:- UV – EPROM version.
• AT89C51:- Flash memory version from Atmel corporation.
• DS5000 series from Dallas semiconductor in the form of NV – RAM.

Table 1: Versions of 8051 From Atmel (All ROM Flash)

Part Number ROM RAM I/O pins Timer Interrupt Vcc Packaging
AT89C51 4K 128 32 2 6 5V 40
AT89LV51 4K 128 32 2 6 3V 40
AT89C1051 1K 64 15 1 3 3V 20
AT89C2051 2K 128 15 2 6 3V 20
AT89C52 8K 128 32 3 8 5V 40
AT89LV52 8K 128 32 3 8 3V 40

Table 2: Various Speeds of 8051 From Atmel

Part Number Speed Pins Packaging Use
AT89C51-12PC 12 MHz 40 DIP plastic commercial
AT89C51-16PC 16 MHz 40 DIP plastic Commercial
AT89C51-20PC 20 MHz 40 DIP plastic Commercial

Table 3:- Versions of 8051 From Dallas Semiconductor’s Soft Micro controller
Part ROM RAM I/O pins Timer Interrupt Vcc Packaging
Number
DS5000-8 8K 128 32 2 6 5V 40
DS5000-32 32K 128 32 2 6 5V 40
DS5000-8 8K 128 32 2 6 5V 20
DS5000T-8 32K 128 32 2 6 3V 40
 PIN DESCRIPTION
P1.0 1 40 VCC
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 35 P0.4 (AD4)
P1.6 34 P0.5 (AD5)
7
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
31 EA/VPP
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
10
11
12
8051 30
29
28
ALE/PROG
PSEN
P2.7 (A15)
(INT1) P3.3 13
27 P2.6 (A14)
(T0) P3.4 14
(T1) P3.5 15 26 P2.5 (A13)

(WR) P3.6 16 25 P2.4 (A12)

(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 PIN DESCRIPTION Contd.
• As per pin diagram out of 40 pins, 32 pins are
assigned for ports P0,P1,P2 and P3, where each
ports takes 8 pins.
• The rest of the pins are Vcc, GND,XTAL1, XTAL2,
RST, EA’/VPP,ALE/PROG’, AND PSEN’.
• Vcc: Pin 40 provides supply Voltage. The voltage
source is 5V.
• GND: Pin 20 is grounded.
• XTAL1 & XTAL2 : 8051 needs external clock to run it.
Most often a crystal is connected to XTAL1 (19) and
XTAL2(18) for supplying operating frequency.
• RST: Pin 9 is the Reset pin. It is an input pin and is
active high. Upon applying a high pulse to this pin
the 8051 will reset and terminate all the activities.
 PIN DESCRIPTION Contd.
• EA’/VPP: Pin 31 is the External access pin, generally we
connected this pin with the Vcc, but when we use the
external memory then this pin must be connected to
Ground.
• The VPP signal is used at the time of EPROM
programming, where we supply a 21V through this pin.
• ALE/PROG’: ALE (pin 30) stands for Address Latch
Enable. This is an output pin and is active high. This pin
is used for de-multiplexing the data and address bus by
connecting to the enable pin of 74LS373 latch.
• PROG’ is used at the time of EPROM programming. A
50 ms pulse is connected to the ground through this pin
for EPROM programming.
• PSEN’: PSEN’ (pin 29) stands for Program Store Enable.
This is an output pin and connected to the external
ROM.
 Oscillator and Clock
• 8051 has on chip oscillator but requires an
external clock to run it. Most often a Quartz
Crystal oscillator is connected to XTAL 1 and
XTAL 2 pins with 2 nos of 30 pf capacitors.
 Oscillator and Clock contd .
• If we use any external frequency source other than
crystal oscillator, it will be connected to XLAT1 and
XLAT 2 is left unconnected.
• Time to execute a one cycle instruction is given by
• T=(c x 12d)/ crystal frequency
Oscillator and Clock contd .
Reset Circuit
 I/O PORT PINS AND THEIR
FUNCTION
• Four Ports P0,P1,P2and P3 of each 8 bit
• All Ports upon RESET are configured as
output Port
• To use them as input Port, it must be
programmed.
• All Ports are bit accessible.
 P0 PORT
• P0 pins may serve as an inputs, outputs,
when used together ,as a bidirectional low
order address and data bus for external
memory.
• To configure it as an input port, a logical 1
must be written to the corresponding port0
latch by program.
• It is used as a data bus during internal
EPROM programming
P0 PORT contd.
 P1& P2 PORT
• P1 AND P2 may be used as an input or
output port.
• They does not required external pull-up
resistors.
• P2 supply the high-order address bus for
external memory or input/output devices.
 P3 PORTS
• P3 may be used Pin Name Use SFR
as an input or P3.0 RXD Serial data input SBUF

P3.1 TXD Serial data output SBUF

output port.
alternate P3.2 INT0’
External interrupt 0 TCON.1
• The
uses of P3 are P3.3 INT1’
External interrupt 1 TCON.3

shown in table: P3.4 T0 External timer o

input
TMOD

P3.5 T1 External timer 1 TMOD

input
P3.6 WR’ External memory --
write pulse
P3.7 RD’ External memory --
read pulse
 REGISTER
• A and B CPU register
• Program Counter and Data Pointer
• Flags and program Status Word (PSW)
• Internal RAM
• Some Special Function Register
• 8 bit Stack Pointer
 A AND B CPU REGISTER
• The A (Accumulator) register is used for many
operation, including Addition, Subtraction,
Integer Multiplication, Division and other logical
operation.
• The A register is also used for all data transfers
between the 8051 and any external memory.
• The B register is used with the A register for
Multiplication and Division operation and has no
other function other than as a location where
data may be stored.
 PROGRAM COUNTER AND DATA
POINTER
• Program Counter (PC) and Data Pointer
(DPTR) are two 16 bit register.
• PC and DPTR are used to hold the address of
a Memory.
• PC is used to hold the address of the next
memory location which is to be executed.
• The PC has no internal Address.
• The DPTR register is made up of two 8 bit
register named DPH and DPL.
• DPTR is used to hold the memory address for
internal and external code memory and
external data memory.
 PROGRAM STATUS WORD AND FLAGS

• Program Status Word (PSW) is a 8 bit

register.
• PSW contains 4 math Flag, user program flag
F0 and the register select bits RS1 and RS0
• PSW register is bit addressable, so all the
flags can be set or reset by the programmer at
will. The PSW structure is shown bellow.

7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV ---- P
 FLAGS Contd.
• Flags are 1 bit register which are grouped inside the
PSW and PCON.
• Flags are provided to store the result of certain program
instruction.
• 8051 has 4 math flags which include Carry flag (C),
Auxiliary Carry (AC), Overflow (OV) and Parity (P), and 3
user flags are named F0,GF0, and GF1.
• GF0 and GF1 are store in PCON register.
• Carry flag is set when there is a carry in the 7th bit of
accumulator, this flag is used in arithmetic, jump, rotate,
and Boolean instruction.
 FLAGS Contd.
• Auxiliary Carry flag is set when there is a carry form 3rd
bit to 4th bit of accumulator. This flag is used in BCD
arithmetic operation.
• Overflow flag is set when there is any overflow in math
operation.
• Parity flag is set to 1 when the number of 1’s in A
register is odd.
• The three user flags are general purpose flags
programmers can be set or reset by the programmer at
will.
• RS0 and RS1 are two register bank select bits which are
used to select the specific register bank of internal RAM.
 FLAGS Contd.

RS1 RS0 REGISTER

0 0 Select register bank 0

0 1 Select register bank 1

1 0 Select register bank 2

1 1 Select register bank 3

 8051 FLAG BITS AND THE PSW REGISTER
• PSW:It is 8 bits wide but use only 6 bits .There are 4
conditional flags (CY,AC,P & OV) , 2 user-definable flags
(PSW.1 & PSW.5) and 2 register bank selector(RS1 &
RS0).
CY AC F0 RS1 RS0 OV P
CY PSW.7 Carry flag.
AC PSW.6 Auxiliary carry flag.
F0 PSW.5 Available to the user for general purpose.
RS1 PSW.4 Register Bank selector bit 1.
RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
-- PSW.1 User definable bit.
P PSW.0 Parity flag. Set/cleared by hardware each
instruction cycle to indicate an odd/even number of
1 bits in the accumulator.
RS1 RS0 Register Bank Address
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH
Problem1:
Show the status of the CY, AC, and P flags after the
addition of 38H and 2FH in the following instructions.
MOV A, #38H
ADD A, #2FH

Problem2:
Show the status of the CY, AC, and P flags after the
addition of 9CH and 64H in the following instructions.

MOV A, #9CH

ADDC A, #64H
 INTERNAL RAM
• There are 128 bytes of RAM in 8051 and their
assigned address are 00H to 7FH.
• A total of 32 bytes from location 00 to 1FH are
assigned for register banks.
• A total of 16 bytes from location 20H to 2FH are
assigned for bit addressable read/ write
memory.
• A total of 80 bytes form location 30H to 7FH are
used for normal read/ write storage memory,
which is called Scratch Pad.
INTERNAL RAM Contd.
INTERNAL RAM Contd.
 INTERNAL RAM Contd.
BANK 0 BANK 1 BANK 2 BANK 3

ADD NAME ADD NAME ADD NAME ADD NAME

7 R7 F R7 17 R7 1F R7
6 R6 E R6 16 R6 1E R6
5 R5 D R5 15 R5 1D R5
4 R4 C R4 14 R4 1C R4
3 R3 B R3 13 R3 1B R3
2 R2 A R2 12 R2 1A R2
1 R1 9 R1 11 R1 19 R1
0 R0 8 R0 10 R0 18 R0
WORKING REGISTER
 INTERNAL RAM Contd.
BYTE ADD BIT ADDRESS BYTE ADD

78 79 7A 7B 7C 7D 7E 7F B
2F I
7F
2E 70 71 72 73 74 75 76 77 T
2D 68 69 6A 6B 6C 6D 6E 6F
A
2C 60 61 62 63 64 65 66 67 D
D
2B 58 59 5A 5B 5C 5D 5E 5F
R
2A 50 51 52 53 54 55 56 57 E
S
29 48 49 4A 4B 4C 4D 4E 4F
S
28 40 41 42 43 44 45 46 47 A
B
27 38 39 3A 3B 3C 3D 3E 3F L
26 30 31 32 33 34 35 36 37 E

25 28 29 2A 2B 2C 2D 2E 2F R
24 E
20 21 22 23 24 25 26 27
G
23 18 19 1A 1B 1C 1D 1E 1F I
S
22 10 11 12 13 14 15 16 17 T 30
21 08 09 0A 0B 0C 0D 0E 0F E
R
20 00 01 02 03 04 05 06 07 GENERAL PURPOSE
 PSW Bits Bank Selection
RS1 (PSW.4) RS0 (PSW.3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1
Example: State the contents of the RAM locations after the following program:
SETB PSW.4 ; select bank 2
MOV R0,#99H ; load R0 with value 99H
MOV R1,#85H ; load R1 with value 85H
MOV R2,#3FH ; load R2 with value 3FH
MOV R7,#63H ; load R7 with value 63H
MOV R5,#12H ; load R5 with value 12H
Solution:

By default, PSW.3=0 and PSW.4; therefore, the instruction “SETB PSW.4” sets RS1=1
and RS0=0, thereby selecting register bank 2. Register bank 2 uses RAM location 10H-
17H. After the execution of the above program we have the following:

RAM location 10H has value 99H RAM location 11H has value 85H
RAM location 12H has value 3FH RAM location 17H has value 63H
RAM location 15H has value 12H
SPECIAL FUNCTION REGISTER
• Special Function Register (SFR) are areas of
memory that control specific functionality of the
8051 microcontroller.
• The SFRs allow the user to access the ports,
serial communication, control and access timers,
configure the 8051’s interrupt system and power
control system.
• Some SFRs can be accessed with bit operations
also, i.e they are bit addressable Special
Function Registers.
 SPECIAL FUNCTION REGISTER Contd..

• SCON: (Serial Control) SCON is used to

configure the behavior of the 8051’s serial
port.
• SBUF: (Serial Buffer) SBUF is used to
send and received data via serial port.
• IE: (Interrupt Enable) IE register is used to
enable and disable specific interrupt.
• IP: (Interrupt Priority) IP register is used to
specify the priority of each interrupt.
 SPECIAL FUNCTION REGISTER Contd..

• PCON: (Power Control) PCON register is used

to control the 8051’s power control mode.
• TCON: (Timer Control) TCON is used to control
the 8051’s timer and counter operation.
• TMOD: (Timer Mode) TMOD is used to control
the mode of operation of timer and counter.
• TL0/TH0: (Timer 0 Low/High )
• TL1/TH1: (Timer 0 Low/High )
SPECIAL FUNCTION REGISTER Contd..
Name Function Internal RAM Address (Hex)

A Accumulator 0E0
B Arithemetic 0F0
DPH Addressing external moeory 83
DPL Addressing external moeory 82

IE Interrupt enable control 0A8

IP Interrupt priority 0B8
P0 Input/output port latch 80
P1 Input/output port latch 90
P2 Input/output port latch 0A0
P3 Input/output port latch 0B0
PCON Power control 87
PSW Program status word 0D0
SCON Serial port control 98
SBUF Serial port data buffer 99
SP Stack pointer 81
TMOD Timer/ Counter mode control 89
TCON Timer/ Counter control 88
TL0 Timer 0 low byte 8A
TH0 Timer 0 high byte 8C
TL1 Timer 1 low byte 8B
TH1 Timer 1 High byte 8D
 The Stack and Stack Pointer
• The Stack is used to store data temporary during any
program execution.
• The 8 bit Stack Pointer is used to hold an internal Ram
address which is called the top of stack.
• Generally 8051 used Bank1 of internal Ram as the
Stack. So the default Stack pointer address is 07 h.
• When data is placed on the stack the SP increments
before storing data on the Stack.
• When data is retrieved from the Stack, the byte is read
from the stack , and then SP decrements.
• The Stack is used during PUSH, POP, CALL, RET
instruction.
A MICROCONTROLLER
DESIGN
 Process of memory block selector:
•Using simple logic gates :
D0

D7

D7 D0

A0

A0 – A11
4K*8
A11
A12
A13
CS
A14
A15
RD WR

MEMR
Logic gate as Decoder MEMW
• Using the 74LS138 3-8 decoder:
D0

D7

D7 D0

A0

A0 – A11
Y0 4K*8
A12 A Y1 A11
A13 B Y2
A14
C Y3
A15
G2A Y4 CE
GND Y5
G2B
Vcc G1 Y6
OE Vpp
Y7

MEMR
74LS138 as Decoder Vcc
CONNECTION WITH EXTERNAL PROGRAM ROM
8031
Vcc
EA P3.7 RD
P3.6 WR
PSEN OE Vpp
C
P2.7 E
A12 A12
P2.0 A8 A8 2864
(2764)
ALE G
8K*8
D Q A7 A7 PROGRAM
P0.7 AD7
ROM
74LS373
P0.0 AD0 A0 A0
OC D7 D0

D7

D0
Connection to External program ROM
 On chip-off chip ROM

8031/51 8051 8052

EA=GND EA=Vcc EA=Vcc

0000 0000 0000

ON-CHIP ON-CHIP
0FFF 1FFF
1000
OFF 2000
CHIP
OFF OFF
CHIP CHIP

FFFF FFFF FFFF

On chip and off-chip program code Access

8051 Connection with external data ROM
Vcc
P3.7 RD
P3.6 WR
PSEN OE Vpp
A15
A14 C
P2.7 A13 E
A12 A12
P2.0 A8 A8
G 8K*8
ALE
DATA
D Q A7 A7 ROM
P0.7 AD7

74LS373

P0.0 AD0 OC A0 A0
D7 D0

D7

D0

8051 Connection to External Data ROM

Connection to External Data ROM and External program ROM
8051
Vcc Vcc
P3.7 RD
EA P3.6 WR
PSEN O Vp OE Vpp
A15 E p CE
A14 CE
P2.7 A13
A12 A12 A12

A8 A8 A8 2864
P2.0 G 8K*8 (2764)
ALE DATA 8K*8
D Q A7 A7 ROM A7 PROGRAM
AD7 ROM
P0.7
74LS373

A0
P0.0 AD0 OC A0 A0
D7 D0 D0
D7 D0

D7

D0

8031 Connection to External Data ROM and External program ROM

 Connection with external data RAM
8051

P3.7 RD
P3.6 WR
PSEN WE OE
A15
A14 C
P2.7 A13
A13 E
A12 A12
P2.0 A8 A8
G 8K*8
ALE
DATA
D Q A7 A7 RAM
P0.7 AD7

74LS373

P0.0 AD0 A0 A0
OC D7 D0

D7

D0
 PART 2

INSTRUCTION SET AND

PROGRAMMING THE 8051
 INSTRUCTION SET OF 8051
MICROCONTROLLER

• MOVING DATA INSTRUCTION

• LOGICAL OPERATION
• ARITHMETIC OPERATION
• JUMP AND CALL INSTRUCTION
MOVING DATA INSTRUCTION
• There are 28 mnemonics that copy data from a source
to a destination, they may be divided in the following
three main types.
1. MOV destination, source
2. PUSH source or POP destination
3. XCH destination, source
• The following four addressing modes are used to
access data.
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Indirect addressing mode
 IMMEDIATE ADDRESSING MODE
• In immediate addressing mode data are
transferred in the register directly.
Mnemonics Operation Example Bytes Cycles/ T-
state
MOV A,#n Copy the immediate data byte n MOV A,#0A0H 2 1/12
to the A register

MOV Rr,#n Copy the immediate data byte n MOV R0,#0A0H 2 1/12
to the Rr register
MOV DPTR,#nn Copy the immediate 16 bit MOV DPTR,#1234h 3 2/24
number nn to the DPTR register
 REGISTER ADDRESSING MODE
• The data are transferred through register to register
using register addressing mode occur between
register A and R0 to R7. It is not possible to move the
data in between R0 to R7 using register addressing
mode.

Mnemonics Operation Example Bytes Cycles/T

-state
MOV A,Rr Copy the immediate data MOV A,R0 1 1/12
byte n to the A register
MOV Rr,A Copy the immediate data MOV R5,A 1 1/12
byte n to the Rr register
 DIRECT ADDRESSING MODE
• In Direct addressing mode all data are moves
or transferred through their direct address.
Mnemonics Operation Example Bytes Cycles/T-
state
MOV A,add Copy the data from direct address MOV A, 80H (P0) 2 1/12
add. to the A register
MOV add,A Copy the data from register A to direct MOV 90H,A (P1) 2 1/12
address add.

MOV Rr,add Copy the data from direct address MOV R0, 07H (R7) 2 2/24
add. to the Rr register
MOV add,Rr Copy the data from register Rr to MOV 0FH,R2 2 2/24
direct address add. (OFH is R7 of Bank 1)
MOV add1,add2 Copy the data from direct address MOV 5CH,77H 3 2/24
add1 to the direct address add2 (location of internal RAM)
MOV add,#n Copy the immediate data byte n to the MOV 5CH,# 77H 3 2/24
direct address add
 INDIRECT ADDRESSING MODE
• The Indirect addressing mode uses a register to hold the
actual address that will finally be used in data moves, the
register itself is not the address, but rather the number in the
register. In this mode only R0 and R1 register is used, often
called a data pointer.
Mnemonics Operation Example Bytes Cycles/T-
state
MOV @RP,#n Copy the immediate byte n MOV @R0,#80H 2 1/12
to the address in Rp.
MOV @Rp,add Copy the contents of add to MOV @R1,80H 2 2/24
the address in Rp

MOV @Rp,A Copy the data in A to the MOV @R0,A 1 1/12

address in Rp
MOV add,@RP Copy the content of the MOV 80H,@R1 2 2/24
address in Rp to add
MOV A, @Rp Copy the content of the MOV A, @R0 1 1/12
address in Rp to the A
register
 CODE MEMORY READ-ONLY
DATA MOVES
• Code Memory Read-Only Data Moves: The 8051 always access
the external code memory using Indirect addressing modes.
Where we uses MOVC instruction and the A register in
conjunction with DPTR or PC, which specify the external code
memory.
Mnemonics Operation Example Bytes Cycles/ T-
state

MOVC A,@A,+DPTR Copy the code byte, found MOV DPTR,#1234H 1 2/24
at the ROM address MOV A,#56H
formed by adding A and MOV C A,@A+DPTR
the DPTR, to A.

MOVC A,@A,+PC Copy the code byte, found MOV A,#56H 1 2/24
at the ROM address MOV C A,@A+PC
formed by adding A and
the PC, to A.
 EXTERNAL DATA MOVES
• The 8051 always access the external memory using
Indirect addressing modes. Where we uses MOVX
instruction, which specify the external memory.
Mnemonics Operation Example Bytes Cycles/
T-state
MOVX A,@DPTR Copy the content of the MOV DPTR,#8000H 1 2/24
external address in DPTR to A MOVX A,@DPTR
MOVX @DPTR,A Copy data from A register to MOV DPTR,#8000H 1 2/24
the external address in DPTR MOVX @DPTR,A

MOVX @Rp,A Copy data from A register to MOV R0,#7FH 1 2/24

the external address in Rp MOVX @R0,A

MOVX A,@Rp Copy the content of the MOV R1,#80H 1 2/24

external address in Rp to A MOVX A,@R1
 DATA EXCHANGE
• Exchange instruction actually move data in two
directions, form source to destination and
destination to source. Here the XCH instruction is
used
Mnemonics Operation Example Bytes Cycles/ t-
state
XCH A, Rr Exchange the bytes between register XCH A, R3 1 1/12
A and register Rr.
XCH A,add Exchange the bytes between register XCH A,80H 2 1/12
A and address add.
XCH A,@Rp Exchange the bytes between register XCH A,@R1 1 1/12
A and address in Rp
XCHD A,@Rp Exchange the lower nibble between XCHD A,@R0 1 1/12
register A and the address in Rp
 PUSH AND POP
• Push opcode copies data from the source address
to stack.
• Pop opcode copies data from the stack to the
destination address.
Mnemonics Operation Example Bytes Cycles/ t-
state

PUSH add Increment sp, copy the data in Mov 81h,#30h 2 2/24
add to the internal RAM Mov Ro,#0ACh
address contained in SP Push 00h
POP add Copy the data from the internal Pop 01h 2 2/24
RAM address contained in SP
to add, and decrement the SP.
STACK IN THE 8051: When the 8051 is powered up , the SP register
contains value 07 i.e RAM location 08 is the first location being used for the stack by
the 8051.

• PUSH:The storing of a CPU register in the stack is called a PUSH.

EX. MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4
After PUSH 6 After PUSH 1 After PUSH 4

0B 0B 0B 0B

0A 0A 0A 0A
F3

09 09 09 09
12 12

08 08 08 08
25 25 25

Start SP = 07 Start SP = 08 Start SP = 09 Start SP = 0A

POP:The loading the contents of the stack back into a CPU register is
called a POP.

EX. POP 4 ;POP stack into R4

POP 1 ;POP stack into R1
POP 6 ;POP stack into R6

After P0P 3 After POP 5 After POP 2

0B 0B 0B 0B
54
0A 0A 0A 0A
F9 F9
09 09 09 09
76 76 76

08 08 08 08
6C 6C 6C 6C

Start SP = 0B Start SP = 0A Start SP = 09 Start SP = 08

 BIT LEVEL DATA MOVE
• The bit level data move opcodes operate on any
addressable RAM or SFR bit.
Mnemonics Operation Example Bytes Cycles/ t-state

MOV C,b Copy the address bit MOV C,7Fh 2 1/12

to the carry flag.
MOV b,C Copy the carry flag to MOV 7Fh,C 2 2/24
the address bit.

NOTE: only carry Flag will be affected.

 PROGRAM
• 1. write an ALP in 8051 to transfer a data from internal RAM
location 30h to external RAM location 8000h.
• 2. write an ALP in 8051 to transfer a data from external RAM
location 9000h to external RAM location 8000h.
• 3. write an ALP in 8051 to transfer a block of data. 10 data are
available in internal RAM location starting from 30h, Copy those
data to external RAM starting from 8000h.
• 4. write an ALP in 8051 to transfer a block of data. 10 data are
available in external RAM location starting from 9000h, Copy those
data to external RAM starting from 8000h.
• 5. write an ALP in 8051 to convert a decimal code to equivalent
ASCII code.
• 6. write an ALP in 8051 to convert a hexadecimal code to equivalent
ASCII code.
 LOGICAL OPERATION
• Logical operation includes AND ,OR, XOR, Complement
and Clear operation.
• LOGICAL AND OPERATION

Mnemonics Operation Example Bytes Cycles/ t-

state
ANL A, #n AND each bit of A with the same bit of ANL A, #60h 2 1/12
immediate date n, put the result in A.
ANL A,add AND each bit of A with the same bit of ANL A,80h 2 1/12
direct RAM address, put the result in A.
ANL A,Rr AND each bit of A with the same bit of ANL A,R0 1 1/12
register Rr, put the result in A.
ANL A,@Rp AND each bit of A with the same bit of ANL A,@R0 1 1/12
register pointer Rp, put the result in A.
ANL add,A AND each bit of A with the same bit of ANL 90h,A 2 1/12
direct RAM address, put the result in RAM.
ANL add,#n AND each bit of RAM address with the ANL 7fh,#n 3 2/24
same bit of immediate data n , put the
 LOGICAL OR OPERATION
Mnemonics Operation Example Bytes Cycles/ t-
state

ORL A, #n OR each bit of A with the same bit of ORL A, #60h 2 1/12
immediate date n, put the result in A.

ORL A,add OR each bit of A with the same bit of direct ORL A,80h 2 1/12
RAM address, put the result in A.

ORL A,Rr OR each bit of A with the same bit of ORL A,R0 1 1/12
register Rr, put the result in A.

ORL A,@Rp OR each bit of A with the same bit of ORL A,@R0 1 1/12
register pointer Rp, put the result in A.

ORL add,A OR each bit of A with the same bit of direct ORL 90h,A 2 1/12
RAM address, put the result in RAM.

ORL add,#n OR each bit of RAM address with the ORL 7fh,#n 3 2/24
same bit of immediate data n , put the
result in RAM
 LOGICAL XOR OPERATION
Mnemonics Operation Example Bytes Cycles/ t-
state
XRL A, #n XOR each bit of A with the same bit of XRL A, #60h 2 1/12
immediate date n, put the result in A.

XRL A,add XOR each bit of A with the same bit of XRL A,80h 2 1/12
direct RAM address, put the result in A.

XRL A,Rr XOR each bit of A with the same bit of XRL A,R0 1 1/12
register Rr, put the result in A.

XRL A,@Rp XOR each bit of A with the same bit of XRL A,@R0 1 1/12
register pointer Rp, put the result in A.

XRL add,A XOR each bit of A with the same bit of XRL 90h,A 2 1/12
direct RAM address, put the result in RAM.

XRL add,#n XOR each bit of RAM address with the XRL 7fh,#n 3 2/24
same bit of immediate data n , put the
result in RAM
 COMPLEMENT OPERATION
Mnemonics Operation Example Bytes Cycles/ t-
state
CLR A Clear each bit of A register to 0. CLR A 1 1/12

CPL A Complement each bit of A, CPL A 1 1/12

NOTE: No flags are affected by the byte level logical operations unless
the direct RAM address is the PSW.
 BIT LEVEL LOGICAL OPERATION
• Bit level logical operation also includes AND, OR and
Complement operation.
Mnemonics Operation Example Bytes Cycles/
t-state
ANL C,b AND C and the address bit, ANL C,70H 2 2/24
put the result in C
ANL C,/b AND C and complement of the ANL C,/80H 2 2/24
address bit, put the result in C
ORL C,b OR C and the address bit, ORL C,70H 2 2/24
put the result in C
ORL C,/b OR C and complement of the ORL C,/80H 2 2/24
address bit, put the result in C
CPL C Complement the Carry Flag CPL C 1 1/12
CPL b Complement the address bit CPL 81H 2 1/12
CLR C Clear the carry flag to 0 CLR C 1 1/12
CLR b Clear the address bit to 0 CLR 81H 2 1/12
SETB C Set the carry flag to 1 SETB C 1 1/12
SETB b Set the address bit to 1 SETB 20H 2 1/12
 ROTATE AND SWAP
INSTRUCTION
MNEMONICS OPERATION Example Bytes Cycles/ t-
state

RL A Rotate the A register one RL A 1 1/12

bit position to the left

RLC A Rotate the A register and RLC A 1 1/12

C Flag one bit position to
the left
RR A Rotate the A register one RR A 1 1/12
bit position to the right

RRC A Rotate the A register and RRC A 1 1/12

C Flag one bit position to
the right
SWAP A Interchange the nibble of SWAP A 1 1/12
register A
 ARITHMETIC OPERATION
• Arithmetic operation includes the basic four operation
Addition, Subtraction, Multiplication, Division,
Incrementing and Decrementing operation.
MNEMONICS OPERATION Example Bytes Cycles/ t-
state

INC A Add a 1 to the A register INC A 1 1/12

INC Rr Add a 1 to the Rr register INC R5 1 1/12

INC add Add a 1 to the content of the direct INC 80h 2 1/12
memory address.
INC @Rp Add a 1 to the content of memory INC @R0 1 1/12
address in Rp
INC DPTR Add a 1 to the 16 bit DPTR register. INC DPTR 1 2/24
 DECREMENTING OPERATION
MNEMONIC OPERATION Example Bytes Cycles/ t-
S state

DEC A subtract a 1 to the A register DEC A 1 1/12

DEC Rr Subtract a 1 to the Rr register DEC R4 1 1/12

DEC add Subtract a 1 to the content of the DEC 20h 2 1/12

direct memory address.
DEC @Rp Subtract a 1 to the content of DEC @R1 1 1/12
memory address in Rp

NOTE: No math flags are affected in increment and decrement operation.

 ADDITION OPERATION
MNEMONICS OPERATION Example Bytes Cycles/ t-
state
ADD A,#n Add A with the immediate ADD A,#0a0h 2 1/12
numberr, put the result in A.
ADD A,Rr Add A with the content of register ADD A,R6 1 1/12
Rr, put the result in A.
ADD A,add Add A with the content of the ADD A, 80h 2 1/12
direct address, put the result in A.
ADD A,@Rp Add A with the content of memory ADD A,@R1 1 1/12
address in Rp, put the result in A.
 ADDITION OPERATION
MNEMONICS OPERATION Example Bytes Cycles/
t-state
ADDC A,#n Add A with the immediate numberr ADDC A,#n 2 1/12
and the carry flag, put the result in A.
ADDC A,Rr Add A with the content of register Rr ADDC A,Rr 1 1/12
and the carry flag, put the result in A.
ADDC A,add Add A with the content of the direct ADDC A,add 2 1/12
address and the carry flag, put the
result in A.
ADDC A,@Rp Add A with the content of memory ADDC A,@Rp 1 1/12
address in Rp and the carry flag, put
the result in A.

Note: In addition operation all math flag will change.

 SUBTRACTION OPERATION
MNEMONICS OPERATION Example Bytes Cycles/
t-state
SUBB A,#n Subtract immediate number n and SUBB A,#40h 2 1/12
the carry flag from A, put the result
in A.
SUBB A,add Subtract the content of address and SUBB A,50h 2 1/12
the carry flag from A, put the result
in A.
SUBB A,Rr Subtract Rr and the carry flag from SUBB A,R0 1 1/12
A, put the result in A.
SUBB A, @Rp Subtract the content of the address SUBB A, @R1 1 1/12
in Rp and the carry flag from A, put
the result in A.

NOTE: All math flag will be affected.

 ADDITION AND DIVISION
OPERATION
MNEMONICS OPERATION Example Byte Cycles/
s t-state
MUL AB Multiply A by B, put the lower byte of the MUL AB 1 4/48
product in A, put the higher byte of the
product in B.
DIV AB Divide A by B, put the integer part of DIV AB 1 4/48
quotient in register A, and the integer part
of the reminder in B

NOTE: In multiplication and division operation carry flag always set to 0,

and the Ov flag will be set.
 JUMP AND CALL INSTRUCTION
• Jump instruction are divided into three category
1. Bit Jump
2. Byte Jump
3. Unconditional Jump
1. BIT JUMP

Mnemonics Operation

JC radd Jump relative if the carry flag is set to 1

JNC radd Jump relative if the carry flag is reset to 0

JB b,radd Jump relative if the addressable bit is set to 1

JNB b,radd Jump relative if the addressable bit is reset to 0

JBC b,radd Jump relative if the addressable bit is set to 1,and

clear the addressable bit
 BYTE JUMP
Mnemonics operation

CJNE A,add,radd Compare the A with the address, if they are not equal then
jump to the relative address
CJNE A,#n,radd Compare the A with the immediate data, if they are not equal
then jump to the relative address
CJNE Rr,#n,radd Compare the Rr with the immediate data, if they are not
equal then jump to the relative address
CJNE @Rp,#n,radd Compare the contents of the address in Rp with the
immediate data, if they are not equal then jump to the
relative address
DJNZ Rn,radd Decrement the Rn by 1 and jump to the relative address if
the result is not 0.
DJNZ add,radd Decrement thedirect address by 1 and jump to the relative
address if the result is not 0.

JZ radd Jump to the relative address if A is 0

JNZ radd Jump to the relative address if A is not 0

 UNCONDITIONAL JUMP

Mnemonics Operation
JMP @A+DPTR Jump to the address formed by adding A with DPTR

AJMP sadd(a11) Jump to the short range address

LJMP ladd(a16) Jump to the long range address

SJMP radd Jump to the relative address

NOP No operation
 CALL INSTRUCTION
MNEMONICS OPERATION

ACALL sadd(a11) Call the subroutine located in

short address.
LCALL ladd(a16) Call the subroutine located in
long address.
RET Return from subroutine.

RETI Return from interrupt

subroutine.
 Address Range
• Relative address: This is the difference between
two 16 bit numbers.
• Short address: This address is generated by 11bit
address. And maximum range is 2K bytes.
• Long address: This address is generated by 16 bit
address. And maximum range is 64K bytes.

A A A 0 0 0 0 1 A A A A A A A A
10 9 8 7 6 5 4 3 2 1 0

Short address generation for AJMP instruction.

A A A 1 0 0 0 1 A A A A A A A A
10 9 8 7 6 5 4 3 2 1 0

Short address generation for ACALL instruction.

Calculating short jump address:
• 1st byte is the opcode
• 2nd byte is the relative address
• Target address is relative to the value of PC

Example: Using the following list file, verify the jump forward address
calculation.
Line PC OPCODE Mnemonic Operand
01 0000 ORG 0000
02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
04 0004 6003 JZ NEXT
05 0006 08 INC R0
06 0007 04 AGAIN: INC A
07 0008 04 INC A
08 0009 2477 NEXT: ADD A,#77H
09 000B 5005 JNC OVER
10 000D E4 CLR A
11 000E F8 MOV R0,#A
12 000F F9 MOV R1,#A
13 0010 FA MOV R2,#A
14 0011 FB MOV R3,#A
15 0012 2B OVER: ADD A,#R3
16 0013 50F2 JNC AGAIN
17 0015 80FE HERE: SJMP HERE
18 0017 END
 First notice that the JZ and JNC instructions both jump forward. The target
address for a forward jump is calculated by adding the PC of the following
instruction to the second byte of the short jump instruction, which is called
the relative address. In line 4 the instruction “JZ NEXT” has opcode of 60 and
operand of 03 at the address of 0004 and 0005. The 03 is the relative
address, relative to the address of the next instruction INC R0, which is 0006.
By adding 0006 to 3, the target address of the label NEXT, which is 0009, is
generated. In the same way for line 9, the “JNC OVER” instruction has opcode
and operand of 50 and 05 where 50 is the opcode and 05 the relative address.
Therefore, 05 is added to 000D, the address of instruction “CLR A”, giving
12H, the address of label OVER.
(b) Solution:
In that program list, “JNC AGAIN” has opcode 50 and relative address F2H.
When the relative address of F2H is added to 15H, the address of the
instruction below the jump, we have 15H +F2H= 07 (the carry is dropped).
Notice that 07 is the address of label AGAIN. Look also at “SJMP HERE”,
which has 80 FE for the opcode and relative address, respectively. The PC of
the following instruction, 0017H, is added to FEH, the relative address, to get
0015H, address of the HERE label (17H+FEH). Notice that FEH is –2 and
17H+(-2)= 15H.
Write a program in 8051 assembly language to
transfer 10 numbers in the internal RAM starting
from 30H from external RAM, data are stored from
memory location 8050H.

• MOV DPTR,#8050H
• MOV R5,#0AH
• MOV R1,#30H
• BACK: MOVX A,@DPTR
• MOV @R1,A
• INC DPTR
• INC R1
• DJNZ R5,BACK
• HERE:SJMP HERE
 ASSEMBLER DIRECTIVES
• ORG:The ORG directives is used to indicate
the beginning of the address.
• EQU (equate):This is used to define a
constant without occupying a memory location.
Ex. COUNT EQU 25
……….. ………….
MOV R3,#COUNT
• END:This indicates to the assembler the end
of the source file.
 DATA TYPES & DIRECTIVES
• The 8051 micro controller has only one data
type of 8 bits & the size of each register is 8
bits. Data may be unsigned or signed.

• DB is used to define data, that can be in

decimal, binary or ASCII formats.

Ex. ORG 500H ;

DATA1 DB 28 ;Decimal(1C inhex)
DATA2 DB 00110101B ;Binary (35 in hex)
DATA3 DB 39H ;Hex
ORG 510H
DATA4 DB “2591” ;ASCII NUMBER
• ASSEMBLY LANGUAGE:By which we command
the CPU is called an Assembly language ,it is a series
of statements or lines.
• FEATURES OF ASSEMBLY LANGUAGE:
1. One instruction appears per line
2. Labels, which give names to memory locations, start in the
first column
3. Instructions must start in the second column or after to
distinguish them from labels
4. Comments run from some designated comment character
to the end of the line
• ASSEMBLY LANGUAGE INSTUCTION:
MOV: EX.MOV A,#55H ;Load value 55H into reg. A
MOV R0,A ;Copy contents of A into R0
;(now A=R0=55H)

ADD:EX.ADD A,R7 ;add to A content of R7

;where A=A+R7
 TIME DELAY GENERATION AND CALCULATION

CPU to execute an instruction takes a certain number of

clock cycles. These clock cycles are referred as ‘Machine
Cycles’. The length of the machine cycle depends on the
frequency of the crystal oscillator. One machine cycle
lasts for 12 oscillator periods. Therefore, to calculate the
machine cycle, we take 1/12 of the crystal frequency,
then take the inverse.
Ex.: for 16 MHz crystal oscillator calculation machine
cycle is as followed:
16MHz/12=1.333MHz
Machine cycle=1/1.333MHz=0.75microseconds
 Delay program using 8 bit register
• MOV R0,#FFH
HERE: DJNZ R0, HERE

• MOV R0,#255
HERE1: MOV R1,#200
HERE: DJNZ R1,HERE
DJNZ R0,HERE1

• MOV R0,#FFH
HERE2: MOV R1,#FFH
HERE1: MOV R2,#FFH
HERE: DJNZ R2,HERE
DJNZ R1,HERE1
DJNZ R0,HERE2
Example1: Find the size of the delay in the following program, if the crystal
frequency is 11.0592 MHz.

MOV A,#55H
AGAIN: MOV P1,A
ACALL DELAY
CPL A
SJMP AGAIN
;……………..Time delay
DELAY: MOV R3,#200
HERE: DJNZ R3,HERE
RET

Solution:

From Table A-1 in Appendix A, the following machine cycles for each
instruction of the DELAY subroutine.

Machine cycle
DELAY: MOV R3,#200 1
HERE: DJNZ R3,HERE 2
RET 1

Therefore, the total time delay=[(200*2)+1+1]*1.085 s=436.17 s.

Example 2: For a machine cycle of 1.085 s, find the time delay in the
following subroutine.

DELAY: Machine cycle

MOV R2,#200 1
AGAIN: MOV R3,#250 1
HERE: NOP 1
NOP 1
DJNZ R3,HERE 2
DJNZ R2,AGAIN 2
RET 1

For the HERE loop, (4*250)1.085 s= 1085 s. The AGAIN loop
repeats the HERE loop 200 times; therefore, 200*1085 s= 217000, if we do
not include the overhead. However, the instructions “MOV R3,#250” and
“DJNZ R2,AGAIN” at the beginning and end of the AGAIN loop add
(3*200*1.085 s)= 651 s to the time delay. As a result we have
217000+651= 217651 s= 217.651 milliseconds for total time delay
associated with the above DELAY subroutine.
1. Write a program to get the x value from P1 and send x2 to P2, continuously
Solution:

ORG 0
MOV DPTR, #300H ; LOAD LOOK-UP TABLE ADDRESS
MOV A, #0FFH ; A=FF
MOV P1, A ; CONFIGURE P1 AS INPUT PORT
BACK: MOV A, P1 ; GRT X
MOVC A, @A+DPTR ; GET X SQUARE FROM TABLE
MOV P2, A ; ISSUE IT TO P2
SJMP BACK ; KEEP DOING IT

ORG 300H
XSQR_TABLE:
DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81
END

Answer the following questions for this example.

(a) Indicate the content of ROM locations 300 – 309H.
(b) At what ROM locations is the square of 6, and what value should be there?
(c) Assume that P1 has a value of 9: what value is at P2 (in binary)?

Solution:
(a) All values are in hex.
300 = (00) 301 = (01) 302 = (04) 303 = (09)
304 = (10) 4 * 4 = 16 = 10 in hex
305 = (19) 5 * 5 = 25 = 19 in hex
306 = (24) 6 * 6 = 36 = 24H
307 = (31) 308 = (40) 309 = (51)

(b) 306H; it is 24H

© 01010001B which is 51H and 81 in decimal (92 = 81).

 TIMER/COUNTER

Timer: To generate time delay.

Counter: To count any external event.
Both timer0 & timer1 registers are 16 bit wide.
8051 has 8 – bit architecture. So 16 – bit timer is
accessed as two separate registers of low byte (TL0/TL1)
& high byte (TH0/TH1).

clock source of timer is the 1/12 of the crystal

frequency.
 Timer 0 register:
TH0 TL0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 1register:Timer 1 is same as timer 0 but the high and low bytes referred to as TH1 & TL1.
TMOD register:Both timer 0 and timer 1 use the same register,called TMOD, to set the various timer
operation modes. (MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
GATE:Gating control when set.Timer/counter is enabled only while the INTx pin is high and the TRx
control pin is set.When cleared ,the timer is enabled whenever the TRx control bit is set.
C/T: Cleared for timer operation and set for counter operation.
M1: Mode bit 1.
M0: Mode bit 0.
M1 M0 Mode Operating Mode
0 0 0 13-bit timer mode
0 1 1 16-bit timer mode
1 0 2 8-bit auto reload
1 1 3 Split timer mode

EX.:Find the value for TMOD if we want to program timer 0 in mode 2, use 8051 XTAL
for the clock source, and use instructions to start and stop the timer.
 When GATE=1 in TMOD

XTAL
12
oscillator
C/T=0

T0 pin C/T=1
Pin 3.4
TR0

Gate

INT0 pin
Pin 3.2 Timer/counter 0
 TIMER CONTROL REGISTER (TCON)
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF1 TCON.7 Timer 1 overflow flag.Set by hardware when

timer/counter 1 overflows.Cleared by hardware as the
processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit.Set by software to turn
timer/counter 1on/off.
TF0 TCON.5 Timer 0 overflow flag.Set by hardware when
timer/counter 0 overflows.Cleared by hardware as the
processor vectors to the interrupt service routine.
TR0 TCON.4 Timer 0 run control bit.Set by software to turn
timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag.Set by CPU when the
external interrupt edge(H-to-L transition) is
detected.Cleared by CPU when the interrupt is processed.
IT1 TCON.2 Interrupt 1 type control bit.Set/cleared by software to
specify falling edge/low-level triggered external interrupt.
IE0 TCON.1 External interrupt 0 edge flag.Set by CPU when the
external interrupt edge(H-to-L transition) is
detected.Cleared by CPU when the interrupt is processed.
IT0 TCON.0 Interrupt 0 type control bit.Set/cleared by software to
specify falling edge/low-level triggered external interrupt.
 XTAL
oscillator
12 THX(8 BIT) TF
TLX(5 BIT)

TF goes high overflow

When FF1F 0 flag

C/T=0 TR

MODE 0 13 BIT TIMER/COUNTER

XTAL
oscillator
12 THX TLX TF

TF goes high overflow

When FFFF 0 flag

C/T=0 TR

MODE 1 16 BIT TIMER/COUNTER

Mode 1 programming:
1. It is a 16 bit timer is; therefore ,it allows values of 0000 to FFFFH to be loaded
into the timer registers TL & TH.
2. After TH and TL are loaded with a 16-bit initial value,the timer must be
started.This is done by “SETB TR0” for timer 0.
3. After the timer is started , it starts to count up.It counts up until it reaches its
limit TF(timer flag).This timer flag can be monitored.
4. After the timer reaches its limit and rolls over, in order to repeat the process the
registers TH and TL must be reloaded with the original value, and TF must be
reset to 0.

EX. Creating a square wave of 50% duty cycle (with equal position high and low) on
the P1.5 bit.Timer 0 is used to generate the time delay.

MOV TMOD,#01 ;Timer 0,mode 1 (16-bit mode)

HERE: MOV TL0,#0F2H ;TL0=F2H, the low byte
MOV TH0,#0FFH ;TH0=FFH, the high byte
CPL P1.5 ;toggle P1.5
ACALL DELAY
SJMP HERE ;load TH,TL again
;----------------delay using timer 0
DELAY:
SETB TR0 ;start the timer 0
AGAIN JNB TF0,AGAIN ;monitor timer flag 0 until
;it rolls over
CLR TR0 ;stop timer 0
CLR TF0 ;clear timer 0 flag
RET
 CALCULATION OF TIME DELAY & SQUARE WAVE
GENERATION OF CRYSTAL FREQUENCY 12MHz

MODE1:
(a) In hex:
(FFFF – YYXX+1) * 1microsec, where YYXX are TH, TL initial value
respectively (for 12 MHz crystal oscillator).

(b) In decimal:
(65536 – nnnnn) * 1microsec, nnnnn will be converted into hex value.

DELAY=[[{256-(THX+1)}x256 + (256-TLX)]X12] / Fosc

Problem 1: To create a square wave of 50% duty cycle, timer delay 14
microsecond with crystal freq. 12 MHz.

Problem 2: Calculate the actual freq. Generated in problem 1.

Problem 3: What is the possible largest time delay excluding overhead due
to the instruction in the loop.
 XTAL Overflow
oscillator
12 TL TF flag

reload

C/T=0 TR
TF goes high
Delay=(256-TLX)X12/ Fosc TH When FF 0

MODE2 AUTO RELOAD OF TL FROM TH

PULSE INTERRUPT
TL0 (8BIT) TF0
INPUT

F/12 TH0 (8 BITS) TF1 INTERRUPT

TR1 BIT IN
TCON

MODE 3, TWO 8 BIT TIMER USING TIMER 0

MODE 2 PROGRAMMING:
1. 8 bit timer, range is 00 to FFH to be loaded into the timer register TH
2. After loading copy to TL automatically.
3. Start timer by SETB instruction.
4. Timer starts to count up by incrementing the TL register up to FFH,
rolls over to 00, set the timer flag, TL is reloaded automatically with
the original value in TH register.
5. Clear TF.

EX.: MOV TMOD, #20H

MOV TH1, #5H
SETB TR1
BACK: JNB TF1, BACK
CPL P1.0
CLR TF1
SJMP BACK
Find the freq. Of the square wave generated on pin 1.0 & the smallest
Frequency achievable in this program.
 Find the delay generated by timer 0 in the following code, using both of the methods of Figure 9-4. Do not include
the overhead due to instructions.

CLR P2 . 3 ; clear P2 . 3
MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode)
HERE: MOV TL0, #3EH ; TL0 = 3E, low byte
MOV T01, #0B8H ; TH0 = B8, high byte
SETB P2 . 3 ; set high P2 . 3
SETB TR0 ; start the timer 0
AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0
CLR TR0 ; stop the timer 0
CLR TF0 ; clear timer 0 flag for next round
CLR P2 . 3
Solution:
(a) (FFFF – B83E + 1) = 47C2H = 18370 in decimal and 18370*1.085 s = 19.93145 ms.
(b) Since TH – TL = B83EH = 47166 (in decimal) we have 65536 – 47166 = 18370. This means that the timer
counts from B83EH to FFFF. This plus rolling over to 0 goes through a total of 18370 clock cycles, where each clock
is 1. 085 s in duration. Therefore, we have 18370*1.085 s =19.93145 ms as the width of the pulse.

Modify TL and TH in Example above to get the largest time delay possible. Find the delay in ms. In your calculation,
exclude the overhead due to the instructions in the loop.

Solution:
To get the largest delay we make TL and TH both 0. This will count up from 0000 to FFFFH and then roll over to zero.

CLR P2 . 3 ; clear P2 . 3
MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode)
HERE: MOV TL0, # 0 ; TL0 = 0, the low byte
MOV TH0, # 0 ; TH0 =0, the high byte
SETB P2 . 3 ; set high P2 . 3
SETB TR0 ; start timer 0
AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0
CLR TR0 ; stop timer 0
CLR TF0 ; clear timer 0 flag
CLR P2 . 3

Making TH and TL both zero means that the timer will count from 0000 to FFFF, and then roll over to raise the TF flag. As a
result, it goes through a total of 65536 states. Therefore, we have delay = (65536-0) x 1. 085 s = 71. 1065 ms.
Assuming that XTAL = 11.0592 MHz, write a program to generate a square wave of 2 kHz frequency on pin P1.5.

Solution:
Here we must toggle the bit to generate the square wave. Look at the following steps.
(a) T = 1 / f = 1 / 2 kHz = 500 s the period of square wave.
(b) 1 / 2 of it for the high and low portion of the pulse is 250 s.
(c) 250 s / 1.085 s = 230 and 65536 – 230 = 65306 which in hex is FF1AH.
(d) TL = 1A and TH = FF, all in hex. The program is as follows:

MOV TMOD, #10H ; timer 1, mode 1 (16 – bit)

AGAIN: MOV TL1, #1AH ; TL1 = 1A, low byte of timer
MOV TH1, #0FFH ; TH1 = FF, Hi byte
SETB TR1 ; start the timer 1
BACK: JNB TF1, BACK ; stay until timer rolls over
CLR TR1 ; stop timer 1
CPL P1.5 ; comp. P1.5 to get hi, lo
CLR TF1 ; clear timer flag 1
SJMP AGAIN ; reload timer since mode 1
; is not auto-reload
Counters:When C/T=1, in TMOD register the timer is used as a
counter and gets its pulses from pin 14 and 15.This pins are called T0
and T1& belongs to port 3.

EX.

Assuming that clock pulses are fed into pin T1, write a program for counter 1
in mode 2 to count the pulses and display the state of the TL1 count on P2.

MOV TMOD,#01100000B
MOV TH1,#0
SETB P3.5
AGAIN SETB TR1
BACK MOV A,TL1
MOV P2,A
JNB TF1,BACK
CLR TR1
CLR TF1
SJMP AGAIN
 Overflow
Timer 0 flag
External
Input TH0 TL0 TF0
Pin 3.4

C/T=1
TF0 goes high
TR0 When FFFF 0

Timer/Counter 0 with External Input (Mode 1)

Timer 0 Overflow flag

External
Input TL0 TF0
Pin 3.4
reload
C/T=1
TR0 TH0
TF0 goes high When FF 0
Timer/Counter 0 with External Input (Mode 2)
 Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses
and display the state of the TL1 count on P2.
Solution:

MOV TMOD, #0110000B ; counter 1, mode 2, C/T= 1; external pulses

MOV TH1, # 0 ; clear TH1
SETB P3 . 5 ; make T1 input
AGAIN: SETB TR1 ; start the counter
BACK: MOV A, TL1 ; get copy of count TL1
MOV P2, A ; display it on port 2
JNB TF1, BACK ;keep doing it if TF =0
CLR TR1 ; stop the counter
CLR TF1 ; make TF=0
SJMP AGAIN ; keep doing it

Notice in the above program the role of the instruction “SETB P3 . 5”. Since ports are set up for output
when the 8051 is powered up, we make P3 . 5 an input port by making it high. In other words. We must
configured (set high) the T1 pin (pin P3 . 5) to allow pulses to be fed into it.

8051

P2 To LEDs
P2 is connected to 8 LEDs
And input T0 to pulses. P3.5
T1
 8051 SERIAL COMMUNICATION
1. Serial communication is used for transferring data between two systems
located at distances of feet to millions of miles apart.
2. Data must be converted in serial bits.
3. To send data using parallel-in serial-out register.
4. To receive data using serial-in parallel-out register.
5. Protocol has to be maintained between sender and receiver.
Types of serial communication data:
1. Synchronous:Transfer a block of data.
2. Asynchronous:Transfer a single byte at a time.

Start and stops bit:In asynchronous serial communication , each character is

placed in between start and stop bits. This is called framing.

Start
space Stop 0 1 0 0 0 0 0 1 mark
bit
bit

d7 d0
Goes out first
Goes out last
Data transfer rate:The rate of data transfer in serial communication is stated in bps.
Simplex Transmitter Receiver

Transmitter Receiver
Half Duplex
Receiver Transmitter

Transmitter Receiver
Full Duplex
Receiver Transmitter

Simplex, Half & full duplex Transfers

• Methods of Serial Communication

1. Synchronous &

2. Asynchronous

The Synchronous method transfers a block of data

(characters) at a time while the Asynchronous transfers a single
byte at a time. Special IC chips made by many manufacturers for
serial data communications, commonly referred to as UART and
USART. The 8051 chip has a built-in UART.
8051 CONNECTION TO RS232:
RS232 is the most widely used serial I/O interfacing standard. In RS232 1 is
represented by –3 to –25 V & 0 is represented by +3 to +25V. For conversion from TTL
to RS232 standard, MAX232 IC chip is used.

+
C3 8051
+ 16 2 MAX232
C1 1
6 11 11
3 P3.1 5
14 2
+ C4 TXD
4 +
C2
5 13 3
T1IN 10 12
11 14 P3.0
R1OUT RXD DB-9
12 13
T2IN
10 7
R2OUT
9 8

TTL SIDE 15 RS232 side

SERIAL COMMUNICATION WITH 8051:

Baud rate is to be selected with the help of Timer 1 with auto

reload mode.
Clock for 8051 UART circuitry: Divide machine cycle by 32 before it is
used by timer 1 to set the baud rate.
For various baud rates, TH1 must be loaded with the following values:
(XTAL = 11.0592 MHz), Why TH1?

BAUD RATE TH1 (decimal) TH1(hex)

9600 -3 FD
4800 -6 FA
2400 -12 F4
1200 -24 E8
SBUF register:SBUF is an 8-bit register used solely for serial
communication in the 8051.For a byte of data to be transferred via the TXD
line, it must be placed in the SBUF register.Similarly it holds the byte of data
received by 8051’s RXD line.
SCON register:The SCON register is an 8-bit register used to program the
start bit,stop bit,and data bits of data framing.

SM0 SM1 SM2 REN TB8 RB8 T1 R1

SM0 SCON.7 Serial port mode specifier
SM1 SCON.6 Serial port mode specifier
SM2 SCON.5 used in mode 2 & 3,set to 1 when bit 9 of received data is 1
and a interrupt is generated.
REN SCON.4 Set/cleared by software to enable/disable reception.
TB8 SCON.3 transmitted bit 8 in modes 2 & 3, set/cleared by program
RB8 SCON.2 received bit 8 in mode 2 & 3, stop bit in mode 1, not used in
mode 0.
T1 SCON.1 Transmit interrupt flag.Set by hardware at the beginning of
the stop bit in mode 1. Must be cleared by software.
R1 SCON.0 Receive interrupt flag.Set by hardware halfway through the
stop bit time in mode 1.Must be cleared by software.
 SM0 SM1
0 0 : Serial mode 0, shift register, baud = f/12
0 1 : Serial mode 1, 8 bit UART, baud = variable
1 0 : 9 bit UART, baud = f/32 or f/64
1 1 : 9 bit UART, baud = variable

REN: receive enable bit (SCON.4) When it is high, it allows the 8051 to
receive data on the RXD pin,

TI: Transmit interrupt (SCON.1) When 8051 finishes the transfer of 8 bit
character, TI flag will be high to indicate that it is ready to transfer another byte.

RI: Receive interrupt (SCON.0) When 8051 receives data, it places the byte in
SBUF register (excluding start and stop bit) and raises RI flag to indicate that a byte is
in SBUF to pick up.
• Mode 0: in mode 0 SBUF configures to receive or transmit 8
data bits using RXD pin for both functions. Pin TXD is
connected to the internal shift frequency pulse source to
supply shift pulses to external circuits. Here the baud rate is
fixed at 1/12 of the oscillator frequency.
• Mode 1: In mode 1 8051’s UART becomes a 10 bit full-duplex
receiver/transmitter that may receive and transmit data at the
same time. Pin RXD receive all data. Pin TXD transmit all
data.
• 10 bit data is configured as a start bit, 8 data bits and a stop
bits. A TI flag is set once when all ten bits have been send.
• The RI flag is set when it received ten data. Of the original 10
bit start bit is discarded, the 8 data bits go to SBUF register,
and stop bit go to RB8 of SCON register.
• Timer 1 is used to generate baud rate. Typically timer1 is
used in mode 2 as an auto reload mode, which generate the
baud frequency.
2 SMOD oscillator frequency
• f baud= ------------ X --------------------------
32d 12d X [256 –(TH1)]
• Mode 2: Here 11 bits are transmitted, a start bits, 9 data
bits and a stop bits. The ninth data bit is copied from TB8
in SCON during transmit and stored in RB8 of SCON
during receive.both start and stop bit are discarded.
Baud rate is as follows:
2 SMOD
• F baud= ----------- x oscillator frequency
64d
Functions of RI and TI flag will be same as mode 1.
• Mode 3: mode 3 is identical to mode 2except that the
baud rate is determined exactly as in mode 1, using
timer 1 to generate communication frequency. Baud rate
is:
2 SMOD oscillator frequency
• f baud= ------------ X --------------------------
32d 12d X [256 –(TH1)]
 POWER MODE CONTROLL(PCON) REGISTER
SMOD -------- --------- ---------- GF1 GF0 PD IDL
BIT SYMBOL FUNCTION
7 SMOD Serial baud rate modify bit. Set to 1 by program to
double the baud rate using timer 1 for modes 1, 2 and 3,
cleared to 0 by program to use timer 1 baud rate.
6 ------ not implemented
5 ------ not implemented
4 ------ not implemented
3 GF1 General purpose user flag bit 1, se/ cleared by program
2 GF0 General purpose user flag bit 0, se/ cleared by program
1 PD Power down bit, set to 1 by program to enter power
down mode.
0 IDL Idle mode bit, set to 1 by program to enter into idle mode
 Programming the 8051 for serial communication

1. The TMOD register is loaded with the value 20H, indicating

the use of timer 1 in mode 2 (8-bit auto-reload) to set the bud
rate.
2. The TH1 is loaded with one of the values of baud rate for
serial data transfer (assuming XTAL =11.0592 MHz).
3. The SCON register is loaded with the value 50H, indicating
serial mode 1, where an 8-bit data is framed with start and
stop bits.
4. TR1 is set to 1 to start timer 1.
5. T1 is cleared by the “CLR T1” instruction.
6. The character byte to be transferred serially is written into
the SBUF register.
7. The T1 flag bit monitored with the use of the instruction “JNB
T1,xx” to see if the next character, go to step 5.
 With XTAL = 11.0592 MHz. Find the TH1 value needed to have the following baud rates. (a) 9600, (b) 2400,
(c) 1200
Solutions:

With XTAL = 11.0592 MHz, we have:

The machine cycle frequency of the 8051 = 11.0592 MHz / 12 = 921.6 kHz, and 921.6 kHz / 32 = 28,800 Hz
is the frequency provided by UART to timer 1 to set baud rate.

(a) 28,800 / 3 = 9600 where – 3 = FD (hex) is loaded into TH1

(b) 28,800 / 12 = 2400 where – 12 = F4 (hex) is loaded into TH1
© 28,800 / 24 = 1200 where – 24 = E8 (hex) is loaded into TH1

Notice that dividing 1/12th of the crystal frequency by 32 is the default value upon activation of the
8051RESET pin. We can change this default setting.

XTAL Machine cycle freq. 32 28800 Hz

oscillator 12 921.6 kHz
By UART To timer
to set the
baud rate
Program for the 8051 to transfer letter “’A” serially at 4800 baud
rate.

MOV TMOD, # 20H ;timer1, mode 2

MOV TH1,# 0FAh ;
MOV SCON,# 50h ; 8bit, 1 stop bit, REN enabled
SETB TR1 ;
MOV SBUF,#”A”
HERE: JNB T1, HERE
CLR TI

1. Write a program to transfer the message “FINE” serially at 2400 baud

rate, 8 bit data, 1 stop bit.

2. Program 8051 to receive bytes of data serially and put them in P1. Set
the baud rate 2400, 8-bit data, 1 stop bit.
 Interrupts & Polling
Two ways by which a micro controller can serve several devices.

1. Interrupt: The program associated with interrupt is called Interrupt

service routine. Many devices can be served by assigning priority, but
not at the same time. In interrupt method the micro controller can ignore
a device request for service.

2. Polling: In polling, the micro controller continuously monitors the

status of a given device; when the condition is met, it performs the
service. The main disadvantage of polling is that it wastes much of the
micro controller’s time. It is not possible to assign priority and ignore a
device for service since polling method checks all devices in a round-
robin process.
Steps in executing interrupt:

After activation of an interrupt, the micro controller goes through the

following steps:
1. Finishes the instruction it is executing and saves the address of
the next instruction on the stack.
2. Saves the current status of all the interrupts.
3. Jumps to a fixed location in memory called the interrupt vector
table that holds the address of the interrupt service routine.
4. The micro controller gets the address of the ISR from the
interrupt vector table, jumps to it and starts to execute it.
5. After executing RETI instruction, the micro-controller returns
to the place from where it was interrupted and starts to execute
from that address.
INTERRUPT PROGRAMMING: An interrupt is an external event
that interrupts the micro controller to inform it that a device needs its
service.The 8051 has 6 interrupts, 5 of which are user-accessible.

1. Reset: When this reset pin is activated, the 8051 jumps to address
location 0000.

2. Two interrupts are set aside for the timers: One for timer 0 and one
for timer 1.Memory locations 000BH and 001BH in the interrupt vector
table belong to timer 0 and timer 1 respectively.

3. Two interrupts are set aside for external hardware interrupts.Memory

locations 0003H and 0013H in the interrupt vector table belong to INT0
and INT1 respectively.

4. Serial communication has a single interrupt that belongs to both receive

and transfer.The interrupt vector table location 0023H belongs to this
interrupt.
 D7 D0

EA --- ET2 ES ET1 EX1 ET0 EX0

IE REGISTER

EA IE.7 Disable all interrupts.If EA=0, no interrupt is acknowledged.If

EA=1, each interrupt source is individually enabled or
disabled by setting or clearing its enable bit.
-- IE.6 Not implemented, reserved for future use.*
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt
(8952).
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables timer 1overflow interrupt.
EX1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables timer 0 overflow interrupt.
EX0 IE.0 Enables or disables external interrupt 0.

* User software should not write 1s to reserved bits.These bits may be

used in future Flash micro controllers to invoke new features.
 Interrupt Vector Table for the 8051

Interrupt ROM Location (Hex) pin

Reset 0000 9
External hardware interrupt 0 (INT0) 0003 P3.2 (12)

Timer 0 interrupt (TF0) 000B

External hardware interrupt 1 (INT1) 0013 P3.3 (13)

Timer 1 interrupt (TF1) 001B

Serial COM interrupt (R1 and T1) 0023

Write a program to create a square wave that has a high portion of 1085 micro second and a low portion of 15 micro
second. Use Timer1.

ORG 0000H
LJMP MAIN

ORG 001BH
LJMP ISR_T1

ORG 0040H
MAIN: MOV TMOD,#10H ;timer1, mode 1
MOV P0,#0FFH
MOV TL1,#18H
MOV TH1,#0FCH
MOV IE,#88H ;enable timer 1 interrupt
SETB TR1
BACK: MOV A,P0
MOV P1,A
SJMP BACK

ISR_T1: CLR TR1

CLR P2.1 ; start of low portion
MOV R2,#4H
HERE: DJNZ R2, HERE
MOV TL1, #18H
MOV TH1,#0FCH
SETB TR1
SETB P2.1
RET1
END
Write a program to generate a square wave of 100 Hz frequency on pin 1.4 using interrupt for timer 0.XTAL = 12
MHz.
External interrupt:There are two activation levels for the external hardware
interrupts.

1.Level triggered:In level triggered mode, INT0 and INT1 pins are normally high
and if a low level signal is applied to them, it triggers the interrupt. Must be held in low
state until the start of execution of ISR. Must be removed before RETI.
Level-triggered
INT0
(Pin 3.2) IT0 0003
1 IE0
0 (TCON.1)
Edge-triggered

Level-triggered

INT1 0
(Pin 3.3) IT1 0013
1 1 IE1
0 (TCON.3)
Edge-triggered
Edge triggered:To make the interrupts edge triggered interrupts,we must program
the bits (IT0 AND IT1) of the TCON register. For edge triggered interrupt, source must
be held high at least one m/c cycle and then held low for at least one m/c cycle.

D7 D0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

IT0 TCON.0 Interrupt 0 type control bit

IE0 TCON.1 Interrupt 0 edge flag
IT1 TCON.2 Interrupt 1 type control bit
IE1 TCON.3 Interrupt 1 edge flag
TR0 TCON.4 Timer 0 run control bit
TF0 TCON.5 Timer 0 overflow flag
TR1 TCON.6 Timer 1 run control bit
TF1 TCON.7 Timer 1 overflow flag
Problem1:
Assume that the INT1 pin is connected to a switch that
is normally high. Whenever it goes low , it should turn on an
LED which is connected to pin P1.3. It should stay on for a
fraction of a second.

Problem2:
Write the same program using edge triggered interrupt.

What difference will you observe if you run the two programs
using a switch.
 TI
0023H
RI

Serial interrupt is invoked by TI or RI flags

SERIAL COMMUNICATION INTERRUPT:

Serial interrupt is invoked using TI or RI flags and interrupt vector table

at 0023h.
*Clear RI/TI flag before RETI instruction.

Problem:
Write a program in which the 8051 gets data from P1 and sends it
to P2 continuously while incoming data from serial port is sent to P0.
XTAL = 12 MHz, baud rate 9600.
 IP REGISTER
(bit addressable)

----- ----- PT2 PS PT1 PX1 PT0 PX0

PT2: Timer 2 int. priority bit

PS: Serial port int. priority bit
PT1: Timer 1 int. priority bit
PX1: External int.1 priority bit
PT0: Timer 0 int. priority bit
PX0: External int.0 priority bit

Problem: To make timer int. 1 highest priority, what will be the value in
IP register. What will be the sequence in which the interrupts are
serviced.
 INTEGRATED CIRCUIT TO BUILD AN
MICROCONTROLLER BASED EMBEDDED SYSTEM

1. Interfacing with external memory.

2. Interfacing with external I/O port.

3. Interfacing with seven segment display.

4. Interfacing with LCD.

5. Interfacing with keyboard.

Memory address decoding :

CPU provides the address of the data desired.

Decoding circuitry locates the selected memory

block.

Methods of decoding the address:

CS pin of memory chips must be activated.

Data bus of CPU connected to the data pins of

memory chip.

Control signals RD connected with OE (o/p

enable) and WR connected with WE (write
enable) of memory chip.
 Interfacing with 8255A
PA3 1 40 PA4
PA2 2 39 PA5
PA1 3 38 PA6
4 37 PA7
PA0
RD
CS
5
6
8 36
35
34
WR
RESET
D0
GND 7
A1
A0
8
9
2 33
32
D1
D2
10 31 D3
PC7
PC6
PC5
11
12
5 30
29
D4
D5
D6
PC4
PC0
PC1
13
14
15
5 28
27
26
D7
Vcc

PC2
PC3
PB0
16
17
18
A 25
24
23
PB7
PB6
PB5
PB1 19 22 PB4
PB2 20 21 PB3
 Interfacing with LCD +5V
+5V 10
K
G
1 2 3

Two Line X 20 Character EN

Intelligent LCD Display 6 14 P2.2
Enable High

14 13 12 11 10 9 8 7 5 4
D7 D6 D5 D4 D3 D2 D1 D0 R/W RS

12 P2.0

13 P2.1

1 P1.0
2 P1.1
3 P1.2
4 P1.3
5 P1.4
6 P1.5
7 P1.6
8 P1.7
 RS, register select: If RS=0, the instruction command code register
is selected, allowing the user to send a command such as clear display,
cursor at home, etc. if RS=1 the data register is selected, allowing the user
to send data to be displayed on the LCD.

R/W, read/write: R/W=1 when reading; R/W=0 when writing.

E, enable: When data is supplied to data pins, a high-to-low pulse

must be applied to this pin in order for the LCD to latch in the data present
at the data pins. This pulse be a minimum of 450 ns wide.

D0 – D7: To display letters and numbers, we send ASCII codes for

the letters A – Z, and a – z, and numbers 0 – 9 to these pins while making
RS=1. We also use RS=0 to check the busy flag bit to see if the LCD is ready
to receive information. It is recommended to writing any data to the LCD.
PIN SYMBOL DESCRIPTION
1 Vss Ground
2 Vcc +5v power supply
3 Vee Power supply to control contrast
4 RS R=0 command register, R=1 data register
5 R/W R/W=0 write, R/W=1 read
6 E Enable (active high)
7 DBO The 8 bit data bus
8 DB1 The 8 bit data bus
9 DB2 The 8 bit data bus
10 DB3 The 8 bit data bus
11 DB4 The 8 bit data bus
12 DB5 The 8 bit data bus
13 DB6 The 8 bit data bus
14 DB7 The 8 bit data bus
RS R/W D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION

0 0 0 0 0 0 0 0 0 1 Clear LCD and memory home curser

0 0 0 0 0 0 0 0 1 0 clear home curser only

0 0 0 0 0 0 0 1 I/O S S=1/0;shift screen /cursor

I/O=1/0; cursor R/L, screen L/R

0 0 0 0 0 0 1 D C B D=1/0; screen on/off,

C=1/0; cursor on/off,
B=1/0;blink/notblink
0 0 0 0 0 1 S/C R/L 0 0 S/C=1/0 screen/cursor
R/L=1/0; shift one space R/L
0 0 0 0 1 DL N F 0 0 DL=1/0;8/4 bit per character
N=1/0; 2/1 rows of character
F=1/0; 5x10/5x7 dots per character
0 1 BF Current address B/F=1/0 busy/notbusy

80h Force cursor to beginning of 1st line

C0h force cursor to beginning of 2nd line
• Write a program to display ABCD in a LCD screen.
ORG 0000H
MOV DPTR,#CONF
ACALL CONF_DISP
MOV DPTR,#MSG1
ACALL DISPLAY
HERE: SJMP HERE

CONF:
DB 38H,0EH,06H,01H,C0H,FFH
MSG1:
DB: 41H,42H,43H,44H,FFH
CONF_DISP:
CLR A
MOVC A,@A+DPTR
INC DPTR
CJNE A,#FFH,COMD
RET
COMD:
ACALL COMNWRT
ACALL DELAY
SJMP CONF_DISP
DISPLAY:
CLR A
MOVC A,@A+DPTR
INC DPTR
CJNE A,#FFH,DATA
RET
DATA:
ACALL DATAWRT
ACALL DELAY
SJMP DISPLAY
COMNWRT:
MOV P1,A
CLR P2.0
CLR P2.1
SETB P2.2
NOP
NOP
CLR P2.2
RET
DATAWRT:
MOV P1,A
SETB P2.0
CLR P2.1
SETB P2.2
NOP
NOP
CLR P2.2
RET
DELAY:
MOV R1,#50H
HERE2: MOV R2,#FFH
HERE1: DJNZ R2,HERE1
DJNZ R1,HERE2
RET
 INTERFACING A STEPPER MOTOR
+12V
+5V

STEPPER MOTOR
31 A 40
9 T
ULN 2803A
8
9 P2.3
18 C P2.4
LS373 LATCH
5 P2.5
19 1 P2.6
 Full step operation with one coil energized
STEP A B C D
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1

Full step operation with two coil energized

STEP A B C D
1 1 1 0 0
2 0 1 1 0
3 0 0 1 1
4 1 0 0 1
Half step operation with two coil energized
STEP A B C D

1 1 0 0 0
2 1 1 0 0

3 0 1 0 0
4 0 1 1 0

5 0 0 1 0

6 0 0 1 1

7 0 0 0 1

8 1 0 0 1
• Write a program to run a stepper motor in full
step configuration.
MOV A,#66H
BACK: MOV P2,A
RR A
ACALL DELAY
SJMP BACK
DELAY:
MOV R2,#50H
H1: MOV R3,#FFH
H2: DJNZ R3,H2
DJNZ R2,H1
RET
 Interfacing With ADC
• Input:
• analog signal with a voltage
e.g., pressure, light intensity, temperature,
sound
• Output
• digital value representing the voltage
• 8-bit, 10-bit, 12-bit, 16-bit, 24-bit etc
depends on the specific ADC's precision
 Purposes of ADC
• Digitize a signal
• The world is analog; computer is digital
=> bridge the real world & computer
• Benefits
• no more noise due to processing
• can be stored/retrieved like any data
• separate timing handling from processing
ADC0808: Multi-(analog)-channel
• Easy interface to all microprocessors
• Operates with 5 VDC
• Adjusted voltage reference
• No zero or full-scale adjust required
• 8-channel multiplexer with address logic
• 0V to 5V input range with single 5V power
supply
• Outputs meet TTL voltage level specifications
Pin Description
 Pin Description contd.
• IN0..IN7: analog input channels
•SC, EOC: (=WR, INTR)
start conv, end-of-conv
• OE: (=RD) output enable
• C B A : 3-bit channel select
• ALE: clock for latching CBA
• Do-D7: digital output
Analog Channel Selection
Timing Diagram
Interfacing 8051 With ADC0809
 Pin Connection between 8051 and
ADC0809
• ALE BIT P2.4
• OE BIT P2.5
• SC BIT P2.6
• EOC BIT P2.7
• ADDR_A BIT P2.0
• ADDR_B BIT P2.1
• ADDR_C BIT P2.2
• DATA P1
 Assembly Program
ORG 0000H
SETB P2.7 ;configure P2.7 as input
;port pin (EOC)
CLR P2.4 ;clear ALE
CLR P2.6 ;clear SC (start conversion)
CLR P2.5 ;clear OE (output enable)
BACK: CLR P2.2 ;ADDR_C
CLR P2.1 ;ADDR_B (select channel=1)
SETB P2.0 ;ADDR_A
ACALL DELAY
SETB P2.4 ; latch address (set ALE)
ACALL DELAY
 Assembly Program contd.
SETB P2.6 ;start conversion (set SC)
ACALL DELAY
CLR P2.4 ;clear ALE
CLR P2.6 ; clear SC
HERE: JB P2.7, HERE ; check EOC
HERE1: JNB P2.7, HERE1 ;check EOC
SETB P2.5 ;set OE
ACALL DELAY
MOV A, P1 :save data in A register
CLR P2.5 :clear OE
SJMP BACK
Interfacing with Seven segment decoder
a

f g b

e c

d
Segment pattern
a b c d e f g

Common cathode

Segment circuit
Connection with 8051(CA)
Connection with 8051(CC)
Display Data for CA Data for CC
.gfedcba(d7-d0) .gfedcba(d7-d0)
0 C0 3F
1 F9 06
2 A4 5B
3 B0 4F
4 99 66
5 92 6D
6 82 7D
7 F8 07
8 80 7F
9 98 67
 Program in CA Mode
HERE: MOV P2,#0C0H
ACALL DELAY
MOV P2,#0F9H
ACALL DELAY
MOV P2,#0A4H
ACALL DELAY
MOV P2,#0B0H
ACALL DELAY
MOV P2,#99H
ACALL DELAY
MOV P2,#92H
ACALL DELAY
MOV P2,#82H
ACALL DELAY
Program in CA Mode (CONTD.)
MOV P2,#0F8H
ACALL DELAY
MOV P2,#80H
ACALL DELAY
MOV P2,#98H
ACALL DELAY
SJMP HERE
 Program in CC Mode
HERE: MOV P2,#3FH
ACALL DELAY
MOV P2,#06H
ACALL DELAY
MOV P2,#5BH
ACALL DELAY
MOV P2,#4FH
ACALL DELAY
MOV P2,#66H
ACALL DELAY
MOV P2,#6DH
ACALL DELAY
MOV P2,#7DH
ACALL DELAY
Program in CC Mode (CONTD.)
MOV P2,#07H
ACALL DELAY
MOV P2,#7FH
ACALL DELAY
MOV P2,#67H
ACALL DELAY
SJMP HERE
 Program to display
HERE: SETB P3.5
MOV P1,#06H
SETB P3.4
MOV P1,#5BH
SETB P3.3
MOV P1,#4FH
SETB P3.2
MOV P1,66H
ACALL DELAY
SJMP HERE
THANK YOU