HKBK College of Engineering

Department of Electronics and Communication Engineering

SEMESTER - 3

Digital System Design Using Verilog

Teaching Learning Plan

Course Code BEC302 CIE Marks 50

Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory +8- 10 Total Marks 100
Lab slots
Credits 04 Exam Hours 03

Course Facilitator: Dr. C. Venkatesan

Faculty: Dr. Suhas A R

Pre-requisite: Basic Electronics

Programme Outcomes (POs) and Programme Specific Outcomes (PSOs)

a. Engineering Knowledge: Apply knowledge of mathematics, science, engineering fundamentals and an

engineering specialization to the solution of complex engineering problems.
b. Problem Analysis: Identify, formulate, research literature and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences and
engineering sciences
c. Design/ Development of Solutions: Design solutions for complex engineering problems and design
system components or processes that meet specified needs with appropriate consideration for public
health and safety, cultural, societal and environmental considerations.
d. Conduct investigations of complex problems using research-based knowledge and research methods
including design of experiments, analysis and interpretation of data and synthesis of information to
provide valid conclusions.
e. Modern Tool Usage: Create, select and apply appropriate techniques, resources and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an under- standing of the
limitations.
f. The Engineer and Society: Apply reasoning informed by contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to professional
engineering practice.
g. Environment and Sustainability: Understand the impact of professional engineering solutions in
societal and environmental contexts and demonstrate knowledge of and need for sustainable
development.
h. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
engineering practice.
i. Individual and Team Work: Function effectively as an individual, and as a member or leader in
diverse teams and in multi-disciplinary settings.
j. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as being able to comprehend and write effective reports and
design documentation, make effective presentations and give and receive clear instructions.
k. Life-long Learning: Recognize the need for and have the preparation and ability to engage in
independent and life- long learning in the broadest context of technological change.
l. Project Management and Finance: Demonstrate knowledge and understanding of engineering and
 management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.

PSOs
1. Professional Skills: An ability to understand the basic concepts in Electronics & Communication
Engineering and to apply them to various areas, like Electronics, Communications, Signal processing,
VLSI, Embedded systems etc., in the design and implementation of complex systems.
2. Problem-Solving Skills: An ability to solve complex Electronics and communication Engineering
problems, using latest hardware and software tools, along with analytical skills to arrive cost effective and
appropriate solutions.
3. An ability to become an entrepreneur or to contribute to industrial services and / or
Govt. organizations in the field of Electronics and Communication Engineering
4. An ability to work on multidisciplinary teams with efficiency in different Programming techniques.

Course Objectives:

1. To impart concepts of simplifying Boolean expression using K-map techniques and Quine- Mc
Cluskey minimization techniques.
2. To impart the concepts of designing and analyzing combinational logic circuits.
3. To impart design methods and analysis of sequential logic circuits.
4. To impart the concepts of Verilog HDL-data flow and behavioral models for the design of digital
systems.

Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.

1. Lecturer method (L) need not be only a traditional lecture method, but alternative effective teaching
methods could be adopted to attain the outcomes.
2. Use of Video/Animation to explain the functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher-order Thinking) questions in the class, which promotes critical
thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop design
thinking skills such as the ability to design, evaluate, generalize, and analyse information rather than
simply recall it.
6. Introduce Topics in manifold representations.
7. Show the different ways to solve the same problem and encourage the students to come up with their
own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.

Module-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of
switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey
Minimization Technique. Quine-McCluskey using Don’t Care Terms. (Section 3.1 to 3.5 of Text 1).
Teaching-Learning Process: Chalk and Talk, YouTube videos
Module-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors,
Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices (PLDs) (Section 5.1 to
5.7 of Text 2)
 Teaching-Learning Process: Chalk and Talk, YouTube videos
Module-3
Flip-Flops and its Applications: The Master-Slave Flip-flops (Pulse-Triggered flip-flops): SR flip-flops, JK
flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters,
Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, JK, D and SR
flip-flops. (Section 6.4, 6.6 to 6.9 (Excluding 6.9.3) of Text 2)
Teaching-Learning Process: Chalk and Talk, YouTube videos
Module-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description.
(Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3) Verilog Data flow description: Highlights of Data
flow description, Structure of Data flow description. (Section 2.1 to 2.2 (only Verilog) of Text 3)
Teaching-Learning Process: Chalk and Talk, PPTs,YouTube videos, Programming assignments
Module-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop
Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to 3.4 (only
Verilog) of Text 3) Verilog Structural description: Highlights of Structural description, Organization of
structural description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text 3)
Teaching-Learning Process: Chalk and Talk, PPTs, YouTube videos, Programming assignments

PRACTICAL COMPONENT OF IPCC

Using suitable simulation software, demonstrate the operation of the following circuits:
Sl.No Experiments
1. To simplify the given Boolean expressions and realize using Verilog program.
2. To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.
3. To realize 4-bit ALU using Verilog program.
4. To realize the following Code converters using Verilog Behavioral description a) Gray to binary
and vice versa b) Binary to excess3 and vice versa
5. To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder, Priority encoder
6. To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder, 2-bit Comparator
7. To realize using Verilog Behavioral description: Flip-flops: a) JK type b) SR type c) T type and d)
D type
8. To realize Counters - up/down (BCD and binary) using Verilog Behavioral description
Demonstration Experiments (For CIE only – not to be included for SEE)
Use FPGA/CPLD kits for downloading Verilog codes and check the output for interfacing experiments.
9. Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the
specified direction (by N steps).
10. Verilog programs to interface a Relay or ADC to the FPGA/CPLD and demonstrate its working.
11. Verilog programs to interface DAC to the FPGA/CPLD for Waveform generation.
12. Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its working

Course Outcomes (Course Skill Set)

At the end of the course the student will be able to:

Description Bloom’s
Sl. Course
Taxonomy
No. Outcome
Level
1. Simplify Boolean functions using K-map and Quine-Mc Cluskey
CO 1 1,2,3
minimization technique.
2. Analyze and design for combinational logic circuits.
CO 2 2,3,4

3. CO 3 Analyze the concepts of Flip Flops (SR, D, T and JK) and to design the 2,3,4
 synchronous sequential circuits using Flip Flops
4. Model Combinational circuits (adders, subtractors, multiplexers) and
CO 4 1,2,3
sequential circuits using Verilog descriptions.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/ course if
the student secures not less than 35% (18 Marks out of 50) in the semester-end examination (SEE), and a
minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and
SEE (Semester End Examination) taken together.
Continuous Internal Evaluation:
CIE for the theory component of IPCC:
Two Tests each of 20 Marks (duration 01 hour)
First test at the end of 5th week of the semester
 Second test at the end of the 10th week of the semester

Two assignments each of 10 Marks

 First assignment at the end of 4th week of the semester
 Second assignment at the end of 9th week of the semester

Scaled-down marks of two tests and two assignments added will be CIE marks for the theory component of
IPCC for 30 marks.
CIE for the practical component of IPCC
 On completion of every experiment/program in the laboratory, the students shall be evaluated and
marks shall be awarded on the same day. The 15 marks are for conducting the experiment and
preparation of the laboratory record, the other 05 marks shall be for the test conducted at the end of
the semester.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of
all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 03 hours) at the end of the 15th week of the semester /after completion
of all the experiments (whichever is early) shall be conducted for 50 marks and scaled down to 05
marks.
Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory component
of IPCC for 20 marks.
SEE for IPCC
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a CIE
component only. Questions mentioned in the SEE paper shall include questions from the practical
component.
 The minimum marks to be secured in CIE to appear for SEE shall be the 12 (40% of maximum
marks-30) in the theory component and 08 (40% of maximum marks -20) in the practical component.
The laboratory component of the IPCC shall be for CIE only. However, in SEE, the questions from
the laboratory component shall be included. The maximum of 04/05 questions to be set from the
practical component of IPCC, the total marks of all questions should not be more than the 20 marks.

SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify in the
SEE. Marks secured will be scaled down to 50

Text Books :
1. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning, 2001.
2. Digital Principles and Design by Donald D Givone, McGraw Hill, 2002.
 3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dreamtech press.
Reference Books:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Logic Design, by Sudhakar Samuel, Pearson/ Sanguine, 2007
3. Fundamentals of HDL, by Cyril P R, Pearson/Sanguine 2010
Web links and Video Lectures (e-Resources):
https://nptel.ac.in/courses/106105165
https://archive.nptel.ac.in/courses/108/103/108103179/
https://nptel.ac.in/courses/117106086
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
1. Poster/Chart preparation
2. Programming assignment
3. Group tasks

Google Classroom:
https://classroom.google.com/c/NTQ4NDgzMzgxMDM4?cjc=tgzppe6

Note: Classroom Contents

1. Notes
2. PPTs
3. Soft copy of Text Books/Reference books
4. Previous University QPs
5. Assignments
6. Question Banks

CO-PO/PSO Mapping:

PO-01 PO-02 PO-03 PO-04 PO-05 PO-06 PO-07 PO-08 PO-09 PO-10 PO-11 PO-12 PSO1 PSO2 PSO3 PSO4

CO01 3 3 3 2 2 2 3 3 3 2

CO02 3 3 3 2 2 2 3 3 3 2

CO03 3 3 3 2 2 2 3 3 3 2

CO04 3 3 3 2 3 3 3 3 2

Overall 3 3 3 2 2 2 3 3 3 2

Session-Wise Plan:

Mod Ses Topic CO Readings and Pedagogy and Assessment Planned Execution
ule sio References Date Date
n Synchronou Asynchron
s ous

1 1. Summarization of Pre 1 Syllabus copy a. PPT and -

requisite, Introduction Objectives, Discussion:
about the Course, Outcomes, PEOs, Review of
Relevance of COs, POs, PSOs pre requisites
POs, PSOs and PEOs and Course
introduction

1 2. Module-1: Principles 1a. T1-3.1 a. Chalk and Assignment

of Combinational b. Notes Talk PPT /Quiz
 Logic, Definition of http://
combinational logic, elearning.vtu.ac.in https://
/econtent/ quizizz.co
courses/video/ m/admin/
ECE/ quiz/
18EC34.html 632d56659
34b99001e
1 3. Canonical Forms 1c. T1-3.2 b. Chalk and 4085ec?
d. Notes Talk PPT source=qui
http:// z_share
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 4. Generation of 1e. T1-3.3 c. Chalk and

switching equations Notes Talk PPT
from truth tables http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 5. Karnaugh maps 3 1g. T1-3.4.1 d. Chalk and

variable h. Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 6. Karnaugh maps 4 1 T1-3.4.1 e. Chalk and

variable Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 7. Karnaugh maps 4 1k. T1-3.4.1 Chalk and

variable Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 8. Quine-McClusky 1m. T1-3.5 g. Chalk and

minimization n. Notes Talk PPT
techniques http://
elearning.vtu.ac.in
/econtent/
 courses/video/
ECE/
18EC34.html

1 9. Quine-McClusky 1o. T1-3.5 h. Chalk and

minimization p. Notes Talk PPT
techniques http://
elearning.vtu.ac.i
n/econtent/
courses/video/
ECE/
18EC34.html

1 10. Quine-McCluskey 1q. T1-3.5.1 Chalk and

using Don’t Care Notes Talk PPT
Terms http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

1 11. Quine-McCluskey 1s. T1:3.5.1 Chalk and

using Don’t Care Notes Talk PPT
Terms. http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 12. Module-2 2u. T2: k. Chalk and Assignment

Logic Design with v. Notes Talk PPT /
MSI Components and http:// Quiz
Programmable Logic elearning.vtu.ac.in
Devices /econtent/ https://
courses/video/ quizizz.co
ECE/ m/admin/
18EC34.html quiz/
5f1852e736
5329001bcf
2 13. Binary Adders and 2w. T2:5.1,5.1.1 Chalk and b02f?
Subtractors x. Notes Talk PPT source=qui
http:// z_share
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 14. Look ahead Carry 2y. T2:5.1.2 m. Chalk and

adder z. Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
 ECE/
18EC34.html

2 15. Binary Comparator 2aa. T2:5.3 n. Chalk and

bb. Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 16. Decoders 2cc. T2:5.4.2 o. Chalk and

dd. Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 17. Decoders 2 T2:5.4.2 p. Chalk and

Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 18. Encoders 2 T2:5.5 q. Chalk and

Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 19. Encoders 2 T2:5.5 Chalk and

Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 20. Multiplexers 2 T2:5.6 s. Chalk and

Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html
2 21. Multiplexers 2 T2:5.6.1 Chalk and
Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

2 22. Programmable Logic 2 T2:5.7 u. Chalk and

Devices (PLDs) Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 23. Module-3 Flip-Flops 3 T2:6.4 v. Chalk and Assignment

and its Applications Notes Talk PPT /Quiz
http:// https://
elearning.vtu.ac.in quizizz.co
/econtent/ m/admin/
courses/video/ quiz/
ECE/ 5f532b3a54
18EC34.html d529001b1
cd365?
source=qui
3 24. The Master-Slave Flip- 3 T2:6.4.1,6.4.2 w. Chalk and z_share
flops (Pulse-Triggered Notes Talk PPT
flip-flops): SR flip- http://
flops elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 25. JK flip flops, 3 T2:6.4.2 x. Chalk and

Characteristic Notes Talk PPT
equations http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 26. Registers 3 T1:6.7 y. Chalk and

Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 27. Registers 3 T1:6.7 z. Chalk and

Notes Talk PPT
 http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 28. Binary Ripple 3 T1:6.8 aa. Chalk and

Counters, Synchronous Notes Talk PPT
Binary Counters http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 29. Counters based on 3 T1:6.8 bb. Chalk and

Shift Registers Notes Talk PPT
http://
elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 30. Design of Synchronous 3 T1:6.8.1,6.8.3 cc. Chalk and

mod-n Counter using Notes Talk PPT
clocked T and JK, flip- http://
flops elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

3 31. Design of Synchronous 3 T1:6.8.1,6.8.3 dd. Chalk and

mod-n Counter using Notes Talk PPT
clocked D and SR flip- http://
flops. elearning.vtu.ac.in
/econtent/
courses/video/
ECE/
18EC34.html

4 32. Module 4:Structure of 4 T3-1.2.2,1.3.2,1.4ee. Chalk and Chart/

Verilog module, Notes Talk PPT Poster
Operators https://youtu.be/ Preparation
s3Dk4CEfNg4 / Quiz
https://youtu.be/ https://
6XAdgJ3-M-Q quizizz.co
m/admin/
4 33. Operators contd., 4 T3-1.4 ff. Chalk and quiz/
Notes Talk PPT, 632c10ba8
https://youtu.be/ 8efe9001da
6XAdgJ3-M-Q
4 34. Data Types 4 T3-1.5.2 gg. Chalk and 9648c?
Notes Talk PPT, source=qui
https://youtu.be/ charts z_share
MbWXdein3fc

4 35. Styles of Description 4 T3-1.6.1,1.6.2, hh. Chalk and Chart/

Notes Talk PPT Poster
https://youtu.be/ Preparation
VVSY6BjOlV8 /
Quiz
4 36. Styles of Description 4 T3-1.6.4 ii. Chalk and
with examples Notes Talk PPT
https://youtu.be/
VVSY6BjOlV8

4 37. Highlights of Data 4 T3-2.1,2.2 jj. Chalk and Assignment

flow description Notes Talk PPT /Quiz
https://youtu.be/ https://
VVSY6BjOlV8 quizizz.co
4 38. Structure of Data flow 4 https://youtu.be/ m/admin/
description QU2qA5PyARY quiz/
632c1441c
bda2f001d0
8b295/
verilog-
hdl?
selfCreated
=true

4 39. Examples of Data flow 4 kk. Chalk and Programmi

description Talk PPT ng
ll. Simulation Assignment
using Xilinx
4 40. Examples of Data flow 4 software
description

5 41. Module 5: Verilog 4 T3 - 3.1,3.2 Chalk and Assignment

Behavioral Notes Talk PPT /
description: Structure, https://youtu.be/ Quiz
Variable Assignment uLqIHN-0Kao https://
Statement https://youtu.be/ quizizz.co
DoqQdddSO3M m/admin/
quiz/
5 42. Sequential Statements, 4 T3-3.4 Chalk and 632c14b9c
Loop Statements Notes Talk PPT bda2f001d0
https://youtu.be/ 8b2be/
sFWExWwgavQ verilog-
https://youtu.be/ fundamenta
Uv3_U5eSUJ8 ls?
selfCreated
=true

5 43. Verilog Behavioral 4 T3-3.4 Chalk and Programmi

Description of Notes Talk PPT ng
Multiplexers https://youtu.be/ Simulation Assignment
uLqIHN-0Kao using Xilinx
 https://youtu.be/ software
DoqQdddSO3M

c 44. Verilog Structural 4 T3-4.1,4.2 Chalk and Assignment

description: Notes Talk PPT /Quiz
Highlights of https://youtu.be/ https://
Structural description, cCV_RfR0i_4 quizizz.co
Organization of m/admin/
structural description quiz/
632c166e9
5 45. Structural description 4 T3-4.1,4.2 Chalk and dc2ac001fe
of ripple carry adder Notes Talk PPT 25104?
https://youtu.be/ source=qui
cCV_RfR0i_4 z_share
5 46. Structural description
of ripple carry adder

5 47. Additional examples of T3-4.1,4.2 Chalk and Programmi

behavioral and Notes Talk PPT ng
structural description Simulation Assignment
using Xilinx
5 48. Additional examples of T3-4.1,4.2 software
behavioral and Notes
structural description

5 49. Additional examples of T3-4.1,4.2

behavioral and Notes
structural description

- 50. Revision of Previous https:// Chalk and

years QPs www.vturesource. Talk,
com/ Discussion

Assessment Scheme: CIE: SEE 50:50

Sl. Assessment Frequency Weightage (%)

No. Instrument
1. Internal Assessment 3 3x40=120 averaged and reduced to
20
2. Assignment/ Quiz/Charts 2 2*10=20 reduced to 10
3. Practical Component conduction and lab record - 15
4. Practical Component Test 1 5
Total CIE 50(30+20)
5. End Semester Examination (UE) 1 50
Total 100
Faculty Signature
Course Coordinator Signature HOD Signature

Signature of IQAC Signature of Principal/IQAC

Coordinator chairman