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A Wide-Band Digital Phase-Locked Looop

Conference Paper · May 2006

DOI: 10.1109/ITNG.2006.21 · Source: IEEE Xplore

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 A WIDE-BAND DIGITAL PHASE-LOCKED LOOP
By
Shilpa Ambarish, MSEE
Mahmoud Fawzy Wagdy, Professor
Department of Electrical Engineering,
California State University, Long Beach, CA, USA

Abstract - A high speed digital phase-locked loop fVCO = 1/ 2N td (2)

(DPLL) is designed using 0.18ȝm CMOS process,
using a 3.3V power supply. It operates in the
frequency range 55MHz – 1.43GHz. A (PFD) phase
frequency detector has a zero dead-zone by including
delay elements in the Reset path. The current source
used in the charge pump makes it insensitive to
supply variations and provides ripple-free control
voltage for the VCO (voltage controlled oscillator),
which provides low jitter and no overshoot in locking
transients. A high damping factor of 1.65 is used to
keep the PLL stable. Simulation results using
CADENCE tools are provided to verify the desired
performance. Fig. 1. Basic DPLL Schematic Diagram [1]

I. INTRODUCTION
High-speed and low-power digital phase locked
loop (DPLL) is of particular interest in today’s
portable wireless applications and clock/data (C/D)
recovery circuits. CMOS high frequency
performance has improved drastically as the MOS
transistors scale down in dimensions. Also, the
reduction of supply voltage provides a direct and
effective way to reduce the power consumption.
The objective of this work is to develop a high
Fig. 2. DPLL Implementation
frequency CMOS PLL, with frequency range
extending beyond 1GHz. The PLL consists of a
voltage controlled oscillator (VCO), a dead-zone free III. SIMULATION RESULTS
phase frequency detector (PFD), a charge pump, and Fig. 2. shows the simulation of VCO waveform for
loop filter [2-5]. The circuit was implemented using Vcrtl=3.3V.
0.18ȝm CMOS technology using Cadence Design
Tool at supply voltage of 3.3V.

II. DESIGN AND IMPLEMENTATION

The block schematic of the DPLL is shown in
Fig.1. For this work, the divide-by-N frequency
divider is omitted since the factor N = 1. The detailed
CMOS implementation is shown in Fig. 2.
The charge-pump current is related to the DPLL
lock time as:
IPUMP = C1. Vcntrl/TLOCK (1)
The VCO [6-7] is a ring oscillator implemented
by 9 current-starved inverters (9 stages). The
oscillation frequency is varied depending on the
inverter propagation delay (td) and the number of
inverters (N), i.e.
Fig. 2. VCO Waveform for Vcntrl=3.3V

Proceedings of the Third International Conference on Information Technology: New Generations (ITNG'06)
0-7695-2497-4/06 $20.00 © 2006 IEEE
 The entire PLL was simulated for frequencies completely eliminated. The ripple-free control
1.43GHz, 1.25GHz, 1GHz, 800Mz, 500MHz, voltage provides low jitter and no overshoot in
300MHz and 55MHz. Fig. 3 shows a comparison of transient locking. A high damping factor of 1.65 is
VCO frequencies when N=7 and N=9 stages. used to keep the PLL stable. The effect of changing
Vcntrl on the PLL as well as the effect of PLL
frequency on the lock time have been investigated.
Performance in the GHz range was verified as in
[8,9]. The DPLL performance covers a wide range of
frequencies from 55MHz to 1.43GHz.

Fref Vctrl Tlock Tlock

(Hz) (V) (calculation) (simulation)
1.43G 1.75 1.100ȝs 1.220ȝs
1.25G 1.57 970ns 1.000ȝs
1.00G 1.41 871ns 840ns
800M 1.29 790ns 750ns
500M 1.14 704ns 630ns
300M 1.01 623ns 548ns
55M 0.707 437ns 800ns

Fig.3. Transfer Function of the VCO for N=7 and 9 Table 1. Lock Time Versus Frequency

The 9-stage VCO was initially designed to give a V. REFERENCES

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Proceedings of the Third International Conference on Information Technology: New Generations (ITNG'06)
0-7695-2497-4/06 $20.00 © 2006 IEEE
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