Issue 5
Uploaded by
Zaid HassoIssue 5
Uploaded by
Zaid HassoMicro blaze the boot loader
Following the successful testing of your software application using the launch on hardware option,
we will want to ensure the software application can be stored in non-volatile memory such that the
application will run following a power on or reset.
This requires a boot loader which will load both the FPGA and the software although first it is
important to understand the way the Zynq boots and configures.
The Zynq requires configuration of both the processor system and the programmable logic, to
simplify the process of configuring both sides, the configuration sequence is slightly different to that
of existing Xilinx FPGA. This difference results from the two types of files needed to get the
maximum benefit from your Zynq system.
• FPGA Bit File – Defines the behavior of the programmable logic section of the design
• SW ELF file – The software program which will be executed by the processing system.
Within a Zynq device the processing system is the master and therefore configures the
Programmable Logic side, the only exception to this is if the JTAG interface is being used. This means
the processing system can be powered and operating while the programmable logic side is
unpowered if so desired to reduce the system power, of course if you want to use the PL side of the
Zynq you will need to power it.
The SW application and FPGA bit file are stored within the same configuration memory device
attached to the processing system. The processing system supports configuration via a number of
different non-volatile memories (Quad SPI Flash, NAND Flash, NOR Flash or SD Card) although the
MicroZed board allows for SD Card and Quad SPI. Therefore the Zynq follows a typical processor
boot sequence to configure both sides of the device, initially running from an internal non-
modifiable Boot PROM, this boot PROM contains drivers for the non-volatile memories supported.
This boot ROM is configured by a header contained within the none-volatile memory which marks
the start of the configuration image and is the first thing the boot ROM looks for. The header defines
a number of boot options the boot ROM can implement such as execute in place (not all memories),
FSBL offset, secure or none secure configuration this ensures the boot ROM operates in the mode
compatible with the how the configuration memory has been formatted.
For designs security users have the option of either secure and non-secure methods of configuration
are supported and defined by the boot ROM header, in secure configuration the programmable logic
section of the device must be powered up as the hard macro AES and SHA needed for decryption are
located within the PL side of the device.
The next stage of configuration is user provided and is called the first stage boot loader (FSBL). The
FSBL can then configure the DDR memory and other peripherals on the processor as defined in the
XPS hardware definition before loading the software application and configuring the programmable
logic. Overall the FSBL is responsible for
• Initializing the processing system with the information provided by Xilinx Platform Studio.
• Programming the programmable logic side of the Zynq if a bit file is provided
• Loading either a second stage boot loader (if an operating system is being used) or loading a
bare metal application into DDR
• Starting the execution of the SSBL or the bare metal application.
The PL side of the Zynq is programmed via the Processor Configuration Access Port (PCAP) which
allows both partial and full configuration of the programmable logic. This means the FPGA can be
programmed at any time once the processing system is up and running or read back and checked for
errors if you are using it in an environment where it may be subject to single event functional
interrupts (SEFI).
To create a bootable image for your Zynq solution you will need at least the following
1. Boot ROM Header – Controls settings for the Boot ROM e.g. execute in place, encryption,
Quad SPI configuration FSBL offset and image length.
2. First stage boot loader
3. Programmable logic bit file
4. Software application for the Programmable System side.
Like all other Xilinx FPGA’s the device uses a number of mode pins to determine which type of
memory the program is stored within along with other crucial system settings. These mode pins
share the multiuse IO pins on the PS side of the device, in all there are seven mode pins mapped to
MIO[8:2]. With the first four defining the boot mode, the fifth defines if the PLL is used or not and
the sixth and seventh define the voltages bank voltages on MIO bank 0 and bank 1 during power up.
The voltage standard defined on MIO bank 0 and 1 can be changed to the correct standard by the
first stage boot loader.
In the next blog we will look at how we create and implement this within SDK