Inputs Required For Synthesis
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apoorva🔷 🔑 Inputs Required for Synthesis (in Detail)
1 RTL Code (Behavioral Description)
1️⃣
File type: .v (Verilog) or .vhd (VHDL)
Purpose: Describes what the circuit should do at the register-transfer level.
Includes:
Modules/entities
Combinational logic
Sequential logic (flip-flops, FSMs)
Arithmetic operations (e.g., +, *)
Example:
verilog
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module adder(input [3:0] A, B, output [4:0] SUM);
assign SUM = A + B;
endmodule
2️⃣ Constraints File (Timing and Design Intent)
Format: SDC (Synopsys Design Constraints)
File type: .sdc
Purpose: Tells the tool what timing requirements the design must meet.
Includes:
Clock definitions: create_clock
Input/output delays: set_input_delay, set_output_delay
False and multicycle paths: set_false_path, set_multicycle_path
Load constraints: set_load
Example:
tcl
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create_clock -name clk -period 10 [get_ports clk]
set_input_delay 2 -clock clk [get_ports data_in]
3️⃣ Technology Library (.lib)
File type: .lib
Purpose: Describes the behavior and characteristics of each standard cell (e.g.,
AND, OR, DFF).
Includes:
Cell names
Pin names
Timing arcs (setup, hold, delay)
Power consumption
Area
Why needed: Synthesis maps RTL logic to these real, characterized cells.
Library example:
AND2_X1: 2-input AND with drive strength 1
DFF_X1: Positive edge-triggered D flip-flop
4️⃣ Technology File (.tf or Milkyway)
File type: .tf or Milkyway technology file
Purpose: Physical rules for place and route tools.
Includes:
Metal layers
Via rules
Width, spacing rules
Capacitance and resistance info (RC extraction)
Why needed: Supports accurate wire load models and physical-aware synthesis.
5️⃣ Design Compiler Setup Scripts
File type: .tcl
Purpose: Automation scripts that:
Read RTL
Set constraints
Read libraries
Run compile steps
Write output (netlist, reports)
Typical content:
tcl
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read_verilog rtl/design.v
read_liberty -lib db/slow.lib
read_sdc constraints/design.sdc
compile_ultra
write -format ddc -hierarchy -output synthesized.ddc
6️⃣ Power Intent (Optional for Low Power Designs)
Format: UPF (Unified Power Format)
File type: .upf
Purpose: Tells the tool how power domains are defined and how logic interacts
across them.
Includes:
Power domains
Isolation strategies
Retention logic
Power switches
Why needed: Enables synthesis of power-aware designs (common in mobile/IoT).
Example:
tcl
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create_power_domain PD1 -elements {u_top}
set_isolation -domain PD1 -name iso1 -clamp_value 0
7️⃣ Scan Configuration (For DFT Insertion)
Format: Tool-specific .cfg or .txt
Purpose: Specifies scan chain setup for Design-for-Test (DFT).
Includes:
Number of scan chains
Scan control signals
Scan enable logic
Why needed: Guides tools when inserting scan flip-flops.
8️⃣ Design Environment Files (Optional but Helpful)
Includes:
Wire load models: for estimating routing delays (if no floorplan yet).
Load capacitance values: set_load on outputs.
Fanout limits: set_max_fanout.
Area budget: set_max_area.
✅ Summary Table
Input Type File Format Required Purpose
RTL Code .v / .vhd ✅ Yes Functional design
Timing Constraints .sdc ✅ Yes Timing closure
Cell Library .lib ✅ Yes Map to real gates
Technology File .tf ✅ Yes Physical tech data
Setup Scripts .tcl ✅ Yes Flow automation
Power Intent (Low Power) .upf ❌ Optional Power-aware design
Scan Config .cfg ❌ Optional Test logic insertion
Wire Load Models In .lib or .tcl ❌ Optional Routing estimates