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Theory / B. Tech / CSE / SEM - VIII / Code – CS 801A / 2015-16
Paper Name: Advanced Computer Architecture
Full Marks: 75 Time Allotted: 3 hours
The figures in the margin indicate full marks. Candidates are required to give their answers in their own words as far as practicable.

GROUP – A
[MCQ Type Questions][Compulsory]
1. Choose the correct alternative of the following questions. Answer all questions. 10 x 1 = 10

i) The number of cycles required to complete n tasks in a k stage pipeline is

a) k+n-1 b) nk+1
c) k d) none of these.
ii) Array Processor are put under which of the categories
a) SISD b) SIMD
c) MISD d) MIMD
iii) Performance (P) and execution time (T) of CPU are related by
a) P α T b) P α 1/T
c) P = T d) P+T
iv) Which of these are examples of 2-dimensional topologies in static networks
a) Mesh b) 3 CCC networks
c) Linear array d) none of these
v) NORMA means
a) Message passing multicomputers b) Mainframes
c) Vector supercomputer d) none of these.
vi) Shuffle of 101 is
a) 010 b) 110
c) 011 d) none of these.
vii) The prefetching is a solution for
a) Data hazard b) Structural hazard
c) Control hazard d) none of these.
viii) SPARC stands for
a) Scalable Processor Architecture b) Superscalar Processor A RISC Computer
c) Scalable Processor A RISC Computer d) Scalable Pipeline Architecture
ix) Which of the following is true about interrupts?
a) They are generated when memory cycles are stolen
b) They are used in place of data channels
c) They can be generated by arithmetic operations
d) They can indicate completion of an I/O operation
x) Which of the following bus is used to transfer data from main memory to peripheral device?
a) DMA bus b) Output bus
c) Data bus d) all of these

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 GROUP – B
[Short Answer Type Questions]
Answer any four of the following
4 x 5 = 20
2. Compare superscalar, superpipeline and superscalar superpipeline architecture. 5
3. Assume a cache of 2K blocks (I Blocks size=4words=16 byte) and 32 bit address .Assume this
machine is byte addressable. Find the tag field, set field and index field in 2-way set associative. 5
4. What is virtual memory? Explain the usefulness of virtual memory. 2+3
5. a) What is vector register?
b) A cache memory needs an access time of 20 ns. Main memory access time is 100 ns. Hit ratio is
80%. What is the average access time? 2+3
6. Compare static and dynamic pipeline. What is data flow program graph? 3+2
7. Compare between RISC and CISC. What is vector stride? 3+2

Group – C
[Long Answer Type Questions]
Answer any three of the following
3 x 15 = 45
8. a) What do you mean by “Data flow computer”?

b) With simple diagram, explain Data flow architecture and compare it with control flow
architrcture.

c) Draw data flow graphs to represent the following computations

i) If (a>b) then (c = c+a)

else (c=c – a)

endif

ii) y = (a4 + b4) / (a4 – b4 ) 2+3+(5x2)

9. Consider the following reservation table (RT):

S 1 2 3 4 5 6
S1 x x X
S2 x x
S3 x X

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i. Draw the simple pipeline for the RT
ii. Find all forbidden latencies.
iii. Draw a state transition diagram.
iv. Find all simple and greedy cycles.
v. Find minimal average latency (MAL)
vi. Find upper and lower bound of MAL 2+2+4+3+2+2

10. a) A job consist of 5 tasks. The time taken by the 5 tasks are 25 ns, 40 ns, 35 ns, 40 ns and 45 ns
respectively. 80 jobs are to be proposed.

i) Find out the speedup obtained by using pipeline processing.

ii) What is the efficiency of the pipeline?

b) Compare between array processor and vector processor.

c) Compare between centralized and distributed shared memory architecture. Which is the best
architecture among them and why? 5+5+5

11. a) What are the different factors that can affect the performance of a pipeline system?

b) Implement the data routing logic to compute the following equation

S(K) = Ai for k = 0,1,2,…..,n

c) Construct a 8x8 omega network using 2x2 switch modules. 3+6+6

12. a) Differentiate between static network and dynamic network.

b) What do you mean by multiprocessor system? Compare between multiprocessor system and

multicomputer system.

c) Explain Superscalar Processor.

d) Discuss different data routing function (DRF). 4+(1+3)+3+4

13. Write short notes on any three of the following: 3 × 5 = 15

a) VLIW processor architecture

b) Pipeline optimization technique

c) Digital Bus

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 d) NUMA

e) Multiport network

f) Flynn’s classification

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