EXPT NO: 1 STUDY OF LOGIC GATES

AIM:
To study about the logic gates and to verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:

Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as
universal gates. Basic gates form these gates.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND

function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR
function. The output is high when any one of the inputs is high. The output is low
level when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input
is low. The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when

both inputs are low and any one of the input is low .The output is low level when
both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.

X- OR GATE:

The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE :

NOR GATE:

RESULT:
Thus, the logic gates were studied and the truth table was verified.
EXPT NO. :2 DESIGN OF CODE CONVERTERS

Design and implementation of the following Code convertors

• BCD to excess-3 code and vice versa
• Binary to gray code and vice-versa
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements
of information results in the use of different codes by different systems. A
conversion circuit must be inserted between the two systems if each uses
different codes for same information. Thus, code converter is a circuit that
makes the two systems compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table, combinational
circuit is designed. The Boolean functions are obtained from K-Map for each
output variable.
 A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. To convert from binary code to Excess-
3 code, the input lines must supply the bit combination of elements as specified
by code and the output lines generate the corresponding bit combination of code.
Each one of the four maps represents one of the four outputs of the circuit as a
function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic
diagram that implements this circuit. Now the OR gate whose output is C+D has
been used to implement partially each of three outputs.

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
K-Map for G3:

G3 = B3
K-Map for G2:

K-Map for G1:

K-Map for G0:

TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

E3 = B3 + B2(B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1
K-Map for B:

K-Map for C:
K-Map for D:

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

E3 E2 E1 E0 B3 B2 B1 B0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
 PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus, the design of code convertor is implemented and the truth table is verified
using logic gates.
EXPT NO.: 3 Design and implementation of 4 bit binary Adder/
Subtractor and BCD adder Using IC7483

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
the output carry from each full adder connected to the input carry of next full
adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated
by subscript numbers from right to left, with subscript 0 denoting the least
significant bits. The carries are connected in chain through the full adder. The
input carry to the adder is C0 and it ripples through the full adder to the output
carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input
carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit
with one common binary adder. The mode input M controls the operation. When
M=0, the circuit is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together
with an input carry from a previous stage. Since each input digit does not exceed
9, the output sum cannot be greater than 19, the 1 in the sum being an input carry.
The output of two decimal digits must be represented in BCD and should appear
in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The
2 decimal digits, together with the input carry, are first added in the top 4 bit
adder to produce the binary sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:4-BIT BINARY ADDER

LOGIC DIAGRAM:4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR
TRUTH TABLE:
Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

LOGIC DIAGRAM:
BCD ADDER
K MAP

Y = S4 (S3 + S2)

TRUTH TABLE:
BCD SUM CARRY
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.
RESULT:

Thus, the design and implementation of 4 bit Adder/Subtractor is

implemented and the truth table is verified using logic gates.
EXPT NO. :4 DESIGN AND IMPLEMENTATION OF
MAGNITUDE COMPARRATOR

AIM:
To design and implement
(i) 4 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operator that determine one number

is greater than, less than (or) equal to the other number. A magnitude comparator
is a combinational circuit that compares two numbers A and B and determine
their relative magnitude. The outcome of the comparator is specified by three
binary variables that indicate whether A>B, A=B (or) A<B.

A = A3 A2 A1 A0
B = B3 B2 B1 B0
 The equality of the two numbers and B is displayed in a combinational
circuit designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs
of significant digits starting from most significant position. A is 0 and that of B
is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B 1 + X A B 1 + X X A B 1 + X X X A B 1

3 3 2 2 3 2 1 1 3 2 1 0 0

A<B = A31B3 + X3A 1B2 + X3X2A11B1 + X3X2X1A01B0

2

The same circuit can be used to compare the relative magnitude of two
BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0+ B0)

🡳 🡳 🡳 🡳
x3 x2 x1 x0
LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

K MAP
TRUTH TABLE

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus, the design of Magnitude comparator is implemented and the truth
table is verified using logic gates.
 EXPT. NO: 5
MULTIPLXERS AND ENCODERS
AIM:
To
a. Study of 8x1 multiplexers using IC 74151.
b. Design of 16x1 using
8x1multiplexerIC
c. Priority Encoders
d. Design of combinational circuit(Full Adder) using 8x1 mux

APPARATUS REQUIRED:
Sl.No COMPONENT SPECIFICATION QTY.
1 8x1 Magnitude comparator IC 74151 2
2. Quad 2 input AND gate IC 7408 1
3. Quad 2 input OR gate IC 7432 1
4. Hex 1 input NOT gate IC 7404 1
5. IC trainer kit - 1
6. Patch cords - As required
.

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there
are 2n input line and n selection lines whose bit combination determine which input is
selected.

ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight inputs,
one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value are zero the outputs are zero.
The zero outputs can also be generated when D0 = 1.
A digital Muxtiplexer is a combinational circuit that select 1 input out of several
inputs and direct to a single output the particular input selection is controlled by a set of
select inputs . For selecting 1 out of n INPUTs a set of m select INPUTs is required where
 n=2m
A circuit diagram for a possible 8 line to 1 line data selector/MUX is shown here
the output y is equal to the ip I0, I1, I2, I3, I4, I5, I6, I7 depending on whether the select lines
S0,S1 & S2.

This device can be used simply as a data selector/MUX,or it can be used to

perform logic functions. The simplest application is to implement a truth table directly this
facility makes the mux a very general purpose logic device

TRUTH TABLE

Data Select
lines Data inputs
S2 S1 S0 D0 D1 D2 D3 D4 D5 D6 D7 OUTPUT
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 0 1 0 0 0 0 0 0 11 1
0 1 0 0 0 1 0 0 0 0 0 1
0 1 1 0 0 0 1 0 0 0 0 1
1 0 0 0 0 0 0 1 0 0 0 1
1 0 1 0 0 0 0 0 1 0 0 1
1 1 0 0 0 0 0 0 0 1 0 1
1 1 1 0 0 0 0 0 0 0 1 1

The output of 8x1 mux

Y= s0’s1’s2’D0+s2’s1’s0D1+s2’s1s0’D2+s2’s1s0D3+

s2s1’s0’D4+S2S1’S0D5+S2S1S0’D6+S2s1s3D7

LOGIC DIAGRAM
 output

BLOCK DIAGRAM FOR 8:1 MUX

DESIGN OF 16X1 MUX USING 8X1 MUX

16x1 mux has 4 select lines, 16 data input lines and one output line. It can be
constructed using two 8x1 mux and one 2x1 mux. Out of 4 select lines higher bit is given as
the select input for 2x1 mux and remaining bits are slect inputs for the 8x1 mux. The output
from the 8x1 muxs are given input to the 2x1 mux.

DESIGN OF 16X1 MUX USING 8X1 MUX

TRUTH TABLE
Data Select lines Data
inputs
D D D D D D D D D D D1 D1 D1 D1 D1 D1 OUT
S3 S2 S1 S0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 PUT
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11
1
0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1
0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 11
0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

TRUTH TABLE

INPUT OUTPUT

D0 D1 D2 D3 Y1 Y0 v

0 0 0 0 X X 0

1 0 0 0 0 0 1

x 1 0 0 0 1 1
 x x 1 0 1 0 1

x x x 1 1 1 1

PRIORITY ENCODERS

A priority encoder is used to determine the relative importance of interrupt requests in a

computer, so that the computer will know which request should be given top priority. The
circuit will have 4-input and one output. the function of circuit is to display the order of the
highest order input bit that is a logic 1.

DESIGN OF FULL ADDER USING MULTIPLEXER

Full adder is combinational circuit that forms the arithmetic sum of three

input bits. Input: A, B, C

Output: Sum, Carry

K-MAP
LOGIC DIAGRAM

FULL ADDER USING 8x1 MUX IC

TRUTH TABLE
SUM= & CARRY=
LOGIC DIAGRAM OF FULL ADDER USING 8x1 MUX IC

ROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.
 RESULT:

Thus, the study and design of 8×1 and 16×1 using 8×1 multiplexer , priority Encoders and full

adder using 8×1 multiplexer has been executed successfully.

EXPT NO. :6 DECODER AND DEMULTIPLEXER

AIM:

To
a)Study of 3x8 decoder using IC
b)Study of a 3 to 8 line decoder as demultiplexer
c)Realization of combinational circuit using decoder IC
d)Realization of 4 to 16 decoder using 3 to 8 decoder ICs
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 To 8 Decoder Ic IC 74138 2
2. 3 input NAND gate IC 7410 1
3. 2 input OR gate IC 7432 1
4. NOT gate IC 7404 1
5. IC trainer kit - 1
6. Patch cords - As required

THEORY:
• A decoder is a device which does the reverse of an encoder, undoing the encoding so
that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.

• In digital electronics, a decoder can take the form of a multiple-input, multiple-output

logic circuit that converts coded inputs into coded outputs, where the input and output
codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be
on for the decoder to function, otherwise its outputs assume a single "disabled" output
code word. Decoding is necessary in applications such as data multiplexing, 7 segment
display and memory address decoding.

IC 74138
• The IC 74138 is a commercially available MSI 3 to 8 decoder. The 74138 has 3 enable
inputs (G1, G2A_L, G2B_L), all of which must be asserted for the selected output it
has 3 active inputs and 8 active low outputs. Based on the select inputs (n) one output
among 2n outputs.

STUDY OF 74138
PIN OUT OF 74138

DECODER BLOCK DIAGRAM

IC 74138

3 TO 8 LINE DECODER AS DEMULTIPLEXER

4 TO 16 DECODER USING 3 TO 8 DECODER

To implement F= ∑(1,4,5,7) or F=
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus, the study of 3×8 decoder using IC, 3 to 8 line decoder using multiplexer, realization

Of combinational circuit using decoder IC and realization of 4 to 16 decoder using 3 to 8 decoder

ICs has been successfully executed.

EXPT. NO: 7 SHIFT REGISTERS

AIM:
To study and implement shift register in various modes of operation
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D flip flop IC 7474 2
2. OR gate IC 7432 1
3. IC Trainer kit - 1
4. Patch cords - As required

THEORY:
SHIFT REGISTER:
The Shift Register is another type of sequential logic circuit that is used for the storage
or transfer of data in the form of binary numbers and then "shifts" the data out once every clock
cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data
Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
The data bits may be fed in or out of the register serially, i.e. one after the other from
either the left or the right direction, or in parallel, i.e. all together. The number of individual
data latches required to make up a single Shift Register is determined by the number of bits to
be stored with the most common being 8-bits (one byte) wide, i.e. eight individual data latches.
The individual data latches that make up a single shift register are all driven by a common clock
(Clk) signal making them synchronous devices.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial inputs Serial outputs

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
 Shift register IC's are generally provided with a “clear” or “reset” connection so that
they can be "SET" or "RESET" as required. Generally, shift registers operate in one of four
different modes with the basic movement of data through a shift register being:

Serial-in to Parallel-out (SIPO):

The register is loaded with serial data, one bit at a time, with the stored data being
available in parallel form.

Serial-in to Serial-out (SISO):

The data is shifted serially "IN" and "OUT" of the register, one bit at a time in either
a left or right direction under clock control.

Parallel-in to Serial-out (PISO):

The parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.

Parallel-in to Parallel-out (PIPO):

The parallel data is loaded simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
Parallel Outputs
CLK Serial QA QB QC QD
inputs
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:

Parallel Inputs Serial

CLK
Q3 Q2 Q1 Q0 Output
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

Parallel Inputs Parallel Outputs

CLK D0 D1 D2 D3 Q0 Q1 Q2 Q3
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the study and implement shift register in various modes of operation such as

Serial in serial out, serial in parallel out, parallel in serial out and parallel in parallel out

has been executed successfully.

EXPT NO.:8 RIPPLE COUNTERS

a. 3-bit binary counter

b. Up/down counter
c. BCD counter
d. MOD 10 counter

AIM:
To design and verify 3 bit ripple counter, 3 bit up/down counter BCD Counter and
MOD - 10 Ripple Counter

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK flip flop IC 7476 2
2. NAND gate IC 7400 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. IC trainer kit - 1
6. Patch cords - As required

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time
all flip flops are not activated at same time which results in asynchronous operation.
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 3 BIT RIPPLE COUNTER:

TRUTH TABLE:
3 BIT RIPPLE COUNTER:

CLK QA QB QC
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 1 0 1
6 0 1 1
7 1 1 1

LOGIC DIAGRAM:
3-BIT UP/DOWN COUNTER:
TRUTH TABLE:
3-BIT UP/DOWN COUNTER:

CLOCK
S Q2 Q1 Q0 COUNT
PULSE
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 1 1 0 6
9 1 1 0 1 5
10 1 1 0 0 4
11 1 0 1 1 3
12 1 0 1 0 2
13 1 0 0 1 1
14 1 0 0 0 0

LOGIC DIAGRAM:
BCD COUNTER:
TRUTH TABLE:
BCD COUNTER:

CLOCK
Q3 Q2 Q1 Q0 COUNT
PULSE
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

 (ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the ripple counter of 3 bit binary counter, up/down counter, BCD counter

MOD 10 counter has been executed successfully.

EXPT NO.:9 DESIGN AND IMPLEMENTATION OF 3 BIT
SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at

its clock input. Counter represents the number of clock pulses arrived. An
up/down counter is one that is capable of progressing in increasing order or
decreasing order through a certain sequence. An up/down counter is also called
bidirectional counter. Usually up/down operation of the counter is controlled by
up/down signal. When this signal is high counter goes through up sequence and
when up/down signal is low counter follows reverse sequence.
K MAP

STATE DIAGRAM:
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:
TRUTH TABLE:
Input Present State Next State A B C
Up/ QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
Down
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the 3 bit synchronous up/down counter was designed and

implemented.
EXPT. NO: 10 STUDY OF MEMORY CHIPS

Memory Types
Two basic types:
1. ROM : Read-only memory
2. RAM : Read-Write memory
Four commonly used memories:
1. ROM
2. Flash (EEPROM)
3. Static RAM (SRAM)
4. Dynamic RAM (DRAM)
Generic pin configuration:

Memory Chips
The number of address pins is related to the number of memory locations.
1. Common sizes today are 1K to 256M locations.
2. Therefore, between 10 and 28 address pins are present.
The data pins are typically bi-directional in read-write memories.
1. The number of data pins is related to the size of the memory location.
2. For example, an 8-bit wide (byte-wide) memory device has 8 data pins.
3. Catalog listing of 1K X 8 indicate a byte addressable 8K memory.

Each memory device has at least one chip select ( CS ) or chip enable ( CE ) or select ( S )
pin that enables the memory device.

1. This enables read and/or write operations.

 2. If more than one is present, then all must be 0 in order to perform a read or write.
Each memory device has at least one control pin.
o For ROMs, an output enable ( OE ) or gate ( G ) is present.
▪ The OE pin enables and disables a set of tristate buffers.
o For RAMs, a read-write ( R/W ) or write enable ( WE ) and read
enable (OE ) are present.
▪ For dual control pin devices, it must be hold true that both are not 0 at
the same time.
ROM
Non-volatile memory: Maintains its state when powered down.
There are several forms:
1. ROM : After programmed, it cannot be changed.
2. PROM : Programmable Read-Only Memory.
▪ Field programmable but only once. Older style.
3. EPROM : Erasable Programmable Read-Only Memory.
▪ Reprogramming requires up to 20 minutes of high-intensity UV light
exposure.
4. Flash EEPROM : Electrically Erasable Programmable ROM.
▪ Also called EAROM (Electrically Alterable ROM) and NOVRAM
(NOn-Volatile RAM).
▪ Writing is much slower than a normal RAM.
▪ Used to store setup information, e.g. video card, on computer systems.
▪ Can be used to replace EPROM for BIOS memory.
EPROMs
• Intel 2716 EPROM (2K X 8):
EPROMs
• 2716 Timing diagram:

Sample of the data sheet for the 2716 A.C. Characteristics.

Symbol Parameter Limits Unit Test Condition
Min Typ. Max
tACC1 Addr. to Output Delay 250 450 ns PD/PGM= CS =VIL
tOH Addr. to Output Hold 0 ns PD/PGM= CS =VIL
tDF Chip Deselect to Output Float 0 100 ns PD/PGM=VIL
... ... ... ... ... ... ...
This EPROM requires a wait state for use with the 8086 ( 460ns constraint).

SRAMs
• TI TMS 4016 SRAM (2K X 8):
 • Virtually identical to the EPROM with respect to the pinout.
• However, access time is faster (250ns).
• SRAMs used for caches have access times as low as 10ns .

DRAMs
1. SRAMs are limited in size (up to about 128K X 8).
2. DRAMs are available in much larger sizes, e.g., 64M X 1.
3. DRAMs must be refreshed (rewritten) every 2 to 4 ms
▪ Since they store their value on an integrated capacitor that loses charge over
time.
▪ This refresh is performed by a special circuit in the DRAM which refreshes the
entire memory using 256 reads.
▪ Refresh also occurs on a normal read, write or during a special refresh cycle.
4. The large storage capacity of DRAMs make it impractical to add the required number
of address pins.
▪ Instead, the address pins are multiplexed .

DRAMs
 TI TMS4464 DRAM (64K X 4):

The TMS4464 can store a total of 256K bits of data.

It has 64K addressable locations which means it needs 16 address inputs, but it has only 8 .
1. The row address (A 0 through A 7 ) are placed on the address pins and strobed into a set
of internal latches.
2. The column addres (A 8 through A 15 ) is then strobed in using CAS.
3. TI TMS4464 DRAM (64K X 4) Timing Diagram:

o CAS also performs the function of the chip select input.

• Larger DRAMs are available which are organized as 1M X 1 , 4M X 1 , 16M X 1 , 64M

X1
• DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.
 o 30-pin SIMMs come in 1M X 8 , 1M X 9 (parity), 4M X 8 , 4M X 9 .
o 72-pin SIMMs come in 1 / 2 / 3 / 8 / 16M X 32 or 1M X 36 (parity).

• Pentiums have a 64-bit wide data bus.

o The 30-pin and 72-pin SIMMs are not used on these systems.
o Rather, 64-bit DIMMs ( Dual In-line Memory Modules) are the standard.
▪ These organize the memory 64-bits wide.
▪ The board has DRAMs mounted on both sides and is 168 pins.
o Sizes include 2M X 64 ( 16M ), 4M X 64 ( 32M ), 8M X 64 ( 64M ) and 16M
X 64 ( 128M ).
o The DIMM module is available in DRAM , EDO and SDRAM (and NVRAM )
with and without an EPROM.

RESULT:

Thus, the study of memory chip of using ROM, RAM has been verified.
EXPT NO.:11(a) IMPLEMENTATION OF EX-OR GATE
USING VERILOG CODE

AIM:
To implement EX-OR gate using Verilog HDL.

APPARATUSREQUIRED:

PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:
// XOR GATE
module gate_xor(y,a,b);
input wire a;
input wire b;
output y;
assign y= a^b;

endmodule

// XOR TESTBENCH
module tb_xor_gate_v;

// Inputs
reg a;
reg b;

// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
gate_xor uut (
.y(y),
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#50;
a=1;
b=0;
#100;
a=0;
b=1;
#100;
a=1;
b=1;
end

endmodule

OUTPUT
X-0R

RESULT:

Thus, the implementation of EX-OR gate usinng Verilog HDL is verified.

EXPT NO.:11(b) IMPLEMENTATION OF FULL ADDER
USING VERILOG CODE

AIM:
To implement full adder circuit using Verilog HDL.

APPARATUSREQUIRED:

PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:
// FULL ADDER
module ff(a,b,c,s,cout);
input a;
input b;
input c;
output s;
output cout;
assign s = (a ^ b) ^ c;
assign cout = (a & b)|( b & c)|(c & a);
endmodule

// FULL ADDER RE
module full_adder_tb_v;

// Inputs
reg a;
reg b;
reg c;
 // Outputs
wire s;
wire cout;

// Instantiate the Unit Under Test (UUT)

ff uut (
.a(a),
.b(b),
.c(c),
.s(s),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=1;
b=1;
c=0;

#10;
a=1;
b=1;
c=1;
end

endmodule
 FULL ADDER

RESULT:

Thus, the implementation of full adder using Verilog HDL is verified.

EXPT NO.:11(c) IMPLEMENTATION OF MULTIPLEXER
USING VERILOG CODE

AIM:
To implement multiplexer circuit using Verilog HDL.

APPARATUSREQUIRED:
PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:

// 2x1 multiplexer
module mux_new(input wire sel,
input wire d_in0,
input wire d_in1,
output d_out);

assign d_out= sel ? d_in1:d_in0; // if sel=0 , d_out=d_in0

// if sel= 1 , d_out=d_in1

endmodule

// multiplexer testbecnh

module testbench_mux_v;

// Inputs
reg sel;
reg d_in0;
reg d_in1;
 // Outputs
wire d_out;
// Instantiate the Unit Under Test (UUT)
mux_new uut (
.sel(sel),
.d_in0(d_in0),
.d_in1(d_in1),
.d_out(d_out)
);

initial begin
// Initialize Inputs
sel = 0;
d_in0 = 0;
d_in1 = 0;

// Wait 100 ns for global reset to finish

#100;
sel=0;
d_in0=1;
# 100
sel =1;
d_in1=1;
// Add stimulus here

end

endmodule
2X1 MUX

RESULT:

Thus, the implementation of multiplexer counter is verified using Verilog HDL.

EXPT NO.: 11(d) IMPLEMENTATION OF UP/DOWN COUNTER
USING VERILOG CODE

AIM:
To implement up/down counter using Verilog HDL.

APPARATUSREQUIRED:

PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:

// Up Down counter Behvioural model

module up_down_contr(input Clk,

input CLR,
input UP_DOWN,
output [3:0] Q);
// Clk- positive edge clk
// CLR clear the counter to 0000
// UP_DOWN=1 Up counter
// UP_DOWN=0 Down counter
// Q -- > counter output

reg [3:0] tmp;

always @(posedge Clk or posedge CLR)

begin
if (CLR)
tmp = 4'b0000;
 else
if (UP_DOWN)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule

// Test bench for Updown counter

module up_down_tb_v;

// Inputs
reg Clk;
reg CLR;
reg UP_DOWN;

// Outputs
wire [3:0] Q;

// Instantiate the Unit Under Test (UUT)

up_down_contr uut (
.Clk(Clk),
.CLR(CLR),
.UP_DOWN(UP_DOWN),
.Q(Q)
);

initial begin
// Initialize Inputs
Clk = 0;
CLR = 0;
UP_DOWN = 0;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
// clear the counter
CLR=1;

#20;
CLR=0;
UP_DOWN=1; // Up counter

#300
UP_DOWN=0;// down counter
#300
CLR=1;
#1000
 $finish;
end

always #10 Clk= ~Clk;

endmodule

RESULT:

Thus, the implementation of up/down counter using Verilog HDL is successfully

executed.
EXPT NO.:11(e) IMPLEMENTATION OF BINARY UP COUNTER
USING VERILOG CODE

AIM:
To implement binary up counter using Verilog HDL.

APPARATUSREQUIRED:

PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:

// Verilog code for UP counter

module up_cntr(input Clk,
input CLR,
output [3:0] Q);
// Clk- positive edge clk
// CLR clear the counter to 0000
// UP_DOWN=1 Up counter
// UP_DOWN=0 Down counter
// Q -- > counter output

reg [3:0] tmp;

always @(posedge Clk or posedge CLR)

begin
if (CLR)
tmp = 4'b0000;
else
 tmp = tmp + 1'b1;
end

assign Q = tmp;

endmodule

// Testbench for UP COUNTER

module up_cntr_tb_v;

// Inputs
reg Clk;
reg CLR;

// Outputs
wire [3:0] Q;

// Instantiate the Unit Under Test (UUT)

up_cntr uut (
.Clk(Clk),
.CLR(CLR),
.Q(Q)
);

initial begin
// Initialize Inputs
Clk = 0;
CLR = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

CLR=1;

#20;
CLR=0;

#310;
CLR=1;
end
always #10 Clk= ~Clk;
endmodule
RESULT:

Thus, the implementation of binary counter using Verilog HDL code has been

executed successfully.
EXPT NO.:11(f) IMPLEMENTATION OF SHIFT REGISTER
USING VERILOG CODE

AIM:
To implement shift register using Verilog HDL.

APPARATUSREQUIRED:

PC with Windows XP
XILINX,
ModelSim
software. FPGA
kit
RS 232 cable.

PROCEDURE:

➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above verilog code (using
ModelSim or
Xilinx) and verify the output waveform as obtained.
➢ Implement the above code in Spartan III using FPGA kit.

PROGRAM:
// shift register
module shft_reg( input [3:0] par_inp,// parelel input
input s1,s0, // select lines
input MSB_in,LSB_in, // serial input
input clk,clr, // clock, clear
output reg [3:0] par_out// parallel output
);
always @(posedge clk or posedge clr)
begin
if (clr) par_out= 4'b0000;
else
begin
case ({s1,s0})
2'b00: par_out= par_out; // No change
2'b01: par_out= {MSB_in,par_out[3:1]}; // shift right
2'b10: par_out= {par_out[2:0],LSB_in}; // shift left
2'b11: par_out= par_inp; // parallel load of input

endcase
 end
end

endmodule

// shift register testbench

module shift_reg_tb_v;

// Inputs
reg [3:0] par_inp;
reg s1;
reg s0;
reg MSB_in;
reg LSB_in;
reg clk;
reg clr;

// Outputs
wire [3:0] par_out;

// Instantiate the Unit Under Test (UUT)

shft_reg uut (
.par_inp(par_inp),
.s1(s1),
.s0(s0),
.MSB_in(MSB_in),
.LSB_in(LSB_in),
.clk(clk),
.clr(clr),
.par_out(par_out)
);

initial begin
// Initialize Inputs
par_inp = 4'b0000;
s1 = 0;
s0 = 0;
MSB_in = 0;
LSB_in = 0;
clk = 0;
clr = 0;

// Wait 100 ns for global reset to finish

#100;
// loading of parallel input
clr=1;
#20;
clr=0;
s1=0;
 s0=0;
#30; // shift right
MSB_in=1;
s1=0;
s0=1;
#80; // shift left
LSB_in=0;
s1=1;
s0=0;
#120;
s1=1;
s0=1;
par_inp = 4'b1101;

// Add stimulus here

end
always #10 clk= ~clk;
endmodule

SHIFT REGISTER

RESULT:

Thus, the implementation of shift register using Verilog HDL code has been executed

successfully.