Name of the Course: Digital Logic Design

 Course Instructor:
Name: Dr Priya Charles
Office Number: 9923240728
Phone:
Email:[email protected]
Office hours: 9.30 am to 5 pm
Location: First Floor

 Teaching Assistant:NIL
Name:
Contact:
Office Hours: Time slots
Location

 Level (who can take this course?): first year semiconductor students
 Credit: 3-0-3-4.5
 Evaluation:
 Breakup of evaluation: % wise
 Maximum Number of Students: 61

Prerequisites: Number System:- Binary, BCD, Octal, Decimal, Hexadecimal their conversion and
arithmetic, De-Morgan’s theorem,Basic Gates,Flip Flops
Course Objectives: To make the students understand
1. The fundamental principles of two-valued logic and various devices used to implement logical
operations on variables.
2. Boolean algebra, Karnaugh maps and its application to the design and characterization of digital
circuits.
3. To analyze logic processes and implement logical operations using combinational logic circuits
4. The principles of logic design and use of simple memory devices, flip-flops, and sequential cir-
cuits
5. Concepts of sequential circuits and to analyze sequential systems in terms of state machines.

Course Syllabus:
Module – I Digital Logic Families (06 Hrs)
Classification and Characteristics of digital Logic Families: Speed, power dissipation, figure
of merit, fan in, fan out, current, voltage, noise immunity, operating temperatures and power
supply requirements. TTL logic. Operation of TTL NAND gate, active pull up, wired AND,
open collector output, unconnected inputs. Tri-State logic. CMOS logic: CMOS inverter,
NAND, NOR gates, unconnected inputs, wired logic, open drain output. Interfacing CMOS
and TTL, Data sheet specifications

Module– II Combinational Design (08 Hrs)

Definition of combinational logic, canonical forms, Standard representations for logic
functions, k-map representation of logic functions (SOP and POS forms), minimization of
logical functions for min-terms and max-terms (upto 4 variables), don’t care conditions,
 Design Examples: Code converters, Adders and their use as subtractor, Digital Comparator,
Parity generators/checkers,
Multiplexers and De-multiplexers their use in combinational logic designs, multiplexer
trees, and their use in combinational logic designs, Decoders, Demultiplexer trees.

Module – III Sequential Design (08 Hrs)

Flip flops, Excitation Table for flip flop, Conversion of flip flops, Application of Flip flops -
Registers, Shift registers, Counters (ring counters, twisted ring counters), ripple counters,
Mod-n counters, up/down counters, synchronous counters, lock out, Clock Skew, Clock jitter.
Effect on synchronous designs, Sequence Generators

Module – IV State Machines - I (06 Hrs)

Basic design steps- State diagram, State table, State reduction, State assignment, Mealy and
Moore machines representation

Module – V State Machine - II (06 Hrs)

finite state machine implementation, Sequence detector. Introduction to Algorithmic state
machines - Construction of ASM chart and realization for sequential circuits

Lesson Plan:

Sr. No Content (Daily Plan) Date (Proposed)

1 Definition of combinational logic, canonical forms 9/1/25
2 Standard representations for logic functions, k-map 15/1/25
representation of logic functions (SOP and POS
forms),
3 minimization of logical functions for min-terms and 16/1/25
max-terms (upto 4 variables),
4 don’t care conditions,Design Examples: Code 21/1/25
converters,
5 Design Examples: Adders and their use as 22/1/25
subtractor
6 Digital Comparator, Parity generators/checkers, 23/1/25
7 Multiplexers and De-multiplexers their use in 28/1/25
combinational logic designs
8 multiplexer trees, and their use in combinational 29/1/25
logic designs, Decoders, Demultiplexer trees.
9 Flip flops, Excitation Table for flip flop 30/1/25
10 Conversion of flip flops, Application of Flip flops - 4/2/25
11 Registers, Shift registers, 5/2/25
12 Counters (ring counters, twisted ring counters), 6/2/25
ripple counters,
13 Mod-n counters, up/down counters 11/2/25
14 synchronous counters, lock out, 12/2/25
15 Clock Skew, Clock jitter. 13/2/25
16 Effect on synchronous designs, Sequence 18/2/25
Generators
17 Basic design steps- State diagram 19/2/25
18 , State table, State reduction 20/2/25
19 State assignment 25/2/25
20 Examples 26/2/25
21 Mealy and Moore machines representation 27/2/25
22 Examples on Mealy and Moore 4/3/25
23 finite state machine 5/3/25
24 finite state machine implementation, 6/3/25
25 Sequence detector. 11/3/25
26 Introduction to Algorithmic state machines 12/3/25
27 Construction of ASM chart & examples 13/3/25
28 realization for sequential circuits 18/3/25
29 Classification and Characteristics of digital Logic 19/3/25
Families: Speed, power dissipation
30 figure of merit, fan in, fan out, current, voltage 20/3/25
31 noise immunity, operating temperatures and power 25/3/25
supply requirements.
32 TTL logic. Operation of TTL NAND gate, active 26/5/254
pull up,
33 wired AND, open collector output, unconnected 27/5/25
inputs.
34 Tri-State logic. CMOS logic: CMOS inverter, 1/4/25
NAND, NOR gates, unconnected inputs
35 wired logic, open drain output. 2/4/25
36 Interfacing CMOS and TTL, Data sheet specifications 3/4/25

Laboratory

Sr. No Content Date

1 Study of IC-74LS153 as a Multiplexer: (Refer Data-Sheet).
Design and Implement 8:1 MUX using IC-74LS153 & Verify its Truth
Table.

2 Study of IC-74LS138 as a Demultiplexer / Decoder: (Refer Data-

Sheet)
Design and Implement full adder and subtractor function
using IC-74LS138.

3 Study of IC-74LS83 as a Binary adder: (Refer Data-Sheet)

Design and Implement 4-bit Binary sub tractor using IC-
 74LS83.

4 Study of IC-74LS85 as a magnitude comparator: (Refer Data-

Sheet)
Design and Implement 4-bit Comparator.
Design and Implement 8-bit Comparator.

5 Study of Counters:
Design and Implement 4-bit counter using JK- Flip flop.

6 Study of Counter ICs (74LS90)

Design and Implement MOD-N and MOD-NN using IC-
74LS90 and draw Timing diagram.

7 Study of synchronous counter:

Design & Implement 4-bit Up/down Counter and MOD-N
Up/down Counter
using IC74HC191

8 Study of Shift Register:

Design and Implement 4-bit Ring Counter/ Twisted ring
Counter using shift registers
9 Design of sequence Detector using Flip flops

 Course Outcome:
CO1 : Identify and prevent various hazards and timing problems in a digital design.
CO2: Analyze, design and implement combinational logic circuits
CO3: Analyze, design and implement sequential circuits.
CO4: : Differentiate between Mealy and Moore machines.
CO5: Design Finite State Machines

 Text Book:
1. R.P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Publication, 3 rd Edition.
2. Thomas Floyd, “Digital Electronics”, 11th Edition.
3. M. Morris Mano, “Digital Logic and Computer Design”, Prentice Hall of India, 4 th Edition. 4. Taub
and Schilling, “Digital Principles and Applications,” TMH.
  Reference Books:
1. Anand Kumar, “Fundamentals of Digital Circuits”, Prentice Hall of India, 1 st Edition.
2. J. F. Wakerly, “Digital Design- Principles and Practices,”, Pearson, 3 rd Edition.
3. M. M. Mano, “Digital Design,” Prentice Hall India

 Study Materials: