PowerArtist User's Guide

ANSYS, Inc. Release 2025R1.2

Southpointe February 2025
2600 ANSYS Drive
Canonsburg, PA 15317 ANSYS, Inc. and
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Table of Contents
1. Introduction to PowerArtist .................................................................................................................... 1
1.1. PowerArtist and Your Design Flow ..................................................................................................... 1
1.2. Tutorials to Get You Started ............................................................................................................... 2
1.3. Sample Flow Script Templates ........................................................................................................... 3
2. Installing and Setting Up PowerArtist .................................................................................................... 5
2.1. Introduction ..................................................................................................................................... 5
2.2. Supported Operating Systems .......................................................................................................... 5
2.3. Platform Compliance Checker ........................................................................................................... 5
2.4. Installing the Software ...................................................................................................................... 6
2.5. Distribution Tree ............................................................................................................................... 6
2.6. Setting the UNIX Environment Variable for PowerArtist ...................................................................... 7
2.7. PowerArtist Licensing ....................................................................................................................... 7
2.7.1. Support for Multiple License Servers ......................................................................................... 8
2.7.2. Monitoring License Server Availability ...................................................................................... 8
2.7.3. Product vs. Feature Licenses ..................................................................................................... 8
2.7.4. Waiting for a Feature License .................................................................................................... 9
2.7.5. Resolving Feature Checkout Problems ...................................................................................... 9
2.7.6. Microsoft Defender vs. ACL ....................................................................................................... 9
3. Using the PowerArtist Shell .................................................................................................................. 11
3.1. Introduction ................................................................................................................................... 11
3.2. Understanding the pa_shell Command Options .............................................................................. 11
3.3. pa_shell Features ............................................................................................................................ 13
3.4. Customizing Your PowerArtist Environment Using Initialization (INI) Files ......................................... 15
3.5. Understanding Log Files and Key Files ............................................................................................. 16
3.6. Invoking the GUI ............................................................................................................................. 16
3.6.1. Understanding the Link between PowerArtist Commands and PowerCanvas ........................... 17
3.7. 'Man' command Support ................................................................................................................. 17
4. PowerArtist Tutorial Part I: Power Analysis ........................................................................................... 19
4.1. Introduction ................................................................................................................................... 19
4.2. Understanding the Tutorial Files ...................................................................................................... 19
4.2.1. Contents of the 'tutorial' Directory .......................................................................................... 20
4.2.2. Contents of the 'analysis' Directory ......................................................................................... 21
4.3. Understanding the Power Analysis Flow .......................................................................................... 21
4.3.1. Inputs .................................................................................................................................... 22
4.4. Understanding the Analysis Tutorial Steps ....................................................................................... 22
4.5. Understanding Power Analysis Setup .............................................................................................. 24
4.5.1. Running the Setup ................................................................................................................. 24
4.5.2. Reading the Library Files ........................................................................................................ 24
4.6. Design Elaboration ......................................................................................................................... 25
4.7. Common Setup for Clock Definitions ............................................................................................... 26
4.7.1. The ReadSDC Command ......................................................................................................... 26
4.7.2. Setup for Clock Tree and Clock Gate Inferencing ...................................................................... 27
4.7.3. Setup for Capacitance Estimation ........................................................................................... 28
4.7.4. Mixed-VT Setup ...................................................................................................................... 29
4.8. Running Static Efficiency Checks ..................................................................................................... 29
4.9. Running Activity Analysis for Clock and Data ................................................................................... 31
4.9.1. Vector Analysis ....................................................................................................................... 31
4.9.2. Generating and Viewing Waveforms ....................................................................................... 33
4.9.3. Flop Clock Activity Analysis .................................................................................................... 35

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4.9.4. Flop Clock Activity Analysis Reports ........................................................................................ 36

4.10. Running Weighted Toggle Coverage (WTC) .................................................................................... 37
4.11. Running Average Power Analysis ................................................................................................... 40
4.12. Generating Additional Power Reports ............................................................................................ 43
4.13. Running Fast Power Profiling ......................................................................................................... 43
4.14. Running Time-Based Power Analysis .............................................................................................. 44
4.14.1. Running Fast Time-based Power Analysis .............................................................................. 46
4.15. Viewing Power Analysis Results in the PowerArtist Graphical Interface ........................................... 47
4.16. Understanding Power Analysis through Text Reports ..................................................................... 50
4.16.1. Average Power Analysis Report ............................................................................................. 50
4.16.1.1. Total Power Consumption ............................................................................................ 50
4.16.1.2. Total Power per Supply ................................................................................................ 51
4.16.1.3. Internal Power Consumption ....................................................................................... 51
4.16.1.4. Instance Average Power Consumption ......................................................................... 52
4.16.1.5. Pad Power Consumption .............................................................................................. 54
4.16.1.6. Mixed-VT Cells Distribution .......................................................................................... 55
4.16.1.7. Clock Power Consumption ........................................................................................... 55
4.16.1.8. Controlling the Clock Tracing Order .............................................................................. 57
4.16.1.9. Additional Information on Clock Gating ....................................................................... 57
4.16.1.10. Inferred Buffer Tree Power .......................................................................................... 58
4.16.1.11. Power Summary for Enable Level Shifter Cells ............................................................. 59
4.16.1.12. Area .......................................................................................................................... 60
4.16.1.13. Net Frequencies ......................................................................................................... 61
4.16.1.14. Power Consumption by Model/Gate Type ................................................................... 61
4.16.2. Cell Selection Report ............................................................................................................ 62
4.16.3. Modal Analysis Reports ........................................................................................................ 62
4.16.4. Generating Power Reports from the Power Database ............................................................ 63
4.16.4.1.The 'reportPower' Command ........................................................................................ 63
4.16.4.2. The 'reportSummary' Command .................................................................................. 64
4.16.4.3. The 'report_cg_efficiency' Command ........................................................................... 65
4.16.5. Time-based Power Analysis Report ....................................................................................... 66
4.16.5.1. Header ........................................................................................................................ 66
4.16.5.2. Power Contribution ..................................................................................................... 67
4.16.5.3. Detailed Instance Power .............................................................................................. 68
4.16.5.4. Mixed-VT Cells Distribution .......................................................................................... 68
4.16.5.5. Clock Power Consumption ........................................................................................... 68
4.16.5.6. Inferred Buffer Tree Power ............................................................................................ 68
4.16.5.7. Power consumption by model/gate type ...................................................................... 68
4.17. Using the Power Analysis Results ................................................................................................... 69
4.17.1. Using the Average Power Analysis Results ............................................................................. 69
4.17.2. Using the Time-based Power Analysis Results ........................................................................ 69
5. PowerArtist Tutorial Part II: Power Reduction ...................................................................................... 71
5.1. Introduction ................................................................................................................................... 71
5.2. About PowerBots ............................................................................................................................ 71
5.3. Copying the 'reduction' Tutorial Files ............................................................................................... 72
5.4. Understanding the Power Reduction Flow ....................................................................................... 72
5.5. Understanding the Power Reduction Tutorial Steps ......................................................................... 73
5.6. Understanding Power Reduction Setup ........................................................................................... 74
5.7. Design Elaboration ......................................................................................................................... 74
5.8. Common Setup for Clock Definitions ............................................................................................... 74
5.9. Specifying the Memory ................................................................................................................... 75

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5.10. Multi-port RAM Support ................................................................................................................ 77

5.11. Running Power Reduction ............................................................................................................. 79
5.12. Generating Additional Power Reports ............................................................................................ 82
5.13. Viewing Power Reduction Results in the PowerArtist Graphical Interface ........................................ 82
5.13.1. Reviewing Simple Power Reductions .................................................................................... 83
5.13.2. Manipulating the Data .......................................................................................................... 84
5.13.3. Using the Context-Sensitive Help Pages ................................................................................ 86
5.13.4. Filtering Reduction Results ................................................................................................... 87
5.13.5. Reviewing Linter Reduction Results ...................................................................................... 89
5.14. Understanding Power Reduction through Text Report ................................................................... 90
5.14.1. Power Reduction Report ....................................................................................................... 91
5.14.1.1. Total Initial Power ........................................................................................................ 91
5.14.1.2. Total Power Savings ..................................................................................................... 91
5.14.1.3. Total Final Power .......................................................................................................... 91
5.14.1.4. Power Reduction by Technique .................................................................................... 92
5.14.2. Power Reduction Clock Gating Report .................................................................................. 93
5.14.3. Observability Don't Care (ODC) Report .................................................................................. 93
5.14.4. Blocks Activity Ranking Report ............................................................................................. 93
5.14.5. Reviewing Power Reports from the Power Database .............................................................. 93
6. PowerArtist Tutorial Part III: Advanced Features .................................................................................. 95
6.1. Introduction ................................................................................................................................... 95
6.2. Vectorless Power Analysis and Reduction ........................................................................................ 95
6.2.1. Copying the 'vectorless' Tutorial Files ...................................................................................... 95
6.2.2. Power Analysis and Reduction in Vectorless Flow .................................................................... 96
6.2.3. Understanding the Tutorial Steps ............................................................................................ 97
6.2.4. Understanding Power Analysis Setup ...................................................................................... 98
6.2.5. Generating the Vectorless Activity File (VAF) ........................................................................... 98
6.2.6. Common Setup for Clock Definitions ...................................................................................... 99
6.2.7. Running Block-level Average Power Analysis ........................................................................... 99
6.2.8. Running Block-level Power Reduction ..................................................................................... 99
6.2.9. Generating Additional Power Reports ................................................................................... 100
6.2.10. Viewing Results in the PowerArtist Graphical Interface ........................................................ 100
6.2.11. Understanding the Text Reports ......................................................................................... 101
6.3. Gate-level Power Analysis .............................................................................................................. 101
6.3.1. Copying the 'gate_power' Tutorial Files ................................................................................. 102
6.3.2. Power Analysis with Gate Stimulus ........................................................................................ 102
6.3.2.1. Understanding the Gate-level Power Analysis with Gate Stimulus Flow ......................... 103
6.3.2.2. Understanding the Tutorial Steps ................................................................................. 103
6.3.2.3. Understanding Power Analysis Setup ........................................................................... 104
6.3.2.4. Running Activity Analysis ............................................................................................. 105
6.3.2.5. Running Average Power Analysis ................................................................................. 105
6.3.2.6. Running Time-based Power Analysis ............................................................................ 106
6.3.2.7. Generating Additional Power Reports .......................................................................... 106
6.3.3. Power Analysis with RTL Stimulus ......................................................................................... 106
6.3.3.1. About Name Mapping ................................................................................................. 106
6.3.3.2. Understanding the Gate-level Power Analysis with RTL Stimulus Flow ........................... 106
6.3.3.3. Understanding the Tutorial Steps ................................................................................. 107
6.3.3.4. Understanding Power Analysis Setup ........................................................................... 108
6.3.3.5. Generating and Reading the Name Mapping File .......................................................... 108
6.3.3.6. Running Average Power Analysis ................................................................................. 109
6.3.3.7. Generating Additional Power Reports .......................................................................... 109

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6.3.4. Viewing Results in the PowerArtist Graphical Interface .......................................................... 109

6.3.5. Understanding the Text Reports ........................................................................................... 109
6.4. UPF/CPF-based Power Analysis ..................................................................................................... 110
6.4.1. Copying the 'upf_cpf' Tutorial Files ....................................................................................... 110
6.4.2. UPF-based Power Analysis .................................................................................................... 111
6.4.2.1. The 'top.upf' File .......................................................................................................... 112
6.4.2.2. Understanding the UPF Flow ....................................................................................... 112
6.4.2.3. Understanding the Tutorial Steps ................................................................................. 112
6.4.2.4. Understanding Power Analysis Setup ........................................................................... 113
6.4.2.5. Define Root Supply Drivers .......................................................................................... 113
6.4.2.6. Running Average Power Analysis ................................................................................. 114
6.4.2.7. Generating Additional Power Reports .......................................................................... 114
6.4.3. CPF-based Power Analysis .................................................................................................... 115
6.4.3.1. The 'top.cpf' File ........................................................................................................... 115
6.4.3.2. Understanding the CPF Flow ........................................................................................ 115
6.4.3.3. Understanding the Tutorial Steps ................................................................................. 116
6.4.3.4. Understanding Power Analysis Setup ........................................................................... 117
6.4.3.5. Running Average Power Analysis ................................................................................. 117
6.4.3.6. Generating Additional Power Reports .......................................................................... 118
6.4.4. Viewing Results in the PowerArtist Graphical Interface .......................................................... 118
6.4.5. Understanding the Text Reports ........................................................................................... 118
6.5. Physically-Aware RTL Power Accuracy with PACE Models ................................................................ 119
6.5.1. About PACE .......................................................................................................................... 119
6.5.2. Copying the 'pace' Tutorial Files ............................................................................................ 119
6.5.3. Understanding the PACE Flow .............................................................................................. 120
6.5.4. Understanding the Tutorial Steps .......................................................................................... 121
6.5.5. Generating the PACE Model .................................................................................................. 122
6.5.5.1. Understanding PACE Model Generation Setup .............................................................. 122
6.5.5.2. Writing the PACE Model ............................................................................................... 123
6.5.6. Using the PACE Model .......................................................................................................... 124
6.5.6.1. Understanding PACE Model Consumption Setup .......................................................... 124
6.5.6.2. Running Average Power Analysis using PACE ................................................................ 124
6.5.6.3. Generating Additional Power Reports .......................................................................... 125
6.5.7. Viewing Results in the PowerArtist Graphical Interface .......................................................... 125
6.5.8. Understanding the Text Reports ........................................................................................... 125
6.6. Generating an RTL Power Model .................................................................................................... 125
6.6.1. About RPM ........................................................................................................................... 126
6.6.2. Copying the 'rpm' Tutorial Files ............................................................................................. 126
6.6.3. Understanding the RPM Flow ............................................................................................... 126
6.6.4. Understanding the Tutorial Steps .......................................................................................... 127
6.6.5. Understanding RPM Generation Setup .................................................................................. 128
6.6.6. Generating the RPM ............................................................................................................. 128
6.6.7. Viewing the RPM Information ............................................................................................... 129
6.6.8. Generating and Viewing Power Waveforms for Selected RPM Frames ..................................... 130
7. Getting Your Design into PowerArtist ................................................................................................. 133
7.1. Introduction ................................................................................................................................. 133
7.2. Case Sensitivity ............................................................................................................................. 133
7.3. Command-Line Flows ................................................................................................................... 134
7.3.1. Verilog ................................................................................................................................. 134
7.3.2. VHDL ................................................................................................................................... 135
7.3.3. Mixed-Language Designs ..................................................................................................... 137

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7.3.3.1. VHDL Designs with One or More Verilog Modules ......................................................... 137
7.3.3.2. Verilog Designs with One or More VHDL Modules ......................................................... 137
7.3.3.3. Compiling Mixed-Language Designs in a Single Run ..................................................... 138
7.4. Creating Custom VHDL Packages ................................................................................................... 139
7.4.1. Technique 1: Modifying Your Installation ............................................................................... 139
7.4.2. Technique 2: Multiple Compile Scripts ................................................................................... 139
7.5. Precompiled VHDL Libraries .......................................................................................................... 140
7.6. The 'wwvmkr' Utility ...................................................................................................................... 141
7.6.1. Creating Your Map Files ........................................................................................................ 141
7.6.2. Running the 'wwvmkr' Utility ................................................................................................ 142
7.7. Precompile RTL Files to a Library (Save/Restore) ............................................................................. 142
7.8. Elaboration Using Advanced Gates ................................................................................................ 144
7.8.1. Understanding the Advanced Gates Model ........................................................................... 145
7.9. Defining Libraries for Command-Line Use ...................................................................................... 148
7.10. Overriding Parameter Settings for Top-Level VHDL/Verilog Modules ............................................. 149
7.11. HDL Advanced Topics .................................................................................................................. 150
7.11.1. Behavioral Clock Gating ...................................................................................................... 150
7.11.2. Using Power Macros ........................................................................................................... 151
7.11.3. Handling Long Parameterized Module Names ..................................................................... 153
7.11.4. Controlling Array Inferencing .............................................................................................. 153
7.11.5. Vector Slicing of Registers and Latches ................................................................................ 156
7.11.6. Enhanced Cell Mapping ...................................................................................................... 157
7.11.7. Default Optimizations and Flows ........................................................................................ 159
7.11.7.1. Compound Cell Modeling .......................................................................................... 159
7.11.7.2. Clock Gating for Inverted Enable Logic ....................................................................... 159
7.11.7.3. Support for Escaped Identifiers .................................................................................. 159
7.11.7.4. Boolean Optimization ................................................................................................ 160
7.12. Gzipped File Support .................................................................................................................. 160
8. PowerArtist RTL Encryption ................................................................................................................ 161
8.1. Introduction ................................................................................................................................. 161
8.2. Use-Model/Flow ........................................................................................................................... 161
8.3. Using the 'ProtectRTL' Command for Encryption ............................................................................ 162
8.3.1. Reading Input RTL Files ........................................................................................................ 162
8.3.2. Generating the Encrypted RTL .............................................................................................. 163
8.4. Decryption and Power Analysis ..................................................................................................... 163
8.5. Support for IEEE-1735 ................................................................................................................... 164
8.5.1. Encryption by IP Creators ..................................................................................................... 164
8.5.2. Decryption by PowerArtist .................................................................................................... 166
9. Preparing for Power Analysis .............................................................................................................. 167
9.1. Introduction ................................................................................................................................. 167
9.2. Estimating Net Capacitances ......................................................................................................... 167
9.2.1. Back-Annotating Capacitance Using SPEF ............................................................................. 168
9.2.2. Using Back-Annotated Load Capacitances for Primary Outputs .............................................. 170
9.2.3. Specifying Default Output Load Capacitance Using a Command Option ................................ 170
9.2.4. Using Back-Annotated Wiring Capacitances for Local Nets ..................................................... 170
9.2.5. Specifying Wire Load Models ................................................................................................ 171
9.2.5.1. Using the Wire Load Model Tcl Commands ................................................................... 171
9.2.5.2. Rules for Estimating Wire Capacitance .......................................................................... 171
9.2.6. Using Default Wire Load Models for Capacitance Analysis ...................................................... 173
9.3. Estimating Pin Capacitance ........................................................................................................... 173
9.4. Handling Voltages in Liberty Format .............................................................................................. 174

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9.5. Handling Designs with Multiple Libraries ....................................................................................... 175

9.6. Handling Designs with Multiple Power Supplies ............................................................................ 175
9.6.1. Creating a Virtual Supply ...................................................................................................... 176
9.6.2. Assigning a Virtual Supply to a Hierarchical Instance ............................................................. 176
9.6.3. Liberty Power Supply Support .............................................................................................. 176
9.6.4. Leakage Power Modeling ..................................................................................................... 177
9.6.5. Fine-Grain Switch Cell Support ............................................................................................. 178
9.6.6. Mode-based Leakage Power in Vectorless Flow ..................................................................... 179
9.7. Running RTL Mixed-VT Power Analysis ........................................................................................... 181
9.7.1. Critical Liberty Leakage Attributes ........................................................................................ 181
9.7.2. Categorizing Cells for Multiple VTs ........................................................................................ 182
9.7.3. Default Cell Selection for Mixed-Vt Analysis ........................................................................... 183
9.7.4. Cell Selection for Clock Gates, Inferred Buffer Tree and MBFs .................................................. 183
9.7.5. SetVT Support for Clock Gate Cell Selection .......................................................................... 184
9.7.6. Sample Mixed-VT Flow and Tcl File ........................................................................................ 185
9.7.7. Understanding Mixed-Vt Analysis Results in the Report File ................................................... 185
9.8. Setting up Clock Power Analysis .................................................................................................... 186
9.8.1. Commands for Clock Power Analysis ..................................................................................... 187
9.8.2. How Clock Power Analysis Works .......................................................................................... 188
9.8.3. Controlling Forward Clock Tracing ........................................................................................ 189
9.9. Setting up Clock Gating for Power Analysis .................................................................................... 190
9.9.1. Clock Gating Flow for Power Analysis .................................................................................... 191
9.9.2. Performing Enhanced Clock Gating ...................................................................................... 191
9.9.3. Library Modeling of Integrated Clock Cells ............................................................................ 193
9.10. Setting up Clock Gating for Power Reduction ............................................................................... 194
9.10.1. Clock Gating Flow for Power Reduction ............................................................................... 194
9.10.2. Clock Gating Algorithm ...................................................................................................... 195
9.10.3. Hierarchical Clock Gating .................................................................................................... 196
9.10.4. Inferring Buffer Trees for Nets with High Fanout .................................................................. 197
9.11. Ideal Clock Network Modeling ..................................................................................................... 197
9.12. Event-based Analysis ................................................................................................................... 198
10. Analyzing Simulation Activity .......................................................................................................... 201
10.1. Introduction ............................................................................................................................... 201
10.2. Defining Different Groups at Each Design Phase .......................................................................... 202
10.3. Understanding the Design Flow with Vector Analysis ................................................................... 202
10.4. Creating Analysis Graphs ............................................................................................................. 203
10.4.1. Determining the Type of Vector Analysis to Run .................................................................. 203
10.4.2. Running Vector Analysis Using Command Files .................................................................... 203
10.4.3. Activity Waveforms per Signal Category .............................................................................. 205
11. Acquiring Simulation Data ................................................................................................................ 207
11.1. Introduction ............................................................................................................................... 207
11.2. Using an FSDB Approach ............................................................................................................. 208
11.2.1. Split FSDB Support ............................................................................................................. 208
11.2.2. FSDB Version ...................................................................................................................... 209
11.2.3. Virtual FSDB (VF) Integration ............................................................................................... 210
11.2.4. Support for Multiple FSDB Readers ..................................................................................... 210
11.2.5. Honoring the FFR FSDB Reader in User Environment ........................................................... 211
11.3. Using the Standard VCD Approach .............................................................................................. 211
11.3.1. Writing a VCD File from a Verilog Simulator ......................................................................... 211
11.3.2. Writing a VCD File from ModelSim ....................................................................................... 211
11.3.3. Writing a VCD File from the Cadence NC-Sim Simulator ....................................................... 212

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11.3.4. Creating a Named Pipe to Manually Compress VCD Files ...................................................... 212
11.3.5. Support for Processing Multi-dimensional Nets in the VCD Flow .......................................... 213
11.4. Acquiring Simulation Data in Palladium Flows ............................................................................. 213
11.5. Troubleshooting Tips ................................................................................................................... 215
11.5.1. Missing 'timescale in Verilog ............................................................................................... 215
11.5.2. Zero Length 'activities.iaf' File ............................................................................................. 215
11.5.3. Problems with ModelSim .................................................................................................... 215
11.5.4. Zero Delay Simulation ........................................................................................................ 215
12. Analyzing Simulation-Based Average Power .................................................................................... 217
12.1. Introduction ............................................................................................................................... 217
12.2. Overall Design Flow .................................................................................................................... 217
12.3. Running a Power Analysis in Full Simulation Mode ....................................................................... 218
12.3.1. Controlling Your Average Power Analysis ............................................................................. 218
12.3.2. Sample CalculatePower Specification for Full Simulation Mode ............................................ 220
12.4. Controlling the Analysis of Simulation Data ................................................................................. 220
12.4.1. Controlling GAF File Creation Explicitly ............................................................................... 220
12.4.2. Determining Weights for a GAF File ..................................................................................... 221
12.4.3. Multiple Testbench Support ................................................................................................ 222
12.4.4. Using the Multiple Testbench Feature to Control FSDB File Size ............................................ 224
12.5. Running Analysis with Incomplete Simulation Data ...................................................................... 225
12.6. Re-Using a Stimulus File from a Previous Run ............................................................................... 225
12.7. Performing Power Analysis with Block-level Simulation Data ........................................................ 226
12.7.1. Performing Top-level Power Analysis ................................................................................... 226
12.7.2. Performing Block-level Power Analysis ................................................................................ 227
12.7.3. Performing Top-level Power Analysis with Multiple Block-level Simulation Activity Files ....... 228
12.8. Performing Gate-level Power Analysis .......................................................................................... 230
12.9. Running Modal Analysis .............................................................................................................. 231
12.10. Understanding the Basics of the Detailed Power Report ............................................................. 232
12.11. Controlling the Contents of the Power Report ............................................................................ 234
12.12. Analyzing Average Power Using a SAIF File ................................................................................ 243
12.13. Analyzing Average Power Using Partial Stimulus Files ................................................................. 245
12.14. Name Mapping Flow ................................................................................................................. 245
12.15. Parallel Activity Processing ........................................................................................................ 247
12.16. RTL Glitch Power Analysis .......................................................................................................... 248
13. Analyzing Vectorless Average Power ................................................................................................ 251
13.1. Flow Overview ............................................................................................................................ 251
13.2. Creating the VAF File ................................................................................................................... 251
13.3. Using the 'SetStimulus' Command ............................................................................................... 251
13.4. What-if Power Analysis with User-specified Signal Activity ............................................................ 253
14. Analyzing Time-Based Power ............................................................................................................ 255
14.1. Introduction ............................................................................................................................... 255
14.2. Overall Design Flow .................................................................................................................... 255
14.3. Understanding the Inputs for a Time-Based Power Analysis .......................................................... 256
14.4. Controlling Your Time-based Power Analysis ................................................................................ 256
14.4.1. Mandatory Options for all Time-based Analyses .................................................................. 256
14.4.2. Additional Options for Gate-Level Designs Only .................................................................. 257
14.4.3. Additional Arguments for RTL and Mixed Designs Only ....................................................... 257
14.5. Setting Timing Windows for Time-based Power Analysis .............................................................. 258
14.6. Running the Analysis ................................................................................................................... 258
14.6.1. Gate-level Time-based Power Analysis ................................................................................. 258
14.6.2. RTL Time-based Power Analysis .......................................................................................... 259

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14.6.3. Cycle-based Power Analysis for GHz+ Designs ..................................................................... 260

14.7. Understanding and Reviewing Outputs and Results of the Time-based Analysis ........................... 260
14.7.1. Contents of the ASCII Report File ......................................................................................... 260
14.7.2. Generating and Viewing Waveforms ................................................................................... 261
14.7.3. Measuring the Distance Between Two Data Points ............................................................... 262
14.7.4. Generating Power Waveforms for Custom Groups ............................................................... 263
14.7.5. Using Results ...................................................................................................................... 266
14.8. Monitoring Flop Clock Activity .................................................................................................... 266
14.8.1. Sample Flop Clock Activity Graphs ...................................................................................... 267
14.8.2. Sample Flop Clock Activity Report ...................................................................................... 268
14.9. Monitoring Signals ...................................................................................................................... 269
14.10. Multi-threading in Time-based Power Analysis ........................................................................... 270
14.11. Power Normalization ................................................................................................................. 271
14.12. Distributed Processing in Time-based Power Analysis ................................................................. 272
14.12.1. Handling Network Delay in Distributed Processing Flow .................................................... 275
15. Examining and Implementing Power Reduction Opportunities ...................................................... 277
15.1. Introduction ............................................................................................................................... 277
15.2. PowerBot Overview .................................................................................................................... 277
15.3. Power Reduction PowerBots ........................................................................................................ 279
15.3.1. Low-Activity Non-Enabled Register (LNR) ............................................................................ 279
15.3.1.1. Usage ........................................................................................................................ 279
15.3.1.2. Implementation ......................................................................................................... 279
15.3.1.3. Trade-offs .................................................................................................................. 280
15.3.1.4. Shared LNR ................................................................................................................ 280
15.3.2. Low-activity Enabled Registers (LER) ................................................................................... 281
15.3.2.1. Usage ........................................................................................................................ 281
15.3.2.2. Reporting Results ...................................................................................................... 281
15.3.2.3. Shared LER ................................................................................................................ 282
15.3.3. Datapath Operator Isolation (DOI) ....................................................................................... 282
15.3.3.1. Usage ........................................................................................................................ 283
15.3.3.2. Implementation ......................................................................................................... 283
15.3.3.3. Trade-offs .................................................................................................................. 283
15.3.4. Local Explicit Clock Enable (LEC) ......................................................................................... 283
15.3.4.1. Usage ........................................................................................................................ 284
15.3.4.2. Implementation ......................................................................................................... 285
15.3.4.3. Trade-offs .................................................................................................................. 286
15.3.4.4. Reporting Results ...................................................................................................... 287
15.3.5. Split Memory Words (SMW) ................................................................................................ 287
15.3.5.1. Implementing Memory Partitioning/Splitting ............................................................. 289
15.3.5.2. Usage ........................................................................................................................ 289
15.3.5.3. Trade-offs .................................................................................................................. 291
15.3.5.4. Understanding the Output of the SMW PowerBot ....................................................... 291
15.3.6. Gate Memory Clock (GMC) .................................................................................................. 293
15.3.6.1. Usage ........................................................................................................................ 294
15.3.6.2. Calculations Performed .............................................................................................. 295
15.3.6.3. Reporting Results ...................................................................................................... 296
15.3.6.4. Ignoring Test Clocks ................................................................................................... 298
15.3.7. Prism .................................................................................................................................. 298
15.3.7.1. Usage ........................................................................................................................ 299
15.3.7.2. Reporting Results ...................................................................................................... 300
15.3.8. Observability Don't Care (ODC) ........................................................................................... 304

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15.3.8.1. Usage ........................................................................................................................ 304

15.3.8.2. Understanding Power Savings and Penalty Calculations in ODC .................................. 305
15.3.8.3. Trade-offs .................................................................................................................. 306
15.3.8.4. Handling Overlaps Between ODC and Other PowerBots .............................................. 306
15.3.8.5. Increased Clock Gating Using Weak Enables ............................................................... 306
15.3.8.6. Optimized Enable Expression by Pruning Don't Care Variables .................................... 307
15.3.8.7. Discrete Gating Logic Support for Enable Derivation ................................................... 308
15.3.8.8. Reset Handling for Functionally-safe ODC ................................................................... 308
15.3.8.9. Controlling ODC Precompute Logic ............................................................................ 309
15.3.8.10. Reporting Results ..................................................................................................... 310
15.3.8.11. Performing Downstream Clock Tracing in ODC ......................................................... 311
15.3.8.12. Displaying Cones of Logic during ODC Analysis ........................................................ 311
15.3.8.13. Observability Don't Care Notes ................................................................................. 312
15.3.8.14. Understanding ODC-based Reductions .................................................................... 313
15.3.9. Strengthened Observability Don't Care (SODC) ................................................................... 315
15.3.9.1. Usage ........................................................................................................................ 316
15.3.9.2. Implementation ......................................................................................................... 317
15.3.9.3. Understanding Power Savings and Penalty Calculations in SODC ................................ 317
15.3.9.4. Trade-offs .................................................................................................................. 318
15.3.9.5. Reporting Results ...................................................................................................... 318
15.3.9.6. Optimizing Enable Expressions in ODC/SODC PowerBots ............................................ 319
15.3.10. Enhanced ODC-based Clock Enable Identification ............................................................. 319
15.3.10.1. Usage ...................................................................................................................... 320
15.3.10.2. Reporting Results ..................................................................................................... 320
15.3.10.3. APSH/Containers Support ........................................................................................ 322
15.3.10.4. GUI Support ............................................................................................................. 322
15.3.10.5. Limitations of the New ODC Algorithm ..................................................................... 322
15.3.11. Enable Signal-based Stability Constraints (STC) ................................................................. 322
15.3.11.1. Usage ...................................................................................................................... 322
15.3.11.2. Reporting Results ..................................................................................................... 323
15.3.11.3. APSH/Containers Support ........................................................................................ 324
15.3.11.4. GUI Support ............................................................................................................. 324
15.4. Power Linter PowerBots .............................................................................................................. 325
15.4.1. Memory Power (MEM) Linter ............................................................................................... 326
15.4.1.1. Implementation ......................................................................................................... 326
15.4.1.2. Usage ........................................................................................................................ 327
15.4.1.3. Reporting Memory Power Wastage ............................................................................ 327
15.4.2. MUX Power (MUX) Linter .................................................................................................... 327
15.4.2.1. Implementation ......................................................................................................... 328
15.4.2.2. Usage ........................................................................................................................ 328
15.4.2.3. Understanding the PowerCanvas Data for the MUX Linter ........................................... 328
15.4.2.3.1. Information in the Upper Pane .......................................................................... 329
15.4.2.3.2. Information in the Tabbed Pane ......................................................................... 331
15.4.2.4. Schematic Display for the Mux Power Linter ............................................................... 331
15.4.2.5. Reporting Wasted Power for Multiplexer Inputs/Cones ............................................... 333
15.4.2.6. Reporting Wasted Power for Inferred Select Nets ........................................................ 333
15.4.3. Register Power (REG) Linter ................................................................................................. 334
15.4.3.1. Implementation ......................................................................................................... 334
15.4.3.2. Usage ........................................................................................................................ 335
15.4.3.3. Reporting Results ...................................................................................................... 335
15.4.4. Clock Enable Condition (CEC) Linter .................................................................................... 336

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15.4.4.1. Implementation ......................................................................................................... 336

15.4.4.2. Usage ........................................................................................................................ 336
15.4.5. Memory Sleep Mode (MSM) Linter ...................................................................................... 337
15.4.5.1. Use Model ................................................................................................................. 337
15.4.5.2. Usage ........................................................................................................................ 337
15.4.5.3. Reporting Results ...................................................................................................... 338
15.4.6. Macro Power Linter (MPL) ................................................................................................... 338
15.4.6.1. Use Model ................................................................................................................. 338
15.4.6.2. Usage ........................................................................................................................ 338
15.4.6.3. Reporting Results ...................................................................................................... 338
15.5. Power Reduction Technique Summary ......................................................................................... 339
15.5.1. Precedence Rule for Optimal Power Reduction ................................................................... 339
15.5.2. Low Noise Register (LNR) / Low-activity Enabled Register (LER) ............................................ 341
15.5.3. Observability Don't-care Condition (ODC/SODC) ................................................................. 342
15.5.4. Power Reduction in State Machines (PRISM) ........................................................................ 343
15.5.5. Gated Memory Clock (GMC) ................................................................................................ 343
15.5.6. Split Memory Word (SMW) .................................................................................................. 344
15.5.7. Memory Sleep Mode Linter (MSM) ...................................................................................... 344
15.5.8. Memory Power Linter (MEM) ............................................................................................... 344
15.5.9. Macro Power Linter (MPL) ................................................................................................... 345
15.5.10. Clock Enable Condition Linter (CEC) .................................................................................. 345
15.5.11. Register Linter (REG) ......................................................................................................... 345
15.5.12. Multiplexer Linter (MUX) ................................................................................................... 345
15.6. Running PowerArtist Clock PowerBots ......................................................................................... 345
15.7. Generating Synthesis Constraints ................................................................................................ 346
15.8. Recommended Flow for Implementing Power Reductions ........................................................... 349
15.9. Viewing Reduction Results .......................................................................................................... 351
15.9.1. Viewing Reduction Results-GUI ........................................................................................... 352
15.9.2. Viewing Reduction Results-Text Reports ............................................................................. 352
15.9.2.1. Power Reduction Summary Report ............................................................................. 352
15.9.2.2. Power Reduction Report ............................................................................................ 352
15.9.2.2.1. Reporting Total Saved Power ............................................................................. 353
15.9.2.3. Clock Gating Report ................................................................................................... 353
15.9.2.4. ODC-by-Enable Report ............................................................................................... 354
15.9.2.5. STC-by-Enable Report ................................................................................................ 354
15.9.2.6. Redundant Reset Report ............................................................................................ 354
15.9.2.7. Memory Access Report .............................................................................................. 354
15.9.2.8. Memory Linter Report ............................................................................................... 355
15.9.2.9. Macro Power Linter (MPL) Report ............................................................................... 355
15.9.3. Blocks Activity Ranking Report ........................................................................................... 355
15.9.4. Clock Gating Report ........................................................................................................... 356
15.9.4.1. Clock Gating Constraints ............................................................................................ 357
15.9.4.2. Clock Gating Summary .............................................................................................. 357
15.9.4.3. Clock Gating by Clock ................................................................................................ 359
15.9.4.4. Clock Gating by Instance - Summary .......................................................................... 360
15.9.4.4.1. Reporting Toggle Numbers for Clock Gating Activity .......................................... 361
15.9.4.5. Clock Gating by Instance - Details ............................................................................... 362
15.9.4.6. Clock Gating Enable Efficiency ................................................................................... 363
15.9.4.7. Clock Gating by Clock Hierarchy ................................................................................. 365
15.9.4.8. Splitting the Clock Gating Report ............................................................................... 366
15.9.5. Hierarchical Clock Efficiency Report .................................................................................... 367

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15.9.6. Memory Access Report ....................................................................................................... 367

15.9.7. Memory Linter Report ........................................................................................................ 369
15.9.8. Accessing Reduction Data Using APSH Containers .............................................................. 372
15.9.8.1. Syntax ....................................................................................................................... 373
15.9.8.2. Examples ................................................................................................................... 373
15.9.8.3. PDB Properties for Querying Clock Enables ................................................................. 374
15.10. Parallel Activity Processing ........................................................................................................ 375
15.11. Fine-Grain Switch Cell Support .................................................................................................. 375
16. Using the PowerCanvas ..................................................................................................................... 377
16.1. Introduction ............................................................................................................................... 377
16.2. Overview of the PowerCanvas Initial View .................................................................................... 378
16.3. PowerCanvas Menus ................................................................................................................... 378
16.3.1. Using the Edit Menu ........................................................................................................... 379
16.3.2. Using the Tools Menu ......................................................................................................... 380
16.3.3. Using the View Menu .......................................................................................................... 380
16.3.4. Using the Help Menu .......................................................................................................... 381
16.4. PowerCanvas Dialogs ................................................................................................................. 382
16.4.1. Using the Find Dialog ......................................................................................................... 383
16.4.2. Using the Preferences Dialog .............................................................................................. 386
16.4.3. Using the Properties Dialog ................................................................................................ 390
16.4.4. Using the Net Activity Dialog .............................................................................................. 391
16.5. Using the Hierarchy Browser ........................................................................................................ 393
16.5.1. Controlling the Hierarchy Browser From the Design Menu ................................................... 393
16.5.2. Column Header Definitions for the Power Table ................................................................... 395
16.6. Using the Schematic Viewer ........................................................................................................ 396
16.6.1. Controlling the Schematic from the Schematic Menu .......................................................... 397
16.6.2. Using the Mouse to Zoom In and Out on the Schematic ...................................................... 400
16.6.3. Expanding the Schematic by Double Clicking Ports ............................................................. 400
16.6.4. Basic Clock Tree Manipulation ............................................................................................. 402
16.6.5. Displaying Observability Don't Care (ODC) Candidates ........................................................ 403
16.7. Using the All Reductions Dialog ................................................................................................... 404
16.7.1. Column Header Definitions for the All Reductions Dialog .................................................... 405
16.7.2. Context Sensitive Help ........................................................................................................ 406
16.7.3. Detecting Duplicate Reduction Opportunities ..................................................................... 406
16.8. Viewing Reductions by Category ................................................................................................. 407
16.8.1. Using the Simple Reduction Dialog ..................................................................................... 407
16.8.1.1. Column Header Definitions for the Simple Reductions Dialog ..................................... 408
16.8.1.2. Column Header Right-Click Menu ............................................................................... 409
16.8.1.3. Simple Reduction Dialog Data Filters .......................................................................... 410
16.8.1.4. Using the Simple Sorting and Filtering Features .......................................................... 411
16.8.1.5. Using the Advanced Sorting and Filtering Features ..................................................... 411
16.8.2. Using the Linter Reductions Dialog ..................................................................................... 413
16.8.2.1. Column Header Definitions for the Linter Reductions Dialog ....................................... 414
16.8.3. The Menus ......................................................................................................................... 415
16.8.3.1. The View Menu .......................................................................................................... 415
16.8.3.2. The Detail Menu ........................................................................................................ 416
16.8.3.3. Help Text in Help Tab ................................................................................................. 418
16.8.4. Using the Prism Dialog ....................................................................................................... 418
16.8.4.1. Categories of Implementation of Suggested Modifications ......................................... 421
16.8.4.2. Definitions for the Bit Counters in the Prism Dialog ..................................................... 421
16.8.4.3. Column Header Definitions for the Prism Dialog ......................................................... 422

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16.8.4.4. Filtering Prism Dialog Data ......................................................................................... 424

16.8.4.5. Using the Normal v s. Optimal Views ........................................................................... 425
16.9. Viewing Reductions by Clock Enables .......................................................................................... 427
16.10. Using the Waveform Viewer ....................................................................................................... 429
16.10.1. Supported Waveform Sources ........................................................................................... 429
16.10.2. Finding and Displaying Waveforms from an FSDB File ........................................................ 430
16.10.3. Manipulating the Waveform Display .................................................................................. 434
16.10.4. Displaying Waveforms from a PTCL File ............................................................................. 434
16.10.5. Displaying Waveforms from an HSPICE or Spectre Simulation ............................................ 434
16.10.6. Using the Waveform Viewer Options ................................................................................. 435
16.10.6.1. Using the Navigation Sub-menu ............................................................................... 435
16.10.6.2. Using the Measurement and Annotation Sub-menu ................................................. 436
16.10.6.3. Using the Display Options Sub-menu ....................................................................... 436
16.10.6.4. Adding Notes to a Plot ............................................................................................. 437
16.10.7. Comparing Waveforms in the Same Plot ............................................................................ 438
16.10.8. Opening Tabs in a Separate Window ................................................................................. 438
16.10.9. Reporting Activity and Duty .............................................................................................. 438
16.10.10. Clock Gating Efficiency Metrics in the Power Table ........................................................... 438
16.10.11. Analyzing Clock Tracing in the GUI .................................................................................. 440
16.10.12. APSH Support in GUI ...................................................................................................... 440
16.11. Using the Signal Viewer ............................................................................................................. 441
16.11.1. Launching the Signal Viewer ............................................................................................. 441
16.11.2. Additional Features .......................................................................................................... 442
16.11.2.1. Drag-Drop Support .................................................................................................. 442
16.11.2.2. Viewing Reduction Opportunities ............................................................................ 442
16.11.2.3. Highlight Accumulated Reduction Data .................................................................... 443
16.11.2.4. Naming Nets ............................................................................................................ 445
16.11.2.5. Selecting the Signal Name Style ............................................................................... 445
16.11.2.6. VCD Stimulus File Support ........................................................................................ 448
16.11.2.7. Auto Loading the Activity File in Signal Viewer .......................................................... 448
16.11.2.8. Cross-probing Support for Linter Reductions ............................................................ 448
16.12. Using the Source Browser .......................................................................................................... 449
16.12.1. Features ........................................................................................................................... 450
16.12.2. Additional Features .......................................................................................................... 451
16.12.2.1. Highlight Important Signals of ODC Opportunities ................................................... 451
16.12.2.2. Highlight the Exact Tokens for Bundled 'Delay Flops' ................................................. 452
16.12.2.3. Highlight Intermediate Elements .............................................................................. 453
16.12.2.4. Highlight Steering Logic ........................................................................................... 454
17. Analyzing the Effects of Power Gating with Proprietary Commands ............................................... 457
17.1. Introduction ............................................................................................................................... 457
17.2. Required Inputs for Power Gating ................................................................................................ 457
17.2.1. Defining Libraries ............................................................................................................... 458
17.2.2. Creating Source Files .......................................................................................................... 459
17.3. Special Option to the 'Elaborate' Command ................................................................................. 460
17.4. Setting up Your Command File for Power Gating .......................................................................... 460
17.5. Performing Simulation-Based Power Analysis with Power Gating ................................................. 462
17.6. Performing Vectorless Power Analysis with Power Gating ............................................................. 462
17.7. Understanding the Output Reports for Power Gating Analysis ...................................................... 463
17.7.1. Sample Report for Simulation-Based Analysis ...................................................................... 463
17.7.2. Sample Report for Vectorless Analysis ................................................................................. 464
18. Generating and Using PACE Technology Files .................................................................................. 467

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18.1. Overview .................................................................................................................................... 467

18.2. Need for PACE ............................................................................................................................. 468
18.3. Types of PACE Models .................................................................................................................. 468
18.4. Capacitance Models .................................................................................................................... 469
18.5. Clock Distribution Network Models ............................................................................................. 470
18.6. RTL Cell Selection ........................................................................................................................ 470
18.7. Cell Mapping in PACE .................................................................................................................. 470
18.8. Generating a PACE Model ............................................................................................................ 471
18.8.1. Selecting the Reference Design .......................................................................................... 471
18.8.2. Data Requirements ............................................................................................................. 471
18.8.3. Using a Tcl Command File ................................................................................................... 472
18.8.4. Resource Tracking During PACE Generation ......................................................................... 473
18.8.5. Sample PACE Generation Script ........................................................................................... 473
18.8.6. Understanding the Internal Process .................................................................................... 475
18.9. Using a PACE Model .................................................................................................................... 475
18.9.1. Using Clock Distribution Network Models ........................................................................... 476
18.9.2. Using the SetClockGatingStyle Command ........................................................................... 476
18.9.3. Advanced Buffer Modeling ................................................................................................. 477
18.9.4. Understanding Priorities and Precedence When Using PACE Models .................................... 477
18.9.5. Additional Guidelines for Using PACE Models ...................................................................... 477
18.9.6. Understanding Output File Changes due to PACE Models .................................................... 478
18.10. PACE Model Version ................................................................................................................... 479
18.11. PACE Technology Migration ....................................................................................................... 479
18.12. Useful APSH Utilities for PACE .................................................................................................... 480
18.13. Performing Correlation Studies .................................................................................................. 481
18.13.1. Setting Up Your RTL Analysis Environment ........................................................................ 481
18.13.2. Setting Up Your Netlist Analysis Environment .................................................................... 481
18.13.3. Leading Correlation Indicators .......................................................................................... 482
18.14. Multi-bit Flip-Flop (MBFF) Mapping in PACE Flow ....................................................................... 482
18.15. PACE Model per Hierarchy ......................................................................................................... 482
18.16. Merge Multiple PACE Models ..................................................................................................... 483
18.17. Using Incremental VT Settings for Cell Assignment/Selection ..................................................... 483
19. Advanced Buffer Modeling in PACE .................................................................................................. 491
19.1. Introduction ............................................................................................................................... 491
19.1.1. Generating PACE Buffer and Repeater Models ..................................................................... 491
19.1.2. Using the PACE Buffer and Repeater Models ....................................................................... 492
19.1.3. Data Visualization and Debugging for PACE Buffer and Repeater Models ............................. 493
19.1.3.1. PACE Report .............................................................................................................. 493
19.1.4. Limitations ......................................................................................................................... 493
19.1.5. Appendix I : Auxiliary Commands and Recommendations for PACE Buffer Categorization ..... 494
19.1.5.1. Recommended Settings ............................................................................................. 495
19.1.5.1.1. Power Management Category ........................................................................... 495
19.1.5.1.2. Logical Category ............................................................................................... 496
19.1.5.1.3. Physical Category .............................................................................................. 497
20. Design-specific PACE ......................................................................................................................... 499
20.1. Introduction ............................................................................................................................... 499
20.2. Generating and Reading Models ................................................................................................. 499
20.3. Name Mapping Gate-Level and RTL Instances .............................................................................. 500
20.4. Cell Mapping File ........................................................................................................................ 501
20.5. Name Map File ............................................................................................................................ 501
20.6. Debugging Name Mapping Issues ............................................................................................... 502

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21. Generating an RTL Power Model ....................................................................................................... 503

21.1. Introduction ............................................................................................................................... 503
21.2. Benefits of the RPM Flow ............................................................................................................. 503
21.3. The RPM Flow ............................................................................................................................. 504
21.3.1. Inputs Required for RPM Generation ................................................................................... 505
21.3.2. Steps for RPM Generation ................................................................................................... 505
21.4. Using the CreateRPM Command .................................................................................................. 506
21.5. Generating a Total Power Plot ...................................................................................................... 506
21.6. RPM Performance Enhancement ................................................................................................. 506
21.7. Fast Power Profiling ..................................................................................................................... 507
21.7.1. Honoring 'reference_clock' during Power Profiling .............................................................. 507
21.7.2. Profile Plotting per Supply .................................................................................................. 507
21.7.3. ProfilePower Split FSDB Flow .............................................................................................. 508
21.7.4. ProfilePower Calibration Flow ............................................................................................. 509
21.7.5. ProfilePower MonitorInstances Flow ................................................................................... 509
21.7.6. Hierarchical Power Profiling ................................................................................................ 509
22. Analyzing Static Power Efficiency ..................................................................................................... 513
22.1. Introduction ............................................................................................................................... 513
22.2. Types of Checks ........................................................................................................................... 513
22.3. Use Model .................................................................................................................................. 514
22.4. Data Requirements ..................................................................................................................... 514
22.5. Syntax ........................................................................................................................................ 515
22.6. Reports ....................................................................................................................................... 515
22.6.1. Custom Reports .................................................................................................................. 515
22.6.2. Logic Optimization Report .................................................................................................. 516
22.6.3. Clock Gating Decision Report ............................................................................................. 516
22.7. Useful PDB Properties for Static Design Efficiency Analysis ........................................................... 516
22.7.1. Register Clock Gating Efficiency Analysis ............................................................................. 517
22.7.2. Memory Clock Gating Analysis ............................................................................................ 518
22.7.3. Glitch Analysis .................................................................................................................... 518
22.8. Support for 'regfiles' and Memory-related Checks ........................................................................ 518
22.9. Accessing Memory Output Pins ................................................................................................... 519
23. Weighted Toggle Coverage (WTC) ..................................................................................................... 521
23.1. Introduction ............................................................................................................................... 521
23.2. Usage Flow ................................................................................................................................. 521
23.3. Use Model .................................................................................................................................. 522
23.4. Outputs ...................................................................................................................................... 524
23.4.1. Reports .............................................................................................................................. 524
23.4.2. FSDB Waveforms ................................................................................................................ 528
23.5. Multiple Time Slices ..................................................................................................................... 529
23.6. Ignore Initial Transitions from 'X' / 'Z' States .................................................................................. 530
24. The Streaming (PAVES) Flow ............................................................................................................. 533
24.1. Introduction ............................................................................................................................... 533
24.2. Veloce-PowerArtist Streaming Flow ............................................................................................. 534
24.2.1. Streaming Modes ............................................................................................................... 534
24.2.2. Benefits .............................................................................................................................. 535
24.3. Parallel Analysis in Activity Streaming Flow .................................................................................. 535
24.4. Environment and Flow Setup ...................................................................................................... 536
24.4.1. Veloce Setup ...................................................................................................................... 536
24.4.2. The PowerArtist-Veloce Setup ............................................................................................. 536
24.4.3. Parallel Analysis Setup ........................................................................................................ 537

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24.4.3.1. Output Files ............................................................................................................... 538

24.5. Veloce-PowerArtist Flow Known Limitations/Issues ...................................................................... 538
25. Supporting DesignWare ® Components ............................................................................................ 539
25.1. Introduction ............................................................................................................................... 539
25.2. Enabling Synthesis of DesignWare Components .......................................................................... 539
25.3. Re-using a Synthesized DW Netlist ............................................................................................... 540
25.3.1. DesignWare Cache Directory Location ................................................................................ 540
25.4. Creating AW Wrappers for Unsupported DW Components ........................................................... 540
25.4.1. Steps to Create an AW Wrapper ........................................................................................... 541
25.4.2. Sample AW Wrappers ......................................................................................................... 542
25.5. Passing Options to External Synthesis Tools ................................................................................. 543
25.6. The DWCompDefinition.txt File ................................................................................................... 543
A. DWCompDefinition Text File .................................................................................................................. 545
A.1. The DWCompDefinition.txt File ..................................................................................................... 545

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List of Figures
4.1. Opening the PowerArtist Waveform Viewer ........................................................................................... 33
4.2. Vector Analysis Waveforms for Each Specified Group (Individual Plots) ................................................... 34
4.3. Vector Analysis Waveforms for Each Specified Group (One Plot) ............................................................. 34
4.4. Average and Absolute Flock Clock Activity Analysis Waveform in PTCL Format (One Plot) ....................... 37
4.5. Display of average_power.pdb (Average Power Analysis Results) ............................................................ 48
4.6. Schematic Display of Module Selected in the Hierarchy ......................................................................... 49
4.7. Properties Dialog for Net txdin .............................................................................................................. 50
5.1. Hierarchy Browser Display of Power Database ........................................................................................ 83
5.2. Simple Reductions Dialog ..................................................................................................................... 84
5.3. Sample of LNR PowerBot Expanded to Show Instances .......................................................................... 85
5.4. Menu for Instance-Level Entry ............................................................................................................... 86
5.5. Sample Context-Sensitive Help Page for the LNR PowerBot .................................................................... 87
5.6. Filtering Simple Reduction Results - Before ............................................................................................ 88
5.7. Filtering Simple Reduction Results - After .............................................................................................. 88
5.8. Linter Power Reductions Results ............................................................................................................ 89
5.9. CEC Linter Power Reduction Results with Detail Tab Displayed ............................................................... 90
6.1. Opening the PowerArtist Waveform Viewer ......................................................................................... 130
6.2. Waveform Viewer showing the peak power and high didt per cycle ...................................................... 131
8.1. RTL IP Flow ......................................................................................................................................... 162
10.1. Sample Vector Analysis Waveforms .................................................................................................... 205
14.1. Sample Power-Over-Time Waveform ................................................................................................. 262
14.2. Measuring Distance between Data Points .......................................................................................... 263
14.3. Sample Waveform in PTCL Format for Instantaneous Analysis ............................................................. 263
14.4. Sample Waveform in PTCL Format for Instantaneous Analysis ............................................................. 268
15.1. Overview of PowerBots ..................................................................................................................... 278
15.2. LNR - Schematic and Timing Diagrams ............................................................................................... 279
15.3. LNR - Circuit Diagram ........................................................................................................................ 280
15.4. DOI - Schematic Diagram 1 ................................................................................................................ 283
15.5. DOI - Schematic Diagram 2 ................................................................................................................ 283
15.6. LEC - Schematic Diagram ................................................................................................................... 284
15.7. LEC - Circuit Diagram ......................................................................................................................... 285
15.8. Split Memory Words - Schematic Diagram ......................................................................................... 288
15.9. Strengthened Observability Don't Care - Schematic Diagram ............................................................. 315
15.10. Linter Reduction Dialog Showing MUX Results ................................................................................. 329
15.11. Exclusive Cone of Logic in Schematic (Colored by Connectivity) ....................................................... 332
15.12. Sample Clock Gating Effectiveness Waveform .................................................................................. 348
16.1. Initial Power Canvas Display (Tutorial Design) .................................................................................... 378
16.2. PowerCanvas Menus ......................................................................................................................... 379
16.3. Schematic Viewer Shortcuts .............................................................................................................. 381
16.4. Find Dialog ....................................................................................................................................... 383
16.5. Find Dialog (Search with Multiple Criteria) ......................................................................................... 384
16.6. Displaying Source for Element in Returned Search List ....................................................................... 385
16.7. Preferences Dialog ............................................................................................................................ 387
16.8. Properties Dialog with Multiple Tabs and Instances Displayed ............................................................ 390
16.9. Displaying the Downstream Cone of Logic for an Output Pin .............................................................. 391
16.10. Hierarchy Browser ........................................................................................................................... 393
16.11. Design Menu .................................................................................................................................. 394
16.12. Schematic Display ........................................................................................................................... 396
16.13. Schematic Menu ............................................................................................................................. 397

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User Guide

16.14. Hierarchical Schematic Body ............................................................................................................ 401

16.15. Nested Schematic for a Hierarchical Block ........................................................................................ 402
16.16. Inferred Clock Tree .......................................................................................................................... 403
16.17. All Reductions ................................................................................................................................. 405
16.18. Reductions By Enable ...................................................................................................................... 407
16.19. Simple Reductions Dialog ................................................................................................................ 408
16.20. Simple Filtering Features ................................................................................................................. 411
16.21. Sample Multi-Level Advanced Sorting and Filtering ......................................................................... 412
16.22. Sorting Total Power Values at Different Hierarchical Levels ................................................................ 413
16.23. Linter Reductions Dialog ................................................................................................................. 414
16.24. Right-Click Menu from Detail Tab ..................................................................................................... 417
16.25. Prism Dialog (Initial View) ................................................................................................................ 419
16.26. Prism Dialog (Expanded View) ......................................................................................................... 420
16.27. Reductions By Enable ...................................................................................................................... 428
16.28. Selecting an FSDB File with the Waveform Viewer ............................................................................ 430
16.29. Waveform Viewer with a List of Available Waveforms ........................................................................ 431
16.30. Waveform Display with Three Plots .................................................................................................. 433
16.31. Break-Down of a Waveform Name ................................................................................................... 433
16.32. Signal Viewer .................................................................................................................................. 441
16.33. Viewing Wasted Power in the Signal Viewer ..................................................................................... 442
16.34. Smart Source Browser ..................................................................................................................... 450
24.1. Veloce-PowerArtist Streaming Interface ............................................................................................. 534
24.2. High Performance Veloce-PowerArtist Flow ....................................................................................... 535
24.3. Veloce Power App + PowerArtist PAVES Flow ...................................................................................... 536

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List of Tables
7.1. Advanced Liberty Cell Models ............................................................................................................. 145
7.2. Description for Arguments and Effective Flow ..................................................................................... 148
15.1. Overview of PowerBots ..................................................................................................................... 278
18.1. Precedence Rules for the WriteTechnologyFile command ................................................................... 486
18.2. User-specified VT Group Override Precedence Rules .......................................................................... 488
18.3. When SetVoltageThreshold command is specified ............................................................................. 488

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Chapter 1: Introduction to PowerArtist
1.1. PowerArtist and Your Design Flow
PowerArtist is a complete RTL Design-For-Power (DFP™) environment with fully-integrated advanced
analysis and automatic reduction. The following diagram illustrates how PowerArtist fits into your design
flow:

Some highlights of the PowerArtist environment include:

• RTL and Gate-Level Full-Chip Power Analysis

You can analyze designs with multiple power supplies, mixed Verilog-Verilog2001-VHDL-System
Verilog descriptions, and embedded IP models. Power analysis includes both average power
analysis and time-based analysis. For detailed information on running these features, see Analyzing
Simulation-Based Average Power (p. 217) and Analyzing Time-Based Power (p. 255).

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Introduction to PowerArtist

• Automatic Analysis-Driven RTL Power Reduction

PowerArtist includes a comprehensive set of power reduction techniques, called PowerBots, that
you can use to perform clock, memory, and datapath power reduction. For complete details on
the available types of power reductions, see Examining and Implementing Power Reduction
Opportunities (p. 277).

• Activity/Vector Analysis

PowerArtist's vector analysis capability allows you to visualize activity for an entire test suite, for
any combination of modules in the design to quickly identify coverage problems and unexercised
power modes. You can select small, power-intensive time slices for detailed power verification.
For details on using vector analysis, see Analyzing Simulation Activity (p. 201).

• Fast Power Profiling

PowerArtist includes a high performance power profiling engine which generates cycle-based
peak and average power profile of a given simulation vector. The engine trades off accuracy
for performance and hence does not report absolute power per cycle. For details on using
fast power profiling, see Fast Power Profiling (p. 507).

• An OpenAccess Database

PowerArtist stores power information in an OpenAccess database. The power information stored
includes netlists, power reduction results and properties that represent calculated or extracted
power data associated with the nets, instances and pins of your design.

1.2. Tutorials to Get You Started

If you are a new user of PowerArtist, you should run the following tutorials:

• Analysis Tutorials

PowerArtist Tutorial Part I: Power Analysis (p. 19)

• Reduction Tutorials

PowerArtist Tutorial Part II: Power Reduction (p. 71)

• Advanced Tutorials

PowerArtist Tutorial Part III: Advanced Features (p. 95)

The tutorial files are available in the tar kit:

$POWERARTIST_ROOT/tutorial

Note: The PowerArtist tutorials are a feature demonstrator and are not intended as an example on how
to set up PowerArtist on a new design.

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 Sample Flow Script Templates

1.3. Sample Flow Script Templates

To enable quick ramp-up for new customers and ease-of-use for existing customers, sample flow
development scripts are included in the PowerArtist installation. These scripts are located at:
$POWERARTIST_ROOT/utils/flow_scripts_template/

The scripts support the common flows, such as Power Analysis, Power Reduction, Vector Analysis,
ProfilePower, Vectorless power analysis and reduction, Static RTL efficiency analysis, and PACE generation
and usage and capture common 'best practices'.

For detailed information on how to make the best use of these sample scripts, contact your support
application engineer for the 'Application Note'.

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Chapter 2: Installing and Setting Up PowerArtist
2.1. Introduction
This chapter provides instructions to enable you to install the software and access the PowerArtist
application. You need to perform the following three steps:

1. Install the software on one of the supported operating systems.

2. Install and point to the appropriate licenses.
3. Set a critical environment variable to point to the installation directory (and modify the 'PATH'
environment variable.

2.2. Supported Operating Systems

PowerArtist is supported on the following 64-bit operating systems/platforms:

Operating Systems (64-bit) Versions Notes

Red Hat Enterprise 7 7.5 and above NA
Red Hat Enterprise 8 8.5, 8.6, 8.7, 8.8 & NA
8.9
SuSE Linux Enterprise Server & Desktop 12 SP5 NA
SuSE Linux Enterprise Server & Desktop 15 SP3, SP4 & SP5 NA
Ubuntu LTS 20.04 & 22.04 NA
Rocky Linux 8.9 NA

2.3. Platform Compliance Checker

In previous releases of PowerArtist, you may have experienced unexpected issues on platforms that are
available in your environment but may not be in the Ansys platform/OS supported list. For example, it
is not uncommon to submit jobs to a farm without specifying the OS type/version and jobs can
unexpectedly be assigned to a machine whose OS is not supported by PowerArtist. To reduce wasted
effort, an additional step is added in PowerArtist to up-front perform the following platform compatibility
checks:

• Kernel version
• Window manager - 'fvwm X' and 'Metacity (Marco)'
• Shared Library requirements
• 'ANSYSLMD_LICENSE_FILE' settings
• Operating System support

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Installing and Setting Up PowerArtist

Note: There is no runtime impact due to this additional step.

You can launch PowerArtist either through 'pa_shell' or the PowerArtist GUI. PowerArtist may emit
warnings about the support that is in place for the platform that you are using (supported by proxy,
not supported) or errors if the platform is unrecognized. These errors, warnings, or informational
messages are written to the screen and captured in the 'pa_shell.log' file.

2.4. Installing the Software

To install the software on a supported OS, perform the following steps:

1. Decide where you want to put the distribution and change your working directory to that directory.
The following sub-directory is created within the current working directory:
PowerArtist/version/PowerArtist

2. Uncompress and extract the software distribution by typing the following command. The name of
the zipped tar file is platform-dependent.
gunzip -c PowerArtistversion.platform.tar.gz | tar xf -

Notes:

• The name of the zipped tar file is platform-dependent.

• You can install multiple platform distributions in the same directory, as discussed in the next
section.

2.5. Distribution Tree

The PowerArtist distribution is organized so that the executables for multiple platforms are installed in
the same location. Therefore, platform-specific files are kept under directories with the following
platform-specific name:

• for 64-bit Linux - linux-x86_64

The 'PATH' environment variable must include the '$POWERARTIST_ROOT/bin' directory. It

need not have any platform-specific path elements, because a platform-independent script invokes
the correct executable.
• bin

Contains the executables. Set your 'PATH' to include this directory.

• doc

Contains the PDF documentation and the release notes.

• examples

Contains some user examples and some examples for library developers.
• lbin

Contains administrative programs that you do not want in your 'PATH'. This includes the FLEXlm
administration utilities and the PowerArtist license server.

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 PowerArtist Licensing

• lib

Contains library files needed by the power tools.

• misc

Contains the source to the 'wwvmkr' VHDL makefile program.

• pthdl_src

Contains VHDL source files for the IEEE, STD, Synopsys, and Vital libraries for the HDL analyzer,
'pthdl' (run by the Elaborate command).
• scripts

Contains Tcl files that implement all OADB utilities, such as, reportPower and reportCGEfficiency.
• sfl_lib

Contains the SFL model file (sfl_lib.dat) and generic technology library information.
• tutorial

Contains files for running command-line tutorials in PowerArtist.

• vhdl_src

Contains VHDL source files for the IEEE, STD, Synopsys and Vital libraries for the legacy VHDL
analyzer, 'wwvhdl'.

2.6. Setting the UNIX Environment Variable for PowerArtist

To configure PowerArtist, set the 'POWERARTIST_ROOT' environment variable to the proper installation
directory. On the UNIX command line, use the following commands to set the environment:
setenv POWERARTIST_ROOT /<your_path>/version/POWERARTIST
set path =($POWERARTIST_ROOT/bin $path)

2.7. PowerArtist Licensing

PowerArtist, like other ANSYS products, uses the ANSYS licensing library to verify if the tool is allowed
to run in the customer environment. The highlights of the licensing library are described below:

• Use the environment variables 'LM_LICENSE_FILE' or 'ANSYSLMD_LICENSE_FILE' to specify the

license file/server path.

Note: The environment variable 'LM_LICENSE_FILE' is not supported on RHEL6.

• The following variable is deprecated:

pa_set multiple_license_files <true | false>

If you set the variable on the 'pa_shell' prompt, it is ignored. When 'pa_set' attempts to set it,
the following warning is printed:
pa_shell % pa_set multiple_license_files true
Warning SHL-72 : 'multiple_license_files' was obsoleted

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Installing and Setting Up PowerArtist

in version 2020 R2.

It will be disregarded by this release.

If you set it via a tcl script, the same warning 'SHL-72' is issued, as shown below:
Warning SHL-72 : 'multiple_license_files' was obsoleted
in version 2020 R2.
It will be disregarded by this release.
pa_shell: Completed successfully with 1 warning(s)

• PowerArtist allows all available license servers to serve license requests and no additional user
setting is required.

• Support for the 'TIMEOUTALL' command (specified in the option file) to control license timeout
is available through the following variable:
pa_set wait_for_license_timeout <integer>

When specified, PowerArtist waits for the required license for the specified number of seconds
before exiting.

• If the license server is down, PowerArtist waits for one hour before shutting down. You can
extend the wait time of one hour to infinity by using the following variable:
pa_set -wait_for_license true

Ansys license logs are report QUEUE_STARTED, QUEUE_GRANTED and QUEUE_RETURNED messages
when a license is queued.

All other licensing inputs (such as environment variables) are documented and supported by the
corporate licensing team. Refer to the Ansys Licensing Guide and Ansys Installation Guides for more details.
Both these guides are available from the Ansys Customer Portal.

2.7.1. Support for Multiple License Servers

PowerArtist supports multiple FLEXlm license servers. See the FLEXlm documentation for details on
how to set up multiple license servers.

2.7.2. Monitoring License Server Availability

PowerArtist monitors license server availability and pauses (instead of terminating) and waits for one
hour only before shutting down. Warning 'UTL-223' is issued while PowerArtist is waiting and Note
'UTL-238' is issued when the license server reconnects. This ensures that there is no loss of work,
in case of failure of the license server(s).

2.7.3. Product vs. Feature Licenses

PowerArtist licenses are categorized into product licenses and feature licenses. Product licenses 'own'
feature licenses. This means that you can perform power analysis steps in parallel only if you have
multiple product licenses.

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 PowerArtist Licensing

2.7.4. Waiting for a Feature License

If you do not have a required feature license available to you immediately, you can instruct the
software to wait for a license to become available. This feature is controlled by the
'-wait_for_license' option to most of the Tcl commands. For example, the following command
waits for the license that controls elaboration to become available rather than exiting when one is
not immediately accessible:
Elaborate -wait_for_license true

At the product level, 'pa_shell' also has an option to wait for a product license, (such as an SOC
license) as shown in the example below:
pa_shell -SOC -wait

2.7.5. Resolving Feature Checkout Problems

If you get random license checkout problems, change the license file's port number to something
else in case there is a conflict with another vendor's daemon.

Example
In the following example, the port number is 7788:
SERVER hostname 000f1f64dc32 7788

2.7.6. Microsoft Defender vs. ACL

There is a potential incompatibility between Microsoft Defender app_version: '101.52.57' and Ansys
Corporate Licensing (ACL). This can cause the process of license checkouts to slow down or fail.

Ansys recommends switching to app_version: '101.47.76' or if that does not work, shutting down
Microsoft Defender.

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Chapter 3: Using the PowerArtist Shell
3.1. Introduction
The PowerArtist shell (pa_shell) is a fully functional Tcl shell, from which all other PowerArtist commands
must be invoked. You can use any standard Tcl command inside of this shell. When you start up the
shell, information about the product is displayed on the stdout, and then receive a 'pa_shell' prompt.
You can run any PowerArtist command at the 'pa_shell' prompt.

3.2. Understanding the pa_shell Command Options

The pa_shell command launches the PowerArtist Tcl shell. You can source Tcl scripts or type the
commands from within the 'pa_shell' prompt. Use the 'exit' command to close the 'pa_shell'
prompt.

Syntax
pa_shell
[-auto_exit]
[-cmd <tcl_command>]
[-ex]
[-key <file_name>]
[-log <log_file>]
[-pt]
[-tcl <tcl_file>]
[-wait]
[-work <directory_name>]

Options
-auto_exit

Automatically exits the PowerArtist shell after the file specified with the '-tcl' option is evaluated.
The default behavior is to remain in the shell if the specified does not contain an 'exit' command.

-cmd <tcl_command>

Executes the specified Tcl command and then exits with the result.

-ex

Consumes licenses at the PowerArtist/EX level.

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Using the PowerArtist Shell

-key <file_name>

Specifies the key file name. The key file is a record of all commands issued during a PowerArtist
shell session.

-log <log_file>

Specifies the alternate log file name. The default file location and name is:
<work_dir>/pa_shell.log

-pt

Consumes licenses at the PowerArtist/PT level. Excludes Powerartist features, including reduction.
You get a 'pa_shell' prompt with this option.

-tcl <tcl_file>

Sources a file containing Tcl commands and then exits with the result. These commands may also
include PowerArtist commands.

-wait

Waits for the appropriate product license to become available rather than exiting immediately with
a message indicating that a license is not available.

-work

Specifies the alternate work directory name. The default location and name is:
./pa_shell_work

Examples
• Example 1: The following command invokes the PowerArtist shell. At the resulting 'pa_shell'
prompt, you can type any Tcl or PowerArtist command. By default, this command consumes the
'sptSOC' and 'sptArtist' licenses and you are able to execute all PowerArtist-PT commands:
pa_shell

• Example 2: The following command invokes the PowerArtist shell. By default, this command consumes
only 'sptSOC' licenses and you will not be able to perform power reduction analysis:
pa_shell -pt

• Example 3: The following command consumes licenses at the PowerArtist level and then runs the
Tcl script Elaborate.tcl:
pa_shell -tcl run_Elaborate.tcl

A sample 'Elaborate.tcl' file is shown below:

source ptSourceFiles.tcl
Elaborate -scenario_file my.scn \

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 pa_shell Features

-top top \
-synlib_files {mylib.lib}

When the Elaborate command completes, the 'pa_shell' is exited.

• Example 4: The following commands do the same thing as the command in Example 3, except that
you remain in 'pa_shell' when 'Elaborate.tcl' is complete. That is, it does not exit 'pa_shell'.
pa_shell
pa_shell % source Elaborate.tcl

• Example 5: When you type 'pa_shell' followed by a carriage return, you get the following prompt:
# Command:
pa_shell
# Output:
pa_shell %

At this point, you can type the following commands :

pa_shell % source ptSourceFiles.tcl
pa_shell % Elaborate -scenario_file my.scn -top top -synlib_files {mylib.lib}
pa_shell % exit

• Example 6: To print a list of commands that you can use in a PowerArtist command file/Tcl script,
use the following command at the 'pa_shell' prompt:
pa_shell
pa_shell % help command

• Example 7: The following command prints help information for the CalculatePower command. The
information is first sent to stdout and then re-directed to a file named 'cphelp':
pa_shell -cmd "CalculatePower -help" > cphelp

To run a Tcl command at 'pa_shell', you must enclose the command in quotes as shown in the
example above.

3.3. pa_shell Features

The 'pa_shell' is a fully functional Tcl shell from which you can invoke any standard Tcl command.
In addition, 'pa_shell' supports a set of TCSH-like features for command editing, file completion, and
more. The 'pa_shell' has the following features:

• Command-line help for commands

– You can type 'help command_name' such as 'help CalculatePower'. You can also specify
a partial command name with standard glob-style wild cards such as 'help Calc*' or 'help
*db*'.
– You can type 'command_name -help' such as 'Elaborate -help' in the 'pa_shell' to get
a list of options for the 'Elaborate' command.
– You can generate an alphabetical list of all accepted PowerArtist Tcl commands by typing
'help command' and of all pa_set variables by typing 'help variable' at the 'pa_shell'
prompt.

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Using the PowerArtist Shell

• Error Messaging

If 'pa_shell' encounters an error, it attempts to provide details using the TCL variable
'errorInfo'. This should enable users to determine the possible cause of the problem. Consider
the following example message:
pa_shell: Error 9675: An error was encountered by pa_shell: invalid command
name
DefineMemory1".
See the log for more details.
pa_shell: Failed with 1 error(s) and 0 warning(s)

When 'pa_shell' runs a sub-command (such as 'CalculatePower'), the result can be the entire
sub-command log file. If the message is more than five lines, 'pa_shell' filters and prints a
summary of the errors encountered, as shown in the following example:
rm: cannot remove directory `pa_shell_work': Directory not empty

Error SHL-6: An error was encountered by pa_shell: <snip>

Eror SCN-76: Can not open .scn file:
Error ENG-55: Unable to read scenario file: Can not open
Error ENG-599: Could not read input netlist (dummy.in)
</snip>

• An auto-generated history file

As each PowerArtist command is executed, it is captured into a 'pa_shell.history' file in

the current working directory. This allows you to run Tcl programs that execute commands that
are stored in the history file. You can then source this file (using the Tcl source command) to
re-run the exact sequence of commands.

• Command/file name completion with the 'Tab' key

The shell expands a command to the next unique character and provides a list of all possible
commands/file names to complete the entry.

• Honor license files

If 'pa_shell' is launched with the following option:

% pa_shell -wait

'pa_shell' automatically sets the variable 'wait_for_license' to 'true'. This ensures that
all commands that are run at the 'pa_shell' prompt now have the value set for them.

Note: Ensure that the environment variable 'ANSYSLMD_LICENSE_FILE' is a colon (':')

separated list of license files or license servers, without any directory names, as shown in the
example below:
% setenv ANSYSLMD_LICENSE_FILE 1XX1@lic0A:1YY1@lic0B

• Command-line editing

Use the left and right arrows, control characters, and escape sequences to edit the current
command on the command line. The following table lists the keystroke combinations and their
associated actions:

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 Customizing Your PowerArtist Environment Using Initialization (INI) Files

Key/Key Combination Action

Ctrl-a Goes to the beginning of the line
Ctrl-b Moves back one character
Ctrl-d Deletes current character
Ctrl-e Goes to end of the line
Ctrl-f Moves forward one character
Ctrl-k Yanks and deletes until the end of the line
Ctrl-n Gets the next command from history
Ctrl-p Gets the previous command from history
Ctrl-y Pastes the yanked buffer
Esc-b Moves back one word
Esc-f Moves forward one word
Left arrow key Moves back one character
Right arrow key Moves forward one character
Up arrow key Gets the previous command from history
Down arrow key Gets the next command from history

• Recalling commands from history

Use the up and down arrows to scroll through commands that were previously executed in the
current session. By default, 20 commands are saved in history. Use 'history keep 50' to
increase the history size to 50.

• An initialization file (.ini) file

The file allows you to customize your pa_shell run. See the next section for details.

3.4. Customizing Your PowerArtist Environment Using Initialization (INI)

Files
You can use '.ini' files to customize the pa_shell setting at multiple levels. You can use this file to
change the default names of the log file and the key file (see, Understanding Log Files and Key
Files (p. 16) for details). You can also specify a custom pa_shell prompt. You can place the .ini files in
different locations to customize at different levels. The shell sources the .ini files in the following order
(the last one taking precedence over previously read files):

1. The default .ini file located at '$POWERARTIST_ROOT/pa_shell.ini' is read first. Further .ini
files (if present) modify the settings in this file.

2. The .ini file located at '$HOME/pa_shell.ini' is read next. Use this .ini file to customize the shell
for yourself as a user.

3. The .ini file located at '$PWD/pa_shell.ini' is read next. Use this .ini file to customize the shell
for a particular run.

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Using the PowerArtist Shell

4. The .ini file pointed to by the environment variable '$PA_SHELL_INI', if present, is read last. Use
this .ini file to customize the shell for a particular project.

Sample Initialization File

The following sample initialization (.ini) file includes 'pash_*' variables that you can use to customize
your PowerArtist shell:
#++++++++++++++++++++++++++++++++++++
# Sample Initialization File
#++++++++++++++++++++++++++++++++++++
set pa_shVerbosity 2

history keep 50

# variables for engine(s)

# set paBexprEffortLevel low

# source generic TCL utils

set paScriptsPath $env(POWERARTIST_ROOT)/scripts
source $paScriptsPath/paSetup.tcl

3.5. Understanding Log Files and Key Files

When you run 'pa_shell', you always get a '.key' file and a '.log' file that capture session information
in different ways:

• pa_shell.log

This file captures all tool outputs for your current session. This includes commands run, output
generated (including the content of each of the individual 'command_name.log' files), and the
contents of any sourced files. You can change the name of this file using the 'pashLogFile'
Tcl variable in your '.ini' file.

• pa_shell.key

This file captures commands executed from the pa_shell. You can source this '.key' file to re-run
the exact sequence of commands from the recorded session. You can change the name of this
file using the 'pashKeyFile' Tcl variable.

3.6. Invoking the GUI

You can invoke the GUI (PowerCanvas) in the following ways:

• You can invoke PowerCanvas from 'pa_shell' using the 'PowerCanvas' command:
pa_shell % PowerCanvas

• You can optionally use the '-pdb' option to specify the power database to load:
pa_shell % PowerCanvas -pdb top.pdb

• You can also bring up the GUI from the UNIX command line as shown below:

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 'Man' command Support

% PowerArtist

This is the recommended way to invoke the PowerArtist's GUI with full analysis and reduction
capabilities.

3.6.1. Understanding the Link between PowerArtist Commands and

PowerCanvas
PowerCanvas is the Graphic User Interface for PowerArtist and it contains features that help you
diagnose power bugs in your design and understand the output of various automated reduction
algorithms.

3.7. 'Man' command Support

'man' pages have historically provided rapid access for Linux users to obtain help on Linux commands.
As opposed to '.pdf' documents, man pages provide rapid look up of command options and examples
without having to invoke another tool to view documentation. To use this capability, PowerArtist now
provides 'man' versions of the documentation of commands and options that is otherwise available
only in the PowerArtist Reference Manual.

PowerArtist includes support for the following Linux commands that enable you to view the description
of PowerArtist commands and options (including all 'pa_set' options and 'pa_shell' commands):

• man

Is a built-in manual for using Linux commands. It allows users to view the reference manuals of
a command or utility run in the terminal. The man page (short for manual page) includes a
command description, applicable options, flags, examples, and other informative sections.

Note: The 'man' command is case sensitive.

Sample output of the 'man' command is shown below:

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Using the PowerArtist Shell

• apropos

If you know what you want to do, but you do not know which command to use, try the 'apropos'
command. The command prints one-line summaries of commands, based on 'keyword' search.

Sample output of the 'apropos' command is shown below:

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Chapter 4: PowerArtist Tutorial Part I: Power Analysis
4.1. Introduction
This tutorial showcases how to perform RTL power analysis for your design using PowerArtist and
highlights design elaboration, vector and clock activity analysis, average and time-based power analysis,
and generation of useful power analysis reports.

Notes:

• This tutorial does not cover power reduction and the advanced features of PowerArtist. To run
the power reduction tutorial, see PowerArtist Tutorial Part II: Power Reduction (p. 71). To run
the tutorials of the advanced features, see PowerArtist Tutorial Part III: Advanced Features (p. 95).
• The PowerArtist tutorials are a feature demonstrator and are not intended as an example on
how to set up PowerArtist on a new design.

Tutorial Organization
The following topics are covered in this tutorial:

• Understanding the Tutorial Files (p. 19)

• Understanding the Power Analysis Flow (p. 21)
• Understanding the Analysis Tutorial Steps (p. 22)
• Understanding Power Analysis Setup (p. 24)
• Design Elaboration (p. 25)
• Common Setup for Clock Definitions (p. 26)
• Running Static Efficiency Checks (p. 29)
• Running Activity Analysis for Clock and Data (p. 31)
• Running Weighted Toggle Coverage (WTC) (p. 37)
• Running Average Power Analysis (p. 40)
• Generating Additional Power Reports (p. 43)
• Running Fast Power Profiling (p. 43)
• Running Time-Based Power Analysis (p. 44)
• Viewing Power Analysis Results in the PowerArtist Graphical Interface (p. 47)
• Understanding Power Analysis through Text Reports (p. 50)
• Using the Power Analysis Results (p. 69)

4.2. Understanding the Tutorial Files

The tutorials focus on the PowerArtist command-line flow, which is designed to allow you to specify
all inputs and commands in a single Tcl command file.

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PowerArtist Tutorial Part I: Power Analysis

There are four directories in the 'tutorial' directory. Ansys recommends that you copy the entire
contents of the directory to a local run directory:
% cp -r $POWERARTIST_ROOT/tutorial .

4.2.1. Contents of the 'tutorial' Directory

The following table lists the contents of the 'tutorial' directory:

Directory Description
Name/FileName
data Contains the technology libraries, design, and simulation data required to
run the RTL and gate-level tutorials. It includes the following directories:

• design
• libraries
• sdc
• sim
• spef
• upf_cpf

analysis Contains the power analysis tutorial files. This tutorial demonstrates how to
perform HDL inferencing, activity analysis for clock and data, and average
and time-based power analysis.
reduction Contains the power reduction tutorial files. This tutorial demonstrates how
to perform RTL power reduction. This tutorial is described in the next chapter.
For instructions on running the reduction tutorial, see PowerArtist Tutorial
Part II: Power Reduction (p. 71).
advanced Contains a number of sub-directories that each run a different type of tutorial
and demonstrate some of the advanced features of PowerArtist:

• gate_power - Gate-level Power Analysis (p. 101)

• pace - Physically-Aware RTL Power Accuracy with PACE Models (p. 119)

• rpm - Generating an RTL Power Model (p. 125)

• upf_cpf - UPF/CPF-based Power Analysis (p. 110)

• vectorless - Vectorless Power Analysis and Reduction (p. 95)

README This is a text file that provides information about the 'tutorial' directory
structure.

For the power analysis tutorial, you need only the 'analysis' and 'data' directories. To get started,
copy the directories from the following location:
$POWERARTIST_ROOT/tutorial/analysis
$POWERARTIST_ROOT/tutorial/data

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 Understanding the Power Analysis Flow

4.2.2. Contents of the 'analysis' Directory

The following table lists the contents of the 'analysis' tutorial:

Directory Description
Name/FileName
README Describes the basic flow for running this tutorial.
input Contains the following files:

• txrx.mode - Is the mode control file for modal analysis.

• txrx.vc - Is the Verilog startup file that tells the HDL
elaborator which Verilog files must be loaded for your design.

pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt and is used
to customize the 'pa_shell' settings at multiple levels.
run.tcl A Tcl script to run the tutorial in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various sub-tasks
related to power analysis (such as, design elaboration, vector
analysis, and average power analysis).
cleanall A script to remove all the files created while running the 'analysis'
tutorial.

4.3. Understanding the Power Analysis Flow

Running power analysis is as shown by the following graphic:

The main steps in this power analysis flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

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PowerArtist Tutorial Part I: Power Analysis

2. GenerateActivityWaveforms

Analyzes the activity file and produces waveform files representing the activity in your design.

3. CalculateFlopClockActivity

Monitors the activity at the clock pins of registers.

4. CalculatePower

a. -analysis_type average - performs average power analysis.

b. -analysis_type time_based - performs time-based power analysis.

4.3.1. Inputs
PowerArtist requires the following inputs to calculate power for an RTL or a gate-level design:

• RTL/Gate-level Design Files

Supported formats are Verilog, VHDL, System Verilog, or a mix of any of these three HDLs.
• Simulation Activity File
Supported formats for activity information are FSDB, VCD, and SAIF.
• Power Libraries
Characterized libraries in Liberty format (.lib).
• Net Capacitance
– SPEF
– Wire Load Models
– Pace Technology File
• Clock Definitions
PowerArtist can infer the clock trees for RTL or pre-CTS gate-level designs, and it can trace
existing clock trees for post-CTS gate-level designs. To infer a clock tree, you need to specify
the root clocks and clock buffers. To trace a clock tree, only root clock names are required.

4.4. Understanding the Analysis Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

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 Understanding the Analysis Tutorial Steps

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi VT, design, and library database:
pa_shell % source ./scripts/power_setup.tcl

7. Perform static efficiency checks:

pa_shell % source ./scripts/static_analysis.tcl

8. Perform simulation activity analysis for data and clocks:

pa_shell % source ./scripts/activity_analysis.tcl

9. Run Weighted Toggle Coverage:

pa_shell % source ./scripts/wtc.tcl

10. Perform average power calculation:

pa_shell % source ./scripts/average_power.tcl

11. Generate additional power reports:

pa_shell % source ./scripts/power_reports.tcl

12. Perform fast power profiling of the vector:

pa_shell % ./scripts/profile_power.tcl

13. Perform time-based power calculation:

pa_shell % source ./scripts/time_based_power.tcl

14. Exit PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single tcl
file (run.tcl):
% pa_shell -tcl run.tcl

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PowerArtist Tutorial Part I: Power Analysis

4.5. Understanding Power Analysis Setup

4.5.1. Running the Setup

Run 'setup.tcl' to create the required directories (such as log files, reports, and current working
directory) before running the analysis tutorial.

Go to 'scripts' and open 'setup.tcl'. An excerpt is shown here:

# Generic settings including directory creation

# Set up common design identifiers

set design top

# Set the variables for input and output directories

set LOG_DIR log
set RPT_DIR reports
set DB_DIR db
set WORK_DIR pa_shell_work

# Create the required output directories

if {![file exists $LOG_DIR]} {
exec mkdir $LOG_DIR
}
if {![file exists $RPT_DIR]} {
exec mkdir $RPT_DIR
}
if {![file exists $DB_DIR]} {
exec mkdir $DB_DIR
}
if {![file exists $WORK_DIR]} {
exec mkdir $WORK_DIR
}

Type 'pa_shell' to launch the PowerArtist shell and source 'setup.tcl' to create the required
directories:
pa_shell % source ./scripts/setup.tcl

4.5.2. Reading the Library Files

Use the 'ReadLibrary' command to specify the Liberty libraries (.libs) required to perform a power
estimation of your design. These include libraries for your memories, IOs, and the libraries needed to
synthesize the design.
ReadLibrary -name lib_<file_name>

You can also specify the '-synlib_files' option to the 'CalculatePower' or 'ReducePower'
commands.

The 'WriteLibraryDatabase' command compiles the specified Liberty library files and ALF library files
into a binary format. This reduces library reading time for downstream processes, such as elaboration,
reduction, and rewrite.

Go to 'scripts' and open 'libraries.tcl'. An excerpt is shown here:

# Specify the technology Libraries
ReadLibrary -name ../data/libraries/hvt.lib
ReadLibrary -name ../data/libraries/lvt.lib

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 Design Elaboration

ReadLibrary -name ../data/libraries/iopad.lib

ReadLibrary -name ../data/libraries/mem_DP256x32.lib
ReadLibrary -name ../data/libraries/mem_DP512x32.lib
ReadLibrary -name ../data/libraries/retention.lib

# Compile them into a binary library database

WriteLibraryDatabase \
-write_library_database_dir ./$DB_DIR/library_db \
-write_library_database_log ./$LOG_DIR/write_lib_db.log

Source 'libraries.tcl' to read the liberty files and create a library database:
pa_shell % source ./scripts/libraries.tcl

4.6. Design Elaboration

When you run the 'Elaborate' command, PowerArtist compiles and elaborates the RTL/gate-level design
and creates a scenario file based on the commands and options you specify. This scenario file is a binary
representation of the elaborated design. Once you generate the scenario file, you do not have to run
this step again unless there is a change in RTL.

• Before running the 'Elaborate' command, you need to specify the appropriate commands to compile
your Verilog and/or VHDL design files.

1. Since this is a mixed design with Verilog and VHDL, you can specify the VHDL libraries and files
by using the 'compile_vhdl.tcl' file:
source ./scripts/compile_vhdl.tcl

Go to 'scripts' and open 'compile_vhdl.tcl'. An excerpt is shown here:

# Compile the standard VHDL library files
CompileFile -type vhdl \-file $env(POWERARTIST_ROOT)/pthdl_src/standard_93.vhd \-93 yes -library STD
CompileFile -type vhdl -file $env(POWERARTIST_ROOT)/pthdl_src/std_1164.vhd \-93 yes -library IEEE
CompileFile -type vhdl -file $env(POWERARTIST_ROOT)/pthdl_src/syn_arit.vhd \-93 yes -library IEEE
CompileFile -type vhdl -file $env(POWERARTIST_ROOT)/pthdl_src/syn_unsi.vhd \-93 yes -library IEEE
...
...

# Compile VHDL file(s)

CompileFile -type vhdl -file ../data/design/rtl/fifocontrol.vhd -93 yes \-library WORK

2. You can specify the Verilog files through a start-up file (that contains a list of Verilog files) by
using the following option:
-verilog_startup_file <file_name>

• Specify the top-level module in your design by using the following option:
-top top_level_module_name

• Specify support for System Verilog by using the following option:

-system_verilog true

• Specify the name of scenario file to create by using the following option:

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PowerArtist Tutorial Part I: Power Analysis

-scenario_file <file_name>

• Specify the directory that contains the library database by using the following option:
-library_database_dirs <dir_name>

• Write and specify name of the power database (.pdb) by using the following options:
-elaborate_write_power_db true
-power_db_name db_name

• Specify the name for the log file for this elaboration run by using the following option:
-elaborate_log elaborate.log

Go to 'scripts' and open 'elaborate.tcl'. An excerpt is shown here:

# Elaborate the design

# Compile VHDL files

source ./scripts/compile_vhdl.tcl

Elaborate \
-top $design \
-verilog_startup_file ./input/txrx.vc \
-system_verilog true \
-library_database_dirs ./$DB_DIR/library_db \
-elaborate_write_power_db true \
-power_db_name ./$DB_DIR/elaborate.pdb \
-scenario_file ./$WORK_DIR/$design.scn \
-elaborate_log ./$LOG_DIR/elaborate.log

Source 'elaborate.tcl' to create a scenario file:

pa_shell % source ./scripts/elaborate.tcl

4.7. Common Setup for Clock Definitions

4.7.1. The ReadSDC Command

This command parses Synopsys Design Constraints (SDC) files, version 1.7, and generates a new
command file for use with PowerArtist. These commands are internally translated into 'SetStimulus'
commands. The 'ReadSDC' command generates the following three output files:

• ReadSDC.vaf - Defines the activity of the clock.

• ReadSDC.scr - Defines the clock gating style and other parameter(s).
• ReadSDC.log - Is the log file.

Go to 'scripts' and open 'read_sdc.tcl'. An excerpt is shown here:

# Import SDC
ReadSDC
-sdc_files ../data/sdc/${design}.sdc \
-power_db_name ./$DB_DIR/elaborate.pdb \
-sdc_clocks_gated true \
-sdc_clocks_mode infer \
-sdc_clocks_ecg true \

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 Common Setup for Clock Definitions

-sdc_out_file ./$WORK_DIR/ReadSDC.scr \
-vectorless_input_file ./$WORK_DIR/ReadSDC.vaf \
-sdc_log ./$LOG_DIR/read_sdc.log

source ./$WORK_DIR/ReadSDC.scr

Source 'read_sdc.tcl' to generate the files described above:

pa_shell % source ./scripts/read_sdc.tcl

4.7.2. Setup for Clock Tree and Clock Gate Inferencing

Before you run power analysis, define the clocks in your design.

• If you specify '-mode infer' you must specify root, branch, and leaf clock buffers for clock tree
inferencing using the 'SetClockBuffer' command:
SetClockBuffer -type (root | branch | leaf)
-name buffer_name -library library_name
-fanout buffer_fanout

Note: The library name you specify with the '-library' option is the logical library name that is
present in the '.lib' with library attribute.

• Use the 'SetClockGatingStyle' command to specify the clock gating cell to be used:
SetClockGatingStyle [-min_bit_width bit_width]
-clock_cell_attribute gating_cell_type
-gating_cells {lib_name:cell_name}

You need to specify the 'clock_gating_integrated_cell' attribute in the library with the
'-clock_cell_attribute' option. PowerArtist looks for it in the .lib to determine the clock
gating cell.

If 'clock_gating_integrated_cell' is present in the .lib as:

clock_gating_integrated_cell : "latch_posedge_precontrol";

then specify 'latch_posedge_precontrol' with the '-clock_cell_attribute' option.

You can explicitly select the clock gating cells using the '-gating_cells' option. If you use the
'-gating_cells' option, then the '-clock_cell_attribute' is optional.

• Similar to clock buffer inferencing, use the 'SetHighFanoutNet' command to infer buffer trees for
high fanout nets in the design:
SetHighFanoutNet -fanout max_signal_fanout
SetBuffer -type (root | branch | leaf) -name buffer_name \
-library library_name -fanout buffer_fanout

Go to 'scripts' and open 'power_setup.tcl'. An excerpt is shown here:

# Compiled design and library databases
pa_set scenario_file ./$WORK_DIR/$design.scn
pa_set library_database_dirs ./$DB_DIR/library_db

# Specify clock tree inferencing

SetClockBuffer -type root -name SEQCLKBUFX4MTH -library hvt -fanout 2

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PowerArtist Tutorial Part I: Power Analysis

SetClockBuffer -type branch -name SEQCLKBUFX8MTH -library hvt -fanout 4

SetClockBuffer -type leaf -name SEQCLKBUFX8MTH -library hvt -fanout 60

# Set up clock gate inferencing

SetClockGatingStyle -clock_cell_attribute latch_posedge_precontrol \
-min_bit_width 3 -min_bit_width_ecg 6

# Specify non-clock high fanout net buffer tree inferencing

SetHighFanoutNet -fanout 16
SetBuffer -type root -name SEQBUFX2MTH -library hvt -fanout 4
SetBuffer -type branch -name SEQBUFX2MTH -library hvt -fanout 8
SetBuffer -type leaf -name SEQBUFX2MTH -library hvt -fanout 16

Source 'power_setup.tcl' to set clock-related constraints and enable clock gating:

pa_shell % source ./scripts/power_setup.tcl

4.7.3. Setup for Capacitance Estimation

PowerArtist has numerous ways to estimate capacitances for your interconnect:

• Wire load models from your .libs

• SPEF files for a gate design extracted from the physical design
• PACE models
• A default wire load model shipped with PowerArtist

This tutorial uses wire load models. To use them, you need to specify some additional Tcl commands
and a few options specific to the 'CalculatePower' command.

• To specify the load on primary outputs, use the following option:

-default_output_load load_value

The capacitance unit is Farads.

• To specify the library containing wire load models, use the following option:
-wireload_library library_name

Note: You must specify the logical library name.

• To specify the wire load mode, use the following Tcl command:
SetWireLoadMode <top | enclosed>

The default setting for this command is 'enclosed'.

• If you specify the wire load mode as 'top', you must specify the wire load model using the following
command:
SetWireLoadModel [-name model_name] -instance inst_name(s) \
-library lib_name [-scaling_factor factor]

• In the absence of wire load models in the .libs, you can use the PowerArtist default wire load
models. You can scale these default wire load models with the following command:

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 Running Static Efficiency Checks

SetCapEstimation -technology technology_size [-scale scale_factor]

Go to 'scripts' and open 'power_setup.tcl'. An excerpt is shown here:

SetWireLoadModel -name cmos65_wl30 -library hvt -instance * -net *

4.7.4. Mixed-VT Setup

Mixed-VT libraries are used for most designs. To run a mixed-VT power analysis, do the following
setup before running the 'CalculatePower' command.

• Classify cells into different VT types. Cells are placed into different VT categories in the .lib using
the following attributes:
– At the library level: default_threshold_voltage_group : "string";
– At the cell level: threshold_voltage_group : "string";
The string value specifies the voltage threshold type. If the .libs do not contain these
attributes, you can categorize the cells using the 'SetVoltageThreshold' command:
SetVoltageThreshold -group threshold_group \ -pattern cell_pattern_list

• Specify the mixed-VT percentage for cell selection using the 'SetVT' command:
SetVT -mode percentage -instance {instance_list} -vt_group {threshold_group_list}

Go to 'scripts' and open 'power_setup.tcl'. An excerpt is shown here:

# Specify unique string pattern per threshold voltage library
SetVoltageThreshold -group LOW_VT -pattern {*L}
SetVoltageThreshold -group HIGH_VT -pattern {*H}

# Specify %VT utilization

SetVT -mode percentage -instance {top.core1.u1 top.core1.a1} \
-vt_group {LOW_VT:30 HIGH_VT:70}

Source 'power_setup.tcl' to specify mixed-VT libraries, threshold, and mixed-VT percentage for
cell selection:
pa_shell % source ./scripts/power_setup.tcl

Note: Multi-VT is not supported for high fanout and clock buffer modeling.

4.8. Running Static Efficiency Checks

The 'AnalyzeStaticEfficiency' command helps you identify clock gating and other RTL related design
inefficiencies early in the design flow before the vectors become available.

To run the 'AnalyzeStaticEfficiency' command you need to specify the scenario file, the log name and
the static pdb name to generate.

• To specify the scenario file, use the following option:

-scenario_file <scenario filename>

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PowerArtist Tutorial Part I: Power Analysis

• To specify the log file, use the following option:

-static_efficiency_log <log filename>

• To enable PDB generation, use the following option:

-static_efficiency_write_power_db <true | false>

• To specify the PDB name, use the following option:

-power_db_name <power db name>

Go to 'scripts' and open 'static_analysis.tcl'. An excerpt is shown here:

# Run static efficiency checks on the design
AnalyzeStaticEfficiency -scenario_file ./$WORK_DIR/$design.scn \
-static_efficiency_log ./$LOG_DIR/static_analysis.log \
-power_db_name ./$DB_DIR/static_analysis.pdb

openPDB ./$DB_DIR/static_analysis.pdb
source $env(POWERARTIST_ROOT)/utils/atcl/
atcl_generate_static_efficiency_report.tcl

atcl_generate_static_efficiency_report -out ./$RPT_DIR/static_analysis.rpt -detailed

Source 'static_analysis.tcl' to run the static efficiency checks and generate the report:
pa_shell % source ./scripts/static_analysis.tcl

Understanding the Static Efficiency Report

The file 'static_analysis.rpt' reports the static clock gating metrics of the design. It also reports
the summary of gated register checks such as enables with tied-high/tied-low, xor self-gating and enable
depth. The report also includes the memory clock gating summary and the input depth difference of
unregistered ALUs, which helps in identifying potential glitches.

An excerpt from 'static_analysis.rpt' is shown here:

1. Summary
======================
1.1 Register clock gating summary:
Total register count : 528
Count Percentage Category
------------------------------------
218 41.28 % Ungated register count
0 0.0 % Inferred & Instantiated gated register count
307 58.14 % Inferred only gated register count
3 0.56 % Inferred ECG only gated register count
0 0.0 % Instantiated only gated register count
1.2 Gated registers summary:
Count Percentage Category
------------------------------------
0 0.0 % Registers with tied-high clock enables
0 0.0 % Registers with tied-low clock enables
0 0.0 % Registers with xor-based self gating
0 0.0 % Registers with clock enable depth > 5
1.3 Memory clock gating summary :
Total memory instances : 20
Total memory clock ports : 40
Count Percentage Category
------------------------------------

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 Running Activity Analysis for Clock and Data

40 100.0 % Ungated memory clock ports

0 0.0 % Clock-gated memory clock ports
0 0.0 % Memory clock ports with ODC condition
1.4 Data path summary:
Count Percentage Category
------------------------------------
0 0.0 % Unregistered ALUs with input depth difference > 5

<snip>

4.9. Running Activity Analysis for Clock and Data

4.9.1. Vector Analysis

You should analyze your vectors before you use them for power analysis and reduction. Vector analysis
displays the activity in the design with respect to time. It helps identify the following:

• Whether or not the testbench is creating the expected activity.

• Whether or not there are any blocks that are active when they should be off. It helps to identify
power bugs.
• The optimal simulation time window that best represents the mode of operation you want to
analyze.

You can perform vector analysis in one of the following two modes:

• activity_per_cycle
• frequency_per_interval

Both modes are supported by the 'GenerateActivityWaveforms' command. In this tutorial, the
'frequency_per_interval' mode is used because the 'activity_per_cycle' mode requires
a free running clock.

Before you can run vector analysis, you need to:

• Define instance groups by using the 'DefineGroup' command:

DefineGroup group_name [hierarchical_instance_name(s)]

• Specify the category to automate the per-category monitoring of activity waveforms by using the
following option with the 'DefineGroup' command:
-category <category_name>

Each defined group generates a separate waveform in the output file (FSDB or PTCL).

Go to 'scripts' and open 'activity_analysis.tcl'. An excerpt is shown here:

# Perform Vector Analysis

# Define design groups for which activity analysis is to be performed

DefineGroup top { top }

DefineGroup top_register { top } -category register

DefineGroup top_clock { top } -category clock
DefineGroup top_memory { top } -category memory

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PowerArtist Tutorial Part I: Power Analysis

DefineGroup core { top.core1 }

DefineGroup pci { top.core1.p1 }
DefineGroup rxchan { top.core1.r1 }
DefineGroup txchan { top.core1.t1 }

As part of the 'GenerateActivityWaveforms' command, you need to specify activity files in the form
of VCD, gzipped VCD, or FSDB files. You also need to specify the '$scope' statement path to the
simulation testbench that corresponds to the top module you specified with the 'Elaborate' command.

• To specify the name of the activity file, use the following option:
-activity_file <activity_filename>

• To specify the hierarchical instance name of the top-level module in the activity file, use the
following option:
-top_instance top_instance_name

The average frequency over a specified interval mode allows you to trace the average frequency of
the design (or group of instances in the design) at every specified time interval. You must specify the
time value for the following options in units of 'fs', 'ps', 'ns', 'us' or 'ms'.

• Specify the groups, defined using the 'DefineGroup' command, for which you want to generate
activity waveforms using the following option:
-activity_waveform_group_list {group1 group2 group3 ...}

• Set the '-activity_waveform_graph_type' to 'frequency_per_interval':

-activity_waveform_graph_type frequency_per_interval

• Specify interval size using the following option:

-activity_waveform_interval_size <time>

• Specify number of intervals:

-activity_waveform_number_of_intervals <integer>

• Specify start time using the following option:

-activity_waveform_start_time <time>

While doing vector analysis, you can specify the form of the output:

• Use the following option to generate an output waveform in FSDB ('.fsdb') format:
-fsdb_output_file <file_name>.fsdb

• Use the following option to generate an output waveform in textual PTCL ('.ptcl') format:
-ptcl_output_file <file_name>.ptcl

• Use the following option to specify a name for the log file for vector analysis:

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 Running Activity Analysis for Clock and Data

-activity_waveform_log <file_name>.log

Go to 'scripts' and open 'activity_analysis.tcl'. An excerpt is shown here:

# Generate activity waveforms
GenerateActivityWaveforms \
-activity_file ../data/sim/rtl_analysis/top.fsdb \
-top_instance txrx_tst.top1
-activity_waveform_group_list { top top_register top_clock top_memory core pci rxchan txchan } \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_interval_size 15160ps \
-activity_waveform_number_of_intervals 400 \
-activity_waveform_start_time 6071580ps \
-fsdb_output_file ./$RPT_DIR/activity_waveform.fsdb \
-ptcl_output_file ./$RPT_DIR/activity_waveform.ptcl \
-activity_waveform_log ./$LOG_DIR/generate_activity_waveforms.log

Source 'activity_analysis.tcl' to perform vector analysis:

pa_shell % source ./scripts/activity_analysis.tcl

4.9.2. Generating and Viewing Waveforms

You can view the resulting waveforms from the vector analysis step through the PowerArtist GUI
waveform viewer. You have a choice of two formats: FSDB or PTCL.

If you specified the FSDB format ('CalculatePower -fsdb_output_file' option), you can load
and display the waveforms in the Waveform Viewer. To launch the Waveform Viewer, do the following:

1. Run PowerArtist on command line:

PowerArtist &

2. Select 'Tools > Waveform Viewer' and open the 'reports' folder. Then select
'activity_waveform.fsdb' from the 'Files' list on the right and click 'OK'.

Figure 4.1: Opening the PowerArtist Waveform Viewer

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PowerArtist Tutorial Part I: Power Analysis

3. In the 'Waveform Name' field, type an '*' to find all the waveforms and click the 'Search' button.

4. Next, select 'all' the waveform names, 'Place waveforms in: Individual Plots' and click the 'Add
waveform to plot area' button.

The resulting waveforms show the average activity over time for the specified groups.

Figure 4.2: Vector Analysis Waveforms for Each Specified Group (Individual Plots)

You can also select 'all' the waveform names, ' Place waveforms in: One Plot' and click the 'Add
waveform to plot area' button. The resulting waveforms are shown below:

Figure 4.3: Vector Analysis Waveforms for Each Specified Group (One Plot)

As you can see in the waveform, the module 'rxchan' has very little activity in the first half of the
simulation but then turns on. The reverse happens with the instance 'txchan'. This clearly indicates
that the tutorial design starts out transmitting packets of information and switches to receiving
packets.

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 Running Activity Analysis for Clock and Data

4.9.3. Flop Clock Activity Analysis

Flop Clock Activity (FCA) provides a measure of clock gating efficiency in your RTL design and monitors
the activity at the clock pins of registers. A low FCA number implies the clocks are well gated, whereas
a high FCA number indicates that clocks have not been well gated (due to either inefficient enables
or non-enabled registers) or the mode captured in the simulations required clocks to toggle. While
running average power analysis, you can do flop clock activity analysis using the
'CalculateFlopClockActivity' command.

You can specify a list of hierarchical instances that you want FCA to monitor using the
'MonitorToggleInstances' command as shown below:
MonitorToggleInstances -instances top.core1.t1
MonitorToggleInstances -instances top.core1.r1

As part of the 'CalculateFlopClockActivity' command, you need to specify the scenario file and
activity files in the form of VCD, gzipped VCD, or FSDB files.

• To specify the name of the activity file, use the following option:
-activity_file <activity_file_name>

• To specify the hierarchical instance name of the top-level module in the VCD/FSDB, use the
following option:
-top_instance top_instance_name

The average frequency over a specified interval mode allows you to trace the average frequency of
the design (or group of instances in the design) at every specified time interval. You must specify the
time value for the following options in units of 'fs', 'ps', 'ns', 'us' or 'ms'.

• To specify the start time, use the following option:

-start_time <time>

• To specify the finish time, use the following option:

-finish_time <time>

• To specify interval size as a number of clock cycles, use the following option:
-num_clock_cycles <integer>

• To specify the reference clock that controls when a clock starts and the length of its period,
use the following option:
-reference_clock <clock_name>

• To specify the name of the flop clock activity waveform output file in ptcl format, use the
following option:
-fca_ptcl_output_file <report_filename>

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PowerArtist Tutorial Part I: Power Analysis

• To generate textual report file ('.rpt'), flop clock activity ('.ptcl'), and average flop clock
activity graphs ('_avg.ptcl'), use the following option:
-fca_report_file <report_filename>

• To specify a name for the log file, use the following option:
-fca_log <filename>

Go to 'scripts' and open 'activity_analysis.tcl'. An excerpt is shown here:

# Define instances for which clock activity analysis is to be performed
MonitorToggleInstances -instances top.core1.t1
MonitorToggleInstances -instances top.core1.r1

CalculateFlopClockActivity \
-activity_file ../data/sim/rtl_analysis/top.fsdb \
-top_instance txrx_tst.top1 \
-start_time 6071580ps \
-finish_time 12135580ps \
-num_clock_cycles 20 \
-reference_clock top.clk \
-fca_ptcl_output_file reports/clock_activity_waveform.ptcl \
-fca_report_file ./$RPT_DIR/fca.rpt \
-fca_log ./$LOG_DIR/fca.log

Source 'activity_analysis.tcl' to perform flop clock activity analysis:

pa_shell % source ./scripts/activity_analysis.tcl

4.9.4. Flop Clock Activity Analysis Reports

The 'CalculateFlopClockActivity' command generates the following outputs:

• Waveforms of flop clock activity and average flop clock activity as a function of time.
• A text report, which includes minimum, maximum, and average counts of flops for which
clocks toggled during an interval expressed as a number and a percentage.

The following files are saved in the 'reports' directory:

• fca.rpt.txt

This is a text report that provides minimum/maximum/average statistics per clock domain per
specified instances. This is for both flop clock activity and average flop clock activity metrics
(see definitions below). The report includes both a number and a percentage as a function of
total flops. It also reports the total number of flops (bits) for each instance per clock-domain.

• clock_activity_waveform_avg.ptcl

This is a PTCL graph that shows averaged flop clock activity over time for all monitored clocks
and instances. The x-axis is the simulation time and the y-axis is the average clock activity for
the inferred register bits contained in that instance. This differs from 'fca.ptcl' because the
numbers in this file are derated by the total number of flops in the block.

• activity_waveform.ptcl

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 Running Weighted Toggle Coverage (WTC)

This PTCL graph shows activity over time for all the monitored instances defined with the
'DefineGroup' command.

• activity_waveform.fsdb

This FSDB graph shows activity over time for all the monitored instances defined with the
'DefineGroup' command.

Ansys recommends that you use the two PTCL graphs together to investigate any potential power
bugs. You can view the flop clock activity graphs, both the average flop clock activity graph (bottom)
and the absolute graph (top) through the Waveform Viewer by loading the '*.ptcl' files.

Figure 4.4: Average and Absolute Flock Clock Activity Analysis Waveform in PTCL Format
(One Plot)

Looking at the average flop clock activity (in the bottom graph), you can see that:

• The transmit clock domain 't1_top.clk' is active when the receive clock domain
'r1_top.clk' is inactive and vice-versa.
• The 'pci' clock domain 'top.pci_clk' is always on, indicating that this is a good candidate
for clock gating.

To determine whether you benefit from clock gating 'pci', you should check the absolute waveforms
(in the top graph). You can see that approximately 20 flops are clocked in the receive block
'ut0|top.core1.r1_top.pci_clk' and even more in the transmit block
'ut0|top.core1.t1_top.pci_clk'. This can indicate a power bug.

Source 'activity_analysis.tcl' a shown below:

pa_shell % source ./scripts/activity_analysis.tcl

4.10. Running Weighted Toggle Coverage (WTC)

The 'CalculateToggleCoverage' command generates the weighted toggle coverage metrics of all the
instances in the design. These metrics score the vector simulation vector quality relative to potential
power consumption of the design instances.

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PowerArtist Tutorial Part I: Power Analysis

To generate the coverage metrics, you need to provide the simulation file settings, type of coverage
analysis of interest and output files to be generated.

• To read the simulation file, use the following options:

-activity_file <fsdb file>
-top_instance <top instance name in fsdb>
-start_time <value>
-finish_time <value>

• To specify the coverage types, use the following option:

-coverage_type_list {max dynamic average}

Note: max, dynamic, and average are the available WTC calculation metrics.

• To specify the output reports and report format, use the following options:
-coverage_report_file <max/avg report>
-coverage_dynamic_report_file <dynamic report>
-coverage_fsdb_output_file <dynamic output fsdb>
-coverage_weight_report_file <weight report>
-coverage_report_format {csv text both}

• To specify the 'interval_size' for dynamic coverage analysis, use the following option:
-interval_size <value>

Go to 'scripts' and open 'wtc.tcl'. An excerpt is shown here:

# Weighted Toggle Coverage of the design
CalculateToggleCoverage \
-activity_file ../data/sim/rtl/top.fsdb \
-top_instance txrx_tst.top1 \
-start_time 6071580ps \
-finish_time 12135580ps \
-coverage_type_list {max dynamic average} \
-coverage_report_file ./$RPT_DIR/wtc_maxavg.rpt \
-coverage_dynamic_report_file ./$RPT_DIR/wtc_dynamic.rpt \
-coverage_fsdb_output_file ./$RPT_DIR/wtc_dynamic.fsdb \
-coverage_weight_report_file ./$RPT_DIR/wtc_weight.rpt \
-coverage_report_format {both} \
-interval_size 15.15e-9 \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-coverage_log ./$LOG_DIR/wtc.log

Source 'wtc.tcl' to run weighted toggle coverage and generate the corresponding reports:
pa_shell % source ./scripts/wtc.tcl

Understanding Weighted Toggle Coverage Reports

The following reports are generated that enable you to understand the coverage metrics:

• Weight Report

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 Running Weighted Toggle Coverage (WTC)

The 'wtc_weight.rpt.txt' reports the weight of all hierarchical and leaf instances in the
design. An excerpt from the weight report is shown here:
CELL WEIGHT(%) INSTANCE
============= ========
0.2374 TOP
0.00196127 top.sclk1
0.0019383 top.sclk2
0.000967999 top.sclk3
0.000941347 top.udo0
0.000941347 top.udo1
0.000941347 top.udo3
<snip>

• MAX and AVG Report

The 'wtc_maxavg.rpt' reports the 'max' and 'average' weighted toggle coverage metrics of
all the hierarchical and leaf instances in the design. This report has two sections:
– summary - The summary section has the top-level summary for different categories
(Register, Memory etc)
– detailed - The detailed section reports the metrics at the instance level.

An excerpt of both sections from this report is shown here:

• Dynamic WTC Report

The wtc_dynamic.rpt.txt has the dynamic WTC metrics for the instances in the design. If the
MonitorInstances command is specified, then only the top-level dynamic WTC metrics are reported.
An excerpt from the dynamic report is shown here:
Timeunit: 1e-12
Time Dynamic-GTC(%) Dynamic-ITC(%) Instance
==== ============= ============= ========
6086740.000000 31.6961 31.6961 TOP
6086740.000000 3.3823 15.317 top.core1.t1
6086740.000000 1.65471 7.51194 top.core1.r1
6086740.000000 0.000758828 20.7559 top.core1.t1.s1
6086740.000000 4.18842e-05 0.255037 top.core1.t1.d1
6086740.000000 0.0246748 47.7584 top.core1.t1.l1
6086740.000000 0.0100966 19.3141 top.core1.t1.f1
6086740.000000 0.0087302 50 top.core1.t1.p1
<snip>

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PowerArtist Tutorial Part I: Power Analysis

• ITC/GTC Waveform

The 'wtc_dynamic.fsdb' shown here displays the ITC/GTC waveform for all the intervals in
the simulation window:

4.11. Running Average Power Analysis

You can run PowerArtist for average power analysis on RTL, gate-level, and mixed RTL and gate designs.

• Large designs often have several operational modes, such as standby, receiving, and transmitting.
The power consumption for these modes will typically vary as different sections of the chip may be
inactive, or even powered down, in each mode.

You can use a mode description file to enter data or design-specific information that the tool uses
to perform multiple RTL power analyses corresponding to different operational modes of the design.
Use the following variable to specify the power mode(s) to analyze:
pa_set mode_file <mode_file_name>

• Use the following variables to specify the inputs related to simulation activity:
pa_set top_instance top_instance_name
pa_set activity_file <activity_file_name>

Go to 'scripts' and open 'average_power.tcl'. An excerpt is shown here:

# Calculate average power of the design

# Specify power modes to analyze

pa_set mode_file ./input/txrx.mode

# Inputs related to simulation activity

pa_set top_instance txrx_tst.top1
pa_set activity_file ../data/sim/rtl/top.fsdb

You can use the 'GenerateGAF' command for explicit control. This command also provides support for
multi-testbench control. The options used in this tutorial are explained below:

• To specify start and finish times for the simulation window for the average analysis, use the
following options:
-start_time <time>
-finish_time <time>

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 Running Average Power Analysis

• To specify the name of the gaf file, use the following option:
-gaf_file <gaf_filename>

• To compress the generated gaf file, use the following option:

-compress_gaf true

• To specify a name for the log file, use the following option:
-gaf_log <filename>

Go to 'scripts' and open 'average_power.tcl'. An excerpt is shown here:

# Process activity for average power calculation
GenerateGAF \
-start_time 6071580ps \
-finish_time 12135580ps \
-gaf_file ./$WORK_DIR/top.gaf \
-compress_gaf true \
-gaf_log ./$LOG_DIR/generate_gaf.log

You can use the 'CalculatePower' command for average power analysis. This command converts
simulation activity data into a global activity file (GAF), runs power analysis, and stores the information
in a power database ('.pdb' file). The GAF is an intermediate file generated when the activity file is
parsed. This allows you to run multiple power analysis and reductions without the runtime overhead
of parsing the simulation file again. The GAF file contains average frequency information for all named
nets and power arcs in the design. The options used in this tutorial are explained below:

• To run an average analysis, use the following option:

-analysis_type average

• To re-read an existing GAF stimulus file, use the following option:

-use_existing_gaf true

• To specify the name of the gaf file, use the following option:
-gaf_file gaf_<filename>

• To perform full scan insertion at RTL, use the following option:

-infer_scan_fanouts true

This is needed if the post-layout netlist has inserted scan chains and helps in better net
capacitance modeling at RTL.

• To set the default output load to the specified value, use the following option:
-default_output_load <float>

• To set the default transition time for any net for which slew is not specified, use the following
option:
-default_transition_time <float>

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• To set the default clock transition time, use the following option:
-default_clock_transition_time <double>

• To store clock trees in the database, use the following option:

-save_clock_trees_netlist true

• To specify the name of the power database (.pdb) file pointer, use the following option:
-power_db_name <pdb_filename>

• To specify a name for the log file, use the following option:
-calculate_log <filename>

During average power analysis, you can generate a text report file containing the results and clock tree
summary details, which are explained in subsequent sections.

• To specify the average power report file name, use the following option:
-average_report_file <report_filename>

• To control the output of the report file for average analysis, use the following option:
-average_report_options {options}

• To generate a detailed vertical power report, use the following option:

-detailed_vertical_report true

• To generate a vertical report that provides summary information for the specified list of instances,
use the following option:
-vertical_report_instances {inst1 inst2 ...}

• To generate a cell selection report that helps achieve more accurate power results by analyzing
the cell type used for power analysis, use the following option:
-cell_selection_report <report_filename>

Go to 'scripts' and open 'average_power.tcl'. An excerpt is shown here:

# Calculate average power
CalculatePower -analysis_type average \
-use_existing_gaf true \
-gaf_file ./$WORK_DIR/@design.gaf \
-infer_scan_fanouts true \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-average_report_file ./$RPT_DIR/average_power.rpt \
-average_report_options agip \
-detailed_vertical_report true \
-vertical_report_instances $design \
-cell_selection_report ./$RPT_DIR/$design.cells.rpt \
-power_db_name ./$DB_DIR/average_power.pdb \

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 Running Fast Power Profiling

-save_clock_trees_netlist true \
-calculate_log ./$LOG_DIR/average_power.log

Source 'average_power.tcl' to run average power analysis and generate the associated reports:
pa_shell % source ./scripts/average_power.tcl

4.12. Generating Additional Power Reports

In addition to standard text reports, you can generate additional power reports. These reports are
generated by accessing the power database (generated during power analysis) using APSH container
commands. These reports contain top-level power summary, design statistics, and clock gating efficiency
information, and are explained in detail in the Generating Power Reports from the Power Database (p. 63)
section.

Go to 'scripts' and open 'power_reports.tcl'. An excerpt is shown here:

# Generating top-level power summary, design statistics, and clock gating
effficiency reports

openPDB ./$DB_DIR/average_power.pdb
reportPower -show_ibp -levels 2 -unit mW -out ./$RPT_DIR/reportPower.rpt
reportSummary -out ./$RPT_DIR/reportSummary.rpt
reportCGEfficiency -sort_by clock_power -out ./$RPT_DIR/reportCGEfficiency.rpt
closePDB

Source 'power_reports.tcl' to generate the additional reports:

pa_shell % source ./scripts/power_reports.tcl

4.13. Running Fast Power Profiling

ProfilePower helps you generate the power profile for long simulation vectors 100-1000X faster than
cycle-accurate time-based power. The fast power profiling can be used to identify power and thermal
critical time windows for real application scenarios.

To run the 'ProfilePower' command, you need to provide the averaging window, the output fsdb to
generate, the log file, the text report, and the interval size.

• To specify the averaging window, use the following option:

-profile_averaging_window <integer%>

• To specify the text report, use the following option:

-profile_text_file <text reportname>

• To specify the log file, use the following option:

-profile_log_file <log filename>

• To set the interval size to the number of clock cycles, use the following option:
-profile_num_clock_cycles <integer>

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PowerArtist Tutorial Part I: Power Analysis

• To specify the output fsdb file, specify the following option:

-profile_fsdb_file <fsdb filename>

Go to 'scripts' and open 'profile_power.tcl'. An excerpt is shown here:

# Run fast power profiling
ProfilePower \
-profile_averaging_window 5% \
-profile_text_file ./$RPT_DIR/profile_power.rpt \
-profile_log_file ./$LOG_DIR/profile_power.log \
-profile_num_clock_cycles 1 \
-profile_fsdb_file ./$DB_DIR/profile_power.fsdb

Source 'profile_power.tcl' to run power profiling and generate the associated reports:
pa_shell % source ./scripts/profile_power.tcl

Understanding Power Profiles

You can view the power profile by loading the 'profile_power.fsdb' in Signal Viewer. The following
power profile waveform is generated:

In this figure, the waveform in red is the average waveform calculated with the '5%' averaging window.
The duration is for the entire simulation window, which is '19us'.

4.14. Running Time-Based Power Analysis

Time-based power analysis allows you to obtain power waveforms as a function of time for RTL, gate-level,
or mixed RTL and gate designs. You can run PowerArtist time-based power analysis by using the
'CalculatePower -analysis_type time_based' command. The command can generate current
and power-over-time waveforms for the categories and instances that you specified using the
'MonitorInstances' command.

When performing a time-based power analysis, ensure that the '-start_time' and '-finish_time'
options are set to be the leading edge of a clock and the trailing edge of a clock, respectively. You also

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 Running Time-Based Power Analysis

need to select the interval size used by your analysis. This is controlled by the '-reference_clock'
and '-num_clock_cycles' options.

• To set the interval size as a number of clock cycles, use the following option:
-num_clock_cycles <integer>

• To specify the reference clock that controls when a clock starts and the length of its period, use
the following option:
-reference_clock <clock_name>

• To specify the edge of the clock that defines the start point for the first interval, use the following
option:
-active_edge <auto | positive | negative>

During time-based power analysis, you can generate text-based power reports and waveforms in either
the FSDB format or PowerArtist Tcl (ptcl) format, which is explained in subsequent sections.

• To specify the time-based power text report file name, use the following option:
-time_based_report_file <report_filename>

• To save the power-over-time waveforms in ptcl format, use the following option:
-ptcl_output_file <filename>

• To save the power-over-time waveforms in fsdb format, use the following option:
-fsdb_output_file <filename>

Note: The explanation of the options common to 'average' and 'time-based' power analysis are
not repeated.

Go to 'scripts' and open 'time_based_power.tcl'. An excerpt is shown here:

# Run time-based power analysis

# Specify hierarchical instances to generate power waveforms for

MonitorInstances -name top.core1.t1 -all 1 -group {Register Memory Clock Other} \
-monitor_dynamic_trace true -monitor_static_trace true
MonitorInstances -name top.core1.r1 -all 1 -group {Register Memory Clock Other} \
-monitor_dynamic_trace true -monitor_static_trace true

# Calculate time-based power

CalculatePower -analysis_type time_based \
-activity_file ../data/sim/rtl_analysis/top.fsdb \
-top_instance txrx_tst.top1 \
-start_time 6071580ps \
-finish_time 12135580ps \
-num_clock_cycles 20 \
-reference_clock top.clk \
-active_edge positive \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-power_db_name ./$DB_DIR/time_based_power.pdb \
-time_based_report_file ./$RPT_DIR/time_based_power.rpt \
-ptcl_output_file ./$RPT_DIR/time_based_power.ptcl \

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-fsdb_output_file ./$RPT_DIR/time_based_power.fsdb \
-calculate_log ./$LOG_DIR/time_based_power.log

Source 'time_based_power.tcl' to do time-based power analysis and generate the reports:

pa_shell % source ./scripts/time_based_power.tcl

4.14.1. Running Fast Time-based Power Analysis

Time-based power analysis computes accurate power consumption profiles over the time window
specified in the switching activities of a design. Resulting profiles are true representations of the end
usage of the device and are essential to identifying peak power consumption, exploring optimization
opportunities, and ensuring power grid integrity. However, time-based analysis is compute-intensive
specially when simulating multi-billion cycle real-life switching activities became necessary for
application level, transient thermal, or side channel attack analysis and becomes infeasible to run
because of its long run time.

To address these challenges, PowerArtist facilitates 'Fast Time-based Analysis', which provides a run
time speedup of many orders of magnitude over traditional time-based power analysis while keeping
cycle accurate power numbers within a small delta. These faster run times once again enable you to:

• Identify multiple power windows

• Identify power waveforms
• Identify peak IR drop scenarios
• Identify power windows for reduction
• Perform cycle-based power waste and clock efficiency checks

Fast Time-based Analysis (FTBA) is an enhanced version of the default time-based analysis. The FTBA
workflow exhibits up to 200X faster performance in generating power waveforms for long vectors.
The tool also supports hierarchical time-based power profiling.

In addition to the FSDB flow, FTBA is enhanced to support the following emulator flows:

• ZeBu flow
• Virtual FSDB flow

The use model for RTL time-based power analysis remains unchanged, and the tool accepts the
following additional inputs for fast time-based power analysis:

• Ensure that the Verdi environment variable 'VERDI_HOME' points to your Verdi installation
path.
• To enable fast time-based analysis, use the following command:
pa_set enable_fast_tba true

By default, the fast time-based analysis runs for the top instance.
• (Optional) To enable hierarchical fast time-based analysis, use the following command:
pa set enable_hier_fast_tba true

The following shows a sample usage script for FTBA flow:

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 Viewing Power Analysis Results in the PowerArtist Graphical Interface

# fast tba
set flow ftba
pa_set top TOP
pa_set enable_fast_tba true
pa_set reference_clock top.clk
pa_set top_instance txrx_tst.top1
pa_set activity_file ../data/sim/rtl/top.fsdb
pa_set start_time 30ns
pa_set finish_time 1.8ms
pa_set num_clock_cycles 1
pa_set active_edge positive
pa_set default_output_load 1epa_set 15
pa_set default_transition_time 50e-12
pa_set default_clock_transition_time 20e-12
pa_set time_based_report_file ./$RPT_DIR/${flow}.rpt
pa_set fsdb_output_file ./$RPT_DIR/${flow}.fsdb
pa_set calculate_log ./$LOG_DIR/${flow}.log
pa_set analysis_type time_based
CalculatePower

The reports generated and PDB-based queries available in regular time-based power analysis are also
generated and available in fast time-based power analysis.

4.15. Viewing Power Analysis Results in the PowerArtist Graphical

Interface
Once you have run any power analysis (average or time-based) you can view those results in PowerArtist
GUI.

1. Load the power database named 'average_power.pdb' that was created by the
'average_power.tcl' script.

2. To see the power results in the hierarchy browser, select 'Design > Hierarchy > Colorize by
> Power'. You can also color the power table by selecting Design > Power Table > Colorize
by > Power.

The hierarchy browser now shows the design colored by power as shown in the following
figure:

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Figure 4.5: Display of average_power.pdb (Average Power Analysis Results)

The colorizing follows a thermal spectrum. The more power consumed, the hotter the color
(red indicating the most power consumed). The less power consumed, the cooler the tab. The
hierarchy browser is not colored, by default.

Manipulating Your Design in the Schematic

This section gives you a basic understanding of how to probe your design using the schematic view.
Once you have a basic understanding, you can experiment with your own design.

1. From the hierarchy browser, click 't1(txchan)' then right-click and select 'Show in Schematic'.

The 't1' instance displays in the schematic.

2. Use the '+' and '-' keys to zoom (or do a press-drag-release to zoom) around 't1', as shown in the
following figure:

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 Viewing Power Analysis Results in the PowerArtist Graphical Interface

Figure 4.6: Schematic Display of Module Selected in the Hierarchy

3. Dynamic information is displayed just above the schematic. This display changes as you move your
cursor over the elements in the schematic. This display includes information such as instance name,
cell name, parent, static/dynamic/total power, clock gating status, and optimization status. From
this figure, you can see that instance 't1' consumes a total of '11.42 mW' of power.

4. Do 'shift + double-click' the border of 't1' to show a detailed view of its schematic.

5. Do 'shift + double-click' again to return to a view that only shows the primary ports.

If you zoom-in, you can see that the port stubs for single-bit pins are thinner than the port stubs
for bus ports.

6. Double-click the bus port stub for 'din[63:0]'.

7. Click the wire coming from this port that is on the outside of the instance boundary and select
'Schematic > Show Properties' or right-click and select 'Show Properties'.

8. To see all the nets, click the '+' sign next to the 'txdin' pin name.

The Properties dialog appears as shown in the following figure:

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Figure 4.7: Properties Dialog for Net txdin

This dialog displays the frequency, capacitance source, transition time, and average activity for each
net in the bus. After launching this dialog, if you click different areas in the schematic, the dialog is
updated accordingly. You can use this dialog to view net information for both single-bit ports and
bus ports.

You can also add tabs to this dialog to display other pins, nets, or instances by clicking on the blue
' +' button on the upper left corner of the Properties dialog.

4.16. Understanding Power Analysis through Text Reports

In addition to reviewing the power analysis results in the PowerArtist GUI, you can also review the
results using text-based power report(s). You can generate:

• Standard Text Reports

Both the average and time-based reports are divided into sections. Every section provides valuable
information about the power analysis of your design. At the top of the report are the date and
program version, along with values for numerous arguments and parameters.

• Power Reports

These reports are generated by accessing the power database using APSH container commands.
The power database is generated during power analysis.

4.16.1. Average Power Analysis Report

This section describes the average power report 'average_power.rpt' generated after running
the analysis tutorial created in the 'reports' directory.

4.16.1.1. Total Power Consumption

The first section is an abstract of total power dissipation, divided into components of internal power,
pad power, clock power, and inferred buffer power.

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1. Total power consumption

==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 15.8uW 3.85mW 3.87mW
Internal latch power 0W 0W 0W
Internal memory power 3.81mW 15.9mW 19.7mW
Other internal power 22.6uW 349uW 372uW
Total internal power 3.84mW 20.1mW 24mW
Pad power 42.8uW 0W 43.3uW
Clock power 634nW 1.02mW 1.02mW
Inferred Buffer power 115nW 13.4mW 13.5mW

Total power 3.89mW 21.1mW 25mW

<snip>

The categories reported in this section are explained in greater detail in sections that follow.

4.16.1.2. Total Power per Supply

The second section reports the total power per supply:
2. Total power per supply
==========================
Estimation Library Power(Watts)
Supply Voltage(V) Voltage(V) Static Dynamic Total
------ ---------- ---------- ------ ------- -----
DP256x32.VDD 1.1 1.1 1.2mW 9.63mW 10.8mW
Estimation Voltage Source = library power_supply
Library Voltage Source = library power_supply
DP512x32.VDD 1.1 1.1 2.61mW 6.27mW 8.88mW
Estimation Voltage Source = library power_supply
Library Voltage Source = library power_supply
...
...
...
lvt.vdd 1.1 1.1 30.5uW 367uW 397uW
Estimation Voltage Source = default_operating_condition (lvt)
Library Voltage Source = nom_voltage
Total power 3.89mW 21.1mW 25mW
<snip>

4.16.1.3. Internal Power Consumption

The next section of the power report shows the details of the internal power consumption.
3. Internal power consumption
=============================

Note: (G) after either a register or 2-1 mux means this instance is affected
by clock gating.
Note: (F) after model name means power of this instance has been forced by
using SetPower command.
Note: (O) after model name means this instance has been partially/fully
optimized.
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top user 3.84mW 20.1mW 24mW
#b0 connect 0W 0W 0W
#b1 connect 0W 0W 0W
#b2 auto 0W 0W 0W
core1 user 3.84mW 20.1mW 24mW

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#b0 connect 0W 0W 0W
...
Total internal power 3.84mW 20.1mW 24mW
<snip>

In the report, fully or partially optimized instances are marked with an '(O)' after the model name.
This is similar to gated logic marked with a '(G)' and logic with power set by the 'SetPower'
command marked with an '(F)'.

And for each module, this report provides several pieces of information:

• The hierarchical name of the HDL component.

• The power model associated with the HDL object.
• The power consumed by that object.

Using the frequency values computed for the ports and the type of power model associated with
the object, PowerArtist can accurately estimate the power consumed by the object.

Among other options, PowerArtist reports enable you to separate static and dynamic power
estimates. The static power is generally independent of the frequency of the object, although for
some modules, such as memories, the static power can depend on the value of control signals,
such as chip select. For example, a ROM can consume a certain amount of static power when active,
and a smaller amount of power in standby mode. PowerArtist computes the amount of time the
ROM is in each mode, and determines the static power based on these modes.

4.16.1.4. Instance Average Power Consumption

Simulation-based average power analysis is enhanced to report detailed instance power file. In
addition to instance name, cell name, and category, the new report also provides computation to
instance power file, static power computations for each supply, and dynamic power computations
for each supply with distinctive breakdown on switching and internal power.

The pa_set, power_debug_report_instances {list_of_instances}, variable reports

detailed static and dynamic power computations of one or more instances.

This is available for all flows under Simulation-Based Average Power Analysis and Power Reduction
enabled by the following command:
CalculatePower -analysis_type average
ReducePower

Specify the new pa_set to report per instance power calculation details in CalculatePower
command:
pa_set power_debug_report_instances {list_of_instances}

You can provide a single instance, or a list of instances. The report prints details for a maximum of
five instances at once.

You can also include the wildcard characters '*', '?', and '[]'. The following snippet shows a set of
valid wildcard entries:
*, top.*, top.core1.*, top.*.#r0

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 Understanding Power Analysis through Text Reports

Outputs
The following snippet shows the report file generated when pa_set
power_debug_report_instances is enabled for specified instance(s):

The report file contains breakup of static and dynamic power for each instance(s) specified
under the pa_set.

The following section describes the file and format details of the report:

• Instance Power File Details

The following shows an example of power file details:

– Instance Name: <string>
Instances specified through the pa_set power_debug_report_instances.
– Cell Name: AND21
The cell name can be derived from instantiated instances, whereas for inferred
instances, the tool uses internal API to get a mapped cell name.
– Category: <same as cell type>
This property is same as cell type, for example, pad, latch, or register.
– Liberty Path: <logical Library name>
Library path is available through libraryLogicalName.

• File Formats of Different Types of Instances

The following snippet shows different file formats for different types of instances:

– Macro instances:
Instance Name: top.core1.#a0 [top.core1.#a0.#c1.or1_1_0]
Lib_name: hvt.lib
Cell_name: CELL_OR

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Instance Type: Adder [OR] <Parent [Child]>

Total Power: Total_Power [power_of_child_instance]

– Vectored instances:
Instance Name: top.core1.#r0 [Index:0, Net: top.core1.net1]
Lib_name: hvt.lib
Cell_name: SDFF_CELL
Instance Type: Register
Total Power: Total_Power [power_of_index0_register_bit]

– MBFF instances:
Instance Name: top.core1.#r0 [Index:0, Net: top.core1.net1]
Lib_name: hvt.lib
Cell_name: SDFF_CELL
Instance Type: Register
Total Power: Total_Power [power_of_index0_register_bit]

– Vectored instance MBF

Instance Name: top.core1.#r0 [Index:2-5, Net: top.core1.net2, top.core1.net3,..., net5]
Lib_name: hvt.lib
Cell_name: MBFF4_CELL
Instance Type: Register
Total Power: Total_Power [power_of_MBFF_register_bits]

Limitations
This version of the feature has the following limitations:

• This feature is available only for Simulation-Based Average Power Analysis and Power
Reduction flow. Time based flow has limitations for this report as printing interval-wise power
data is not feasible.

• If five or more than five instances are specified under the pa_set
power_debug_report_instances {list_of_instances}, the tool reports details
for the first five instances. The following user message is reported:
Note 999: pa_set 'power_debug_report_instances' supports generating power
debug data for maximum five instances. Other instances, if provided,
will be ignored.

• Some instances in the report file may show internal or static power different from power
database (.pdb). Static power mismatches could be observed for registers and mux21 type
of instances and internal power mismatches could be observed for a few combinational
instances.

4.16.1.5. Pad Power Consumption

This section of the report shows the power consumed by each pad instantiated in your design:
4. Pad power consumption
========================
Power(Watts)
Component Pad type Cap(F) Static Dynamic Total
--------- --- ---- ------ ------ ------- -----
top.udi0 SEQPIC 155fF 151nW 0W 151nW
top.udi1 SEQPIC 31.3fF 151nW 0W 151nW

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 Understanding Power Analysis through Text Reports

top.udi2 SEQPIC 0F 151nW 0W 151nW

top.udi3 SEQPIC 31.3fF 151nW 0W 151nW
...
Total pad power 42.8uW 0W 42.8uW
<snip>

For each I/O pad, several pieces of information is reported:

• The hierarchical name of the pad in the HDL design.

• The name of the pad model in the chosen technology for that pad.
• The power consumed by that pad.
• The load capacitance attached to the output of the pad.

Power consumed by pads is often a significant fraction of total power and PowerArtist uses specific
models for each pad in a technology to accurately estimate the power. Power is estimated using
the frequency value for the output net, parameters of the pad, and a user-provided value for the
off-chip capacitance driven by the net if it is an output.

4.16.1.6. Mixed-VT Cells Distribution

This section of the text power report shows the distribution of the Mixed-VT cells in the design:
5. Mixed-VT Cells Distribution
==============================
Hier-Instance VT Group Specified Number of Cells
Name Name Percentage Selected
------------- -------- ---------- ---------------

top.core1.u1
HIGH_VT 70 99
LOW_VT 30 43
---------------
Total 142
top.core1.a1
HIGH_VT 70 29
LOW_VT 30 12
---------------
Total 41
top.core1.s1
HIGH_VT 70 424
LOW_VT 30 179
---------------
Total 603
<snip>

4.16.1.7. Clock Power Consumption

This section of the power report shows the power consumed by each clock net. Details about clock
gating prediction and clock tree inferencing are included in this clock power report section:
6. Clock power consumption
==========================

Note: * after a number means this value is user specified.

(L) after an instance level means the instance drives a clock pin of
a sequential device.
(r) after an instance name means the instance is multi-vectored, and
has already been included in the clock path via a different bit.
(ECG) after an output net name means its driver register instance is
enhanced clock gated.

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Power (Watts)
Net Type Static Dynamic Total
--- ---- ------ ------- -----
top.Pclk ( clk ) Inferred 1.4uW 352uW 353uW

Net properties:
Area : 8.10e-09
Senses : 1
Frequency : 63.2MHz
Transition time : 20ps*
Fanout capacitance : 0F, clock net is a primary input
Wire/Pin Power : 0W, clock net is a primary input

Wireload models used:

top.Pclk ( clk ) : cmos65_wl30
top.Pclk ( clk ) : cmos65_wl30
<snip>

For each clock net, the following information is provided:

• The hierarchical net name, the type of analysis, and the total power for the clock tree. The
analysis type is 'Instantiated' (it was traced) or 'Inferred' (clock inferencing was done).
• Area occupied by the net.
• Clock senses.
• Frequency of the clock net.
• Transition Time.
• Fanout capacitance of the clock net (split into contributions from wire and pin capacitances).
• Power consumed as the net toggles (split by wire and pin components).
• The wire load model applied to the net (the first entry is the net name, the second entry is
the wire load model applied to that net). If you assigned wire load models to sub-nets of
the clock tree, they are also listed here.
• Descriptions of the instances that are traced as part of the clock tree, which includes the
following:
– Library Model: the Liberty model name.
– Clock Level: the depth in the clock tree for this particular instance
– Driven Net Numbers: the net numbers from the 'Traced nets' section that this instance
drives. Most instances drive one net, but some instances may drive multiple nets. The
power section is split into 'static', 'dynamic', and 'total' just like in the 'Internal Power
Consumption' section of this report.
– Driven by Net Number: the net number that is traced through to get to this particular
instance.
Note: The 'Driven by' net may have Index 0. This means that this is the clock net you
are inferring or tracing.
– Driven Loads: the number of loads this particular instance is driving.
– Traced Instance the full hierarchical instance name (listed last to accommodate a
long name).
Note: If the instance is a leaf buffer that is driving only clock pins, it is marked with
an '(L)' in the 'Clock Level' column.
• Descriptions of each clock net in the design. This section lists every net in the clock tree and
contains the following fields:
– Net Number: this number allows you to figure out the instance driving this net.
– Frequency: the toggling frequency of this net.

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– Transition Time: the slew time either back-annotated or calculated by the slew calculator,
the back annotated slew values are annotated with an asterisk. The power portion is split
into 'Pin Power' and 'Wire Power'.
– Wire Capacitance: capacitance determine from a wire load model or a back-annotated
value. In the case of a back-annotated value, the number is annotated with an asterisk to
indicate that it was a user-specified value.
– Pin Cap: the total capacitance of the pins driven by this net.
– Net Wire Power and Net Pin Power : the total power split into pin and wire amounts
– Net: the full hierarchical instance name for this net.

4.16.1.8. Controlling the Clock Tracing Order

The order in which clocks are traced does not impact power calculation, but it does impact how
the power is associated with a particular clock. The contents of the clock power section in the
power analysis reports depends completely on the order in which clocks are traced. The order in
which you specify your clock nets in the clock file and if you specify the '-frequency' option to
the 'SetClockNet' command completely control the order in which nets are traced in a predictable
fashion.

Clock tracing depends only on the order of the clock commands even if frequency is specified,
though you can override this by using the '-frequency_dependent_clock_tracing' option.
This happens even if some clocks have frequency and some do not.

You can optionally honor the duty cycle of the clock multiplexer (mux) select pin and determine
the input clock that is traced to the mux output. The mux and downstream logic are accounted in
the power of the clock that gets traced through the mux.

4.16.1.9. Additional Information on Clock Gating

If you performed clock gating, the following additional information is included in the clock power
report.

• All output nets of clock-gated registers are listed in a separate row.

• For each clock-gating cell, the cell type, enable signal, and duty percentage are listed.
• For each clock-gating cell, the static, dynamic, and total power usage is reported.

Additionally, there is a separate section called 'Clock Gating Summary' for every clock and for the
entire design at the end of the 'Clock power consumption' section of the report. See the following
sample:
<snip>
Clock Gating Summary:
---------------------
Clock net: top.Ppci_clk
Number of inferred clock gating cells: 10
Number of registers gated by inferred clock gating cells: 376
Number of registers enhanced gated by inferred clock gating cells: 0
Number of instantiated clock gating cells: 0
Number of registers gated by instantiated clock gating cells: 0
Total number of gated registers: 376
Total number of ungated registers: 76
...
...
Clock Gating Summary:
---------------------

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Instance: top
Number of inferred clock gating cells: 13
Number of registers gated by inferred clock gating cells: 464
Number of instantiated clock gating cells: 0
Number of registers gated by instantiated clock gating cells: 0
Total number of gated registers: 464
Total number of ungated registers: 229
<snip>

Notes:

• The counts are the total number of register bits and not the number of register instances
(where an entire register bank is one instance).

• The sum of 'Number of gated registers' and 'Number of registers gated by instantiated clock
gating cells' may not be equal to the 'Total number of gated registers'. This is because a register
may have a block-level instantiated clock gate and a local inferred clock gate.

• The 'Total number of gated registers' row includes registers that are gated by inferred clock
gates, instantiated clock gates, or both.

• The 'Total number of ungated registers' row includes those registers that are not gated by
either inferred or instantiated clock gates.

For more information on clock gating, see section 'Setting up Clock Gating for Power Analysis (p. 190)'.

4.16.1.10. Inferred Buffer Tree Power

This section describes the buffer inferencing that happens when a net exceeds the number of
fanouts specified by the 'SetMaxFanout' command. The report format is similar to the clock buffer
section of the report. For each inferred buffer tree, the following information is supplied:

• Name of the net with a fanout that exceeds the limit specified by the 'SetMaxFanout'
command.
• The hierarchical instance being driven by the net.
• The frequency of the net toggles.
• The number of loads.
• A description of the fanout tree. This includes the cells that were used to build up the buffer
tree, the library the cells came from, the counts of the cells, fanout limitations of the cells,
and the power consumed by the cells. The capacitance in the buffer tree is also supplied
because it controls the number of cells inferred.
7. Inferred buffer tree power
=============================
Total dynamic power = 13.4uW
Total static power = 115nW

Inferred Buffer Tree:

Net name : top.core1.r1.f1.wr_ptr[8]
Driver instance: top.core1.r1.f1.wrcntr.wr_ptr(#r0)
Frequency : 0Hz
Number of Loads: 74
Leaf Driver :
Cell : SEQBUFX2MTH
Library : hvt
Count : 5
Cell maximum fanout : 16
Buffer power: static 6.61nW; dynamic 0W

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 Understanding Power Analysis through Text Reports

Fanout capacitance: wire 2.22pF; pins 97.2fF

Total capacitance : wire 2.22pF; pins 97.2fF

<snip>

4.16.1.11. Power Summary for Enable Level Shifter Cells

The tool reports Isolation Power Summary, LevelShifter Power Summary and Combined Isolation
and LevelShifter Power Summary in the text report.

The following snippet shows a sample report:

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4.16.1.12. Area
This section reports the width, height, and number of registers and gates for each component. This
section of the report is generated if you use '-average_report_options a' with
'CalculatePower':
8. Area
=======

Component Width Height Regs Gates

--------- ----- ------ ---- -----
top 1.98K 1.98K 693 3070817
core1 1.98K 1.98K 693 3070817
a1 7.16 7.16 0 45
<snip>
Total Counts 693 3070783
Total Internal Area 3.93M
Total Pad Area 2.32M
Total IP core Area 0
Total Clock Tree Area 243
Total Inferred Buffer Tree Area 120
Total Net Routing Area 1.05M

Total Area (Gates+Routing) 7.31M

<snip>

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 Understanding Power Analysis through Text Reports

4.16.1.13. Net Frequencies

This section reports the type, glitch, and frequency for each net. This section of the report is
generated if you use '-average_report_options g' with 'CalculatePower':
9. Net frequencies
==================

Net Type Glitch Frequency

--- ---- ------ ---------
top.Pclk PI 0.00% 63.2MHz
top.Pnreset PI 0.00% 0Hz
top.Pcs PI 0.00% 0Hz
top.Prd PI 0.00% 0Hz
<snip>

4.16.1.14. Power Consumption by Model/Gate Type

This section provides summary information for every type of instance in the design. This section
of the report is generated if you use the '-vertical_report_instances' and
'-detailed_vertical_report' options with 'CalculatePower'.

For inferred elements, the cell count equals the number of separate instances in the design and
not the total bit width for bundled elements like registers and muxes. For vendor_gates, the cell
count is the number of gates of that type in the design.

This section reports the pins of the RTL instances that exist in the design after netlist optimizations.
Optimized logic is not included. Additionally, for RTL instances, such as registers or multiplexers,
all the bits in the vectored/bundled instance are reported. The numbers match the numbers obtained
from the Cell Selection Report (p. 62) or the reports based on the power database (p. 63) (pdb):
10. Power consumption by model/gate type
========================================

Power(Watts)
Component Model Cell Static Dynamic Total
Count
--------- ----- ------ ------- ------- -----
top 1906 3.89mW 21.1mW 25mW
Register Power 30 15.8uW 3.85mW 3.87mW

Latch Power 0 0W 0W 0W

Memory Power 20 3.81mW 15.9mW 19.7mW

Other Power 1403 22.6uW 280uW 303uW

Pad Power 284 42.8uW 0W 42.8uW

Clock Power 75 634nW 1.09mW 1.09mW

Inferred Buffer Power 94 115nW 13.4uW 13.5uW

DP256x32 8 1.2mW 9.63mW 10.8mW

DP512x32 12 2.61mW 6.27mW 8.88mW
SEQPIC 150 22.6uW 0W 22.6uW
<snip>

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PowerArtist Tutorial Part I: Power Analysis

4.16.2. Cell Selection Report

The report 'top.cells.rpt' provides a list of technology library cells that PowerArtist maps for
RTL power estimation and helps you to identify similar cells used in the gate-level netlist.

In order to achieve more accurate power results by analyzing the cell type used for power analysis,
PowerArtist generates a cell selection report. The report provides a list of technology library cells that
PowerArtist maps for RTL power estimation and helps you to identify similar cells used in the gate-level
netlist.

The report contains a summary of:

• Inferred netlists
• Inferred clock tree and net buffer tree
• Inferred clock gates
• Instantiated netlist elements

A sample is shown below:

Cell VT Group Function Class Occurrence

1. Cell summary of inferred netlist elements.

SEQINVX12MTL LOW_VT Inverter HighFast 1
SEQCLKNAND2X2MTL LOW_VT Nand LowFast 1
SEQCLKNAND2X2MTL LOW_VT Nand HighFast 48
SEQXOR2X1MTL LOW_VT Xor HighFast 47
SEQSDFFQX1MTL LOW_VT Scan flop HighFast 90
...
...
2. Cell summary of infered clock tree and net buffer tree.
SEQCLKBUFX8MTH HIGH_VT Leaf clock buffer - 15
SEQBUFX2MTH HIGH_VT Branch net buffer - 15
SEQBUFX2MTH HIGH_VT Leaf net buffer - 267

3. Cell summary of inferred clock gates.

SEQTLATNTSCAX2MTH HIGH_VT Clock gate - 42

4. Cell summary of instantiated netlist elements.

DP256x32 - Memory - 24
DP512x32 - Memory - 36
<snip>

4.16.3. Modal Analysis Reports

Modal Analysis generates a top-level report and a report per mode. You can then combine the results
into one or more reports. You can also print the mode analysis results or compute a weighted average.

In this tutorial, PowerArtist performs power analysis in two modes, the transmit and the receive modes,
and generates the following reports for each mode:

• The Receive Mode Report ('receive_mode.rpt')

The report shows the mode signal 'txrx_tst.top1.rx_rq', which indicates that power
analysis is performed in the 'receive' mode and the mode signals are set in the mode file. A
sample is shown below:
<snip>
Mode signal: txrx_tst.top1.rx_rq

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 Understanding Power Analysis through Text Reports

Global activity file: ./pa_shell_work/top.gaf

Mode file: ./input/txrx.mode
<snip>

• The Transmit Mode Report ('transmit_mode.rpt')

The report shows the mode signal txrx_tst.top1.tx_rq, which indicates that power
analysis is performed in 'transmit' mode and the mode signals are set in the mode file. A sample
is shown below:
<snip>
Mode signal: txrx_tst.top1.tx_rq
Global activity file: ./pa_shell_work/top.gaf
Mode file: ./input/txrx.mode
<snip>

• The Average Report ('average_report.rpt')

You can also view the time spent during mode analysis. This information is available in
'average_report.rpt'. A sample is shown below:
<snip>
Total time in modes: 96%
Global activity file: ./pa_shell_work/top.gaf
Mode file: ./input/txrx.mode
<snip>

4.16.4. Generating Power Reports from the Power Database

The reports described in this section are generated by accessing the power database (generated
during power analysis) using APSH container commands.
4.16.4.1.The 'reportPower' Command
4.16.4.2.The 'reportSummary' Command
4.16.4.3.The 'report_cg_efficiency' Command

4.16.4.1. The 'reportPower' Command

The report named 'reportPower.rpt' is generated in the 'reports' directory as the following
command is used in 'power_reports.tcl':
reportPower -show_ibp -levels 2 -unit mW -out ./$RPT_DIR/reportPower.rpt

The report summarizes the power of each hierarchical instance in the design, starting from the top
module 'top', down to the lowest level of hierarchy '/top/core1/*/*/*' (if '-levels all' is
set). A section of the report is shown below:
Instance: /top
Power Unit: mW
Category Internal Switching Leakage Total
---------------------------------------------------------
register 3.851 0.000 0.016 3.867
latch 0.000 0.000 0.000 0.000
logic 0.349 0.013 0.023 0.385 (+ibp)
bbox 0.000 0.000 0.000 0.000
memory 15.909 0.000 3.806 19.715
pad 0.000 0.000 0.043 0.043

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PowerArtist Tutorial Part I: Power Analysis

clock 0.025 0.996 0.001 1.022

--------------------------------------------------------
Subtotal 20.134 1.009 3.889 25.032
Percentage 80.43% 4.03% 15.54% 100.00%
(*) ibp 0.000 0.000 0.000 0.013 (Inferred Buffer Power)
<snip>

In this report, power is reported for the 'register', 'latch', 'logic', 'bbox', 'memory', 'pad',
and 'clock' categories. For each category, power is reported in four columns:

Column Name Description

Internal Is cell internal power.
Switching Is the switching power of output (or load) nets
Leakage Is the cell static (leakage) power
Inferred Buffer Is included in the 'logic' category.
Power (ibp)
Note: It is also displayed at the end of the power table. All the power
data is in 'mW' units as specified by the use of option '-unit'.

4.16.4.2. The 'reportSummary' Command

The report named 'reportSummary.rpt' is generated in the 'reports' directory as the following
command is used in 'power_reports.tcl':
reportSummary -out ./$RPT_DIR/reportSummary.rpt

This command generates a comprehensive summary of the design, its power, and activity. The
generated report is shown below:
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Design: /top
Category #insts #bits #eff_bits area pwr/stat pwr/dyn pwr/load
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
pad 287 287 287 2.32e-06 4.28e-05 0.00e+00 0.00e+00
memory 20 640 640 3.92e+06 3.81e-03 1.59e-02 0.00e+00
register 30 694 693 6.87e+03 1.58e-05 3.85e-03 0.00e+00
MUX 44 938 752 2.81e+03 2.10e-06 2.60e-04 0.00e+00
ALU 12 296 296 2.05e+03 1.97e-05 4.67e-05 0.00e+00
DPX 7 58 58 1.60e+02 2.27e-07 1.48e-07 0.00e+00
Logic 196 196 196 1.95e+03 5.30e-07 4.27e-05 1.32e-05
clock 72 72 72 4.35e+01 6.34e-07 2.50e-05 9.96e-04
ibp n/a n/a n/a n/a 1.15e-07 1.34e-05 1.31e-05
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Total 668 3181 2994 3.93e+06 3.89e-03 2.01e-02 1.02e-03
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Primary clocks = 3, #clock nets = 121, 0-freq nets = 38.02%
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
freq #flops %flops cg/pct #icgcs #buffs #combs | primary-clock-net
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
6.32e+07 239 34.49 34.05% 3 4 17 | /top/Ppci_clk
6.32e+07 452 65.22 64.79% 10 21 17 | /top/Pclk
0.00e+00 2 0.29 0.29% 0 0 0 | /top/Ptck
<snip>

In this report, instance, bit-width, area, and power information for the following is reported:

pad Pads (if present)

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 Understanding Power Analysis through Text Reports

memory Instantiated memories and inferred Regfile and Latchfiles

register Inferred and instantiated registers
latch Inferred and instantiated latches
MUX Inferred and instantiated muxes (includes inferred CGs)
ALU Inferred adder and multipliers
DPX Inferred decoder, comparator, and shift operators
Logic All other logic
clock Clock tree(s)
ibp Inferred buffer power (RTL only)

Additionally, there is one row for each clock domain, showing the number of flop-bits, percentage
of total flop-bits, clock gating percentage, number of ICGCs, and number of clock buffers.

4.16.4.3. The 'report_cg_efficiency' Command

The 'report_cg_efficiency' command is used to generate the enable efficiency of each clock gate
and the power each clock gate controls. For usage syntax and detailed description of the column
elements, refer to the 'report_cg_efficiency' command APSH Containers Reference section of the
PowerArtist Reference Manual.

The report named 'reportCGEfficiency.rpt' is generated in the 'reports' directory as the

following command is used in 'power_reports.tcl':
reportCGEfficiency -sort_by clock_power -out ./$RPT_DIR/reportCGEfficiency.rpt

This command generates a comprehensive efficiency report of all inferred and instantiated clock
gates in the design. This command also reports gated registers and latches with the part select
associated with the clock gating. The option '-sort_by clock_power' is used to sort the
information by 'clock power'.

A sample is shown below:

"Inst Name","Gater Type","En Duty","Cum En Eff","Dwns Clk Power","Pr Clock","En Eff",
"En Net","File","Line","In Freq","Out Freq"
"/top/core1/t1/l1/#m3","inferred","0.53","0.47","8.59e-05","/top/Ppci_clk","0.47",
"/top/core1/t1/l1/#n199","../data/design/rtl/lencntr.v","22","6.32e+07","3.38e+07"
"/top/core1/s1/#m5","inferred","0.96","0.04","7.72e-05","/top/Pclk","0.04",
"/top/core1/en_wdtmr","../data/design/rtl/stats.v","101","6.32e+07","6.05e+07"
"/top/core1/u1/#m1","inferred","0.42","0.58","6.72e-05","/top/Pclk","0.58",
"/top/core1/u1/#n133","../data/design/rtl/upi.sv","48","6.32e+07","2.64e+07"
<snip>

The first line in the report is the heading specifying the various columns of the information table.
The default columns are as follows:

Column Description
Name
Inst Hierarchical Instance name
Name

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PowerArtist Tutorial Part I: Power Analysis

Column Description
Name
Gated Inferred or Instantiated
Type
En Duty Enable duty
Cum En Cumulative enable efficiency
Eff
Dwns Clk Downstream clock power
Power
Pr Clock Primary clock
En Eff Enable efficiency
En net Enable net name
File RTL file path
Line Line number corresponding to the ICGC logic in the RTL file
In Freq Input frequency
Out Freq Output frequency

The default sorting order of the report is 'clock_power'. If there are multiple entries with the
same ' clock_power', the instance name ('Inst Name') is used for a secondary level of sorting
and reporting is in the alphabetical order of the instance names.

Note: The tool does not support calculation of CGE metrics for macros with multiple clock pins.
This is because gating conditions and relations between input-clock-output pins are not
straightforward to define for a cell with multiple clock pins.

4.16.5. Time-based Power Analysis Report

After time-based power analysis is complete, the following outputs are generated:

• A report file containing an ASCII representation of the power analysis results ('text' format).
A text report is generated if you specify '-time_based_report_file
<report_filename>' with 'CalculatePower'. For a sample time-based text power report,
go to the 'reports' directory and open 'time_based_power.rpt'. The various sections
in the report are explained in the next sections.
• Waveforms in either the FSDB format or PowerArtist Tcl-based format that holds the current
and power-over-time information you requested. This includes peak power per category and
the time at which they were computed.

4.16.5.1. Header
A 'header' section provides the following information:

• The date of the power analysis.

• The version of the software used to perform the analysis.
• The options applied during this run.

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 Understanding Power Analysis through Text Reports

• Summary information on the simulation run including simulation duration, start, and finish
times.
• The power supply values used.
• The initial input transition time.
• The monitor file name.
• The wire load mode and model information.

4.16.5.2. Power Contribution

This section is divided into the following sub-sections:

• Category Power Summary

This group power section lists for each group:

– The category name.
– The average power for all elements in the category broken into static, dynamic, and
total power.
– The maximum power for all elements in the category broken into static, dynamic,
and total power.
– One or more time steps in your simulation at which the maximum power occurred.

• Instance Power Summary

For each instance specified by the 'MonitorInstances' command, this section reports the
following:
– Average power for all children of the instance (or just the instance itself if it were a
cell in a library) broken into static, dynamic, and total power.
– The maximum power in Watts.
– One or more time steps in your simulation that the maximum power occurred.
– The instance name.

The report generated is shown below:

1. Power contribution
=====================

Average Power(Watts) Maximum At Time

Category Static Dynamic Total Power(Watts) (s)
-------- ------ ------- ----- ------------ ---
Register 16.184uW 3.8939mW 3.9101mW 4.8839mW 10.62us
Latch 0W 0W 0W 0W 0s
Memory 3.9747mW 16.385mW 20.359mW 21.188mW 9.1036us
Other 23.416uW 398.3uW 421.72uW 503.43uW 9.1036us
IO 43.29uW 0W 43.29uW 43.29uW 6.3748us
6.678us, 6.9812us, 7.2844us, 7.5876us, 7.8908us, 8.194us, 8.4972us, 8.8004us, 9.1036us
...
Clock 625.53nW 1.0741mW 1.0747mW 1.1397mW 10.62us
11.529us
InferredBuffer 115.06nW 15.073uW 15.188uW 32.022uW 9.4068us
-------- -------- --------
Total Average 4.0584mW 21.766mW 25.824mW

Average Power(Watts) Maximum At Time Instance

Static Dynamic Total Power(Watts) (s) Name
------ ------- ----- ------------ --- ----
4.0584mW 21.766mW 25.824mW 27.509mW 10.62us top
1.9907mW 9.1367mW 11.127mW 16.072mW 9.1036us top.core1.t1

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PowerArtist Tutorial Part I: Power Analysis

1.98998mW 7.9034mW 9.8932mW 15.178mW 10.62us top.core1.r1

NOTE: ellipsis at the end of line means that there are more time stamps,
which can be displayed using switch -max_time_stamps.
<snip>

4.16.5.3. Detailed Instance Power

This section provides a per-instance power consumption report. The report generated is shown
below:
2. Detailed Instance Power
==========================

Average Power(Watts) Type Instance

Static Dynamic Total Name Name
------ ------- ----- ---- ----
4.0143mW 20.677mW 24.691mW user top
1.9906mW 8.9645mW 10.955mW user top.core1.t1
94.229pW 0W 94.229pW and -#c0
118.15nW 19.882uW 20uW user -s1
718.84pW 3.3379nW 4.0567nW and --#c0
526.63pW 5.716nW 6.2426nW and --#c1
<snip>

4.16.5.4. Mixed-VT Cells Distribution

This section of the report shows the distribution of the Mixed-VT cells in the design. The report
generated is described in the Mixed-VT Cells Distribution (p. 55) section of the Average Power
Analysis Report (p. 50) section.

4.16.5.5. Clock Power Consumption

This section of the report shows the power consumed by each clock net. Details about clock gating
prediction and clock tree inferencing are included in this clock power report section. The report
generated is described in the Clock Power Consumption (p. 55) section of the Average Power
Analysis Report (p. 50) section.

4.16.5.6. Inferred Buffer Tree Power

If your design requires buffer trees for high fanout nets, this section describes the affected nets
and how the buffer tree is created. The generated report is described in the Inferred Buffer Tree
Power (p. 58) section of the Average Power Analysis Report (p. 50) section.

4.16.5.7. Power consumption by model/gate type

This section is described in the Power Consumption by Model/Gate Type (p. 61) section of the
Average Power Analysis Report (p. 50) section.

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 Using the Power Analysis Results

4.17. Using the Power Analysis Results

4.17.1. Using the Average Power Analysis Results

You can use PowerArtist average power analysis results at various stages of the design implementation:

• While designing your RTL

Use PowerArtist concurrently with RTL simulation to analyze power and identify hot spots. If
the design consists of mixed RTL and gate-level models, use PowerArtist and apply simulation
data as it becomes available for individual modules or sub-systems to improve the analysis
accuracy for those blocks.

• After synthesizing

After using PowerArtist at the RT-level to decide among design alternatives, you can start
synthesizing portions of your design. Since logic synthesis can substantially restructure control
logic to minimize area or meet timing constraints, you should repeat power analysis using
post-synthesis information. This can be done on a mixed RTL and gate-level design or on a
fully synthesized gate-level netlist.

• After place and route

Use PowerArtist with back-annotated capacitance values in a gate-level simulation to use

parasitic information from layout in the analysis.

4.17.2. Using the Time-based Power Analysis Results

You can use the results from a time-based power analysis in a number of ways:

• The peak power and current information can be used during physical implementation to size
the power grid. By selecting various hierarchical instances in your design that correspond to
physical blocks, you get a good idea of the power grid needs on a block-by-block basis.
• The total peak power and current values give you some idea of the power supply needs of
your chip.
• By examining areas of the waveform that have large swings in power or current from one time
step to the next, you can ascertain if there are any di/dt issues.

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Chapter 5: PowerArtist Tutorial Part II: Power
Reduction
5.1. Introduction
This tutorial showcases how to perform RTL power reduction for your design using PowerArtist and
highlights various steps involved starting from design elaboration, reduction analysis, generation of
some useful power reduction reports, and rewriting the RTL.

Note: The PowerArtist tutorials are a feature demonstrator and are not intended as an example on how
to set up PowerArtist on a new design.

Tutorial Organization
The following subjects are covered in this chapter:

• About PowerBots (p. 71)

• Copying the 'reduction' Tutorial Files (p. 72)
• Understanding the Power Reduction Flow (p. 72)
• Understanding the Power Reduction Tutorial Steps (p. 73)
• Understanding Power Reduction Setup (p. 74)
• Design Elaboration (p. 74)
• Common Setup for Clock Definitions (p. 74)
• Specifying the Memory (p. 75)
• Multi-port RAM Support (p. 77)
• Running Power Reduction (p. 79)
• Generating Additional Power Reports (p. 82)
• Viewing Power Reduction Results in the PowerArtist Graphical Interface (p. 82)
• Understanding Power Reduction through Text Report (p. 90)

5.2. About PowerBots

Power reduction in PowerArtist is based on modules called 'PowerBots'. These PowerBots scan your
design looking for a specific design feature, such as an enable signal that can be constructed to turn
off unobserved register toggles. A PowerBot performs an analysis of the topology of your design and
activities on nets and then makes recommendations on potential changes you should make to your
design. It reports either power savings numbers or power wastage numbers to help you make your
decision. If it can determine an example change to make, it provides code snippets as well. For details
on the different PowerBots available, see PowerBot Overview (p. 277).

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PowerArtist Tutorial Part II: Power Reduction

5.3. Copying the 'reduction' Tutorial Files

For the reduction tutorial, you need only the 'reduction' and 'data' directories. To get started, copy
the directories from the following location:
$POWERARTIST_ROOT/tutorial/reduction
$POWERARTIST_ROOT/tutorial/data

Contents of the 'reduction' Directory

The following table lists the contents of the reduction tutorial:

Directory Description
Name/FileName
README Describes the basic flow for running this tutorial.
input Contains the following file:

txrx.vc - Is the Verilog startup file that tells the HDL elaborator
which Verilog files must be loaded for your design.
pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt and is used
to customize the 'pa_shell' settings at multiple levels.
run.tcl A Tcl script to run the reduction tutorial in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various sub-tasks related
to power analysis (such as,design elaboration and vector analysis)
and reduction analysis).
cleanall A script to remove all the files created while running the 'reduction'
tutorial.

5.4. Understanding the Power Reduction Flow

Running power reduction process is shown by the following graphic:

The main steps in the power reduction flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. ReducePower

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 Understanding the Power Reduction Tutorial Steps

Performs reduction analysis on your design.

3. Generate Power Reports

Understand the reports generated after reduction analysis and schedule changes.

5.5. Understanding the Power Reduction Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi Vt, design, and library database:
pa_shell % source ./scripts/power_setup.tcl

7. Set up memories for reduction:

pa_shell % source ./scripts/memory_setup.tcl

8. Run RTL power reduction:

pa_shell % source ./scripts/reduce_power.tcl

9. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

10. Exit PowerArtist:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single tcl
file (run.tcl):
% pa_shell -tcl run.tcl

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PowerArtist Tutorial Part II: Power Reduction

5.6. Understanding Power Reduction Setup

1. Running the Setup

This step is identical to the step explained in detail in the Running the Setup (p. 24) section of the
Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source 'setup.tcl' to create the required
directories:
pa_shell % source ./scripts/setup.tcl

2. Reading the Library Files

This step is identical to the step explained in detail in the Reading the Library Files (p. 24) section
of the Power Analysis tutorial.

Source 'libraries.tcl' to read the liberty files and create a library database:
pa_shell % source ./scripts/libraries.tcl

5.7. Design Elaboration

When you run the 'Elaborate' command, PowerArtist compiles and elaborates the RTL/gate-level design,
and creates a scenario file based on the commands and options you specify. This scenario file is a binary
representation of the elaborated design. Once you have the scenario file, you do not have to run this
step again unless there is a change in RTL.

This step is identical to the step explained in detail in the Design Elaboration (p. 25) section of Power
Analysis tutorial.

Source 'elaborate.tcl' to create a scenario file:

pa_shell % source ./scripts/elaborate.tcl

5.8. Common Setup for Clock Definitions

1. The ReadSDC Command

This step is identical to the step explained in detail in the The ReadSDC Command (p. 26) section
of the Power Analysis tutorial.

Source 'read_sdc.tcl' to generate the output files:

pa_shell % source ./scripts/read_sdc.tcl

2. Setup for Clock Tree and Clock Gate Inferencing

This step is identical to the step explained in detail in the Setup for Clock Tree and Clock Gate
Inferencing (p. 27) section of the Power Analysis tutorial.

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 Specifying the Memory

Source 'power_setup.tcl' to set clock-related constraints and enable clock gating:

pa_shell % source ./scripts/power_setup.tcl

3. Setup for Capacitance Estimation

This step is identical to the step explained in detail in the Setup for Capacitance Estimation (p. 28)
section of the Power Analysis tutorial.

Source 'power_setup.tcl':
pa_shell % source ./scripts/power_setup.tcl

4. Mixed-Vt Setup

This step is identical to the step explained in detail in the Mixed-VT Setup (p. 29) section of the
Power Analysis tutorial.

Source 'power_setup.tcl' to specify mixed-vt libraries, threshold, and mixed-vt percentage for
cell selection:
pa_shell % source ./scripts/power_setup.tcl

5.9. Specifying the Memory

The 'DefineMemory' command defines memory cells and critical memory ports in your Liberty libraries.
This command is also used by the 'Split Memory Words' and 'Gate Memory Clock' power reduction
techniques (PowerBots) to identify critical memory ports like chip-select and read/write enable.

PowerArtist analyzes your simulation input file by using the information in your 'DefineMemory'
commands to:

• Monitor the clocks of all recognized memory instances in your design.

• Collect a variety of data for your memories.
• Write out statistics on your memories into a side Tcl file (.stcl), which is read in the next step.

You can also use the 'DefineMemActivityThreshold' command to specify the number of clock cycles
during which a memory (of a given type and size) must maintain a stable state ('1' or '0') for memory
splitting. In addition to the MSB/LSB of a memory address maintaining a stable state, some activity must
also happen on other address bits. Therefore, this count is the count of clock cycles where there is
activity on other address bits. For example, if the MSB/LSB address is in state '0' for 100 clock cycles,
but in those 100 cycles, there is activity on other address bits for 10 cycles, this would be equivalent
to a threshold value of '10'.

Note: If you do not specify the 'DefineMemActivityThreshold' command, PowerArtist uses their default
values.

As a part of the 'DefineMemory' command, you need to specify these options:

• To specify a tcl list of the logical library names, use the following option:
-library {lib_name1 lib_name2 ...}

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PowerArtist Tutorial Part II: Power Reduction

• To define the Tcl list of ports as access enable ports that indicate whether a read or write operation
will occur, use the following option:
-access_enable {access_enbl_port_name1 access_enbl_port_name2 ...}

• To define the Tcl list of ports as read address ports, use the following option:
-read_address {read_address_port1 read_address_port1 ...}

• To define the Tcl list of ports as write address ports, use the following option:
-write_address {write_address_port1 write_address_port1 ...}

• To define the Tcl list of ports as input and output pins carrying data ports, use the following
option:
-data {pin_name1 pin_name2 ...}

• To define the Tcl list of ports as memory enable or select ports, use the following option:
-memory_enable {mem_enbl_or_sel_port1 mem_enbl_or_sel_port2 ...}

• To define the Tcl list of cells as memory cells, use the following option:
-cell {cell_name2 cell_name2 ...}

As a part of the 'DefineMemActivityThreshold' command, you need to specify these options:

• To specify the number of clock cycles for which the address bus must be stable, use the following
option:
-num_clocks <num_clock_cycles>

• To specify the type of memory to which the given threshold (clock cycles) apply, use the following
option:
-mem_type <RAM | ROM>

• To specify the size of the memory to which the given threshold (clock cycles) applies, use the
following option:
-mem_size <word_x_width>

Go to 'scripts' and open 'memory_setup.tcl'. An excerpt is shown here:

# Identify memory ports for reduction
DefineMemory -library DP256x32 \
-access_enable { WENA WENB } \
-read_address { AA* AB* } \
-write_address { AA* AB* } \
-data { QA* QB* DA* DB* } \
-memory_enable { CENA CENB } \
-cell { DP*}
DefineMemory -library DP512x32 \
-access_enable { WENA WENB } \
-read_address { AA* AB* } \
-write_address { AA* AB* } \

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 Multi-port RAM Support

-data { QA* QB* DA* DB* } \

-memory_enable { CENA CENB } \
-cell { DP*}

# Define the length of a stable address as 1 clock cycle for RAMs of size 256x32 and 512x32
DefineMemActivityThreshold -num_clocks 1 -mem_type RAM -mem_size 256x32
DefineMemActivityThreshold -num_clocks 1 -mem_type RAM -mem_size 512x32

Source 'memory_setup.tcl' to define memories for power reduction:

pa_shell % source ./scripts/memory_setup.tcl

5.10. Multi-port RAM Support

PowerArtist supports dual-port RAMs with one-read and one-write port. Dual-port RAM support means
inferring a single two-dimensional register or latch file or a collection of individual state devices (register
and latches) with read and write decoding logic from a two-dimensional array.

Support for multi-port RAM is also available. Multi-port RAM support means recognizing multiple (more
than one) read and write ports from a two-dimensional array. This is enabled by setting the following
variable to 'true':
pa_set elaborate_infer_multi_port_ram <true | false>

You must also set the following additional variable to 'true':

pa_set categorize_regfile_as_memory <true | false>

Specifying this variable ensures that power numbers are reported under the 'memory' category.

This support is available in the following flows:

• Power Analysis (CalculatePower)

No additional options/steps are required to enable to this support in the power analysis flow.

• Power Reduction (ReducePower)

In power reduction, multi-port inferred regfile (register file) support is added to the 'Gated
Memory Clock (GMC)' PowerBot. For this support, 'redundant write clock cycles' are
identified by the PowerBot and then reduced power is calculated for multi-port inferred regfiles.
Consider the following sample RTL:
// clk1 controls writing on both port1 and port2;
// clk2 controls reading on both port1 and port2;
===================================================
module top (clk1, clk2, wen, waddr1, waddr2, wdata1, wdata2,
raddr1, raddr2, rdata1, rdata2);
parameter ADDR_BITS = 3 ;
parameter DATA_SIZE = 16 ;
parameter TOTAL_ADDR_WORDS = 8 ;

input clk1, clk2 ;

input wen;

input [ADDR_BITS - 1 : 0] waddr1, waddr2, raddr1, raddr2 ;

input [DATA_SIZE - 1 : 0] wdata1, wdata2 ;

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output [DATA_SIZE - 1 : 0] rdata1, rdata2 ;

reg [DATA_SIZE - 1 : 0] rdata1, rdata2 ;

reg [DATA_SIZE - 1 : 0] myRegF [TOTAL_ADDR_WORDS - 1 : 0] ;

always@(posedge clk1)
if (wen)
myRegF[waddr1] <= wdata1 ;

always@(posedge clk1)
if (wen)
myRegF[waddr2] <= wdata2 ;

always@(posedge clk2)
if (!wen)
rdata1 <= myRegF[raddr1] ;

always@(posedge clk2)
if (!wen)
rdata2 <= myRegF[raddr2] ;

endmodule

The following is a schematic representation of the RTL, which is elaborated to model a multi-port
regfile:

The schematic representation shows that the 'read' operations from the regfile are not synchronized
by any clock in the regfile. The 'read' data is stored in two flip-flops, which are driven by clocks outside
the 'regfile'. Therefore, only the 'write' clocks are important to calculate the reduced power of a regfile
instance. PowerArtist calculates the 'redundant write cycles' for such regfiles.

The following types of clock cycles are recognized for each clock in the inferred regfile:

Clock Cycle Name Description

Unknown Unable to determine the mode in this cycle.
Disable Memory is disabled in this cycle.
Write Memory is in write mode in this cycle. This implies the memory is enabled
and the write enable is active high.
Redundant If the previous and current cycle are 'write' cycles and the write address has
Write not changed, then the current cycle is a redundant write cycle.

The updated results are available in the GMC opportunities section in both the text report and GUI.

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 Running Power Reduction

5.11. Running Power Reduction

You can perform RTL power reduction on RTL, gate-level, and mixed RTL and gate designs and use the
following variables to specify the inputs related to simulation activity:
pa_set top_instance top_instance_name
pa_set activity_file <activity_file_name>

Go to 'scripts' and open 'reduce_power.tcl'. An excerpt is shown here:

# Calculate and reduce the average power of the design

# Inputs related to simulation activity

pa_set top_instance txrx_tst.top1
pa_set activity_file ../data/sim/rtl/top.fsdb

You can use the 'GenerateGAF' command for explicit control. The options used in this tutorial are
explained below:

• To enable the command to perform reduction analysis, use the following option:
-gaf_enable_reduction_data true

• To specify start and finish times for the simulation window for the average analysis, use the
following options:
-start_time time
-finish_time time

• To specify the name of the '.gaf' file, use the following option:
-gaf_file <gaf_filename>

• To compress the generated '.gaf' file, use the following option:

-compress_gaf true

• To specify a name for the log file, use the following option:
-gaf_log <filename>

Go to 'scripts' and open 'reduce_power.tcl'. An excerpt is shown here:

# Process activity for average power calculation
GenerateGAF \
-gaf_enable_reduction_data true \
-start_time 6071580ps \
-finish_time 12135580ps \
-gaf_file ./$WORK_DIR/${design}_sleep.gaf \
-compress_gaf true \
-gaf_log ./$LOG_DIR/generate_gaf.log

Block Activity Ranking (BAR) performs hierarchical analysis and identifies block-level clock and data
gating opportunities in the design. BAR analyzes port activities of all the blocks in the design on a per
clock domain basis and presents the results in text and comma-separated value (CSV) reports. To
generate the report, use the following command:

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PowerArtist Tutorial Part II: Power Reduction

SetBAR -output_file report_file_name.bar

Go to 'scripts' and open 'reduce_power.tcl'. An excerpt is shown here:

# Port activity for block-level data and clock gating
SetBAR -output_file ./$RPT_DIR/block_clock_data_activity.rpt

Use the 'ReducePower' command for power reduction with the required arguments. The options used
in this tutorial are explained below:

• To read an existing GAF stimulus file, use the following option:

-use_existing_gaf true

• To specify the name of the '.gaf' file, use the following option:
-gaf_file <gaf_filename>

• To control whether reduction opportunities are allowed to cross hierarchical boundaries, use the
following option:
-reduction_hierarchy full

• To disable read address stability based gating on the memories in the design, use the following
option:
-reduction_memory_stability_gating true

• To skip reduction techniques (PowerBots), use the following option:

-skip_reduction_list {}

• To specify the logical liberty library name in which the power analyzer searches for wire load
models, use the following option:
-wireload_library hvt

• To set the default output load to the specified value, use the following option:
-default_output_load float

• To set the default transition time for any net for which slew is not specified, use the following
option:
-default_transition_time float

• To set the default clock transition time, use the following option:
-default_clock_transition_time double

• To perform full scan insertion at RTL, use the following option:

-infer_scan_fanouts true

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 Running Power Reduction

This is needed if the post-layout netlist has inserted scan chains and helps in better net
capacitance modeling at RTL.

• To overwrite the existing power database ('.pdb') file, use the following option:
-reduction_overwrite_power_db true

• To specify the name of the power database ('.pdb') file, use the following option:
-power_db_name <pdb_filename>

• To generate power database schematics for the clock trees in the design, use the following
option:
-save_clock_trees_netlist true

• To specify a name for the log file, use the following option:
-reduction_log <filename>

During power reduction, you can generate top level power summary, design statistics, and other reports.
The reports are explained in subsequent sections and the report options used in this tutorial are explained
below:

• To specify the power reduction report file name, use the following option:
-reduction_report_file <report_filename>

• To generate an additional 'Clock Gating by Instances' section in the clock gating report, use the
following option:
-reduction_report_clock_gating_by_instance true

• To generate the clock gating enable efficiency power report, use the following option:
-reduction_report_clock_gating_enable_efficiency true

Go to 'scripts' and open 'reduce_power.tcl'. An excerpt is shown here:

# Generate RTL power reduction opportunities
ReducePower \
-use_existing_gaf true \
-gaf_file ./$WORK_DIR/${design}_sleep.gaf \
-reduction_hierarchy full \
-reduction_memory_stability_gating true \
-reduction_report_file ./$RPT_DIR/reduce_power.rpt \
-reduction_report_clock_gating_by_instance true \
-reduction_report_clock_gating_enable_efficiency true \
-skip_reduction_list {smw} \
-wireload_library hvt \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-infer_scan_fanouts true \
-reduction_overwrite_power_db true \
-power_db_name ./$DB_DIR/reduce_power.pdb \
-save_clock_trees_netlist true \
-reduction_log ./$LOG_DIR/reduce_power.log

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Source 'reduce_power.tcl' to perform power reduction:

pa_shell % source ./scripts/reduce_power.tcl

5.12. Generating Additional Power Reports

After power reduction, you can also generate additional power reports. These reports are generated by
accessing the power database (generated during power analysis) using APSH commands. This step is
identical to the Generating Additional Power Reports (p. 43) section of the Power Analysis tutorial.

Source 'power_reports.tcl' to generate the reports:

pa_shell % source ./scripts/power_reports.tcl

5.13. Viewing Power Reduction Results in the PowerArtist Graphical

Interface
The PowerArtist GUI provides a convenient way to review the power reduction analysis results and any
RTL changes that are automatically scheduled to be re-written before performing an RTL rewrite. You
can also see any other opportunities that you can implement manually.

Use the following process to review your reduction results and, if necessary, modify the scheduled
changes.

1. Launch the GUI from the Unix prompt by using the following command:
PowerArtist -pdb reduce_power.pdb

This brings up the GUI and loads the power database.

2. Expand the modules in the hierarchy browser left-hand pane by clicking the '+' icons.

3. Select 'top(top)' in the hierarchy browser to populate the power table in the right-hand pane.

4. Select 'Design > Hierarchy > Colorize By > Power'. The hierarchy is colorized for power, as shown
in the following figure:

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 Viewing Power Reduction Results in the PowerArtist Graphical Interface

Figure 5.1: Hierarchy Browser Display of Power Database

5. From the main menu, click 'View' and notice the last three menu items. Each of these menu items
opens a unique dialog that is optimized to show the results of particular PowerBots:

• Simple Power Reductions: Displays non-linter PowerBots that include Low-Activity

Non-Enabled Register (LNR) (p. 279), Gate Memory Clock (GMC) (p. 293), Local Explicit Clock
Enable (LEC) (p. 283), Datapath Operator Isolation (DOI) (p. 282), Observability Don't Care
(ODC) (p. 304), and Split Memory Words (SMW) (p. 287).

• Linter Power Reductions: Displays linter PowerBots that include Clock Enable Condition
(CEC) Linter (p. 336), Memory Power (MEM) Linter (p. 326), Register Power (REG) Linter (p. 334),
and MUX Power (MUX) Linter (p. 327).

• Prism Reductions: Displays reductions found by the Prism (p. 298) PowerBot. To review sample
Prism results, see Reporting Results (p. 300).

Note: In the 'Simple' and 'Linter' reduction dialogs, the opportunities use the acronyms for the PowerBots
instead of their full names, such as 'GMC' instead of 'Gate Memory Clock'.

5.13.1. Reviewing Simple Power Reductions

To view these results on a module by module basis, select 'View > Simple Power Reductions'. This
opens the dialog shown in the following figure:

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PowerArtist Tutorial Part II: Power Reduction

Figure 5.2: Simple Reductions Dialog

Notes:

• Data shown in gray text is summarized data that consists of multiple parts. When you expand
each entry by clicking the '+' signs, the values are displayed in black text.
• The registers are displayed as either vectors or as a concatenated list of scalars.

5.13.2. Manipulating the Data

If a module with potential reductions is instantiated multiple times, you get a better idea of the
contribution to the overall power saving if you can see power savings for all instances of the module
together. To enable you to do this, PowerArtist organizes the available reductions by module. The
power saving for each instantiation is shown in rows that are colored light blue.

For example, if you expand 'pci > LNR > pci_dout[63:0] at line 58', you see that there is one instance
of this change, as shown in the following figure:

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 Viewing Power Reduction Results in the PowerArtist Graphical Interface

Figure 5.3: Sample of LNR PowerBot Expanded to Show Instances

Note: You can expand the width of the 'Module/Reduction' column by dragging the right field separator
and see all the text in the column, as shown in the figure above.

If you right-click any entry, a menu displays as shown in the following figure:

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PowerArtist Tutorial Part II: Power Reduction

Figure 5.4: Menu for Instance-Level Entry

If you are on an instance-level entry, this menu allows you to cross-probe. For example, you can
cross-probe to the hierarchy display, schematic, or source and to trace cones of logic (upstream or
downstream).

Note: The disabled items on this menu are available for instance-level entries only.

The two right-most columns 'Accept' and 'Rewrite?', help you manage decisions on whether or
not to accept a particular reduction opportunity and if so, to implement them manually or
automatically.

5.13.3. Using the Context-Sensitive Help Pages

If you click the 'Help' button in the 'Simple Reductions' dialog, you see context-sensitive Help pages,
as explained below:

• If you click the 'Help' button before clicking on any of the results, you see the 'Reduction Index'.
This page lists each of the PowerBots on this dialog. From here, you can click any of the links
to get information on a specific PowerBot.
• If you first click a row in the reduction results and then click the 'Help' button, you see the
help pages for that specific PowerBot.
For example, if you click an 'LNR' line in the reduction results, and then click the 'Help' button,
you see a detailed help page for the 'Low activity non-enabled register', as shown
in the following figure:

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 Viewing Power Reduction Results in the PowerArtist Graphical Interface

Figure 5.5: Sample Context-Sensitive Help Page for the LNR PowerBot

The context-sensitive help is also available in the 'Linter Reductions' and 'Prism' dialogs.

5.13.4. Filtering Reduction Results

You can use the filter tool bar to filter your data in a variety of ways. Once you have selected your
filter criteria, use:

• the magnifying glass icon (or just hit the 'Enter' key) to perform the filtering.

or

• the cancel icon to cancel the filtering.

For example, you could perform the following filtering:

1. On the 'Simple Reductions' dialog, in the 'Match:' field, select Mod Saved Total from the
first pull-down and greater than from the second.

2. Enter '170uW' and click the icon. This filters out all line-level reductions that do not reduce
power by at least '170uW'.

The following figures show the results before and after the filtering is applied:

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PowerArtist Tutorial Part II: Power Reduction

Figure 5.6: Filtering Simple Reduction Results - Before

Figure 5.7: Filtering Simple Reduction Results - After

The triangle on the far right allows you to do more complex filtering. You can create boolean
combinations of filters using the '+' and '-' symbols.

3. Take a close look at the reduction results.

Click any column header to sort the results in either ascending or descending order. To
rearrange the column headers, select a header and drag it left or right using the mouse.

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 Viewing Power Reduction Results in the PowerArtist Graphical Interface

4. Click the icon to cancel the filtering and re-display all results.

5.13.5. Reviewing Linter Reduction Results

You have linter reduction results if you included the linter PowerBots in your scripts. By default, all
reduction types are run. This section describes the linter reduction opportunities in this tutorial.

1. Select 'View > Linter Power Reductions'.

The 'Linter Reductions' dialog displays as shown in the following figure:

Figure 5.8: Linter Power Reductions Results

This dialog provides a list of wasted power results for each linter PowerBot.

Note: In the tutorial, only the CEC bot is listed.

2. Navigate to an instance in the 'CEC' (Clock Enable Condition Linter) results line. You can click the
'+' symbols to move down one level at a time. Alternately, you can select 'View > Expand All To
Instances' or 'Expand Selected To Line Instances' (if you have selected multiple lines).

3. Select an instance line. Select 'Auto Size Column' from the right-click menu on the 'Module/Linter'
header to display the full name of the instance.

4. Click the 'Detail' tab in second pane to see more details of the instance you selected, as shown
in the following figure:

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PowerArtist Tutorial Part II: Power Reduction

Figure 5.9: CEC Linter Power Reduction Results with Detail Tab Displayed

5. To accept all linter reductions, click 'Linters > Mark All Accepted'. The 'Accepted Savings' line in
the bottom pane of this dialog displays the wasted power savings you get with these changes.

Note: You need to manually implement all the wasted power savings opportunities listed in this
dialog.

5.14. Understanding Power Reduction through Text Report

In addition to reviewing the power reduction results in the PowerArtist GUI, you can also review the
results using the text-based power report file(s). The reports are divided into sections that each provide
valuable information about power reduction in your design. At the top of the report are the date and
program version, along with values for numerous arguments and parameters.
5.14.1. Power Reduction Report
5.14.1.1.Total Initial Power
5.14.1.2.Total Power Savings
5.14.1.3.Total Final Power
5.14.1.4. Power Reduction by Technique
5.14.2. Power Reduction Clock Gating Report
5.14.3. Observability Don't Care (ODC) Report
5.14.4. Blocks Activity Ranking Report
5.14.5. Reviewing Power Reports from the Power Database

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 Understanding Power Reduction through Text Report

5.14.1. Power Reduction Report

The power reduction report 'reduce_power.rpt' is a top-level summary of the reduction run. This
report provides a breakdown of the power values in the design. It has a header section and four body
sections. The header section contains information such as date run, program version information, all
of the specified options and a summary of information used to perform the analysis. The body sections
are explained in the next sections.

5.14.1.1. Total Initial Power

This section reports the initial total static and dynamic power for your design. The total power is
split into three categories: Core, Memory, and Design Power. The report records which types of RTL
elements go into each category.

A sample output is shown below:

1. Total Initial Power
======================

Core* Memory Design+

---------------------------------
Static : 8.56uW 3.97mW 4.03mW
Dynamic : 1.08mW 12.4mW 13.5mW
---------------------------------
Total : 1.09mW 16.4mW 17.5mW

* Core Power = Registers + Latches + Combinational Gates + Clocks - Black Boxes

+ Design Power = Core + Memory + Black Boxes + IO Pads

5.14.1.2. Total Power Savings

This section summarizes the total savings reported for all of the PowerBots. The bulk of the PowerBots
currently reduce dynamic power so those savings are split. The 'Total Power Saving' columns
consider the impact on both static and dynamic power. The 'Auto Accept' rows show the opportunities
that can potentially be automatically rewritten. The 'Potential' rows show the total savings you can
potentially achieve if you implement all the identified reduction opportunities. The 'percentage'
numbers are the savings for the given category (for example, Core) as a percentage of the 'Total'
power (reported in section 1) for that category.

A sample output is shown below:

2. Total Power Savings
======================

Dynamic Power Saving Total Power Saving

Core Memory Design Core Memory Design
--------------------------------------------------------------
Auto Accept : 14.7uW 6.39mW 6.4mW 14.7uW 6.39mW 6.4mW
% Auto Accept : 1.36% 51.38% 47.37% 1.34% 38.93% 36.49%

Potential : 109uW 9.58mW 9.69mW 109uW 9.9mW 10mW

% Potential : 10.06% 77.04% 71.67% 9.96% 60.35% 57.06%

5.14.1.3. Total Final Power

This section subtracts the 'auto-accepted' power savings (reported in section 2) from the 'Total
Initial Power' (reported in section 1) and presents that as the total final power.

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A sample output is shown below:

3. Total Final Power
======================

Core* Memory Design+

---------------------------------
Static : 8.56uW 3.97mW 4.03mW
Dynamic : 1.08mW 12.4mW 13.5mW
---------------------------------
Total : 1.09mW 16.4mW 17.5mW

5.14.1.4. Power Reduction by Technique

This section supplies the total savings for each PowerBot. The techniques are split into two categories
- those that affect 'Core' power and those that affect 'Memory' power. The savings are reported as
a percentage of dynamic savings as well as total savings, which factors in the impact on static
power.

A sample output is shown below:

4. Power Reduction by Technique
===============================

Core Core
Core Techniques Dynamic Saving Total Saving
----------------------------------------------------------------------------
Datapath operator isolation : 1.02uW 0.09% 954nW 0.09%
MUX Power Linter : 39.7pW 0.00% 39.7pW 0.00%
Register Power Linter : 43.6nW 0.00% 43.6nW 0.00%
Clock Enable Condition Power Linter : 4.73uW 0.44% 4.73uW 0.43%
Low activity non-enabled register :
Auto-accepted (width <= 16bits) : 9.92uW 0.92% 9.89uW 0.90%
Potential : 98.5uW 9.08% 98.2uW 8.99%
Observability Don't Care :
Auto-accepted : Topology based auto-accept#
Strengthened : 0W 0.00% 28.9nW 0.00%
Potential : 0W 0.00% 28.9nW 0.00%
Low activity enabled register :
Auto-accepted (width <= 16bits) : 4.81uW 0.44% 4.8uW 0.44%
Potential : 4.81uW 0.44% 4.8uW 0.44%

# All viable reductions accepted regardless of power saving.

----------------------------------------------------------------------------

Memory Memory
Memory Techniques Dynamic Saving Total Saving
----------------------------------------------------------------------------
Split memory words : 3.19mW 25.66% 3.52mW 21.42%
Gate Memory Clock :
Auto-accepted : 6.39mW 51.38% 6.39mW 38.93%
Potential : 6.39mW 51.38% 6.39mW 38.93%
----------------------------------------------------------------------------

Notes:

• The local explicit clock enable ('lec') information describe the savings when running standard
synthesis clock gating using constraints like 'minimum bit width'. PowerArtist constraints
information explains what you may save if you supply the generated constraint file to your
synthesis tools to further eliminate registers that may meet physical constraints but cannot
save enough power to warrant clock gating them.

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 Understanding Power Reduction through Text Report

• The low activity non-enabled register ('lnr') information describes what you save given the
LNR constraints you supplied that are automatically accepted for rewrite versus the total
potential savings you get if all registers were considered.
• The Prism ('prism') information describes what you save given the constraints you supplied
that were automatically accepted for rewrite versus the most you can save if you create the
missing optimal enables. Comparing these two results indicates how far you are from reaching
the maximum you can save given the simulation data you supplied.

5.14.2. Power Reduction Clock Gating Report

The reduction clock gating report 'reduce_power_cg.rpt' provides detailed information about
clock gating in this design. The generated report is described in the Clock Gating Report (p. 356)
section.

5.14.3. Observability Don't Care (ODC) Report

The Observability Don't Care (ODC) report 'reduce_power_odc_by_enable.rpt' provides
information about the clock enable expressions. The generated report is described in the Reporting
Results (p. 320) section.

5.14.4. Blocks Activity Ranking Report

Block Activity Ranking (BAR) analysis highlights redundant clock and data activity at the interfaces of
each user-defined block in a design. The generated reports contain block-specific data and are
described in the Blocks Activity Ranking Report (p. 355) section.

The following reports are generated and saved in the 'reports' directory:

• Comma-Separated Value (.CSV) Report (block_clock_data_activity.rpt.csv)

• Text (.TXT) Report (block_clock_data_activity.rpt.txt)

5.14.5. Reviewing Power Reports from the Power Database

The reports described in this section are generated by accessing the power database (generated
during power reduction) using APSH container commands. The reports are generated in the 'reports'
directory and are similar to the corresponding reports generated during power analysis.

• The 'reportPower' Command Report

For complete details of the report named 'reportPower.rpt', refer to The 'reportPower'
Command (p. 63) section.

• The 'reportSummary' Command Report

For complete details of the report named 'reportSummary.rpt', refer to The 'reportSummary'
Command (p. 64) section.

• The Clock Gating Efficiency Report

For complete details of the report named 'reportCGEfficiency.rpt', refer to The

'report_cg_efficiency' Command (p. 65) section.

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Chapter 6: PowerArtist Tutorial Part III: Advanced
Features
6.1. Introduction
This chapter showcases the following advanced features of PowerArtist:

• Vectorless Power Analysis and Reduction (p. 95)

• Gate-level Power Analysis (p. 101)
– Power Analysis with Gate Stimulus (p. 102)
– Power Analysis with RTL Stimulus (p. 106)
• UPF/CPF-based Power Analysis (p. 110)
– UPF-based Power Analysis (p. 111)
– CPF-based Power Analysis (p. 115)
• Physically-Aware RTL Power Accuracy with PACE Models (p. 119)
• Generating an RTL Power Model (p. 125)

Note: The PowerArtist tutorials are a feature demonstrator and are not intended as an example on how
to set up PowerArtist on a new design.

6.2. Vectorless Power Analysis and Reduction

Accurate power numbers come from simulation-based analysis, but simulation activity is not available
early in the flow. In the absence of a simulation activity file, vectorless power analysis and power
reduction is an easy way to quickly generate 'what-if' scenarios that give you a good idea of what your
power may be in various situations.

This tutorial showcases how to perform vectorless power analysis and reduction on an RTL design using
PowerArtist. The tutorial focuses on setting vectorless activity for key signals in the design. These include
the frequency and duty cycle of clocks, primary inputs, sequential elements (such as flops and memories),
and additional control signals.

6.2.1. Copying the 'vectorless' Tutorial Files

For the Vectorless tutorial, you need only the 'vectorless' and 'data' directories. To get started,
copy the directories from the following location:
$POWERARTIST_ROOT/tutorial/advanced/vectorless
$POWERARTIST_ROOT/tutorial/data

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PowerArtist Tutorial Part III: Advanced Features

Contents of the 'reduction' Directory

The following table lists the contents of the vectorless tutorial:

Directory Description
Name/FileName
README Describes the basic flow for running this tutorial.
input Contains the following files:

• rxchan.vc - Is the Verilog startup file that tells the HDL

elaborator which Verilog files must be loaded for your design
• idle.vaf - Is the vectorless activity file to set design activity
and represents idle operation mode
• maxpower.vaf - Is the vectorless Activity file to set design
activity and represents high activity switching mode

pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt and is used to
customize the 'pa_shell' settings at multiple levels.
run.tcl A Tcl script to run the vectorless power analysis and reduction tutorial
in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various sub-tasks related
to power analysis and reduction (such as, design elaboration, creating
a vectorless activity file, vectorless power analysis, and vectorless power
reduction).
cleanall A script to remove all the files created while running the 'vectorless'
tutorial.

6.2.2. Power Analysis and Reduction in Vectorless Flow

Running vectorless power analysis and reduction is a simple process, as shown by the following figure:

The main steps in the vectorless flow are controlled by the following commands:

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 Vectorless Power Analysis and Reduction

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. CalculatePower -analysis_type average

Performs average power analysis on your design using vectorless activity file.

3. ReducePower

Performs reduction analysis on your design using vectorless activity file.

6.2.3. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi Vt, design, and library database:
pa_shell % source ./scripts/power_setup.tcl

7. Perform block-level average power calculation:

pa_shell % source ./scripts/average_power.tcl

8. Perform block-level reduction:

pa_shell % source ./scripts/reduce_power.tcl

9. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

10. Exit PowerArtist shell:

pa_shell % exit

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PowerArtist Tutorial Part III: Advanced Features

These steps are explained in detail in the next sections. You can also run all the steps via a single tcl
file (run.tcl):
% pa_shell -tcl run.tcl

6.2.4. Understanding Power Analysis Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl

6.2.5. Generating the Vectorless Activity File (VAF)

The VAF is used to specify activity and duty cycle information for critical signals in the design.

Go to 'input' and open 'idle.vaf', which represents idle operation mode. An excerpt is shown
here:
set top rxchan
SetStimulus -port $top \
-signal_type {primary_input} \
-activity 0

SetStimulus -instance $top \

-instance_type {register} \
-signal_type output \
-activity 0

SetStimulus -instance $top \

-instance_type {latch} \
-signal_type output \
-activity 0

SetStimulus -instance $top \

-instance_type {memory} \
-signal_type output \
-activity 0

SetStimulus -instance $top \

-instance_type {black_box} \
-signal_type output \
-activity 0

SetStimulus -instance $top \

-instance_type icgc_inferred \
-signal_type cg_enable \
-duty 0 \
-activity 0

SetStimulus -instance $top \

-instance_type icgc_instantiated \
-signal_type cg_enable \
-duty 0 \
-activity 0

# set activity on clock nets

#source ./ReadSDC.vaf

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 Vectorless Power Analysis and Reduction

# or set activity/frequency on clock nets using below command

SetStimulus -net {clk} -frequency 5e+07 -duty 0.05
SetStimulus -net {pci_clk} -frequency 5e+07 -duty 0.05

Note: The 'input' directory contains another file 'maxpower.vaf', which represents high activity
switching mode.

6.2.6. Common Setup for Clock Definitions

This step is identical to the step explained in detail in the Common Setup for Clock Definitions (p. 26)
section of the Power Analysis tutorial.

Source 'power_setup.tcl' to set clock-related constraints and enable clock gating:

pa_shell % source ./scripts/power_setup.tcl

6.2.7. Running Block-level Average Power Analysis

This step is identical to the step explained in detail in Running Average Power Analysis (p. 40). The
only difference is that you must specify a vectorless activity file as the design input file.

To specify the vectorless activity file as the design input file (instead of a simulation-based activity
file - FSDB, VCD, or SAIF), use the following command:
-vectorless_input_file <vaf_file_name>

Go to 'scripts' and open 'average_power.tcl'. An excerpt is shown here:

# Calculate the power of the design

CalculatePower -analysis_type average \

-vectorless_input_file ./input/idle.vaf \
-infer_scan_fanouts true \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-average_report_file ./$RPT_DIR/average_power.rpt \
-power_db_name ./$DB_DIR/average_power.pdb \
-average_write_power_db true \
-reset_negative_power true \
-detailed_vertical_report true \
-vertical_report_instances $design \
-save_clock_trees_netlist true \
-calculate_log ./$LOG_DIR/average_power.log

Source 'average_power.tcl' to perform average power analysis on a block:

pa_shell % source ./scripts/average_power.tcl

6.2.8. Running Block-level Power Reduction

This step is identical to the step explained in detail in Running Power Reduction (p. 79). The only
difference is that you must specify a vectorless activity file as the design input file.

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PowerArtist Tutorial Part III: Advanced Features

To specify the vectorless activity file as the design input file (instead of a simulation-based activity
file - FSDB, VCD, or SAIF), use the following command:
-vectorless_input_file <vaf_file_name>

Go to 'scripts' directory and open 'reduce_power.tcl'. An excerpt is shown here:

# Calculate and reduce the average power of the design

# Specify compiled library db

pa_set library_database_dirs ./$DB_DIR/library_db

# Generate RTL power reduction opportunities using vectorless activity file

ReducePower -reduction_report_file ./reports/$design.red_pwr.rpt \
-reduction_hierarchy full \
-reduction_memory_stability_gating true \
-reduction_report_file ./$RPT_DIR/reduce_power.rpt \
-reduction_report_clock_gating_by_instance true \
-reduction_report_clock_gating_enable_efficiency true \
-skip_reduction_list {smw} \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-reset_negative_power true \
-reduction_report_file ./$RPT_DIR/reduce_power.rpt \
-power_db_name ./$DB_DIR/reduce_power.pdb \
-vectorless_input_file ./input/idle.vaf \
-reduction_log ./$LOG_DIR/reduce_power.log

Note: In the above excerpt, the vectorless activity file is specified as the design input file (instead of
a simulation-based activity file - FSDB, VCD, or SAIF) to obtain accurate power numbers.

Source 'reduce_power.tcl' to perform power reduction on a block in the design:

pa_shell % source ./scripts/reduce_power.tcl

6.2.9. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power Analysis
tutorial. Source 'power_reports.tcl' to generate the reports:
pa_shell % source ./scripts/power_reports.tcl

6.2.10. Viewing Results in the PowerArtist Graphical Interface

After running power analysis (average or time-based) and power reduction, you can view the results
in the PowerArtist GUI:

• Power Analysis Results

For the complete details, refer to the Viewing Power Analysis Results in the PowerArtist Graphical
Interface (p. 47) section.
• Power Reduction Results
For the complete details refer to the Viewing Power Reduction Results in the PowerArtist
Graphical Interface (p. 82) section.

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 Gate-level Power Analysis

6.2.11. Understanding the Text Reports

In addition to reviewing the power analysis results in the PowerArtist GUI, you can also review the
results using the text-based power report file(s). The following reports are generated:

• Average Power Analysis Report

The report 'average_power.rpt' is similar to the report generated during average power analysis.
Refer to the Average Power Analysis Report (p. 50) section for complete details of the report.

• Power Reduction Report

The report 'reduce_power.rpt' is similar to the report generated during power reduction. Refer
to the Power Reduction Report (p. 91) section for complete details of the report.

• Power Reduction Clock Gating Report

The report 'reduce_power_cg.rpt' is similar to the clock gating report generated during power
reduction. Refer to the Clock Gating Report (p. 356) section for complete details of the report.

• Observability Don't Care (ODC) Report

The report 'reduce_power_odc_by_enable.rpt' is similar to the Observability Don't Care

(ODC) report generated during power reduction. Refer to the Reporting Results (p. 320) section for
complete details of the report.

• Reports from the Power Database

The reports described in this section are generated by accessing the power database (generated
during power reduction) using APSH container commands. The reports are similar to the
corresponding reports generated during power analysis.

– The 'reportPower' Command Report

For complete details of the report named 'reportPower.rpt', refer to The 'reportPower'
Command (p. 63) section.

– The 'reportSummary' Command Report

For complete details of the report named 'reportSummary.rpt', refer to The

'reportSummary' Command (p. 64) section.

6.3. Gate-level Power Analysis

These tutorials showcase flows where gate-level power analysis can be performed using Gate-level VCD
or the RTL stimulus file using PowerArtist. The following tutorials demonstrate these two gate-level
power analysis techniques:

• Power Analysis with Gate Stimulus (p. 102)

• Power Analysis with RTL Stimulus (p. 106)

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PowerArtist Tutorial Part III: Advanced Features

6.3.1. Copying the 'gate_power' Tutorial Files

For the gate-level tutorial, you need only the 'gate_power' and 'data' directories. To get started,
copy the directories from the following location:
$POWERARTIST_ROOT/tutorial/advanced/gate_power
$POWERARTIST_ROOT/tutorial/data

Contents of the 'gate_power' Directory

The following table lists the contents of the 'gate_power' tutorial:

Directory Name/FileName Description

README Describes the basic flow for running this tutorial.
input Contains the following files:

• txrx_gate.vc - Is the Verilog startup file that

tells HDL elaborator which gate-level design files
must be loaded for your design.
• txrx_rtl.vc - Is the Verilog startup file that
tells HDL elaborator which RTL design files must
be loaded for your design.

mapFile Provides name mapping of RTL net names to gate-level

net names.
pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt
and is used to customize the 'pa_shell' settings at
multiple levels.
run_with_gate_activity.tcl A Tcl script to run power analysis using gate-level VCD
tutorial in batch mode.
run_with_rtl_activity.tcl A Tcl script to run power analysis using gate-level RTL
stimulus tutorial in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various
sub-tasks related to this tutorial (such as, design scripts
elaboration, average and time-based power calculation
using gate-level simulation activity, and mapping RTL
activity to gate netlist).
cleanall A script to remove all the files created while running
the 'gate-level' power analysis tutorial.

6.3.2. Power Analysis with Gate Stimulus

This tutorial showcases a flow where you can perform gate-level analysis on a fully synthesized netlist
or a placed and routed design. This design is a synthesized version of the RTL design used in the
Power Analysis tutorial.

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 Gate-level Power Analysis

This section highlights only those inputs that are unique to this tutorial and highlights various steps
involved starting from design elaboration to gate-level power verification using activity analysis (with
or without back-annotated parasitics), and finally generation of useful power analysis reports.

6.3.2.1. Understanding the Gate-level Power Analysis with Gate Stimulus Flow
Running gate-level power analysis with a simulation activity file is a simple process, as shown by
the following figure:

The main steps in this flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. GenerateActivityWaveforms

Analyzes the activity file and produces waveform files representing the activity in your
design.

3. CalculatePower
• -analysis_type average - performs average power analysis.
• -analysis_type time_based - performs time-based power analysis.

6.3.2.2. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

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PowerArtist Tutorial Part III: Advanced Features

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up gate-level power - clocks, wire capacitance, design, and library database:
pa_shell %source ./scripts/power_setup.tcl

7. Perform simulation activity analysis:

pa_shell % source ./scripts/activity_analysis.gate_activity.tcl

8. Perform gate-level average power calculation using gate-level simulation activity:

pa_shell % source ./scripts/average_power.gate_activity.tcl

9. Perform gate-level time-based power calculation using gate-level simulation activity:

pa_shell % source ./scripts/time_based_power.gate_activity.tcl

10. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

11. Exit the PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single
tcl file (run_with_gate_activity.tcl):
pa_shell -tcl run_with_gate_activity.tcl

6.3.2.3. Understanding Power Analysis Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

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 Gate-level Power Analysis

6.3.2.4. Running Activity Analysis

This step is identical to the step explained in detail in the Running Activity Analysis for Clock and
Data (p. 31) section of the Power Analysis tutorial. The difference is explained below:

To specify the scenario file, the following command has been included:
-scenario_file <scenario_filename>

Go to 'scripts' and open 'activity_analysis.gate_activity.tcl'. An excerpt is shown

here:
# Generate activity waveforms
GenerateActivityWaveforms \
-scenario_file ./$WORK_DIR/top.scn \
-activity_file ../../data/sim/gate/top.fsdb \
-top_instance txrx_tst.top1
-activity_waveform_group_list { top core pci rxchan txchan } \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_interval_size 15160ps \
-activity_waveform_number_of_intervals 400 \
-activity_waveform_start_time 6071580ps \
-ptcl_output_file ./$RPT_DIR/activity_waveform.ptcl \
-fsdb_output_file ./$RPT_DIR/activity_waveform.fsdb \
-activity_waveform_log ./$LOG_DIR/generate_activity_waveforms.log

Source 'activity_analysis.gate_activity.tcl' to perform activity analysis on a gate-level

design using gate-level stimulus file:
pa_shell % source ./scripts/activity_analysis.gate_activity.tcl

6.3.2.5. Running Average Power Analysis

This step is identical to the step explained in detail in the Running Average Power Analysis (p. 40)
section of the Power Analysis tutorial. The difference is explained below:

To run average power analysis on a gate-level netlist using gate-level stimulus, the following
command has been included:
pa_set gate_level_netlist true

Go to 'scripts' and open 'average_power.gate_activity.tcl'. An excerpt is shown here:

# Calculate gate-level power using gate-level activity file

# Enable power computation using RTL activity on gate netlist

pa_set gate_level_netlist true
<snip>

Source 'average_power.gate_activity.tcl' to perform average power analysis on a

gate-level design using gate-level stimulus file:
pa_shell % source ./scripts/average_power.gate_activity.tcl

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6.3.2.6. Running Time-based Power Analysis

This step is identical to the step explained in detail in the Running Time-Based Power Analysis (p. 44)
section of the Power Analysis tutorial. The difference is explained below:

To run time-based power analysis on a gate-level netlist using gate-level stimulus, the following
command has been included:
-gate_level_netlist true

Source 'time_based_power.gate_activity.tcl' to perform time-based power analysis on

a gate-level design using gate-level stimulus file:
pa_shell % source ./scripts/time_based_power.gate_activity.tcl

6.3.2.7. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power
Analysis tutorial. Source 'power_reports.tcl' to generate the reports:
pa_shell % source ./scripts/power_reports.tcl

6.3.3. Power Analysis with RTL Stimulus

This tutorial showcases a flow where gate-level power analysis is performed with an RTL stimulus file
using PowerArtist and highlights the various steps involved starting from design elaboration to power
analysis using a name mapping file, and finally generation of useful power analysis reports.

6.3.3.1. About Name Mapping

PowerArtist can perform power analysis on gate-level design using an RTL stimulus. When this
happens, the RTL hierarchy is flattened and the RTL nets that are inferred as registers are transformed
to gate-level instances. Therefore, it is important to map as many RTL net names to gate-level net
names as possible. The activity of the gate-level mapped nets is determined during power calculation
using the RTL toggles.

6.3.3.2. Understanding the Gate-level Power Analysis with RTL Stimulus Flow
Running gate-level power analysis with a simulation activity file is a simple process, as shown by
the following figure:

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 Gate-level Power Analysis

The main steps in this flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. CalculatePower -analysis_type average

Performs average power analysis on your design.

6.3.3.3. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up gate-level power:

pa_shell %source ./scripts/power_setup.tcl

7. Read the name mapping file to map RTL activity to gate netlist:

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PowerArtist Tutorial Part III: Advanced Features

pa_shell % source ./scripts/read_map_file.tcl

8. Perform gate-level average power calculation using RTL activity:

pa_shell % source ./scripts/average_power.rtl_activity.tcl

9. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

10. Exit the PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single
tcl file ('run_with_rtl_activity.tcl'):
% pa_shell -tcl run_with_rtl_activity.tcl

6.3.3.4. Understanding Power Analysis Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to start the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

6.3.3.5. Generating and Reading the Name Mapping File

In the 'rtlsim2gate' flow, you have a gate-level netlist, but the activity file is from its corresponding
RTL netlist. To annotate the activity correctly, PowerArtist needs to map the RTL and gate points
correctly. A mapping file must be provided to enable this. You can use one of the following ways
to generate the mapping file:

• Third party verification tools

You can generate a name mapping file using third party formal verification tools. Then, you
can use this script to enable PowerArtist to read the name mapping file.

Go to 'scripts' and open 'read_map_file.tcl'. An excerpt is shown here:

# Read RTL to Gate name map file
SetNameMapFile -map_file mapFile -format conformal

Source 'read_map_file.tcl' to map RTL nets names to gate-level net names and enable
name mapping:
pa_shell % source ./scripts/read_map_file.tcl

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• External utility provided in PowerArtist

The 'atcl_GenerateMapfile' is an AE-ware that helps in generating the mapping file by

parsing through the VCD file and pdb and generating the matching names. The mapping
file 'rtl2gate.map.points' is generated and stored in the following location:
pa_shell_work/Mapping/rtl2gate.map.points

The 'SetNameMapFile' command automatically reads the name mapping file

'rtl2gate.map.points' generated by the AE-ware.

Note: Contact your local support AE for the Application Note of this AE-ware.

6.3.3.6. Running Average Power Analysis

This step is identical to the step explained in detail in the Running Average Power Analysis (p. 40)
section of the Power Analysis tutorial. The difference is explained below:

To run power analysis on a gate-level netlist using an RTL stimulus, use the following commands:
pa_set use_rtl_sim_data true
pa_set gate_level_netlist true

Go to 'scripts' and open 'average_power.rtl_activity.tcl'. An excerpt is shown here:

# Calculate gate-level power using RTL activity file

# Enable power computation using RTL activity on gate netlist

pa_set use_rtl_sim_data true
pa_set gate_level_netlist true

Source 'average_power.rtl_activity.tcl' to perform average power analysis on a gate-level

design by using the RTL stimulus file:
pa_shell % source ./scripts/average_power.rtl_activity.tcl

6.3.3.7. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power
Analysis tutorial. Source 'power_reports.tcl' to generate the reports:
pa_shell % source ./scripts/power_reports.tcl

6.3.4. Viewing Results in the PowerArtist Graphical Interface

After running power analysis (average or time-based), you can view the results in the PowerArtist
GUI. Refer to the Viewing Power Analysis Results in the PowerArtist Graphical Interface (p. 47) section
for the complete details.

6.3.5. Understanding the Text Reports

In addition to reviewing the power analysis results in the PowerArtist GUI, you can also review the
results using the text-based power report file(s). The following text reports are generated:

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• Average Power Analysis Report

The report 'average_power.rtl_activity.rpt' is similar to the report generated during

average power analysis. Refer to the Average Power Analysis Report (p. 50) section for complete
details of the report.

• The 'reportPower' Command Report

For complete details of the report named 'reportPower.rtl_activity.rpt', refer to

The 'reportPower' Command (p. 63) section.

6.4. UPF/CPF-based Power Analysis

Power management techniques like power gating, voltage islands are commonly used in design flows
to manage static power consumption in semiconductor designs. Existing HDLs do not have a way to
model the power distribution and power management of a design. Unified Power Format (UPF) and
Common Power Format (CPF) are two industry standard formats that enable you to define the power
architecture of designs. These formats are portable across design flows.

PowerArtist allows you to perform average power analysis using UPF/CPF to estimate the power of
power gated designs, without requiring low power simulations. Time-based power analysis in PowerArtist
enables users to analyze the power profile of various power domains.

Designers can also ensure that the power saved by power management techniques is more than the
power that would be consumed by cells like isolation cells and retention cells after implementation.

The following tutorials demonstrate the use of UPF and CPF commands for power analysis using
PowerArtist:

• UPF-based Power Analysis (p. 111)

• CPF-based Power Analysis (p. 115)

6.4.1. Copying the 'upf_cpf' Tutorial Files

For the gate-level tutorial, you need only the 'upf_cpf' and 'data' directories. To get started, copy
the directories from the following location:
$POWERARTIST_ROOT/tutorial/advanced/upf_cpf
$POWERARTIST_ROOT/tutorial/data

Contents of the 'upf_cpf' Directory

The following table lists the contents of the 'upf_cpf' tutorial:

Directory Description
Name/FileName
README Describes the basic flow for running this tutorial.
input Contains the following file:

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Directory Description
Name/FileName
txrx.vc - Is the Verilog startup file that tells the HDL elaborator
which Verilog files must be loaded for your design.
pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt and is used
to customize the 'pa_shell' settings at multiple levels.
run_cpf.tcl A Tcl script to run average power analysis using a CPF file in batch
mode.
run_upf.tcl A Tcl script to run average power analysis using a UPF file in batch
mode.
scripts Tcl scripts called by 'run.tcl' that perform various sub-tasks
related to power analysis (such as, design elaboration, specifying
UPF constraints, and average power analysis).
cleanall A script to remove all the files created while running the 'upf_cpf'
power analysis tutorial.

6.4.2. UPF-based Power Analysis

PowerArtist allows you to define techniques like power gating and multiple voltage domain constraints
using UPF. Power gating analysis is performed by defining different power domains in UPF and then
establishing power and ground connections for different supply nets as shown in the following figure:

Domains are defined for 'PD_TOP' and 'PD_RX', supply nets 'VDD' and 'VSS' are used for connections,
'PD_TX' is not shown in the figure. You can selectively switch the supply on and off using power

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switch ['SW'] as shown in the figure. Retention strategy is defined for 'PD_RX' and 'PD_TX', which is
used to retain the state of power in which the cell was before shutting it off/on. You can also define
isolation strategies to isolate power-off domains from powered-on domains.

6.4.2.1. The 'top.upf' File

Use 'top.upf' to create the setup required to run UPF-based power analysis. It is located in the
following directory:
$POWERARTIST_ROOT/tutorial/data/upf_cpf/top.upf

6.4.2.2. Understanding the UPF Flow

Running average power analysis using a UPF file is as shown by the following figure:

The main steps in this flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. CalculatePower -analysis_type average

Performs average power analysis on your design.

6.4.2.3. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

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 UPF/CPF-based Power Analysis

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi Vt, design, and library database:
pa_shell %source ./scripts/power_setup.tcl

7. Define root supplies

pa_shell % source ./scripts/set_root_supplies.tcl

8. Perform UPF-based average power analysis:

pa_shell % source ./scripts/average_power.upf.tcl

9. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

10. Exit the PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single
tcl file (run_upf.tcl):
% pa_shell -tcl run_upf.tcl

6.4.2.4. Understanding Power Analysis Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

6.4.2.5. Define Root Supply Drivers

Use the 'DefineRootSupply' command to define the root supply drivers and enable UPF/CPF-based
power analysis. You can specify more than one 'DefineRootSupply' command. For example, one
for VDD (primary power) and one for VSS (primary ground).

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Go to 'scripts' and open 'set_root_supplies.tcl'. An excerpt is shown here:

# Specify supply settings
DefineRootSupply -name VDD -voltage 1.1 -on 1
DefineRootSupply -name VSS -voltage 0 -on 1

Source set_root_supplies.tcl to define the root supply drivers:

pa_shell % source ./scripts/set_root_supplies.tcl

6.4.2.6. Running Average Power Analysis

This step is identical to the step explained in detail in the Running Average Power Analysis (p. 40)
section of the Power Analysis tutorial. The differences are explained below:

• To specify the logical liberty library name in which the power analyzer searches for the wire
load models, use the following command:
pa_set wireload_library power_gate

This is useful when reading multiple libraries that can contain wire load models.

• To read the power constraints specified in the UPF file and enable UPF-based average power
analysis, use the following command:
-upf_in_file <upf_file_name>

Go to 'scripts' and open 'average_power.upf.tcl'. An excerpt is shown here:

<snip>
# Calculate average power
CalculatePower -analysis_type average \
-upf_in_file ../../data/upf_cpf/$design.upf \
-gaf_file ./$WORK_DIR/${design}_upf.gaf \
-use_existing_gaf true \
-infer_scan_fanouts true \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-average_report_file ./$RPT_DIR/average_power.upf.rpt \
-average_report_options aVip \
-detailed_vertical_report true \
-vertical_report_instances $design \
-power_db_name ./$DB_DIR/average_power.upf.pdb \
-save_clock_trees_netlist true \
-wireload_library power_gate \
-calculate_log ./$LOG_DIR/average_power.upf.log

Source 'average_power.upf.tcl' to perform average power analysis on a gate-level design

by using the RTL stimulus file:
pa_shell % source ./scripts/average_power.upf.tcl

6.4.2.7. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power
Analysis tutorial. Source 'power_reports.tcl' to generate the reports:

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 UPF/CPF-based Power Analysis

pa_shell % source ./scripts/power_reports.tcl

6.4.3. CPF-based Power Analysis

PowerArtist allows you to define power gating and multiple voltage domain constraints using CPF
for power analysis. You can also use CPF to define power domains for different blocks and sub-blocks.
The following figure shows different domains defined for 'PD_TOP', 'PD_RX' and 'PD_TX':

Nominal operating conditions are set with specified voltages, and the power supply and ground nets
are provided using the CPF file. PowerArtist can perform power analysis (average or time-based) using
CPF.

Note: You can use PowerArtist's proprietary commands with CPF commands but cannot use CPF and
UPF commands together.

6.4.3.1. The 'top.cpf' File

Use 'top.cpf' to create the setup required to run CPF-based power analysis. It is located in the
following directory:
$POWERARTIST_ROOT/tutorial/data/upf_cpf/top.cpf

6.4.3.2. Understanding the CPF Flow

Running average power analysis using a CPF file is as shown by the following figure:

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The main steps in this flow are controlled by the following commands:

1. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

2. CalculatePower -analysis_type average

Performs average power analysis on your design.

6.4.3.3. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi Vt, design, and library database:
pa_shell %source ./scripts/power_setup.tcl

7. Perform CPF-based average power analysis:

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 UPF/CPF-based Power Analysis

pa_shell % source ./scripts/average_power.cpf.tcl

8. Generate power reports:

pa_shell % source ./scripts/power_reports.tcl

9. Exit the PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single
tcl file ('run_cpf.tcl'):
% pa_shell -tcl run_cpf.tcl

6.4.3.4. Understanding Power Analysis Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to start the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

6.4.3.5. Running Average Power Analysis

This step is identical to the step explained in detail in the Running Average Power Analysis (p. 40)
section of the Power Analysis tutorial. The difference is explained below:

To read the power constraints specified in the CPF file and enable CPF-based average power analysis,
use the following command:
-cpf_in_file <cpf_file_name>

Go to 'scripts' and open 'average_power.cpf.tcl'. An excerpt is shown here:

<snip>
# Calculate average power
CalculatePower -analysis_type average \
-cpf_in_file ../../data/upf_cpf/$design.cpf \
-gaf_file ./$WORK_DIR/${design}_cpf.gaf \
-use_existing_gaf true \
-infer_scan_fanouts true \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-average_report_file ./$RPT_DIR/average_power.cpf.rpt \
-average_report_options aVip \
-detailed_vertical_report true \
-vertical_report_instances $design \
-power_db_name ./$DB_DIR/average_power.upf.pdb \
-save_clock_trees_netlist true \
-wireload_library power_gate \
-calculate_log ./$LOG_DIR/average_power.cpf.log

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Source 'average_power.cpf.tcl' to perform average power analysis on a gate-level design

by using the RTL stimulus file:
pa_shell % source ./scripts/average_power.cpf.tcl

6.4.3.6. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power
Analysis tutorial. Source 'power_reports.tcl' to generate the reports:
pa_shell % source ./scripts/power_reports.tcl

6.4.4. Viewing Results in the PowerArtist Graphical Interface

After running power analysis (average or time-based), you can view the results in the PowerArtist
GUI. Refer to the Viewing Power Analysis Results in the PowerArtist Graphical Interface (p. 47) section
for the complete details.

6.4.5. Understanding the Text Reports

In addition to reviewing the power analysis results in the PowerArtist GUI, you can also review the
results using the text-based power report file(s). The following text reports are generated:

• Average Power Analysis Reports

– average_power.upf.rpt - after UPF-based power analysis
– average_power.cpf.rpt - after CPF-based power analysis

These reports are similar to the report generated during average power analysis. The following
section of the report is unique to the UPF (and CPF-based) power analysis text report:
5. Power Domain Summary
=======================

Domain top.PD_top
-----------------
Library power_gate
File: ../../data/libraries/power_gate.lib
Library iopad
File: ../../data/libraries/iopad.lib
Library RETENTION_EXAMPLE_LIB
File: ../../data/libraries/retention.lib
Library DP256x32
File: ../../data/libraries/mem_DP256x32.lib
Library DP512x32
File: ../../data/libraries/mem_DP512x32.lib
Virtual Supply: VSS
Library Supplies: None
Estimation Voltage: 0V (from TCL file)
On condition: 1
Static Power: 0W
Dynamic Power: 0W
Virtual Supply: VDD
Library Supplies: None
Estimation Voltage: 1.1 V (from TCL file)
On condition: 1||1
Static Power: 5.69mW
Dynamic Power: 4.05mW

Domain top.PD_top_rx

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 Physically-Aware RTL Power Accuracy with PACE Models

--------------------
...

Domain top.PD_top_tx
--------------------
<snip>

This section of the report provides information on the power domain's setup for the different
blocks in the design. It summarizes all the domains defined in the UPF (or CPF) file with their
on conditions, static and dynamic power, and user-defined voltage estimation for that domain.
Refer to the Understanding Power Analysis through Text Reports (p. 50) section for complete
details of the remaining sections of the reports.

• The reportPower Command Reports

– reportPower.upf.rpt - after UPF-based power analysis
– reportPower.cpf.rpt - after CPF-based power analysis

These reports are generated by accessing the power database (generated during power analysis)
using APSH commands. Refer to the The 'reportPower' Command (p. 63) section for complete
details of the report.

6.5. Physically-Aware RTL Power Accuracy with PACE Models

This tutorial showcases the generation and consumption of a PACE (PowerArtist Calibration and
Estimation) model and highlights the various steps involved starting from design elaboration, PACE
model generation, vector analysis, average power analysis using the generated PACE model, and finally
generation of useful power analysis reports.

6.5.1. About PACE

PACE is an acronym for PowerArtist calibration and estimation. A PACE model is used to achieve
accurate power numbers at the RTL level. PowerArtist reads a post-layout, post-CTS identical design
to estimate clock tree models and capacitance to generate PACE model. This generated PACE model
can then be used on an RTL design for power analysis to obtain power numbers, which have good
correlation with power numbers at gate-level.

6.5.2. Copying the 'pace' Tutorial Files

For this tutorial, you need only the 'pace' and 'data' directories. To get started, copy the directories
from the following location:
$POWERARTIST_ROOT/tutorial/advanced/pace
$POWERARTIST_ROOT/tutorial/data

Contents of the 'pace' Directory

The following table lists the contents of the 'pace' tutorial:

Directory Name/FileName Description

README Describes the basic flow for running this tutorial.

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Directory Name/FileName Description

input Contains the following files:

• txrx_gate.vc - Is the Verilog startup file that

tells HDL elaborator which gate-level design
files must be loaded for your design.
• txrx_rtl.vc - Is the Verilog startup file that
tells HDL elaborator which RTL design files must
be loaded for your design.

pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt

and is used to customize the 'pa_shell' settings at
multiple levels.
run_pace_generation.tcl A Tcl script to generate and write the PACE model in
batch mode.
run_rtl_power_with_pace.tcl A Tcl script to use the generated PACE model and
perform average power analysis in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various
sub-tasks related to this tutorial (such as, design
elaboration, generating a pace model, vector analysis,
and average power analysis using the generated pace
mode).
cleanall A script to remove all the files created while running
the 'pace' tutorial.

6.5.3. Understanding the PACE Flow

Running power analysis in the PACE flow is as shown by the following graphic:

The main steps in the power reduction flow are controlled by the following commands:

1. Generating the PACE Model:

a. Elaborate

Compiles the gate-level netlist into an internal binary format called the scenario file.

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 Physically-Aware RTL Power Accuracy with PACE Models

b. WriteTechnologyFile

Generates the PACE model.

2. Using the PACE Model:

a. Elaborate

Compiles the HDL design description into an internal binary format called the scenario file.

b. CalculatePower -analysis_type average

Performs average power analysis on your design.

6.5.4. Understanding the Tutorial Steps

To run the tutorial, you will perform the following steps:

• PACE model generation using a representative post-layout design:

1. Invoke PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell % source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform elaboration for the representative post-layout gate netlist:

pa_shell % source ./scripts/elaborate_gate.tcl

5. Read SDC files:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up for PACE model generation - clocks, buffers, design, and library database:
pa_shell % source ./scripts/power_setup.tcl

7. Generate a PACE model:

pa_shell % source ./scripts/generate_pace_model.tcl

8. Exit PowerArtist shell:

pa_shell % exit

• PACE model consumption:

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1. Invoke PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell % source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform elaboration (RTL design):

pa_shell % source ./scripts/elaborate_rtl.tcl

5. Read SDC files:

pa_shell % source ./scripts/read_sdc.tcl

6. Set up RTL power - clocks, multi VT, design, and library database:
pa_shell % source ./scripts/power_setup.tcl

7. Perform average power calculation using PACE:

pa_shell % source ./scripts/average_power.tcl

8. Generate additional power report:

pa_shell % source ./scripts/power_reports.tcl

9. Exit PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via the following
tcl files:
% pa_shell -tcl run_pace_generation.tcl
% pa_shell -tcl run_rtl_power_with_pace.tcl

6.5.5. Generating the PACE Model

6.5.5.1. Understanding PACE Model Generation Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate_gate.tcl

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pa_shell % source ./scripts/read_sdc.tcl

pa_shell % source ./scripts/power_setup.tcl

6.5.5.2. Writing the PACE Model

PACE file or the '.tech' file is an encrypted file generated using the 'WriteTechnologyFile' command
on a gate-level netlist.

Specify these options to generate the PACE model:

• To disable estimation of inter/intra-module net capacitances, use the following option:

-no_module_net_capacitances true

• To specify a PACE technology file for capacitance estimation, use the following option:
-power_tech_file <filename>

Capacitance estimation using PACE overrides capacitance estimation using wire load models.

• To specify the name for the log file, use the following option:
-tech_file_log <filename>

• To generate capacitance model, clock tree model, or both in a PACE model, use the following
option:
-generate_pace_model_category [cap | clock | all]

• The 'ReadParasitics' command is used to read the SPEF file with a specific hierarchical
instance in the design. The instance name must be fully rooted (that is, it must contain the
top module name). In PowerArtist, a full-stop ('.') separates the levels of hierarchy.

• The 'reportPaceInfo' command provides a description of how the PACE model was generated
and what the PACE model contains.

• The 'pacePlotCapTables' command plots the capacitance chart for various categories for a
given range of fanout.

Go to 'scripts' directory and open 'generate_pace_model.tcl'. An excerpt is shown here:

# Generate PACE model

ReadParasitics -path $design -file ../../data/spef/design.spef.gz

WriteTechnologyFile \
-top $design \
-power_tech_file ./$WORK_DIR/pace.tech \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-generate_pace_model_category all \
-default_output_load 1e-12
-no_module_net_capacitances true \
-scenario_file ./$WORK_DIR/$design.gate.scn \
-tech_file_log ./$LOG_DIR/write_pace_model.log \

reportPaceInfo -in ./$WORK_DIR/pace.tech -out ./$RPT_DIR/pace_info.rpt

pacePlotCapTables -png pace.png -in ./$WORK_DIR/pace.tech

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Source 'generate_pace_model.tcl' to generate the pace model:

pa_shell % source ./scripts/generate_pace_model.tcl

6.5.6. Using the PACE Model

6.5.6.1. Understanding PACE Model Consumption Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate_rtl.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

6.5.6.2. Running Average Power Analysis using PACE

This step is identical to the step explained in detail in the Running Average Power Analysis (p. 40)
section of the Power Analysis tutorial. The difference is explained below:

To use the generated PACE model or '.tech' file for power analysis, the following command is
included:
pa_set power_tech_file <pace_file_name>

Go to 'scripts' and open 'average_power.tcl'. An excerpt is shown here:

<snip>
# Specify PACE model
pa_set power_tech_file ./$WORK_DIR/pace.tech

# Calculate average power using PACE model

CalculatePower -analysis_type average \
-use_existing_gaf true \
-gaf_file ./$WORK_DIR/$design.gaf \
-default_output_load 1e-15 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-infer_scan_fanouts true \
-average_report_file ./$RPT_DIR/average_power.rpt \
-average_report_options agip \
-detailed_vertical_report true \
-vertical_report_instances $design \
-power_db_name ./$DB_DIR/average_power.pdb \
-save_clock_trees_netlist true \
-calculate_log ./$LOG_DIR/average_power.log

Source 'average_power.tcl' to perform average power analysis on a chip-level design using a

PACE model:
pa_shell % source ./scripts/average_power.tcl

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 Generating an RTL Power Model

6.5.6.3. Generating Additional Power Reports

This step is identical to the Generating Additional Power Reports (p. 43) section of the Power
Analysis tutorial. Source 'power_reports.tcl' to generate the reports:
pa_shell % source ./scripts/power_reports.tcl

6.5.7. Viewing Results in the PowerArtist Graphical Interface

After running power analysis (average or time-based), you can view the results in the PowerArtist
GUI. Refer to the Viewing Power Analysis Results in the PowerArtist Graphical Interface (p. 47) section
for the complete details.

6.5.8. Understanding the Text Reports

In addition to reviewing the power analysis results in the PowerArtist GUI, you can also review the
results using the text-based reports file(s) created in the 'reports' directory. The following text
reports are generated:

• PACE Report

The report 'pace_info.rpt' provides a description of how the PACE model was generated
and what the PACE model contains.

• Average Power Analysis Report

The report 'average_power.rpt' is similar to the report generated during average power
analysis. Refer to the Average Power Analysis Report (p. 50) section for complete details of
the report.

• Reports from the Power Database

The reports described in this section are generated by accessing the power database (generated
during power reduction) using APSH container commands. The reports are similar to the
corresponding reports generated during power analysis.

– The 'reportPower' Command Report

For complete details of the report named 'reportPower.rpt', refer to The

'reportPower' Command (p. 63) section.

– The 'reportSummary' Command Report

For complete details of the report named 'reportSummary.rpt', refer to The

'reportSummary' Command (p. 64) section.

6.6. Generating an RTL Power Model

This tutorial showcases how to generate an RTL power model using PowerArtist and highlights various
steps involved starting from design elaboration, RTL power model generation, and finally generation
of useful reports.

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PowerArtist Tutorial Part III: Advanced Features

6.6.1. About RPM

The RTL Power Model (RPM) enables Power Delivery Network (PDN) planning early in the design flow.
RPM is a direct interface between PowerArtist and RedHawk.

RPM is generated using RTL data well before layout data is available. It identifies realistic power-related
worst-case vectors from thousands of RTL simulation cycles along with other key power-related
parameters that affect the power grid. This enables early right-sizing of the power grid. RPM also
enables better coverage for power grid sign-off analysis by focusing RedHawk on the largest change
in power (or di/dt) and largest peak power cycles.

6.6.2. Copying the 'rpm' Tutorial Files

For this tutorial, you need only the 'rpm' and 'data' directories. To get started, copy the directories
from the following location:
$POWERARTIST_ROOT/tutorial/advanced/rpm
$POWERARTIST_ROOT/tutorial/data

Contents of the 'rpm' Directory

The following table lists the contents of the 'rpm' tutorial:

Directory Description
Name/FileName
README Describes the basic flow for running this tutorial.
input Contains the following file:

txrx.vc - Is the Verilog startup file that tells the HDL elaborator
which Verilog files must be loaded for your design.
pa_shell.ini Is the initialization file that sets the 'pa_shell' prompt and is used
to customize the 'pa_shell' settings at multiple levels.
run.tcl A Tcl script to run the RPM tutorial in batch mode.
scripts Tcl scripts called by 'run.tcl' that perform various sub-tasks
related to this tutorial (such as, design elaboration, vector analysis,
and average power analysis).
cleanall A script to remove all the files created while running the 'rpm'
tutorial.

6.6.3. Understanding the RPM Flow

The following figure shows how PowerArtist generates an RPM, which is an input to RedHawk:

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 Generating an RTL Power Model

When PowerArtist generates an RPM, it performs the following three steps:

1. RTL inferencing

2. Power-critical frame selection

3. RPM generation

The resulting RPM contains the following types of information:

• Activity for selected power critical nets

• Estimated parasitics (R, C)
• Average and per-cycle power numbers

6.6.4. Understanding the Tutorial Steps

To run the tutorial, perform the following steps:

1. Invoke the PowerArtist shell:

pa_shell

2. Set up common design identifiers and directories for log and report files:
pa_shell $ source ./scripts/setup.tcl

3. Compile libraries into a binary database:

pa_shell % source ./scripts/libraries.tcl

4. Perform HDL elaboration:

pa_shell % source ./scripts/elaborate.tcl

5. Read SDC file:

pa_shell % source ./scripts/read_sdc.tcl

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6. Set up for RPM generation:

pa_shell % source ./scripts/power_setup.tcl

7. Generate RPM:
pa_shell % source ./scripts/create_rpm.tcl

8. Exit PowerArtist shell:

pa_shell % exit

These steps are explained in detail in the next sections. You can also run all the steps via a single tcl
file (run.tcl):
% pa_shell -tcl run.tcl

6.6.5. Understanding RPM Generation Setup

This step is identical to the step explained in detail in the Understanding Power Analysis Setup (p. 24)
section of the Power Analysis tutorial.

Type 'pa_shell' to launch the PowerArtist shell and then source the following files:
pa_shell % source ./scripts/setup.tcl
pa_shell % source ./scripts/libraries.tcl
pa_shell % source ./scripts/elaborate.tcl
pa_shell % source ./scripts/read_sdc.tcl
pa_shell % source ./scripts/power_setup.tcl

6.6.6. Generating the RPM

Use the 'CreateRPM' command to generate an RPM. The command performs fastframe analysis on
the FSDB to generate events with worst case scenario for high di/dt and peak power. When
'CreateRPM' runs, it performs the following critical steps:

1. It determines the parasitic capacitance associated with the nets in your design and the counts
of all the cells that are used during time-based power analysis of your design.

2. It performs a rapid power-based frame selection that identifies the di/dt and peak power
frames.

3. It creates the RPM. The RPM is actually a directory with the 'rpm_model_name' you specified.
You can copy this directory anywhere you need to, but you must not alter the contents.

Go to 'scripts' and open 'create_rpm.tcl'. An excerpt is shown here:

#Create RTL Power Model
CreateRPM \
-rpm ./$RPT_DIR/top_rpm \
-rpm_comment "RPM Power Model for design top" \
-activity_file ../../data/sim/rtl/top.fsdb
-top_instance txrx_tst.top1 \
-active_edge positive \
-wireload_library hvt \
-time_based_write_power_db false \

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 Generating an RTL Power Model

-default_output_load 1e-12 \
-default_transition_time 50e-12 \
-default_clock_transition_time 20e-12 \
-rpm_log_file ./$LOG_DIR/create_rpm.log

Source 'create_rpm.tcl' to generate the RPM and the waveforms:

pa_shell % source ./scripts/create_rpm.tcl

6.6.7. Viewing the RPM Information

The 'CreateRPM' command generates a directory named 'top_rpm' in the 'reports' directory that
contains the following files:

• didt.fsdb
• peak.fsdb
• rpm.info
• rpm.power
• rpm.toggle

The file 'rpm.info' provides supply info for 'di/dt' and 'cycle power'. An excerpt is shown
below:
RPM Version: 4.4
Modules: top
Comment: RTL Power Model for design top
Average power for supply OtherVirtualSupplies_top_vdd_1.1 (1.1) = 0.0014917
Average power for supply VDD_M1 (1.1) = 0.0201294
Average power for supply VDD_io (1.1) = 0.00119774
Average power for supply VDD_M2 (1.1) = 0.00790979
Average power for supply VDD (1.1) = 0.0020225
Average power for supply OtherVirtualSupplies_top_VSS_0 (0) = 0
Tick time: 1e-11
Frame: DIDT
Start time: 9.3613e-06 (936130)
Finish time: 9.6645e-06 (966450)
Presim interval: 3.032e-07 (30320)
Average leakage for supply OtherVirtualSupplies_top_vdd_1.1: 0.000620232
Average power for supply OtherVirtualSupplies_top_vdd_1.1: 0.000962828
Peak power for supply OtherVirtualSupplies_top_vdd_1.1: 0.00195548
Average leakage for supply VDD_M1: 0.00125371
Average power for supply VDD_M1: 0.00828784
Peak power for supply VDD_M1: 0.0109408
Average leakage for supply VDD_io: 4.36528e-05
Average power for supply VDD_io: 0.000947266
Peak power for supply VDD_io: 0.00120323
Average leakage for supply VDD_M2: 0.00272101
Average power for supply VDD_M2: 0.00844438
Peak power for supply VDD_M2: 0.00980323
Average leakage for supply VDD: 1.68193e-06
Average power for supply VDD: 0.000253165
Peak power for supply VDD: 0.00202231
Average leakage for supply OtherVirtualSupplies_top_VSS_0: 0
Average power for supply OtherVirtualSupplies_top_VSS_0: 0
Peak power for supply OtherVirtualSupplies_top_VSS_0: 0
Frame: CYCLE_POWER
<snip>

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PowerArtist Tutorial Part III: Advanced Features

6.6.8. Generating and Viewing Power Waveforms for Selected RPM Frames
You can generate waveforms of the total power profile by using the following command:
% rpminfo -r top_rpm

The output of the above command is as shown below:

Copyright 1995-2015 by ANSYS, Inc.
DIDT avg: 0.0189003
CYCLE_POWER avg: 0.0268345

The 'rpminfo' command also generates the following xgraph format files (in the 'reports' directory)
for each frame in the RPM:

• CYCLE_POWER.xg
• DIDT.xg

You can view these files in the PowerArtist 'Waveform Viewer', 'xgraph', or 'gnuplot' (version 4
or later). To launch the PowerArtist Waveform Viewer, do the following:

1. Run PowerArtist on command line:

PowerArtist &

2. Select ' Tools > Waveform Viewer'. In the 'Waveform Name' field, type an ' *' to find all the files
and click the 'Filter' button.

Figure 6.1: Opening the PowerArtist Waveform Viewer

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 Generating an RTL Power Model

3. Select 'CYCLE_POWER.xg' and click the 'OK' button. Similarly, add 'DIDT.xg' and click the 'OK'
button. The resulting output is shown in the figure below:

Figure 6.2: Waveform Viewer showing the peak power and high didt per cycle

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Chapter 7: Getting Your Design into PowerArtist
7.1. Introduction
This chapter describes the command-line flow for creating a scenario file for Verilog, VHDL, and
mixed-language designs. The designs may be RT-level, gate-level, or mixed-RTL and gate. The scenario
file is a binary representation of the hierarchical micro architectural netlist for your design. You can use
the 'Elaborate' command to create the scenario file for all types of designs.

This chapter includes simple command examples to help you understand the flow. More complex
examples of commands can be found in the 'examples/command_files' directory in the installation.

You can create a scenario file from the command line. For this approach, you must make sure the
PowerArtist design environment is set up correctly, as described in Installing and Setting Up
PowerArtist (p. 5).

Chapter Organization
The following topics are covered in this chapter:

• Case Sensitivity (p. 133)

• Command-Line Flows (p. 134)
• Creating Custom VHDL Packages (p. 139)
• Precompiled VHDL Libraries (p. 140)
• The 'wwvmkr' Utility (p. 141)
• Precompile RTL Files to a Library (Save/Restore) (p. 142)
• Elaboration Using Advanced Gates (p. 144)
• Defining Libraries for Command-Line Use (p. 148)
• Overriding Parameter Settings for Top-Level VHDL/Verilog Modules (p. 149)
• HDL Advanced Topics (p. 150)
• Gzipped File Support (p. 160)

7.2. Case Sensitivity

Design languages are case sensitive or insensitive by default where:

• Verilog is a case sensitive language

• VHDL is case insensitive language
• Mixed designs (Verilog + VHDL) are case sensitive for Verilog parts and case insensitive for VHDL
sections

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Getting Your Design into PowerArtist

Case sensitivity is critical when matching design names supplied in external files like net names in SPEF
files or clock files, or instance or module names in options such as '-top'. By default, the scenario
database is constructed to be case sensitive if the design is entirely in Verilog, or case insensitive if the
design is VHDL or a combination of VHDL and Verilog.

If you have a mixed-language design, PowerArtist can identify and differentiate between the Verilog
and VHDL portions of the mixed-language design. It performs only case insensitive name matching in
VHDL designs and in the VHDL portions of a mixed design.

The following enhancements improve the usability of case sensitivity support in PowerArtist:

• Library cell or pin is matched in liberty files as case sensitive if instantiated in Verilog designs and as
case insensitive in VHDL designs.
• The scenario file generated during elaboration with case sensitive information, either derived from
the design language or user-specified, is marked through an attribute in the elaborated netlist.
• Default language specific settings are applied in the 'Elaborate' command.

7.3. Command-Line Flows

The following command-line flows are available in PowerArtist:
7.3.1. Verilog
7.3.2. VHDL
7.3.3. Mixed-Language Designs
7.3.3.1. VHDL Designs with One or More Verilog Modules
7.3.3.2. Verilog Designs with One or More VHDL Modules
7.3.3.3. Compiling Mixed-Language Designs in a Single Run

7.3.1. Verilog
This section describes the steps to prepare Verilog design files to perform power analysis:

1. Ensure that the design successfully compiles in your target simulator and functions the way you
expect.

2. Run the 'Elaborate' command to create a scenario file for your design:
Elaborate
-scenario_file <scn_file>
-top <top_module>
-verilog_startup_file <startup_file>

where: '<scn_file>' is the scenario file name, '<top_module>' represents the root of your design,
and '<startup_file>' is the Verilog startup file.

Example:
Elaborate -scenario_file my.scn -top top -verilog_startup_file startup.vc

See the 'Elaborate' command in the PowerArtist Reference Manual for a list of all the available
options.

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 Command-Line Flows

3. At this point, the flow becomes language independent. Use the 'CalculatePower' and
'ReducePower' commands to analyze the simulation information and run either power analysis
or power reduction.

Note: You can create run scripts that run these commands instead of entering them directly on
the command line. For sample scripts, see Contents of the 'tutorial' Directory (p. 20).

File Extension-based Parsing

This feature enables identification of Verilog and SystemVerilog files from a mix of HDL files based
on file extensions. The solution is based on the '-verilog_startup_file <filename>' option.

Use the 'SetHDLFileExtensionMapping' command to set the analysis mode for the Verilog design
files specified using the '-verilog_startup_file <filename>' option. The analysis mode is
set based on the extension of the design files.

7.3.2. VHDL
This section describes the steps to prepare VHDL design files to perform power analysis:

1. Ensure that the design successfully compiles in your target simulator and functions the way you
expect.

2. Generate your list of VHDL files that need to be compiled into the appropriate libraries. There are
three ways to do this:
• Automatically generate it using your internal processes just like you probably generate your
simulation compile script.
• Translate an existing command file format, like that used for your simulator of choice to the
PowerArtist format.
• Run the 'map-file/makefile/ptCompileScript' option. To enable this flow, do the
following:

a. Build a 'mapping file' that describes the names of all the VHDL libraries and the files you
want to compile into them. For more detail, see section Creating Your Map Files (p. 141).

b. Build 'Makefiles' using the mapping file generated during step #a by running the 'wwvmkr'
utility. These Makefiles define rules that compile your VHDL design units in the correct order
to meet VHDL language requirements, where all design units must be compiled before they
can be referenced. For more detail, see section Running the 'wwvmkr' Utility (p. 142).

c. Run the 'ptCompileScript' utility. This utility executes 'make' on all the makefiles created
in step #b, determines all the libraries and files used in your design, and generates a file
'ptSourceFiles.tcl', that contains a series of 'CompileFile' commands that compile
each of your VHDL files into the correct library in the correct order. See ptSourceFiles.tcl File
Format for more information on this file.

3. Generate a scenario file using the 'Elaborate' command to analyze, elaborate, and infer your
design:
source ptSourceFiles.tcl
Elaborate -top <top_module_name> -scenario_file <scn_filename>

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Getting Your Design into PowerArtist

where: 'ptSourceFiles.tcl' is generated by ptCompileFileScript, 'top_module_name' is the

VHDL top-module name, and 'scn_filename' is the scenario file.

Example:
source ptSourceFiles.tcl
Elaborate -top top -scenario_file my.scn

4. At this point, the flow becomes language independent. Use the 'CalculatePower' command or
the 'ReducePower' commands to analyze your simulation information and either run power
analysis or perform power reduction.

Note: You can create run scripts that run these commands instead of entering them directly on
the command line. For sample scripts, see Contents of the 'tutorial' Directory (p. 20).

Metacomment Processing
VHDL is a strongly typed language and, furthermore, since you can create many different types,
frequent use is made of functions and procedures to provide type conversion and to overload
arithmetic and Boolean operators for your defined types.

When the 'Elaborate' command processes your design, it analyzes the VHDL into equivalent hardware
elements ranging from simple gates to more complex blocks such as adders, and memories. In many
cases, sub-programs used to overload operators and to perform type conversions contain VHDL, which
has no practical hardware implementation and if included in the elaboration process would impair
the accuracy of the power analysis.

For example, to satisfy VHDL syntax and semantics, you must use the 'CONV_INTEGER function' to
convert a 'STD_LOGIC_VECTOR' to an 'INTEGER'. From a hardware point of view, the two types
have the same representation and so the 'CONV_INTEGER' function passes the 'STD_LOGIC_VECTOR'
argument bit for bit through to the 'INTEGER' return value. To accomplish this without interfering
with the VHDL simulation, special comments are embedded in the VHDL source code. These special
comments are called 'metacomments' and are often of the following form:
-- pragma keywords

So, passing a function argument of 'STD_LOGIC_VECTOR' to an 'INTEGER' is achieved by including

the following 'metacomment' in the declaration section of 'CONV_INTEGER':
-- pragma BUILT_IN SYN_UNSIGNED_TO_INTEGER

When the 'Elaborate' command encounters this metacomment, it passes the argument bit for bit to
the return value and bypasses the body of the function. You can also ensure that the 'Elaborate'
command ignores a section of VHDL (such as sections that contain 'TEXTIO' statements) by using
the following metacomment:
-- pragma translate_off
.. some VHDL to ignore..
-- pragma translate_on

PowerArtist can handle the class of metacomments used by Synopsys, which are included in the
packages they distribute. So if you use these libraries you do not need to be concerned about inserting

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 Command-Line Flows

your own metacomments to ensure that the elaboration process infers appropriate hardware from
your VHDL.

7.3.3. Mixed-Language Designs

When you compile on the command line (or use a script), you need to ensure that your design files
contain instantiations and declarations of modules (or entities) from different languages. In PowerArtist,
you can compile mixed-language design files together, which allows you to leverage information
from your mixed-language simulation environments. This section describes the steps to prepare
mixed-language design files to perform power analysis.

7.3.3.1. VHDL Designs with One or More Verilog Modules

Before you compile a VHDL design that instantiates one or more Verilog modules, you must ensure
that:

• The VHDL source files must contain a component declaration and an instantiation for each Verilog
module. The component must have the same name as the corresponding Verilog module. The
component ports must have the same name, ordering, size, and direction as the ports of the
corresponding Verilog module.

For example, the VHDL source files can contain the following component declaration for a Verilog
module 'LEAF':
-- component declaration for the verilog module LEAF
component LEAF
port( I1, I2 : in bit_vector(1 downto 0 );
OUTPUT : out bit_vector(1 downto 0 ));
end component;

It should also contain an instantiation of 'LEAF':

-- component instantiation of LEAF
INST_LEAF : LEAF
port map(I1(1 downto 0), I2(1 downto 0), OUTPUT(1 downto 0));

• The Verilog source files must contain definitions of the modules.

For example, your Verilog source files can contain the following definition of 'LEAF':
module LEAF (I1, I2, OUTPUT );
input [1:0] I1, I2;
output [1:0] OUTPUT;
...
endmodule

7.3.3.2. Verilog Designs with One or More VHDL Modules

Before you compile a Verilog design that instantiates one or more VHDL modules, you must ensure
that:

• The Verilog source files must contain instantiations of VHDL entities/architectures. For the module
type name in the instantiation, you must escape the work library name followed by the entity

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Getting Your Design into PowerArtist

name and optionally append the architecture name in parentheses, as shown in the example
below:
\work_lib_name.entity_name(arch_name)

The following are also allowed as long as they are not ambiguous and represent legal VHDL
references:
// Use model #1:
entity_name (arch_name)

// Use model #2:

entity_name

• The instance ports must have the same ordering, size, and direction as ports of the corresponding
VHDL entity. For example, the Verilog source files can contain the following instantiation for a
VHDL module 'LEAF':
module top_level(..., I1, I2, OUT);
...
input [1:0] I1, I2;
output [1:0] OUT;
...
// work is the VHDL work library, LEAF the entity name,
// and RTL is the corresponding architecture
\work.LEAF(RTL) inst(.I1(I1), .I2(I2), .OUTPUT(O1));
...
endmodule

• The VHDL source files must contain definitions of the modules. For example, the VHDL source
files can contain the following definition of 'LEAF':
entity LEAF is
port( I1, I2 : in bit_vector(1 downto 0 );
OUTPUT : out bit_vector(1 downto 0 ));
end;

7.3.3.3. Compiling Mixed-Language Designs in a Single Run

Using the 'Elaborate' command, you can compile both Verilog and VHDL source into a single
scenario database file. With this method, PowerArtist searches first to match Verilog instances with
a Verilog module definition, and then a VHDL entity-architecture pair. Similarly, PowerArtist searches
first to match VHDL instances with a VHDL entity-architecture pair (if no configuration is specified)
and then with a Verilog module.

The 'Elaborate' command can read both a Verilog startup file (specified with the
'-verilog_startup_file' option) and a script to compile VHDL source files (specified with
the '-compile_script' option).

Sample Command
Elaborate -top my_lib.my_design_unit -scenario_file my_chip.scn \
-verilog_startup_file my_file.f -compile_script ptSourceFiles.tcl

Alternatively, you can specify Verilog files and VHDL files together using a series of 'CompileFile'
commands in a script passed to 'Elaborate' using the '-compile_script' option.

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 Creating Custom VHDL Packages

Sample Script
CompileFile -type verilog -file my_verilog.v -2001 yes
CompileFile -type vhdl -library toplib -file my_top_vhdl.vhdl AddLibrary STD
CompileFile -type vhdl -library STD -file standard.vhd
AddLibrary IEEE
CompileFile -type vhdl -library IEEE -file std_1164.vhd
AddLibrary WORK
CompileFile -type vhdl -library work -file mydesign.vhd

Refer to the PowerArtist Reference Manual to see the available options of the 'CompileFile' command.

7.4. Creating Custom VHDL Packages

PowerArtist supplies all the standard Synopsys and standard IEEE VHDL libraries as part of its distribution.
These are all located in the following directory:
$POWERARTIST_ROOT/pthdl_src

You might need to substitute these standard definitions with ones supplied as part of your company's
standards. To do this, you must specify the location of these new standard library files to the 'Elaborate'
command. There are two techniques to make this happen and they are explained in the next sections.

7.4.1. Technique 1: Modifying Your Installation

The first and recommended technique requires you to modify the PowerArtist installation directory.
There are two files in the 'pthdl_src' directory:

• stdlibs.87.map - for VHDL 87 designs

• stdlibs.93.map - for VHDL 93 designs

These files are automatically read by the 'wwvmkr' command depending on the language standard
you are following. These map files have identical syntax to the ones that you use to define the
file/library matching for your design and define three standard libraries by default: 'IEEE', 'STD', and
'SYNOPSYS'.

To add or delete a file from one of these three standard libraries, edit the appropriate map file line.
For example, if you are a Synopsys user you might want to add support for 'Cyclone' to the
'SYNOPSYS' library for all VHDL 93 designs. In this case, you can modify the file as shown below:
map SYNOPSYS ww_synopsys $r -i syn_attr.vhd \
/my-cyclone-directory-path -i cyclone.vhd

Then, run 'wwvmkr' and 'ptCompileScript'.

7.4.2. Technique 2: Multiple Compile Scripts

The second requires you to run the 'Elaborate' command with multiple 'compile_scripts', as
shown below:

1. Use the 'AddLibrary' and 'CompileFile' commands to compile the base packages of your design
into a script called 'myBaseFiles.tcl':

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AddLibrary STD
CompileFile -library STD -file mydir/standard.vhd
AddLibrary IEEE
CompileFile -library IEEE -file mydir/std_logic_1164.vhd

Due to VHDL semantic rules, any design unit you need defined must appear before it is referenced.
In short, your standard libraries must get compiled before all other files and they must be in the
correct order.

In this step, the 'standard.vhd' file, which is compiled into 'STD' must be compiled before
'std_logic_1164.vhd' is compiled into 'IEEE'. Since these two files appear in
'myBaseFiles.tcl' they are automatically compiled before the files defined in
'ptSourceFiles.tcl'.

The 'myBaseFiles.tcl' file is a standard Tcl file. You can use standard Tcl features to locate
your libraries using environment variables and Tcl variables. For example, the 'myBaseFiles.tcl'
script can be re-written as shown below:
global env

set path $env(VHDL_STD_DIR)

AddLibrary STD
CompileFile -library STD -file $path/standard.vhd
AddLibrary IEEE
CompileFile -library IEEE -file $path/std_logic_1164.vhd

2. Create the compile script for the remainder of the design:

wwvmkr ## create make files for VHDL design
ptCompileScript -c ## source make files, create ptSourceFiles.tcl

The 'wwvmkr' run would be identical to that used by someone using the PowerArtist standard
supplied libraries. When you run 'ptCompileScript' with the '-c' option, PowerArtist generates a
'ptSourceFiles.tcl' file that does not contain any information related to PowerArtist standard
libraries. The '-c' option suppresses the output.

3. Source the compile scripts and run the 'Elaborate' command:

source myBaseFiles.tcl
source ptSourceFiles.tcl
Elaborate

The sourced files must follow the format for a standard compile script. The 'Elaborate' command
reads and processes the scripts in the listed order.

7.5. Precompiled VHDL Libraries

You can automatically load precompiled VHDL standard libraries, even if they are not specified. The
version of the VHDL standard library selected is based on the highest VHDL standard used to compile
the RTL. The location of the precompiled version of the standard libraries and the corresponding VHDL
standard libraries in the installation is given below:

• The precompiled version of the standard libraries:

lib/hdl/<platform>/vhdl_precompiled/<vhdl_std>/bin/

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 The 'wwvmkr' Utility

• The corresponding VHDL standard libraries:

lib/hdl/<platform>/vhdl_precompiled/<vhdl_std>/src/

7.6. The 'wwvmkr' Utility

7.6.1. Creating Your Map Files

Each file that you supply to the 'wwvmkr' utility must include the following:

• The names of your VHDL logical libraries.

• The UNIX file location of the compiled VHDL libraries and file dependency data used by your
Makefiles.
• The VHDL file names to be compiled into your VHDL logical libraries.

Sample Mapfile
map LIB1 ./ww_lib1 \
/home/tmiller/unit1 -i {unit1a.vhdl unit1b.vhdl} \
/home/gramirez/stypes -i {type1.vhdl type2.vhdl}

where:

map

Indicates that a 'map' statement is coming. Line continuations are indicated by a trailing backslash
(\).

LIB1

Is the logical name of a VHDL library.

./ww_lib1

Indicates the location of the physical library. 'LIB1' is compiled into the physical library at location
'./ww_lib1'.

unit1 and stypes

Are the two UNIX directories that contain VHDL source to be compiled into logical library 'LIB1'.

For 'unit1', the files to include (specified by '-i') are 'unit1a.vhdl' and 'unit1b.vhdl'. For 'stypes',
the files to include are 'type1.vhdl' and 'type2.vhdl'.

Note:

You must use the VHDL standard libraries supplied with PowerArtist and not the libraries
provided with your simulator when running PowerArtist. Using the PowerArtist libraries
ensures that the 'pragmas' needed by the VHDL compiler are inserted in the libraries.

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The synonym Statement

If you are using ModelSim™ as your simulator, you may need to supply an additional map file
statement. This simulator allows you to create 'synonym' libraries. Different logical library names may
point to the same physical location. The 'synonym' statement maps a new logical library name to a
previously specified logical library name. For example, once IEEE appears in a map statement, it can
be followed by the 'synonym' statement:
synonym SYNOPSYS IEEE

Now, 'SYNOPSYS' and 'IEEE' point to the same location. The order of the parameters is 'new name'
followed by 'old name'.

7.6.2. Running the 'wwvmkr' Utility

The PowerArtist 'wwvmkr' utility reads in a map file, which can be created manually, or through an
automated process, or by using the 'make_mti_mapfile' utility and creates makefiles that you can
use to compile your design. Do the following steps:

1. Build the Makefiles in your local working directory, following VHDL 93 rules. The top-level logical
library is 'work', which is case-insensitive:
wwvmkr -m mapfile -w work

2. Execute 'ptCompileScript', which calls the 'wwcompile' script generated by the 'wwvmkr' run.
ptCompileScript

This creates a file called 'ptSourceFiles.tcl' that you need to source before you specify the
'Elaborate' command.

For complete contents and details of this file, see ptSourceFiles.tcl File Format in the PowerArtist
Reference Manual.

7.7. Precompile RTL Files to a Library (Save/Restore)

PowerArtist supports precompilation of blocks into persistent libraries, which can then be used for
elaborating the 'top' design. This may also reduce the overall elaboration time of the 'top' design. It
also saves time that is spent in complicated file setup for large designs and prevents errors due to
duplication of macro definitions across different sub-designs.

A precompiled Verilog (or SystemVerilog) parse-tree is saved in binary format in a '.svdb' file and a
precompiled VHDL design is saved in binary format in a '.vdb' file.

Another benefit of this functionality is its restore-on-demand feature. If a Verilog (or SystemVerilog)
design depends on some package(s), and if the related .svdb's exist, and if the Verilog library search
path is pointing to them, then the '.svdb' is automatically restored-on-demand without having to
specifically read them again.

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 Precompile RTL Files to a Library (Save/Restore)

Use Model
Do the following steps to use this feature:

1. During elaboration, define the library mapping between the logical and precompiled libraries
directories. To do this, use the following command:
AddLibrary <logical-library-name> <physical-library-path>

2. Save the parsed designs into persistent libraries by using the following command:
pa_set elaborate_precompile true

The modules are saved in their corresponding '.svdb' and '.vdb' files inside the library path
specified by the 'AddLibrary' command.

Examples
• Example 1: If the modules are specified in the same logical library, do the following steps:

1. Map the physical library path 'work_lib' to logical library 'work':

AddLibrary work work_lib

2. Precompile file 'mid.v':

CompileFile -type verilog -file mid -library work_lib
pa_set elaborate_precompile true
pa_set top mid
Elaborate

Note: The module 'mid' is saved at:

mid_lib/mid.svdb

While compiling the design, if module definition 'work.mid', is not found then PowerArtist
searches for it in the user-specified pre-compiled library paths.

3. Compile 'top' design:

AddLibrary work work_lib
CompileFile -type verilog -file top.v -library work_lib
pa_set top top
Elaborate

Note: The module 'mid' is automatically restored from 'work_lib'.

• Example 2: If the modules are specified in different logical libraries, you have to specify appropriate
configurations to map the instance to the right library, as shown in the example below:
// file: mid.v
module mid (output logic out1, input logic in1, in2);
assign out1 = in1 & in2;
endmodule

// file: save.tcl -- Save mid to library mid_lib

pa_set top mid

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Getting Your Design into PowerArtist

pa_set scenario_file top.scn

pa_set system_verilog true
pa_set elaborate_precompile true

pa_set work_library mid

AddLibrary mid mid_lib
CompileFile -file mid.v -type verilog -sv true -library mid_lib
Elaborate

// file: top.v - 'cfg' configuration that maps top.inst to mid_lib

config cfg;
design work.top;
default liblist work;
instance top.inst liblist mid;
endconfig

module top (output logic out1, input logic in1, in2);

mid inst(.*);
endmodule

// file: restore.tcl -- compile 'cfg' in work_lib,

// it will associate top.inst with library mid as specified by configuration.
pa_set top cfg
pa_set scenario_file top.scn
pa_set gld true
pa_set system_verilog true

AddLibrary work work_lib

AddLibrary mid mid_lib
CompileFile -file top.v -type verilog -sv true -library work_lib
Elaborate

// top script runme.csh

pa_shell -tcl save.tcl
pa_shell -tcl restore.tcl

7.8. Elaboration Using Advanced Gates

PowerArtist has a feature to enable additional generic cell models for advanced gate elaboration. If
elaboration using advanced gates is enabled, the tool supports a large subset of liberty cell models.
This results in improved runtime, design coverage, and logic reduction.

If advanced gates are enabled for elaboration, boolean optimization gets enabled by default. This allows
synthesis and technology mapping with new liberty cell models such as multi-input gates and complex
AOIs. These larger sets of liberty cell models is used for compound cell inferencing for RTL design.

The following new pa_set is added to enable advanced gates with new liberty cell models:
pa_set elaborate_use_advanced_gates <true | false>

Default value: false

You can also use the following command to enable advanced gates:

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 Elaboration Using Advanced Gates

Elaborate -elaborate_use_advanced_gates true

Table 7.1: Advanced Liberty Cell Models

CELL FLAVOURS/MODELS
TYPE
AND AND3, AND4
OR OR3, OR4
NAND NAND3, NAND4
NOR NOR3, NOR4
XOR/XNOR XOR3, XOR4, XNOR3, XNOR4
INOR/IINOR INOR2, INOR3, INOR4 (IINOR Flavors)
IND/IIND INAND2, INAND3, INAND4 (IIND Flavors)
AOI/OAI OAI211, AOI211, OAI222, AOI222, OA22, AO22, OAI221, AOI221, OAI31, AOI31, OAI32,
AOI32, OAI33, AOI33, OA211, AO211, AOAI211, OAOI211, IOA21, IAO21

7.8.1. Understanding the Advanced Gates Model

The following figure shows liberty cell models being used during optimization. The optimized netlist
is further read by Power Analysis and Power Reduction engines.

The advanced liberty cell models flow is also supported by PDB, GUI, ReducePower, GAF (Critical
Signal Flow) and ProfilePower command flows.

Use Flow
The following describes the usage in Elaboration:

• Elaboration

The optimized netlist generated after Elaboration is written into a scenario file with advanced
liberty cell gates. These files are then read by Power Analysis and Reduction flows.

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Getting Your Design into PowerArtist

In Power Analysis, these liberty cell models are considered during macro optimization and
power calculation. The models are mentioned in the average power report.

• PACE-driven Elaboration and Analysis

For PACE-driven elaboration, PACE models must be generated before running the Elaboration.
The elaborate_use_advanced_gates command enables the advanced gates flow
ensuring only those types of advanced liberty cell models are selected for power analysis which
are present in both PACE.tech and myCells.lib files.

– Use the following pre-defined Tcl command script to generate PACE technology file:
pa_shell % source WriteTechnologyFile.tcl

By default, liberty cell models are captured in the PACE technology files.

– Out of supported liberty cell models, the tool picks targeted liberty cell models from the
PACE files.

– During macro optimization, only targeted liberty cell models are considered during power
analysis.

Input
By default, new liberty cell models are captured in the PACE flow. This step is identical to the step
explained in detail in the Understanding Power Analysis Setup (p. 24) section of the Power Analysis
tutorial. The advanced gate model is enabled using an additional pa_set variable:

To use advanced gates with new liberty cell models, use the following command:
pa_set elaborate_use_advanced_gates true

By default, the variable is False.

NOTE: If you use old PACE technology files, the tool gives 'HDL-245' warnings. You may observe no
changes in the results.

Outputs
The following is the list of outputs in this flow:

• Vertical Report

Multiple new categories for all new liberty cell models are now present in the vertical section
of the power report. The following snapshot of detailed vertical power report reflect new
liberty cell models:

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 Elaboration Using Advanced Gates

• GUI

The following snippet shows the new cell types with tags as rendered in the GUI:

• Log Messages

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Getting Your Design into PowerArtist

The following messages are reported:

– The tool now records the new liberty cell count coverage with respect to gate.

– If the elaborate_enable_advanced_gates command is enabled and old PACE

technology files are used for elaboration, the following warning is reported:
WARNING HDL-245: Using older version of PACE file in advanced gates flow
might degrade QoR. Re-generate newer version of PACE file for advanced gate
flow to work as expected.

Summary
Table 7.2: Description for Arguments and Effective Flow

Advanced Boolean PACE Pace Liberty Effective Flow / SCN

Elaboration Optimization FilteringFiltering
true true/false Yes Yes Yes Advanced gates flow.
SCN with new models
(new
version)
true true/false Yes No Yes Advanced gates flow.
SCN with new models.
(old Note: Warning
version) HDL-245 is issued.
true true/false No No Yes Advanced gates flow.
SCN with new models.
false false Yes/No No Yes Basic gates flow. SCN
without the new
models.
false true Yes/No No Yes Basic sates flow with
boolean optimization.
SCN without the new
models.

A decrease in overall top power and design area is expected. Decrease in net pin capacitance, macro
instances power numbers, inferred buffer count and power numbers are expected.

7.9. Defining Libraries for Command-Line Use

Technology-specific information is supplied using Liberty format library files. To specify the Liberty
libraries, you can use one of following methods:

• The '-synlib_files' option.

You can use the '-synlib_files' option (available with several commands) to specify the
Liberty library files, as shown below:
Elaborate -synlib_files {mylibrary1.lib mylibrary2.lib}
-verilog_startup_file my.vc
-scenario_file mychip.scn
-top core

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 Overriding Parameter Settings for Top-Level VHDL/Verilog Modules

This example loads two libraries called 'mylibrary1.lib' and 'mylibrary2.lib'.

• The 'ReadLibrary' command.

You can also use the 'ReadLibrary' command to specify the Liberty library files, as shown below:
ReadLibrary mylibrary1.lib

Note: If you specify a large number of 'ReadLibrary' commands such that the command line
generated to perform elaboration, power calculation, or power reduction exceeds the Unix limits
of command-line size, PowerArtist automatically generates a file 'ptshell.libs.opts' that
contains the Liberty library names. This file is then referenced using the '-i' option of various
commands.

Scaling Power Data of Liberty Files

Library support is enhanced to support user-specified factors to scale 'internal_power' and
'leakage_power' values. Use the 'SetLibraryScalingFactor' command to enable scaling.

Refer to the PowerArtist Reference Manual for complete details of the 'SetLibraryScalingFactor' command
and its supported options.

7.10. Overriding Parameter Settings for Top-Level VHDL/Verilog Modules

The PowerArtist elaborate process allows you to assign a value to a top-level VHDL or Verilog module.
The '-parameter_maps' option allows you to override parameter settings, including generics.

Consider the example of the following Verilog (or equivalent VHDL) fragment:
module top(in,out);
parameter size=2;
input [size-1:0] in;
output [size:0] out;
assign out = in+1;
endmodule

You can override the size parameter by adding the '-parameter_maps' option to your Tcl command
file:
Elaborate -parameter_maps {size=4} ...

When PowerArtist elaborates the Verilog design, size is set to '4'. To override multiple parameters, you
can specify a Tcl list of parameters. For example:
Elaborate -parameter_maps {p1=4 p2=5}

You can also use the '-parameter_maps' option to set generics. Consider the example of the following
VHDL fragment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TOP IS
GENERIC(SIZE : integer);
PORT ( AA, BB, TT : IN STD_LOGIC_VECTOR(SIZE-1 downto 0);

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Getting Your Design into PowerArtist

CC : OUT STD_LOGIC_VECTOR(SIZE-1 downto 0));

END TOP;

ARCHITECTURE A0 OF TOP IS

BEGIN
CC <= BB AND TT;
END A0;

For this example, the following line in your Tcl command file sets the 'SIZE' parameter:
Elaborate -parameter_maps {size=4}

7.11. HDL Advanced Topics

This section provides information on several advanced HDL topics.

7.11.1. Behavioral Clock Gating

In some designs, clock gating cells are modeled using behavioral description, such as by instantiating
a latch followed by an 'AND' operation. Support for identifying behavioral clock gating logic is available
in PowerArtist. Consider the sample latch-based model of a clock gating cell in RTL shown below:
module LATCH_AND(input logic in_clk, en, output logic enabled_clk);
logic latch_out;
always_latch begin
if (en)
latch_out <= in_clk;
end
assign enabled_clk= latch_out && in_clk;
endmodule

module top(input logic in_clk, en, in, output logic out);

logic enabled_clk;
LATCH_AND u0 (in_clk, en, enabled_clk);
always @(posedge enabled_clk)
out <= in;
endmodule

In behavioral clock gating, the cell 'LATCH_AND' is replaced by an integrated clock gating cell (ICGC)
from the library, based on user input. This support is available for RTL written in any HDL language
including Verilog, System Verilog, or VHDL.

Use the 'MapBehavioralCell' command to capture the mapping information of a module to library
cell and module port to library cell pins. Refer to the PowerArtist Reference Manual for complete details
of the command and its supported options.

Example:
In this example, module 'LATCH_AND' represents a behavioral clock gate that is mapped to the ICGC
'cell_415' from the library. Ports of the module 'LATCH_AND' are mapped to pins of the library
cell 'cell_415' using the '-pin_mapping' option:
MapBehavioralCell -module LATCH_AND -lib_cell cell_415 \
-pin_mapping {{en E}{in_clk CK}{enable_clk ECK}}

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 HDL Advanced Topics

A sample schematic of the design 'before' enabling behavioral clock gating is shown below:

The schematic represents the RTL netlist for the 'LATCH_AND' module instance. After mapping this
module to an ICGC from the library, the logic for 'u0' instance is replaced by Rising-Edge Latch-Based
Integrated Cell 'cell_415' from the library.

The schematic of the design 'after' enabling behavioral clock gating is as shown below:

This enhancement impacts power analysis, power reduction, clock tree inferencing, and clock gating
efficiency as logic driven by the behavioral clock gate in the RTL is considered as driven by a clock
gate.

7.11.2. Using Power Macros

The PowerArtist elaborate process supports power macros. This allows you to replace HDL models
written for simulation with more synthesis- and power-aware models without modifying your design
source. This is useful for the following situations:

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Getting Your Design into PowerArtist

• You are using DesignWare ™, which contains many models that are not synthesizable, and you
want to create some models that more closely represent what is synthesized.
• Your designers have used simulation models in their design to improve simulation performance
and you wish to replace those models with versions that are normally synthesized.

PowerArtist provides a default set of power macro models that contain definitions to replace some
of the simulation models from the base DesignWare ™ library. The 'Elaborate' command looks for
these macro models in the power macro directory. The default location for this directory is:
$POWERARTIST_ROOT/pthdl_src/macros

You can provide a different directory name using the 'Elaborate -macro_directories' option.
This directory must contain:

• A set of Verilog source files that contain module definitions.

• A mapping file, named 'MacroMap', that specifies the name of each module to be replaced
in the design and the name of the module with which to replace it. The name of each Verilog
file should be the same as the name of the module plus the '.v' extension. The Verilog module
must be port compatible with the module it is replacing. This also works for VHDL designs
following standard conventions that ensure that a VHDL architecture can instantiate a
component written in Verilog. For example, the macro directory can contain a macro map file
that includes the following line:
originalAndGate myAndGate

In this example, the macro directory must also contain a Verilog file named 'myAndGate.v',
which contains the module definition for the module 'myAndGate'. The elaborate process
marks all occurrences of Verilog modules or VHDL entities of 'originalAndGate'. It compiles
'myAndGate.v' and replaces instances of 'originalAndGate' with the model constructed
from 'myAndGate'. It also applies any parameters or generic values to this new model. The
scenario database that 'Elaborate' generates contains instances of 'myAndGate' instead of
'originalAndGate'.

PowerArtist has modeled the following components that are mapped to the base DesignWare ™
library:

• adder
• adder/subtracter
• decrementer
• incrementer
• subtracter
• absolute value
• simple multiplier
• 2-6 stage pipelined multipliers
• wallace tree multiplier
• partial multiplier

If you use DesignWare ™, you do not have to do anything to take advantage of this feature. By default,
PowerArtist automatically substitutes any modules it finds in the 'macros' sub-directory. If you have
created your own power macros and cannot install them into the 'macros' sub-directory, then you

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 HDL Advanced Topics

must use the 'Elaborate -macro_directories' option to point to the directory containing the
power macros. If you use multiple directories, use a Tcl list to specify the directories, as shown in the
following example:
Elaborate -macro_directories {
dir1
dir2
dir3
...}

7.11.3. Handling Long Parameterized Module Names

During elaboration, parameters and their values are appended to the internal representation of RTL
module names, in order to create unique identifiers. When there are multiple parameters or long
values, this can potentially create very long module names impacting graphical debug and analysis.
If the uniquified module name exceeds the OA limit of 255-characters, module names cannot be
stored in the power database ('.pdb').

The issues associated with long module names are now addressed. If the uniquified module name
exceeds 150 characters, the following happens:

• The uniquified module name is truncated and named as

'<moduleName>_pa_uniquified_<integerCount>'. For example, a module named
'dut(param1=val1, param2=val2, ...................)', is renamed to
'dut_pa_uniquified_1'.

• During pdb creation, the parameter-value pair is annotated as a PDB property named
'mod_parameter_list'. You can use the APSH command 'getPropVal' to access this property
as shown in the example below:
getPropVal <moduleName> mod_parameter_list

Note: The 'getPropVal' command returns the parameter-value pair only for those instances for
which the module names are truncated. If the uniquified module name is not truncated, 'getPropVal'
returns ' -1'.

7.11.4. Controlling Array Inferencing

When a two-dimensional array is modeled in Verilog RTL, the array may be inferred in one of two
ways: either as a single two-dimensional register file or latch file, or as a collection of individual state
devices (registers and latches) with read and write address decoding logic. For large arrays, register
or latch files provide the best balance of analysis accuracy versus capacity and power analysis
performance. For small arrays, the PowerArtist power analyzers can better account for clock gating
and other synthesis effects when inferencing maps an array to individual state devices.

The options of the 'Elaborate' command allow you to control array inferencing. You can use these
options to tell PowerArtist to 'blast' arrays into a combination of state devices and the supporting
control logic rather than to infer a single register or latch file.

If you make extensive use of arrays and you plan to clock gate the registers that are ultimately
synthesized, then you should take advantage of these options to force bit-blasting to occur in as
many places as possible. The options all have the term 'regfile' in their names. These options
should also be used for instances that must be inferred as a latch file.

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The following options enable bit-blasting:

• To bit-blast a Tcl list of 2-D arrays or all arrays, use:

-blast_regfile <{list} | all>

• To preserve a Tcl list of 2-D arrays or all arrays, use:

-preserve_regfile <{list} | all>

• To specify the minimum bit count (words x length) of 2-D arrays to preserve as register or
latch files, use:
-min_regfile_bit_count <int>

The default value of this option is '32'.

• To specify the minimum word count of 2-D arrays to preserve as register or latch files, use:
-min_regfile_word_count <int>

The default value of this option is '8'.

• To specify the minimum word length of 2-D arrays to preserve as register or latch files, use:
-min_regfile_word_length <int>

The default value of this option is '3'.

The format to specify 2-D arrays that must either be bit-blasted ('-blast_regfile') or preserved
('-preserve_regfile') is:
module_name. array_name

If the 2D array is used in a named block, generate statement, or other named scope in your Verilog,
you must include that scope value. In such cases, the format is:
module_name. scope_name. array_name

Application of the Options

You need to specify the options to bit-blast or preserve arrays to the 'Elaborate' command. The
options are applied by PowerArtist in the following sequence:

1. Any two dimensional arrays specified with '-blast_regfile' or '-preserve_regfile' are

marked to be 'bit-blasted' or 'preserved' respectively.

2. If either -blast_regfile all' or '-preserve_regfile all' is specified, then 'all' remaining

arrays are 'bit-blasted' or 'preserved' as specified.

3. Otherwise, for each array, the word length, word count, and total number of bits are compared
with the minimum limits for register files. You set these limits using the '-min_regfile_*'
options. If any of these are lower than the specified or default limits, then the array is marked to
be 'bit-blasted'.

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 HDL Advanced Topics

Examples
The following Verilog examples show how to translate the names in your Verilog to the names required
in the bit-blasting options. All the examples show how the array names are used in the
'-preserve_regfile' option:

• Example 1: Simple use

module top(clk, wen, wadr, wdata, radr, rdata);
<snip> ....

always @(posedge clk)

begin
reg [5:0] myRam [15:0];
if (wen)
myRam[wadr] = wdata;
rdata = myRam[radr];
end

In this case, the array name specified with '-preserve_regfile' is:

Elaborate -preserve_regfile top.myRam

• Example 2: Named begin block

module top(clk, wen, wadr, wdata, radr, rdata);
<snip> ....

always @(posedge clk)

begin : myblock
reg [5:0] myRam [15:0];
if (wen)
myRam[wadr] = wdata;
rdata = myRam[radr];
end

In this case, the array name specified with '-preserve_regfile' is:

Elaborate -preserve_regfile top.myblock.myRam

• Example 3: Nested named begin block

module top(clk, wen, wadr, wdata, radr, rdata);
<snip> ....

always @(posedge clk)

begin : myblock
begin : mysubblock
reg [5:0] myRam [15:0];
if (wen)
myRam[wadr] = wdata;
rdata = myRam[radr];
end
end

In this case, the array name specified with '-preserve_regfile' is:

Elaborate -preserve_regfile top.myblock.mysubblock.myRam

• Example 4: Generate Statement

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module top(clk, wen, wadr, wdata, radr, rdata);

<snip> ....

genvar i;
generate
for(i = 0; i < 4; i = i+1)
begin : blk

always @(posedge clk)

begin : myblock
begin : mysubblock
reg [7:0] myRam [31:0];
if (wen)
myRam[wadr] = wdata[i*8+3:i*8];
rdata[i*8+3:i*8] = myRam[radr];
end // mysubblock
end // myblock
end // blk
endgenerate

In this case, the array name specified with '-preserve_regfile' is:

Elaborate -preserve_regfile top.blk.myblock.mysubblock.myRam

Note: The scope name for the generate block must be specified without the [ index] for each
'genvar' iteration. The option applies to 'all' generated copies of the block, so that all copies
of 'myRam' are preserved.

Notes, Warnings, and Error Messages

With respect to register and latch files, the following warning messages are added in the
'Elaborate.log' file:

• If bit-blasting occurs, the warnings are 'HDL-105' or 'HDL-104'. For example:

HDL-104: design.v:12 3x4 memory myRam not recognized as dual-port RAM.
Will be bit-blasted.

• If bit-blasting does not occur, the warnings are 'HDL-71' or 'HDL-54'. For example:
HDL-71: design.v:15 inferred regfile instance myblock:myRam with data
width of 6, address width 4.

The 'Elaborate' command does not generate 'Notes' or 'Error' messages specific to bit-blasting.

Note: In some cases, the colon ':' separator is printed for named scopes. All 'regfile' options are
specified using a dot .' separator only.

7.11.5. Vector Slicing of Registers and Latches

Bundling during elaboration re-arranges the bits and slices of design elements that share common
control logic, such as, clock and reset. Register bundling preserves the logic and the implicit intent
of the designer as far as possible. Bundling enables efficient RTL power debug as it correlates to the
designer's register assignment in RTL. Consider the following example:
module Top (clk, _a, _b, _c, out) ;
input clk;
input [2:0] _a , _b, _c ;

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 HDL Advanced Topics

output [6:0] out ;

reg [6:0] a, b ;
always @ (posedge clk) begin
a[2:0] <= _a ;
a[6:3] <= _a ;
b[2:0] <= _b ;
b[6:3] <= _c ;
end
assign out = a & b ;
endmodule

The GUI output of the above RTL code shows that the design representation within PowerArtist is
consistent with the RTL code:

Use the following variable to enable this support:

pa_set disable_register_slicing false

The default value of the variable is 'true'.

7.11.6. Enhanced Cell Mapping

Support is added to use cells ('AND', 'OR', 'NOR', and 'XNOR') from design libraries and/or PACE model
for cell mapping and accurate capacitance modeling of RTL design and macros ('adder',
'comparator', 'decoder', 'unencoded_mux', 'multiplier', and 'shift'). This results in improved
RTL power accuracy in the PACE and non-PACE flows.

To enable this enhancement, set the following variable to 'true':

pa_set map_original_gates <true | false>

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Getting Your Design into PowerArtist

Cell Mapping in Non-PACE Flow

After you enable this enhancement in the non-PACE flow:

• If PowerArtist finds 'AND', 'OR', 'NOR', and 'XNOR' cells in the design libraries, they are honored,
else 'NAND' and 'XOR' are used for cell mapping. The 'SetVT' command is enhanced to accept
cell types 'AND', 'OR', 'NOR', and 'XNOR'.
• Cell mapping is enabled for design instances and the sub-netlist of macros ('adder',
'comparator', 'decoder', 'unencoded_mux', 'multiplier', and 'shift') with the
'AND'/'OR'/'NOR'/'XNOR' cells.

Cell Mapping in PACE Flow

For details, refer to the section Cell Mapping in PACE (p. 470) in 'Generating and Using PACE Technology
Files'.

Outputs
The following files are updated when you perform power analysis after enabling the enhancement:

• Power Analysis Text Report

Power numbers are expected to change due to this enhancement and the changes are expected
in the following sections of the report:
– The 'Internal Power Consumption' section for the power numbers of the leaf-level
instances.
– The 'Mixed-VT Cells Distribution' section for the new supported cell types.
– The 'Power Consumption by Model/Gate Type' section for the cumulative power of the
new cell types.

• Cell Selection Report

This updated report contains details of the supported cell types in the 'Function' column and
their count in the 'Occurrence' column:
Cell VT Group Function Class Occurrence

1. Cell summary of inferred netlist elements.

SEQCLKINVX1MTH - Inverter LowFast 17

SEQMX2X1MTH - Mux LowFast 809
SEQCLKNAND2X2MTH - Nand LowFast 329
SEQXOR2X1MTH - Xor LowFast 388
SEQADDFX1MTH - Full adder LowFast 22
SEQAND2X1MTH - And LowFast 159
SEQOR2X1MTH - Or LowFast 89
SEQNOR2X1MTH - Nor LowFast 1
SEQXNOR2X1MTH - Xnor LowFast 64
SEQSDFFQX1MTH - Scan flop HighFast 65
SEQSDFFRQX1MTH - Scan flop with clear LowFast 322
<snip>

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 HDL Advanced Topics

7.11.7. Default Optimizations and Flows

Several optimizations are added to PowerArtist that result in improved RTL inferencing and netlist
optimizations thereby correlating better with post-synthesis power numbers. These optimizations are
explained below.

7.11.7.1. Compound Cell Modeling

When the compound gates flow is enabled, PowerArtist infers compound gates, such as AOI22,
OAI22, AOI21, and OAI22 to implement and-or logic and macros such as unencoded_mux, decoders,
mux21, and shifters. The use of compound gates has been found to improve RTL power accuracy
as gate-level netlists commonly contain compound gates-based logic. Using the compound gates
flow is expected to correlate better with post-synthesis results. You can disable the flow by using
the following variables:
pa_set dont_use_aoi21_compound_gates true
pa_set dont_use_compound_gates true

7.11.7.2. Clock Gating for Inverted Enable Logic

The default clock gating mechanism identifies multiplexer feedback paths for registers with even
number of inversions through inverter, NAND or NOR gates. Earlier PowerArtist used to ignore such
feedback paths and not infer clock gating. The improved algorithms enable PowerArtist to identify
more clock gating opportunities.

Power is expected to reduce and correlate better with post-synthesis results if PowerArtist identifies
more clock gating opportunities using the inverted logic in the register feedback path. Clock gating
efficiency metrics can also change.

7.11.7.3. Support for Escaped Identifiers

RTL often contains escaped identifiers. Prior to this support, the escape character in identifiers was
lost when the 'Elaborate' command was run. In the example shown below, escaped sequences
were removed leaving modified names in the generated netlist:
wire \a[0] ;
wire \a[1] ;

wire [1:0] a;

always @(...)
begin
a[1] <= \a[1] ;
a[0] <= \a[0] ;
end

Moreover, an escape character was sometimes added to the identifiers to allow correct generation
of OpenAccess-based power database.

In the example shown below, the column on the left shows a sample code with the corresponding
generated names in the column on the right:
Sample Code: Net names stored in the pdb (when support
typedef struct packed { for escaped identifiers is enabled):
logic [20:0] m ; top.\abc[1] .temp.d.m[0]

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Getting Your Design into PowerArtist

} t_sub; top.\abc[1] .temp.d.m[1]

typedef struct packed { top.\abc[1] .temp.d.m[100]
logic [15:0] a;
t_sub d;
} t_mystruct;

module top (clk, mystruct);

input clk;
output t_mystruct mystruct;
begin: \abc[1]
t_mystruct temp;
Net names stored in the pdb (when support
always @(posedge clk) for escaped identifiers is disabled):
mystruct = temp; \top.abc[1].temp.d.m[0]
end \top.abc[1].temp.d.m[1]
endmodule \top.abc[1].temp.d.m[10]

This change in object names adversely impacted usability while debugging power. To enable
appropriate handling of the escaped identifiers, the flow is enhanced to preserve the original RTL
names in the power database.

Additionally, the power analysis engines (average and time-based) are enhanced to deal with name
mapping issues related to non-escaped identifiers in saif, simulation, and spef files and escaped
identifiers in RTL. This enhances debuggability at RTL as escaped identifiers are retained throughout
the flow.

With this enhanced flow (enabled by default), you can:

• Use original RTL names to map objects in the simulation database.

• Search and find RTL names using their original names while debugging in the PowerArtist
GUI.

7.11.7.4. Boolean Optimization

Selectively bit-blasts combinational macros such as unencoded muxes and decoders, and multi-input
gates to minimize logic in the design.
SetDontTouch -boolean_optimization <true | false>

Default: false

Notes: Enabling boolean optimization:

• is expected to improve the accuracy of logic power when compared to post-synthesis results.

• can increase the runtime of the Elaborate command in the order of ~30%.

7.12. Gzipped File Support

The 'Elaborate' command is also able to read gzipped RTL files. The files specified using '`include'
in RTL are also un-gzipped and read by the 'Elaborate'.

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Chapter 8: PowerArtist RTL Encryption
8.1. Introduction
This chapter describes the encryption support in PowerArtist.

Encryption is a common approach for protecting the RTL source from unauthorized access. PowerArtist
supports RTL encryption via a native RTL encryption utility called ProtectRTL. RTL files are encrypted
by a hidden key in PowerArtist such that the encrypted RTL can be decrypted and read only by
PowerArtist. Since the encryption is performed using a hidden key, the IP provider is not required to
ship the encryption key file along with PowerArtist encrypted RTL IP. This allows for a secure exchange
of RTL IP between design groups or companies.

Chapter Organization
The following topics are covered in this chapter:

• Use-Model/Flow (p. 161)

• Using the 'ProtectRTL' Command for Encryption (p. 162)
• Decryption and Power Analysis (p. 163)
• Support for IEEE-1735 (p. 164)

8.2. Use-Model/Flow
The diagram below shows the RTL IP exchange flow:

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PowerArtist RTL Encryption

Figure 8.1: RTL IP Flow

While parsing the encrypted RTL for power analysis, PowerArtist does not issue any parser messages
or warnings related to syntax and semantics checks. Only a summary containing the total number of
errors and warnings that were suppressed during elaboration of the encrypted RTL are reported. This
ensures additional decryption security for the IP vendor. An example of the error/warning summary is
shown below:
Warning HDL-142 : 0 error(s) and 1 warning(s) suppressed for RTL encryption.

After analyzing power for the encrypted RTL, PowerArtist reports static, dynamic, and total power of
the RTL IP in reports and GUI. The contents of RTL IP, such as the hierarchical and leaf instances and
nets within the RTL IP, are not available through the PowerArtist GUI, reports or by queries to the
PowerArtist shell. Instances of the modules defined in the encrypted RTL appear as black-boxed instances
in the PowerArtist GUI. This ensures that the GUI and text reports do not reveal information about the
encrypted RTL. The power reduction flow does not support encrypted RTL.

8.3. Using the 'ProtectRTL' Command for Encryption

RTL IP can be encrypted using the ProtectRTL command. ProtectRTL provides flexibility to specify
input RTL files for encryption in three different ways. Several controls are also provided to choose how
the encrypted RTL is generated.

8.3.1. Reading Input RTL Files

Input RTL files can be provided to ProtectRTL in three different ways:

• Specify a directory path containing the RTL files to encrypt using '-protect_rtl_dir
<dirname>'.
• Specify a single RTL file using '-protect_rtl_file <filename>'.
• Specify a list of Verilog and/or VHDL RTL files in startup file format using:
– '-protect_rtl_verilog_startup_file <filename>' and/or
– '-protect_rtl_vhdl_startup_file <fiename>'

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 Decryption and Power Analysis

In addition, the '-protect_rtl_include_file_extensions <string>' option can be used

to control the type of files to be encrypted.

8.3.2. Generating the Encrypted RTL

ProtectRTL generates encrypted RTL in a manner that enables easy transfer of encrypted IP. The
various outputs generated by ProtectRTL are listed below:

• Encrypted RTL files

By default, ProtectRTL generates and writes the encrypted files to the current directory. To
save the encrypted RTL in a specific output directory, use '-protect_rtl_output_dir
<output_dir_name>'.

• Tarball of encrypted RTL

A tarball of the encrypted RTL directory is created for easy handshake of encrypted RTL. The
name of the tarball is derived from the name of output directory. For example, if the output
directory is 'pa_protected_rtl', the tarball is named 'pa_protected_rtl.tar.gz'.

• List of encrypted files

ProtectRTL automatically generates a file containing a list of all the encrypted files. By default,
the filename is 'ProtectedFile.list'. To change the default filename, use
'-protect_rtl_list <filename>'.

• Startup files for PowerArtist

ProtectRTL also has the ability to generate a Verilog and/or VHDL startup file to enable easy
RTL power analysis setup for encrypted RTL in PowerArtist. The output startup files are generated
only when the input RTL files are provided to ProtectRTL in startup file format. The default
names of the output startup files are 'ProtectedVerilogOutputFile.list' and/or
'ProtectedVhdlOutputFile.list'. Use the following options to customize the names
of the output startup files:
– '-protect_rtl_output_verilog_startup_file <filename>' and/or
– '-protect_rtl_output_vhdl_startup_file <filename>'

Note: Refer to the ProtectRTL command in the PowerArtist Reference Manual for detailed explanations
of all the supported options.

8.4. Decryption and Power Analysis

ProtectRTL includes a hidden decryption key in the encrypted RTL, which can only by used by PowerArtist
to decrypt the RTL for power analysis.

PowerArtist performs power analysis of the encrypted RTL, but provides access to limited power data
in the text power reports, the GUI, and the power database (PDB). If all files of the design are encrypted,
PowerArtist reports power numbers for the 'top-level' only.

The following properties of the encrypted RTL can be queried from the PDB after power analysis in
PowerArtist:

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PowerArtist RTL Encryption

• static_power
• dynamic_power
• clock_static_power
• clock_dynamic_power and
• power per supply per clock domain

These values are accessible through the following container commands:

• get_property
Use 'get_property' for the attributes static_power, dynamic_power,
clock_static_power, or clock_dynamic_power:
get_property -class cell <instance path> <attribute_name>

• get_instance_power
Use 'get_instance_power' for the attributes logic, clock, and buffer power per supply
per clock domain:
get_instance_power [options] <object_spec>

8.5. Support for IEEE-1735

PowerArtist can perform power analysis of RTL that is encrypted as per the IEEE1735-2014 standard.
The 'Elaborate' command can read a fully or partially encrypted RTL. In a fully encrypted RTL, the
complete RTL file is encrypted according to the IEEE standard. In a partially encrypted RTL, certain
portions of the RTL are encrypted according to the IEEE standard.

PowerArtist ensures IP protection during power analysis and reduction flows. The generated log messages
and reports do not show any information for the encrypted modules. The encrypted design or the
encrypted part of the design appears as a black-box in the PDB, GUI, and text reports.

The following two types of encryptions, as recommended by the IEEE standard, are supported:

• Symmetric Encryption
– AES (128) [aes128-cbc]
– AES (256) [aes256-cbc]
• Asymmetric Encryption
– RSA (>=2048)

PowerArtist reports an error if any other types of algorithms are mentioned in the digital envelop other
than the ones that are supported, even if those algorithms are as per IEEE 1735-2014 standard.

8.5.1. Encryption by IP Creators

As per the IEEE 1735-2014 standard, IP creators can control both encryption and decryption of HDL
source by adding special 'pragmas' to the source. The combination of HDL code with 'pragmas' is
referred to as a digital envelope. For each potential analysis tool (such as PowerArtist), information
about that tool must be provided in the digital envelope.

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 Support for IEEE-1735

The encrypting tool generates a random key (for tools such as PowerArtist to use) with a symmetric
method, called a 'session key'. The IP protected source code is encrypted using this 'session
key'. The 'session key' is also encrypted using a public key, which must be added to the design
file(s) before encrypting them.

PowerArtist’s public key is shown below:

For Verilog designs:
================
`pragma protect key_keyowner = "Ansys Incorporated"
`pragma protect key_method = "rsa"
`pragma protect key_keyname = "AI-POWERARTIST-RSA-1"
`pragma protect key_public_key
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA2BkoXY5LmpUaNkX5hEqaOe8t1XAqXsNGypeHw7
zehfigBmNae4Wz1RjdFIFbirUIsaQvDf2qa01B1ceNR3rimHBv1cZpZ7xYoNSH2ZRTk4aHJEcO766VCb61
Y2sMSZ1MZVb7DpQPkhh2T+Iiq/
8xFB0BiSIB07cJlZuH5z8A8PUpOi3tNXk9+D4YBzKpAsNBhBbQ18hmZxOiMHsf/
rWnt0Ueu1bWFVhZG6CFzdFJhVVVPrRQRi/
Xr04a47Ni74WCQClzj0fuzAvLHHNrqRU3yxUf72d1ac2SnrtVF2IeXw+PtYeQyUx/
X68IpPe+7EPOqiCL2/QgR/Q/gNQvuGPzwQIDAQAB
================
For VHDL designs:
================
`protect key_keyowner = "Ansys Incorporated"
`protect key_method = "rsa"
`protect key_keyname = "AI-POWERARTIST-RSA-1"
`protect key_public_key
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA2BkoXY5LmpUaNkX5hEqaOe8t1XAqXsNGypeHw7
zehfigBmNae4Wz1RjdFIFbirUIsaQvDf2qa01B1ceNR3rimHBv1cZpZ7xYoNSH2ZRTk4aHJEcO766VCb61
Y2sMSZ1MZVb7DpQPkhh2T+Iiq/
8xFB0BiSIB07cJlZuH5z8A8PUpOi3tNXk9+D4YBzKpAsNBhBbQ18hmZxOiMHsf/
rWnt0Ueu1bWFVhZG6CFzdFJhVVVPrRQRi/
Xr04a47Ni74WCQClzj0fuzAvLHHNrqRU3yxUf72d1ac2SnrtVF2IeXw+PtYeQyUx/
X68IpPe+7EPOqiCL2/QgR/Q/gNQvuGPzwQIDAQAB
================

The encrypting tool shares the 'session key' with PowerArtist by means of a 'KEY_BLOCK'. The
following information is included in a 'KEY_BLOCK':

• Owner of the key (key_keyowner)

• Name of the key (key_keyname)
• Asymmetric method for encrypting/decrypting the key (key_method)
• Key itself (key_public_key)

The following is an example of a digital envelope (for Verilog designs) with the 'key_block' and
'data_block':
`pragma protect begin_protected
`pragma protect version=1
`pragma protect author="XXX Corporation"
`pragma protect key_keyowner="Ansys Incorporated"
`pragma protect key_keyname=" AI-POWERARTIST-RSA-1"
`pragma protect key_method="rsa"
`pragma protect key_block

FWVB0D8B2Z0Rb1/
zTMq7K8e40aBjr1IyeqJLm5S6u2eEDRn1NumCxbw1fAFz8WJFzZ3Kfw96UOOgTQRA2vnXpDOARpEWgJ+m
NcQRrxSZJP389gOYIdMzln8U6zaTrJGJm+pfmym2dYa33ghnP3oY+Ky7I0GinQLpOr7d1ZdAvFaSaKW/
sKKvf17CxyV1BLv+RkvrD3HA3AYq5JJeMnfT6oe+eGwvtiNIg8MJrSf4OfDojxNODZ2/sa9q60/x/
TGqDq8PNNpYR7HoM//x00QgQqSN8vXVLIRUUJz0tQx/
4GinBa7uJRMzvnszGziWI8WJlKUC44gBfqwUX0U+IIfNAw==

`pragma protect data_method="aes128-cbc"

`pragma protect data_block

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PowerArtist RTL Encryption

9ye+oUptTpWf7PktA6B9Ksw1mZRcmcGyAAo2GzJxD1byQdKP2ei91hdlSHTCDcXPh3YGPWbb6gxcJL76P
mNI7eEFlDXQ6Uk834vrbGmQNeQh0p2PpzMte4eMh4MCNQsshUCmGwQg98edZEj7zKeuVWnT+pB2bgVN5t
ZwqH2UUzCbFL9HFaksqHhOLvxnZKCY

`pragma protect end_protected

8.5.2. Decryption by PowerArtist

The decryption process is as explained below:

• For the 'aes128-cbc' and 'aes256-cbc' algorithms

PowerArtist detects the digital envelope automatically, parses the envelope, and internally
decrypts the encrypted data. PowerArtist reads each 'KEY_BLOCK' until it finds one that
includes a key it recognizes. It then decrypts the associated 'KEY_BLOCK' data to determine
the original session key and uses that session key to internally decrypt the IP source code.

Decryption commands use standard prefixes. The general format of a decryption command
is:
<prefix> <command> <optional arguments> ...

where the '<prefix>' for:

– Verilog and SystemVerilog is '`pragma protect'.
– VHDL is '`protect'.

• For the 'RSA' algorithm

PowerArtist shares the public key of a (public, private) key-pair with the IP creator/encryption
tool. PowerArtist then internally decrypts the encrypted RSA block with the private key of the
pair. Contact your local support AE for the public key.

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Chapter 9: Preparing for Power Analysis
9.1. Introduction
This chapter describes the steps required before you can run power analysis or reduction. It includes
information on setting net capacitance, handling designs with multiple power supplies and libraries,
and clock power specification.

Chapter Organization
The following topics are covered in this chapter:

• Estimating Net Capacitances (p. 167)

• Estimating Pin Capacitance (p. 173)
• Handling Voltages in Liberty Format (p. 174)
• Handling Designs with Multiple Libraries (p. 175)
• Handling Designs with Multiple Power Supplies (p. 175)
• Running RTL Mixed-VT Power Analysis (p. 181)
• Setting up Clock Power Analysis (p. 186)
• Setting up Clock Gating for Power Analysis (p. 190)
• Setting up Clock Gating for Power Reduction (p. 194)
• Ideal Clock Network Modeling (p. 197)
• Event-based Analysis (p. 198)

9.2. Estimating Net Capacitances

Accurately estimating dynamic power in your design requires good estimates of your net capacitances.
Therefore, before you begin your power analysis, you need to determine how to provide net capacitance
information to PowerArtist. You can use any of the following methods:

• Back-annotate capacitances using SPEF. For details, see Back-Annotating Capacitance Using SPEF (p. 168).

• Back-annotate load capacitances for primary outputs using a PowerArtist capacitance file. You can
get output load information based on the package you use for your design. Capacitance files for this
purpose should supply loads representing output load capacitances. For details, see Using
Back-Annotated Load Capacitances for Primary Outputs (p. 170).

• Specify default output load capacitance using the 'CalculatePower -default_output_load <>'
option. For details, see Specifying Default Output Load Capacitance Using a Command Option (p. 170).

• Back-annotate capacitances for local signal nets using a PowerArtist capacitance file. RTL floorplanners
may be able to generate signal capacitances. This format is most often used for RTL and mixed

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Preparing for Power Analysis

RTL/gate designs. If you are back-annotating signal capacitances, you can only choose one format.
You cannot mix SPEF and wiring capacitances files. For details, see Using Back-Annotated Wiring
Capacitances for Local Nets (p. 170).

• Specify a PowerArtist Calibrator and Estimator (PACE) technology file (using the '-power_tech_file
<filename>' option) to estimate net capacitance for RTL, mixed RTL/gate, or pure gate-level designs.
PACE files are also used for clock distribution network modeling. For details on how to use a PACE
file, see Generating and Using PACE Technology Files (p. 467).

• Use wire load models to estimate signal capacitances. This can be used for RTL, mixed RTL/gate, or
pure gate-level netlists. You can set the wire load models using Tcl commands. For details, see
Specifying Wire Load Models (p. 171).

• Use default wire load models. For details, see Using Default Wire Load Models for Capacitance
Analysis (p. 173).

The capacitance, length, and routing-area values of all nets not explicitly listed in a net capacitance file
are estimated from capacitance models either available in your technology libraries or supplied
automatically by PowerArtist. If you do not want to perform net capacitance estimation, you must
specify the 'CalculatePower -no_module_net_capacitances true' or the 'ReducePower
-no_module_net_capacitances true' command.

If you are using one of the capacitance file formats to back-annotate capacitances onto your nets,
PowerArtist performs the checks and generates the following warnings:

• A warning for every net in your back annotation file that it cannot find in the scenario file.
• A warning for every net in the scenario file that was not back-annotated after all back annotation
files are processed.

9.2.1. Back-Annotating Capacitance Using SPEF

This method is most often used for gate-level designs that are placed and routed. SPEF files can be
gzipped and PowerArtist determines if a file is gzipped by examining the first bytes of the file (not
by the file extension). Only simple, lumped RC SPEF is supported.

If there is only one SPEF file that covers the entire design, use the '-spef_file' option as shown
in the following example:
CalculatePower -scenario_file my_chip.scn -spef_file my_chip.spef

For multiple SPEF files, use the hierarchical flow described next.

Hierarchical SPEF Processing

You can provide parasitic information using hierarchical SPEF files. PowerArtist supports two different
flows:

• You can specify the list of SPEF files using the 'SetSpefFiles' command and the top SPEF design
name using the 'SetTopSpef' command. The SPEF reader then determines the hierarchy by
going through the instantiations in the SPEF files (by looking at the '*DEFINE' statements),
and then processing them.

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 Estimating Net Capacitances

To use the flow with '*DEFINE' statements, specify the following commands:

1. SetSpefFiles

This command provides the SPEF reader with all the files that you want to process
(you can specify a single SPEF file). The SPEF reader performs a rapid 'read' of these
files to determine the associated design names. These design names must later be
referenced in '*DEFINE' statements following the SPEF specification.
SetSpefFiles { file_name(s)}

2. SetTopSpef

This command tells the SPEF reader the name of the design that forms the root of
your SPEF hierarchy. Typically, this maps to the top-level design unit in your design
hierarchy. The design name is then used to find the top-level SPEF file, which is read.
As the SPEF reader encounters '*DEFINE' statements, the other SPEF files are located
and read-in. This command is not required when you specify only one SPEF file.
SetTopSpef top_design_name

Sample SetSpefFiles and SetTopSpef Commands

SetSpefFiles { top.spef middle.spef bottom.spef }
SetTopSpef top

• Alternatively, you can specify a hierarchy (hierarchical instance) in the design along with the
SPEF file associated with it, using the 'ReadParasitics' command.

To use a flow that follows SPEF back-annotation methodologies established by industry standard
timing analysis products, include the 'ReadParasitics' command in your PowerArtist command
file (Tcl script).
ReadParasitics -path hierarchical_inst_name -file SPEF_file_name

This command associates a particular SPEF file with a specific hierarchical instance in the
design. The instance name must be fully rooted (that is, it must contain the top module name)
and include dots (.) to separate the levels of hierarchy.

Sample ReadParasitics Commands

ReadParasitics -path mydesign -file ../spef/mydesign.spef
ReadParasitics -path mydesign.mymodule0 -file ../spef/mymodule.spef
ReadParasitics -path mydesign.myblock1 -file ../spef/myblock.spef

SPEF files can represent parasitics either as detailed or reduced models. The reduced model
represents parasitics as a single RC pi-model. Such a model includes the receiver pin capacitance.
PowerArtist supports the reduced and detailed parasitic models. Use the following command
to specify that the parasitic model is reduced and the receiver pin cap is included in the SPEF
file:
ReadParasitics -pin_cap_included true

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Preparing for Power Analysis

The two flows are mutually exclusive. The SPEF reader generates an error if the flows are mixed. Do
not use the 'SetSpefFiles'/'SetTopSpef' commands if you are using the 'ReadParasitics' command.

Handling SPEF Comments

To ignore C-style comments, include the 'SetCCommentsIgnore' command. This command is identical
to the '-iscc' option. This command indicates that C-style comments should be ignored in the SPEF
file.

A sample line that contains a C-style comment is:

*NAME_MAP
*1931 buffer/read_rc1/buf_rp_read/*suffix*/a

If you ignore C-style comments, the exact string is taken as the net name.

Notes: Be aware of the following points when using these new commands:

• Do not use the '-spef', '-spef_file', and any of the hierarchical SPEF commands together.
This causes an error.
• The SPEF reader does an incremental back-annotation. If a net already has parasitics associated
with it, the parasitics specified in the SPEF are added to them.
• If a net specified in the SPEF file is not found in the design, a warning is reported.

9.2.2. Using Back-Annotated Load Capacitances for Primary Outputs

You can specify load capacitances for any primary output of the design by specifying the output pin
name and capacitance for that pin. The format of the capacitance file is provided in the Capacitance
File Format section of the PowerArtist Reference Manual. To specify a file containing load capacitances
from the command line, use the '-load_file' option as shown in the following example:
CalculatePower -scenario_file my_chip.scn -load_file my_chip_lds.cap

9.2.3. Specifying Default Output Load Capacitance Using a Command Option

You can specify default output load capacitance using the '-default_output_load' option as
shown in the following example:
CalculatePower -scenario_file my_chip.scn -default_output_load 3.9e-11

You should always specify output loads. This is especially true if you have pads instantiated in your
design. If you supply a default load value using the '-default_output_load' option or have
annotated your loads using the '-load_file' option, then you do not get messages about your
primary output nets. Primary input nets are not flagged as missing annotations since capacitances
on primary inputs do not impact power consumption.

9.2.4. Using Back-Annotated Wiring Capacitances for Local Nets

You also have the option of specifying a capacitance file that includes capacitances for local nets
including primary outputs. To specify a wiring capacitance file, use the 'CalculatePower
-capacitance_file' option.

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 Estimating Net Capacitances

CalculatePower -scenario_file my_chip.scn -capacitance_file my_chip_wirecaps.cap

9.2.5. Specifying Wire Load Models

You can set the wire load mode and wire load models for your design using Tcl commands. These
are then used for power analysis. You can specify wire load models at the following levels:

• The design level

• Hierarchically, on an instance-by-instance basis
• On a net-by-net basis

The following sections provide an overview of the various commands and precedence rules used to
select the wire load models. You can specify the wire load models using the following commands or
option:

• SetWireLoadMode
• SetWireLoadModel
• SetWireLoadSelectionTable
• SetCapEstimation
• '-wireload_library' option to the 'CalculatePower' or 'ReducePower' commands

9.2.5.1. Using the Wire Load Model Tcl Commands

The following table provides a quick synopsis of the available wire load Tcl commands and the
objects to which they apply:

Applicable Design Object Tcl Command Valid Assignment Values

Design SetWireLoadMode Top or Enclosed
Design, Hierarchical Module SetWireLoadModel wire_load model from library
Instance, or Net file
Design or Hierarchical SetWireLoadSelectionTable selection table group from
Instance library file
Design or Hierarchical SetCapEstimation wire_load model from the
Instance default library file

For details on how to use these Tcl commands in the command file, see Estimating Pin
Capacitance (p. 173).

9.2.5.2. Rules for Estimating Wire Capacitance

Capacitance annotation takes precedence over capacitance estimation methods. This section
discusses precedence rules for capacitance estimation only. The Liberty semantics define a hierarchy
of defaulting rules that must be applied to determine how tools should estimate capacitance using
wire_load models.

PowerArtist has to determine and locate the library to be searched for wire load models. PowerArtist
determines the correct library to be searched by applying the following rules in the given order:

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1. If the 'SetWireLoadMode' command explicitly supplies a logical library name, use that
library as the default library.

2. If there is no explicit specification of a logical library name and you have specified the
'-wireload_library' option, use that library as the default library.

3. Otherwise, select the first library that contains wire_load models in the technology library
list as the default library.

Once you have identified the library to search, then the commands have a set of hierarchical rules.
The rules are:

1. The wire_load mode dictates how wire_load models of children instances are assigned. If
the mode is 'top', assign the wire_load of the parent instance if a parent exists and no
commands pertain to this instance.

2. If the 'SetWireLoadModel' command is specified for a particular instance, use that model.

3. If the 'SetWireLoadSelectionTable' command is specified:

• Locate the wire_load selection table in the library.
• Determine the area of the design.
• Locate the area range and determine the wire_load model.
• If the area is not within the range specified by the selection table, choose the closest
matching range and use that wire_load model.

4. If the 'SetCapEstimation' command is specified, locate the wire_load model in the default
capacitance file.

5. If the 'SetWireLoadSelectionTable' command is not specified, look for the selection table
specified by the 'default_wire_load_selection' attribute in the default library. If
the attribute is supplied, use the same rules as the 'SetWireLoadSelectionTable' command
to determine the wire_load model.

6. If the default library does not contain the 'default_wire_load_selection' attribute

but it contains selection tables then:
• Start from the beginning of the library file.
• Find the first selection table with area limits that meet the area requirements.
• If such a selection table doe not exist, find the selection table that has the closest
matching area requirements.

7. If the default library does not contain selection tables, then use the wire_load model
specified by the 'default_wire_load' attribute.

8. If at this point, nothing has matched, consider the following command:

SetCapEstimation -technology 90 -scale 1

And, follow the 'SetCapEstimation' rules to locate the wire_load model.

These default rules ensure that the power analyzers always estimate capacitance for your design.
When all else fails, capacitance is estimated using the default 90nm technology libraries that are
included with the PowerArtist installation. This is discussed in the following section. If you want to

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 Estimating Pin Capacitance

suppress capacitance estimation completely, use the '-no_module_net_capacitances true'

option (to 'CalculatePower' or 'ReducePower').

The wire load mode has the following default rules:

1. Use the mode specified by the 'SetWireLoadMode' command.

2. If the command is not specified, use the 'default_wire_load_mode' attribute in the

default library being searched for wire_load models.

3. If the 'default_wire_load_mode' attribute is not found, then use 'enclosed' as the

default mode.

Note: The power analyzers do not estimate the wiring capacitance of a net without a fanout. For
example, a primary output has no fanout and the only pin on the net is the driver. Therefore, the
estimators do not compute the wiring capacitance for a primary output.

9.2.6. Using Default Wire Load Models for Capacitance Analysis

Steps '4' and '8' in the previous section describe the conditions under which PowerArtist uses the
default wire load library that comes with the PowerArtist installation. This section describes the reasons
why you should use this built-in library and what it contains.

Some sub-90nm (and smaller) technology libraries do not contain wire load model information. Some
technologists believe that wire load models are not effective at predicting capacitance to a high
enough accuracy for them to be used for timing closure. Therefore, some companies do not include
wire load models in their Liberty files. However, wire load models have a strong role to play in power
analysis, especially at high levels of design abstraction.

If wire load models are not defined in your libraries, but you want to consider wire capacitance during
power analysis using PowerArtist, use the default wire load library that comes with the PowerArtist
installation. This default library has models for various technology sizes. These models were generated
based on experiences with a variety of technology sizes. Ansys recommends that you use these
libraries rather than not consider capacitance at all. The default wire load library is available at:
$POWERARTIST_ROOT/sfl_lib/generic/seqcap.lib

The file contains 'wire_load_selection' tables for 180nm, 150nm, 130nm, 90nm, 65nm, and
45nm technologies. You can use this library, if there is no wire_load model information in any of your
technology libraries. To use this library for capacitance estimation, specify the 'SetCapEstimation'
command.

Unlike all your other Liberty files, you do not need to specify the location of this file using the
'-synlib_files' option. The analyzers automatically locate this library and insert it at the end of
the library search path. Therefore, it is always available for use. This library is read-only, so you can
not accidentally modify it. However, once you install PowerArtist, you can modify it to create a
site-specific set of technology defaults.

9.3. Estimating Pin Capacitance

PowerArtist recognizes the following .lib attributes, which are used to calculate pin capacitance:

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Preparing for Power Analysis

rise_capacitance_range (Min_rise, Max_rise)

fall_capacitance_range (Min_fall, Max_fall)

When you specify the '-interpret_pin_caps_as' option to the 'CalculatePower'/'ReducePower'

commands, PowerArtist uses the 'rise_capacitance_range' and 'fall_capacitance_range'
attributes to calculate pin capacitances, as shown in the example below:
CalculatePower -scenario_file my_chip.scn -interpret_pin_caps min

The valid values of the '-interpret_pin_caps_as' option are 'min', 'max' and 'avg'. The actual
pin capacitance values are calculated as follows:

• min: (Min_rise + Min_fall) / 2

• max: (Max_rise + Max_fall) / 2
• avg: (Min_rise + Max_rise + Min_fall + Max_fall) / 4

The value you select determines the manner in which PowerArtist calculates pin capacitance. PowerArtist
calculates pin capacitance using the following algorithm:

1. If 'rise_capacitance_range' and 'fall_capacitance_range' are present then calculate

pin capacitance using the 'min', 'max' or 'avg' algorithm.

2. Otherwise, use the value from the capacitance pin-level attribute.

3. Otherwise, use the 'rise_capacitance' and 'fall_capacitance' attribute values.

4. Otherwise, set the pin capacitance to '0'.

If the '-interpret_pin_caps_as' option is not specified, then PowerArtist calculates pin capacitance
using the following algorithm:

1. Use the value of the 'capacitance pin-level' attribute, if present.

2. Otherwise, use the 'rise_capacitance' and 'fall_capacitance' attribute values.

3. Otherwise, use the 'rise_capacitance_range' and 'fall_capacitance_range' attribute

values following the 'avg' algorithm.

4. Otherwise, set the pin capacitance to '0'.

9.4. Handling Voltages in Liberty Format

Normally, the characterization voltage is taken from the 'nom_voltage' or the default 'power_rail'
attribute within the 'power_supply' group. The estimation voltage is taken from the voltage set in
'default_operating_conditions'.

If 'nom_voltage' or default 'power_rail' values are not supplied, the characterization voltage is
taken from values within the default operating conditions. If 'default_operating_conditions'
are not supplied, the estimation voltage is taken from the 'nom_voltage' or the default 'power_rail'
attribute within the 'power_supply' group.

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 Handling Designs with Multiple Power Supplies

To get the dynamic power, PowerArtist derates the dynamic energy number by the square of the
estimation voltage divided by square of the characterization voltage. For details about characterization
and estimation voltages, see Liberty Power Supply Support (p. 176).

Any voltage you supply using the '-voltage' option to 'ReducePower' becomes the estimation voltage
for the entire design. Using '-voltage' is an obsolete technique and is replaced with the
'CreateVirtualSupply' command. If the estimation voltage does not equal the characterization voltage,
voltage derating occurs.

9.5. Handling Designs with Multiple Libraries

If you have a hierarchical design, a Liberty library for one portion of the hierarchy might not be suitable
for a different portion of the hierarchy. In general, you might want to do this because you are designing
with multiple voltage domains or power domains. More specifically, you might want to do this because:

• There are different operating conditions for different modules.

• A different set of cells should be considered for default cell selection during RTL power analysis.
• The design was synthesized to gates using different libraries for various blocks in the design.

Choices like these impact the power analysis of your chip. In PowerArtist, you can assign Liberty libraries
to hierarchical instances with libraries further down in the hierarchy, overriding those higher in the
hierarchy. All children of the hierarchical instance inherit the library of the parent unless you specifically
assign them their own power library. You can control these choices using the 'SetLibrary' command.

Handling Multiple Libraries with Different Nominal Voltages

If you specify multiple libraries and if there are conflicting values of voltage in the first library rail of
the different libraries, PowerArtist generates a critical warning 'ADP-27', if it identifies conflicting values
of nominal voltage of different libraries.

9.6. Handling Designs with Multiple Power Supplies

Many designs use more than one power supply (or voltage rail). Common examples include:

• A design with two voltage islands — one supply for the core of the chip and the other for the
I/Os.
• A design that uses power gating. The supplies to the power domains must be explicitly turned
on and off due to the use of sleep signals to put various power domains of your chip in a stand
by mode.

This section describes the ways in which PowerArtist supports designs with more than one power
supply. In addition, this section describes the special support requirements for designs that require
more than one power library (common in hierarchical designs).

PowerArtist provides general support for multiple power supplies by allowing you to:

• Define additional power supplies, which are referred to as virtual supplies.

• Set virtual power supplies on an instance-by-instance basis.

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Note: Any changes to the power supply configurations should be completed after generating a scenario
file.

9.6.1. Creating a Virtual Supply

Creating virtual supplies is most useful for power gating applications. In this application, you can
define one virtual supply per library supply rail, per power domain. This method of creating virtual
supplies supports the specification of on/off conditions for power gating applications. To create a
virtual supply, use the 'CreateVirtualSupply' command.

For voltage domain applications, use the 'SetLibrary' command. You might also use the
'CreateVirtualSupply' command to create virtual supplies with different voltages than those defined
as the default operating condition in the library. If you provide a voltage, it becomes the estimation
voltage and then the library's characterization voltage is derated using the new estimation voltage
value. The new voltage is then used to compute new energy and power numbers. This flow incorporates
the standard PowerArtist derating technique.

9.6.2. Assigning a Virtual Supply to a Hierarchical Instance

If you have a mixed-voltage design, you might want to explore the effects of changing your voltage
values. If your design is organized so that an entire hierarchical sub-section of your design is at the
same voltage, you can set the correct values using the 'CreateDomain' command.

9.6.3. Liberty Power Supply Support

For a library with 'nom_voltage' and operating conditions, the characterization voltage is considered
as the 'nom_voltage' and the estimation voltage is picked up from the default operating conditions.

Similarly, if a library defines multiple supplies using the power supply attribute as shown below:
nom_voltage : 1;
power_supply() {
default_power_rail : VDDlow;
power_rail(VDDhigh, 1.32) ;
power_rail(VDDlow, 1.32) ;
power_rail(VSShigh, 0.00) ;
power_rail(VSSlow, 0.00) ;
}
operating_conditions("BEST"){
process : 0.70;
temperature : 110;
tree_type : balanced_tree;
power_rail(VDDhigh, 1.00) ;
power_rail(VDDlow, 1.00) ;
power_rail(VSShigh, 0.00) ;
power_rail(VSSlow, 0.00) ;
}
default_operating_conditions : "Best";

and the 'default_operating_conditions' are selected 'Best', the estimation voltages for the
supplies are taken as:
VDDhigh - 1V
VDDlow - 1V
VSShigh - 0V
VSSlow - 0V

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 Handling Designs with Multiple Power Supplies

The power numbers are derated accordingly, based on the supply voltages defined in the
'power_supply' construct. To get the dynamic power, PowerArtist derates the dynamic energy
number by the square of the estimation voltage divided by square of the characterization voltage.
Similarly, PowerArtist derates leakage power by the estimation voltage divided by the characterization
voltage.

The Liberty 'rail_connection' attribute is used to specify the power rails to which a cell is tied.
Power for an instance of the cell is derived from those power rails only.

9.6.4. Leakage Power Modeling

Accurate leakage power estimation requires the Liberty leakage power model to be associated with
power and ground pin. The following is an example of such a leakage power model:
library (...) {
...
voltage_map(VDD2, 0.9);
voltage_map(VDD1, 1.2);
voltage_map(VSS, 0.0);

cell (XYZ) {
...
pg_pin (PVDD) {
voltage_name : VDD1;
pg_type : primary_power;
}
pg_pin (PVSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
...
leakage_power () {
value : P;
related_pg_pin : PVDD;
}
}
...
}

If the power and ground pin association is not specified, then such leakage power models are
associated with the first power supply of the library. In the above example, in the absence of the
'related_pg_pin' attribute, the 'leakage_power' model is associated with the first power supply
'VDD2'.

This default association is changed to the first power supply of the cell of type primary_power. In the
above example, in the absence of the 'related_pg_pin' attribute, the 'leakage_power' model
is associated with power and ground pin 'PVDD'. This change can shift the leakage power reporting
to other power supplies of the design. This can also impact the value of leakage power in the presence
of power-gating.

The following critical warning message is reported for the leakage power models without pre-defined
power and ground pin association:
Warning LCF-12: Line 38, file 'switch_cell.lib': For Cell 'switch_cell_1', 'leakage_power'
attributes does not have associated supply/pg_pin. Using 'v_vcc_in' as default supply.

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9.6.5. Fine-Grain Switch Cell Support

The Liberty attributes 'switch_function' and 'pg_function' of fine-grain switch cell are used
to identify fine-grain switch cell and calculate the internal power and leakage power of the cell.

This improves the accuracy of power calculation for fine-grain switch cells. For example, if the
'switch_function' is evaluated as 'one(1)' based on simulation signal values, the corresponding
energy for the related arcs is calculated as 'zero(0)'.

This enhancement is available in 'CalculatePower' (average and time-based power analysis) and
'ReducePower' flows.

Average Power Analysis

During average power analysis, duty of the 'switch_function' is calculated using event-based
evaluation. However:

• If simulation data of any net that is a part of the 'switch_function' is missing, then
event-based evaluation is not performed and the following warning is reported:
VCD-306: Event-based analysis will not be performed for the switch function
'!(top.in1)' of instance 'top.x.memInst' as simulation data for
net(s): 'top.in1' is not available.

• When event-based evaluation is not performed, duty is calculated through activity propagation.
Therefore, when duty evaluates to:

'one(1)':

The energy/power of liberty cell arcs of cells that use the switched supplies as their
Power-Ground (PG) supplies is calculated as 'zero(0)'.

'zero(0)':

The energy/power of liberty cell arcs of cells that use the switched supplies as their
Power-Ground (PG) supplies remains the same.

any other value:

The energy/power of liberty cell arcs of cells that use the switched supplies as their
Power-Ground (PG) supplies is scaled based on this duty value.

Time-based Power Analysis

During time-based power analysis, the 'switch_function' is evaluated using event based calculation.
When any signal in the 'switch_function' toggles, the 'switch_function' expression is
re-evaluated and the PG pins related to the 'switch_function' are updated. If simulation data of
any net that is a part of the 'switch_function' is missing, then the following warning is reported:
TBE-243: The switch function: '!(top.in1)' of instance 'top.x.memInst' will not
be evaluated as simulation data for net(s): 'top.in1' is missing.

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 Handling Designs with Multiple Power Supplies

Power Reduction
Refer section Fine-Grain Switch Cell Support (p. 375) for details of this support in the power reduction
flow.

9.6.6. Mode-based Leakage Power in Vectorless Flow

Leakage power is computed using the 'when' condition expressions in the static vectors in the liberty
library files. Consider the following example of a library:
cell (test_cell) {
...
...
...
leakage_power () {
related_pg_pin : VDD;
when : "! AON_IN & !S_D & D_SLP & !D_SLPLV";
value : 47.628600;
}
}

In the absence of activity information for the cell's pin in the activity file or in the vectorless flow,
leakage power is computed using the 'mode_definition' and 'mode_value' attributes in a library.
Consider the following example of a library:
cell (test_cell) {
...
mode_definition(t*_sram_mode) {
mode_value(DSLP_*_SEL01) {
when : "AON_IN & !S_D & D_SLP & !D_SLPLV" ;
sdf_cond : "when_pm_d_slp_diodedrop_01";
}
mode_value(DSLP_*_SEL00){
when : "!AON_IN & !S_D & D_SLP & !D_SLPLV";
sdf_cond : "when_pm_d_slp_diodedrop_00";
}
mode_value(DSLP_*_SEL02){
when : "!AON_IN & !S_D & D_SLP & D_SLPLV";
sdf_cond : "when_pm_d_slp_diodedrop_02";
}
}
}
...
...
leakage_power () {
related_pg_pin : VDD;
mode(t*_sram_mode, DSLP_*_SEL01)
value : 47.628600;
}

PowerArtist can recognize modes specified using expressions such as 'DSLP_*_SEL01' and obtain
the associated leakage power. This support is enabled by the option '-mode' to the 'SetStimulus'
command:
SetStimulus -instance <instance_name> -mode <string>

This enhancement is supported in average power analysis and power reduction using the following
variable:
pa_set report_mode_based_power <true | false>

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Preparing for Power Analysis

The default value of the variable 'report_mode_based_power' is 'false'.

Outputs
• Average Power and Reduction Reports

A section is added to the average power analysis and power reduction reports, where the 'per
supply per mode' power numbers are reported. A sample report is shown below:
<snip>
3. Power Per Mode
=================
Power(Watts)
Component Mode Supply Static Dynamic Total
--------- ---- ------ ------ ------- ------
top.x1.mInst DSLP_*_SEL0 tsn5p_*_*.VDDM 206nW 0W 206nW
tsn5p_*_*.VDD 47.6uW 0W 47.6uW
Total mode power 47.8uW 0W 47.8uW
<snip>

• APSH/Container Support

The leakage power numbers can also be obtained by specifying 'mode_based_leakage_power'

with the 'get_property' container command, as shown in the example below:
% get_property -class cell x1/mInst mode_name
DSLP_*_SEL0

% get_property -class cell x1/mInst mode_based_leakage_power

206nW

• Message

The value specified for the '-mode' option should exist in the library specified in the design. If the
mode specified with the 'SetStimulus' command is not found in the library, the following warning
is issued:
ENG-956: Mode '<mode name>' specified with the 'SetStimulus' command is not
found in any library for the following instances:
<instance name>
<instance name>

The enhancement is available in available in the following flows/commands:

• Average Power Analysis (CalculatePower -analysis_type average)

• Power Reduction (ReducePower)

Examples
• Example 1: In this example, although there are two instances, mode-based leakage power is needed
only for one instance:
SetStimulus -instance inst_01 -mode mode_t_01
pa_set report_mode_based_power true

Note: Leakage power for the second instance 'inst_02' is then computed using the 'when'
condition expressions in the static vectors in the liberty library files.

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 Running RTL Mixed-VT Power Analysis

• Example 2: In this example, there is one instance with multiple mode definitions and one mode
is selected to compute the leakage power:
SetStimulus -instance inst_01 -mode mode_t_02
pa_set report_mode_based_power true

• Example 3: In this example, wildcards are used to specify one mode across multiple instances:
SetStimulus -instance inst_0* -mode mode_t_0_x
pa_set report_mode_based_power true

9.7. Running RTL Mixed-VT Power Analysis

Using cells characterized for different threshold voltages (Vt) is a critical way to control leakage power
in low-power designs. Many gate-level synthesis and physical design tools can optimize your design to
reduce your leakage power by replacing regular threshold voltages cells with cells that have a higher
threshold voltage. This optimization is typically done to cells on paths that have positive timing slack.

To perform this optimization you must either have multiple libraries characterized at a single threshold
level or libraries characterized for multiple thresholds. Some tools, such as PowerCompiler ™, suggest
that you get superior optimization results using libraries characterized for multiple thresholds. PowerArtist
allows you to perform power analysis that takes mixed-Vt libraries into consideration and supports both
library methodologies.

9.7.1. Critical Liberty Leakage Attributes

Synopsys' Library Compiler ™ supports two attributes related to threshold voltage:

• At the library level:

default_threshold_voltage_group : "string" ;

Example: For this example, assume that the library provider has established conventions where
HVT implies high threshold voltage devices and LVT implies low threshold voltage devices:
default_threshold_voltage_group : "HVT" ;

In this example, unless a particular cell has a 'threshold_voltage_group' that cell is a high
VT device.

• At the cell level:

threshold_voltage_group : "string" ;

Example: Another example for a mult-Vt library is multiple cells with different
'threshold_voltage_group' attributes as shown below:
cell (NAND2_HVT) {
threshold_voltage_group : "HVT";
...
}

cell (NAND2_LVT) {
threshold_voltage_group : "LVT";

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Preparing for Power Analysis

...
}

Your libraries should be defined with these attributes. PowerArtist uses the supplied strings to
differentiate threshold voltages for mixed-VT power analysis.

PowerArtist allows you to use Tcl commands to supply these attributes if they are missing from your
libraries using the 'SetVoltageThreshold' command. See the next section Categorizing Cells for
Multiple VTs (p. 182).

The 'SetVT' command is used to assign different thresholds to hierarchical instances in your design.
The methodology is based on the assumption that most customers have an idea of the typical spread
between different VT points in their modules. An example command is:
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {HVT:70 LVT:30}

In this example, the default cells of all the inferred elements that are children of 'top.block1' and
'top.block2' are chosen from the libraries used for power analysis and assigned such that '70%' of
the default cells have a 'vt_group' with the value 'HVT' and '30%' have the value 'LVT'. The standard
PowerCompiler ™default values are used. If the 'threshold_voltage_group' attribute is not
found in a cell, then the 'default_threshold_voltage_group' value is used. Instances that
are not children of 'top.block1' and 'top.block2' are assigned default cells without any
consideration for the threshold voltage attributes.

It is possible to assign the 'SetVT' command hierarchically. For example, if the 'SetVT' command is
specified for one of the instances 'top.block1.child1', it overrides the percentage values set by
the 'SetVT' command specified for 'top.block1'.

9.7.2. Categorizing Cells for Multiple VTs

If your libraries do not categorize cells using Liberty threshold voltage attributes, you need to categorize
cells for different threshold voltages using the 'SetVoltageThreshold' command. An example command
is shown below:
SetVoltageThreshold -group LVT -pattern { *_TL1 *_TL2 }
SetVoltageThreshold -group HVT -pattern { *_TH }

This example sets the threshold voltage string of cell names in the supplied libraries as explained
below:

• The threshold voltage string of any cell names that match the patterns '*_TL1' or '*_TL2' is
set to 'LVT'.
• The threshold voltage string of any cell names that match the pattern '*_TH' is set to 'HVT'.

Note: The 'SetVoltageThreshold' command overrides any existing threshold voltage string previously
set for a particular group.

The 'SetVT' example, in the previous section, assumes that the supplied libraries categorize the cells
based on the Liberty threshold voltage attributes. If they are not categorized this way, you must use
the 'SetVoltageThreshold' command in addition to the 'SetVT'' command.

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 Running RTL Mixed-VT Power Analysis

SetVoltageThreshold -group LVT -pattern { *_TL }

SetVoltageThreshold -group HVT -pattern { *_TH }
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {HVT:70 LVT:30}

In this example, any cells from the supplied libraries that are available for 'top.block1' and
'top.block2' with names that match the pattern '*_TL' are included in the 'LVT' threshold voltage
group. Cells that match the pattern '*_TH' are included in the 'HVT' threshold voltage group.

9.7.3. Default Cell Selection for Mixed-Vt Analysis

If you do not perform mixed-VT analysis using the 'SetVT' command, for each of the default cells,
PowerArtist automatically chooses three cells from your .libs that can drive 'low', 'medium', and 'high'
loads.

With mixed-VT analysis, PowerArtist selects three additional default cells for each cell type for each
threshold group. This happens even if you specify only one mixed-VT library.

In this example, PowerArtist searches for three candidate cells, one each for the default cells, one
each for the three voltage groups in the library 'mixed-vt':
SetLibrary -instance top.block1 -library mixed-vt
SetVT -instance top.block1 -vt_group {HVT:50 REG:20 LVT:30}

9.7.4. Cell Selection for Clock Gates, Inferred Buffer Tree and MBFs
Mixed-VT analysis is extended to support cell selection for clock gates, inferred buffer tree, and
multi-bit flops.

• Mixed-VT Support for High Fanout Net Buffers

Use the 'SetBuffer -cells' command to specify buffer cells of different VT types. The option value
is a comma-separated list of cell names along with their logical library names. It is mandatory to
specify the cells of each desired VT type.

Use the 'SetVT' command to specify the desired VT percentage of the buffers cells. Each level in
an inferred buffer tree uses buffer cells of the same VT type.
SetBuffer -type root -cells { library1:cell_a1, library2:cell_b2 } \
-fanout 2
SetVT -mode percentage -instance {top} -type inferred_buffer \
-vt_group {HIGH_VT:70 LOW_VT:30}

The 'SetBuffer' command implies that the cells, 'cell_a1' and 'cell_b2', are used for the root
node of the inferred buffer tree. The 'SetVT' command implies that '70%' of all inferred buffers are
mapped to 'HIGH_VT' cells and '30%' are mapped to 'LOW_VT' cells.

• Mixed-VT Support for Clock Gates

Use the 'SetClockGatingStyle' command to specify clock gating cells of different VT types. The
option value is a comma-separated list of cell names along with their logical library names. It is
mandatory to specify the cells of each desired VT type.

Use the 'SetVT' command to specify the VT percentage of the clock gating cells.

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Preparing for Power Analysis

SetClockGatingStyle -gating_cells {library1:cell_a1, library2:cell_b2}

SetVT -mode percentage -instance {top} -type clock_gate \
-vt_group {HIGH_VT:70 LOW_VT:30}

The 'SetClockGatingStyle' command implies that the cells 'cell_a1' and 'cell_b2' are used for
the clock gates. The 'SetVT' command implies that '70%' of all clock gates are mapped to 'HIGH_VT'
cells and '30%' are mapped to 'LOW_VT' cells.

• Mixed-VT Support for Multi-bit Flops (MBFs)

Use the 'SetVT -type mbf' command to specify MBF specific mixed-VT percentage.

9.7.5. SetVT Support for Clock Gate Cell Selection

Several enhancements are integrated to clock gate cell selection as it relates to different threshold
voltage libraries. The details of the enhancements are given below:

• In the non-PACE flow, by default, PowerArtist infers a single clock gate instance for all loads
driven by a common clock gate enable expression. However, if 'SetClockGatingStyle
-max_bit_width' is specified, the inferred clock gate is split into multiple clock gate instances
based on the value of '-max_bit_width'. This ensures that the inferred clock gate instance
is not driving a load higher than the specified '-max_bit_width' value. PowerArtist selects
multiple cells such that the ratio of the inferred and split clock gating cells match the VT
distribution specified with the 'SetVT' command for clock gating cells.

Consider the following example of the usage of the 'SetVT' command:

SetVoltageThreshold -group RVT -pattern {*uniquePattern_for_RVT}
SetVoltageThreshold -group LVT -pattern {*uniquePattern_for_LVT}
SetVoltageThreshold -group SLVT -pattern {*uniquePattern_for_SLVT}
SetVT -mode percentage -instance ${topModule} \
-vt_group {RVT:100.0 LVT:0 SLVT:0}

And its corresponding impact on the 'Cell Selection' report, where 'RVT' cells are setup as
specified in the 'SetVT' command:
<snip>
3. Cell summary of inferred clock gates.

<cell_name1>_{uniquePattern_for_RVT} RVT Clock gate - 3

<cell_name2>_{uniquePattern_for_RVT} RVT Clock gate - 174
<cell_name3>_{uniquePattern_for_RVT} RVT Clock gate - 295
...
<cell_name9>_{uniquePattern_for_RVT} RVT Clock gate - 1038
<cell_name10>_{uniquePattern_for_RVT} RVT Clock gate - 90
<cell_name11>_{uniquePattern_for_RVT} RVT Clock gate - 267
<cell_name12>_{uniquePattern_for_RVT} RVT Clock gate - 25

<snip>

• In addition, PowerArtist always applies VT distribution from the user-specified 'SetVT' constraints
for clock gating cells:
SetVT -mode percentage -type clock_gate -instance ${topModule} \
-vt_group { RVT:100.0 LVT:0 SLVT:0 }

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 Running RTL Mixed-VT Power Analysis

PowerArtist also applies the VT distribution as specified through the 'SetVT' command when
enhanced clock gating (ECG) spans across more than one hierarchical instance.

• The 'SetVT' command has higher precedence over PACE clock gate cell selection when 'SetVT'
commands are specified along with PACE clock models.

9.7.6. Sample Mixed-VT Flow and Tcl File

To prepare for mixed-VT power analysis, first create a file 'mixed_vt.tcl' as shown below:
# Mixed-VT Lib and Threshold Settings#
SetLibrary -instance {top}
-library {scmetro_cmos10lp_hvt_ff_1p1v_125c scmetro_cmos10lp_lvt_ff_1p32v_125c}
SetVoltageThreshold -group LOW_VT -pattern {*L}
SetVoltageThreshold -group HIGH_VT -pattern {*H}

##Mixed-VT Specific Settings##

SetVT -mode percentage -instance {top} -vt_group {LOW_VT:30 HIGH_VT:70}

To perform power gating with mixed-VT analysis, combine the power gating related commands with
the mixed-VT commands. For this example, append the following commands after the commands in
the 'mixed_vt.tcl' file:
############################################# Power Gating Commands
# rx_rq and tx_rq are sleep signals
CreateVirtualSupply -supply vdd -virtual_supply VDDRX -on top.rx_rq
CreateVirtualSupply -supply vdd -virtual_supply VDDTX -on top.tx_rq
CreateVirtualSupply -supply VDDNW -virtual_supply RX_VDDNWS -on top.rx_rq
CreateVirtualSupply -supply VDD -virtual_supply RX_VDDNWS -on top.rx_rq
CreateVirtualSupply -supply VRET -virtual_supply RX_VRET -on (!top.rx_rq)
CreateVirtualSupply -supply VDDNW -virtual_supply TX_VDDNWS -on top.tx_rq
CreateVirtualSupply -supply VDD -virtual_supply TX_VDDNWS -on top.tx_rq
CreateVirtualSupply -supply VRET -virtual_supply TX_VRET -on (!top.tx_rq)
CreateDomain -instance top.core1.r1 -virtual_supply {VDDRX RX_VDDNWS RX_VRET}
CreateDomain -instance top.core1.t1 -virtual_supply {VDDTX TX_VDDNWS TX_VRET}
MapRetentionCell -instance {top.core1.r1} -attribute CK_LOW
MapRetentionCell -instance {top.core1.t1} -attribute CK_LOW -tag NoMap -notag true

This is also an example of a complex Tcl file containing a variety of commands.

9.7.7. Understanding Mixed-Vt Analysis Results in the Report File

PowerArtist generates a section in the .rpt file when you specify the 'SetVT' command and run a
power analysis or reduction.

• Sample Report Section for Mixed-VT Analysis

For every hierarchical instance specified in the 'SetVT' command, the report includes the total
number of default cells selected for each of the specified VT values.
Mixed-VT Cells Distribution
===========================
Hier-Instance VT Group Specified Number of Cells
Name Name Percentage Selected
------------- -------- ----------- ---------------
top.block1
HVT 50 40
REG 30 24
LVT 20 16
---------------

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Preparing for Power Analysis

Total 80
-----------------------------------------------------
top.block2
HVT 50 20
REG 30 12
LVT 20 8
---------------
Total 40

• Mixed VT Analysis Report with 'Other VTs'

If a particular default cell type is not found in the 'threshold_group' specified in the 'SetVT'
command, then default cells of that type are chosen independent of the 'threshold_group',
from the libraries that are set on that hierarchical instance. The total number of the default cells
selected are shown in an additional row where 'Other VTs' is specified under the 'VT Group Name'
column.

For example, if you specify the following 'SetVT' command:

SetVT -mode percentage -instance {top.block1} -vt_group {HVT:90 LVT:10}

And a few default cells were not found for 'threshold_group' 'HVT' and 'LVT'. Then the cells
are chosen from other VTs. For this example, the following report is generated:
Hier-Instance VT Group Specified Number of Cells
Name Name Percentage Selected
------------- -------- ----------- ---------------
top.block1
HVT 90 110
LVT 10 13
Other VTs 0 7
---------------
Total 130

9.8. Setting up Clock Power Analysis

You can set-up PowerArtist to perform clock power analysis. Clock power has two primary components:

• Power consumed by the clock buffer (internal cell power) driving the capacitive load.
• Power due to the capacitive load.

The capacitive load has two primary components:

• Load due to the cumulative input capacitance of the inputs of all clock loads.
• Capacitance due to the wiring on the clock line.

Therefore:
Pclk = (Cfanout + Cwire)V2fclk

Where:

Cfanout This value is determined by analyzing the HDL code, coupled with input capacitance
information from the technology file.

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 Setting up Clock Power Analysis

Cwire The wiring capacitance is based on an estimate of the amount of wiring required to distribute
the clock. 'C wire ' therefore depends on the fanout of the net and is calculated from a wire
load model in the specified libraries.

You can either specify this wire load model for a clock net or allow PowerArtist to do the selection
based on standard wire model selection rules.

9.8.1. Commands for Clock Power Analysis

PowerArtist provides a set of commands to specify the clock net in the design and provide information
on any clock buffers for which a clock tree must be inferred. To enable clock power analysis, you
must include the appropriate commands in your PowerArtist command file.

The two commands that you can use to define your clock net are:

• SetClockNet

The command specifies a clock net in the design and is mandatory.

• SetClockBuffer

The command specifies the clock buffers for which PowerArtist must infer a clock tree. If you
specify 'SetClockNet -mode trace' command, the 'SetClockBuffer' command is optional.
It is required only for inferred clock trees.

Note: 'tree' is the only topology PowerArtist supports.

Sample Usage
Suppose you want to trace a clock named 'tclk', which has special circuitry beginning with instance
'chip_top.mux21-a' that you do not want to include in the power analysis. Also suppose that the
wire load model 'WL_05x5' should be applied to 'chip_top.tclk' and all the sub-nets that make
up this traced clock net. For these parameters, you should specify the following 'SetClockNet' command
in your command file:
SetClockNet -name chip_top.tclk -mode trace -stop_at_instance chip_top.mux21-a

Next, suppose you want to infer a clock net, 'pciclock', you should also include the following:
SetClockNet -name chip_top.pciclock -mode infer
SetClockBuffer -type root -name clkr -library lib1 -fanout 12
SetClockBuffer -type branch -name clkb -library lib1 -fanout 10
SetClockBuffer -type leaf -name clkl -library lib1 -fanout 8

And to set a wire load model for the clock net defined, you can specify the 'SetWireLoadModel'
command shown below:
SetWireLoadModel -name WL05x5 -library * -net chip_top.tclk

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Preparing for Power Analysis

9.8.2. How Clock Power Analysis Works

For clock power analysis on a net driving a large number of clock pins, PowerArtist first determines
the pin load due to all clock pins on the net and the capacitance needed due to wiring to drive all
the clock pins.

If there is an instance driving the clock net, PowerArtist determines the maximum fanout for the
instance output or the maximum capacitive load that the output can drive.

• For a gate-level instance, this information is obtained from the 'max_fanout' or

'max_capacitance' attributes for the cell output pin represented in Liberty format. If these
attributes are not in the library, then use the 'SetCellDefaultFanout' or the 'SetDefaultFanout'
command to specify the default fanout.
• For an RTL instance, PowerArtist searches the output of the default 'NAND' cell for
'max_fanout'/'max_capacitance' information, which is then used on the instance output.
To specify the default fanout for an RTL instance, use the 'SetCellDefaultFanout' command
on the default 'NAND' cell.
Since the 'SetCellDefaultFanout' command does not override the value of 'max_fanout' in
your library, if you are performing an RTL power analysis, you could do one of the following:
– Find all cells that are two-input NANDs and set the defaults for just the NAND gates
using wild cards in one or more commands.
or,
– Do a complete wild card specification on cells and libraries, as shown in the following
example:
SetCellDefaultFanout -cell * -library * -fanout <value>

If there are no drivers for the net (that is, the clock net is a primary input) clock buffers are always
inserted. Using the specified buffers and their fanouts, PowerArtist synthesizes a clock tree using the
following process:

1. Calculates the number of leaf-level buffers to be inserted based on the number of clock pins
on the net, and the specified fanout for the leaf buffer.

2. Checks the branch fanout to determine how many branch buffers are needed and then inserts
branch-level buffers to drive the leaf buffers.

Using this method, PowerArtist continues to insert branch buffers, level after level, until a stage is
reached in which a single root buffer can drive all of the next branch-level buffers.

Example
If there are '100' pins on a primary clock net (no driver) and the leaf buffer fanout is '4', then '25'
buffers are inserted at the leaf-level. If the branch driver fanout is '10' and they have to drive '25'
leaf-level buffers, 'three' buffers are inserted at the branch-level. Finally, 'one' root driver is added
to drive the 'three' branch buffers.

The wiring capacitance from the root buffer to all leaf-level buffers is calculated using the wire load
model for the clock net on which the buffers are inserted.

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 Setting up Clock Power Analysis

9.8.3. Controlling Forward Clock Tracing

PowerArtist performs forward clock tracing to isolate an instantiated clock path in a design and create
a separate report showing the power consumed by the clock path. PowerArtist starts tracing forward
from a net specified with the 'SetClockNet' command in the clock nets file. Tracing stops when any
of the following are encountered:

• A clock pin of a sequential device

• A primary output of the design
• Black-boxes

You can also control when the tracing stops by using one of the followings options for a given clock,
such as 'chiptop.CLKIN':

• -stop_at_instance

In the following example, PowerArtist stops tracing the net 'CLKIN' when it reaches the
specified instance:
SetClockNet -name chiptop.CLKIN -mode infer -gate_clock yes
-stop_at_instance { chiptop.corepinmux.coretop.pbustop.syscfg_if.SYSPLL }

• -stop_at_cell

In the following example, PowerArtist stops tracing at the cell type 'PLL':
SetClockNet -name chiptop.CLKIN -mode infer
-gate_clock yes -stop_at_cell { PLL }

In the above example, tracing continues if any instances are specified using the
'TraceThruInstance' or the 'TraceThruCell' commands.

Supported Timing Arcs

The following 'combinational' timing arcs are supported:

• combinational
• combinational_rise
• combinational_fall
• three_state_disable
• three_state_disable_rise
• three_state_disable_fall
• three_state_enable
• three_state_enable_rise
• three_state_enable_fall

The following 'sequential' timing arcs are supported:

• rising_edge
• falling_edge

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Preparing for Power Analysis

RTL Designs without Timing Arcs

Tracing RTL designs whose libraries do not contain any timing arcs is affected by the number of
output pins on an instance. If there are three or more output pins, clock tracing stops at that point.
The inferred model types: 'decoder', 'comparator', 'adder', 'tri-state' driver, 'unencoded_mux',
''regfile', 'latchfile', or 'multiplier can cause tracing to stop. When tracing fails, buffers
leading up to the failure point are not included in the clock report.

Estimating Instantiated Clock Tree Capacitance

If you have back annotated capacitances for your clock nets, PowerArtist uses those values. Otherwise,
it uses wire load models for all wires up to and including the leaf buffers. A wire load model for a net
in the clock tree is selected based on the following rules:

1. If you supplied a wire load model for the clock net, that wire load model is used for the clock net
and all the sub-nets in the clock tree. 'Sub-nets' are nets between clock buffers in the clock tree.

2. If you supplied a wire load model for any of the sub-nets, that wire load model is used to estimate
the capacitance of the sub-net.

3. If a wire load model was not supplied, PowerArtist uses standard area-based wire load model rules
to determine the wire load model, as is done for any net in the design, to determine the wire
load model assigned to the net.

PowerArtist then uses a heuristic algorithm to estimate the capacitances of wires between the leaf
buffers and the clock pins of sequential devices by inferring clock trees between them, if needed.

Calculating Switching Power of Primary Input Power

Use the following variable to calculate and report the switching power of primary clock nets as part
of total clock power:
pa_set include_primary_clock_net_switching_power true

9.9. Setting up Clock Gating for Power Analysis

PowerArtist allows you to select the conditions under which clock gating should be performed to
conserve power. PowerArtist takes this information into consideration and performs clock gating during
power analysis. The power report generated at the end of the analysis includes information on clock
gating, specifying which registers were gated and providing details about which clock gating cells were
used in addition to the resulting power numbers.

The key features of PowerArtist clock gating are:

• Clock gating is performed using integrated clock gating cells that are defined using the
methodology established by Synopsys ™.
• You control which integrated clock cells are selected from the library, the clock nets that are
gated, and the minimum bit width required for a register bank to be clock gated.
• Reports that describe the clock gating performed by PowerArtist.

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 Setting up Clock Gating for Power Analysis

9.9.1. Clock Gating Flow for Power Analysis

The flow for performing clock gating with power analysis in PowerArtist is as follows:

1. Define your integrated clock cells in your Liberty (.lib) libraries.

2. Add a section to your PowerArtist Tcl command file that indicates your clock gating decisions.
For every net you want to gate, specify the following command:
SetClockNet -gate_clock yes <options>

3. Run your PowerArtist command file to perform an average power analysis.

4. Review the generated report file (.rpt) to see the clock gating results.

See the 'Running Power Analysis with Clock Gating' section in the tutorial for a sample power analysis
with clock gating.

9.9.2. Performing Enhanced Clock Gating

One of the constraints for register-based clock gating is the required minimum bit width that register
banks must satisfy before they are clock gated. You set this constraint using the '-min_bit_width'
option to the SetClockGatingStyle command. However, synthesis tools create 'weak' enables that
extract common sub-expressions from enable expressions that do not meet the minimum bit width
constraint. Consider the following sample RTL:
always @(posedge clk)
if (en1 and en2)
out1 = in1;

always @(posedge clk)

if (en1 and en3)
out2 = in2;

Assuming the two register assignments are a total of 3 bits, you can insert an ICGC with 'en1' as the
enable signal. The output clock of the ICGC then becomes the clock input to the two register banks'
that have feedback muxes with 'en2' as one select line and 'and3' as the other. Assuming that 'en1'
is not enabled 100% of the time, then the clock going to the registers is toggling less often, saving
power.

Similar to synthesis tools, PowerArtist has constraints controlling the use of weak enables. There are
two commands that control the options and they are explained below:

• Specify the following options in the 'SetClockNet' command:

– -enhanced_cg <true | false>

The default value of this option is 'false'. If you set this to 'true', weak enables are
used when possible. This option is valid only when you have also specified
'-gate_clock yes'. If you do not specify '-gate_clock yes' with '-enhanced_cg
true', PowerArtist issues the following warning:
ENG-139: "Clock net XXX will not be clock gated...".

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Preparing for Power Analysis

Note: The option '-enhanced_cg true' is mandatory and enables the enhanced
clock gating flow in PowerArtist.

– -cg_effort <low | medium | high>

This option locates enhanced clock gating (ECG) opportunities and takes 'low', 'medium',
and 'high' as values. The default value is 'low'. Higher the effort level, harder the tool
works to locate the ECG opportunities.

During RTL power analysis and reduction, PowerArtist extracts common weak enables
across registers to gate their clocks, modeling the effects of synthesis enhanced clock
gating (ECG). The ECG expressions can often be complex especially those involving
multi-dimensional signals. Specifying 'medium' or 'high' achieves high power and clock
gating accuracy for ECG expressions and improves QoR without impacting the runtime.

• Specify the following options in the 'SetClockGatingStyle' command:

-min_bit_width_ecg <integer>

The combined bit width of all register banks gated with this weak enable must be greater
than or equal to this value. The default is '2 * -min_bit_width' constraint.

ECG can be performed for complex clock enable expressions, such as those containing a large number
of XOR operations. ECG can also recognize clock gating opportunities for wide registers, especially
greater than 512 bits.

The weaker enables are clock gated among themselves. Thereafter, any left-over bits are processed
and merged with strong enables. This improves the QoR.

The enable expressions are merged so that groups of registers that are too small to have their own
clock gate are grouped together under a common clock gate enabled with the merged expression.

For designs containing a large number of 2D signals, such as register files, you can gain additional
accuracy by trading-off runtime using the following variable:
pa_set ecg_trace_depth_regfile <integer>

By default, the value of the above variable is set to a number based on the value of the -cg_effort
option specified in the SetClockNet command. A high value (for example, 6 or more) can lead to
identification of more ECG opportunities.

Note: This is similar to the variable 'pa_set ecg_trace_depth <integer>', which is applicable
to registers that are not multi-dimensional arrays.

Changes to the Power Analysis Report and the Power Database

If enhanced clock gating is performed, the following changes happen:

• In the Clock Power Consumption section in the power analysis report:

– There is a new sub-section titled 'Integrated Clock Cell Power for Enhanced Gating'. The
format of this section is identical to the existing section, but it contains information
describing the enhanced clock gating performed.

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 Setting up Clock Gating for Power Analysis

– The 'Clock Gating Summary' has the following additional line:

Number of registers enhanced gated by inferred clock gating cells.

This represents the total number of register bits gated using weak enables.
• In the power database (.pdb):
Registers that are enhanced clock gated are marked as other clock gated registers.

Improving QoR and Performance

The clock gating algorithm is enhanced to improve QoR and performance and is enabled by using
the following variables:

• pa_set ecg_clique_creation <sns3 | sns4>

For ECG, to determine the common weak enable among the candidate register enable
expressions, PowerArtist uses a pseudo-random simulation and satisfiability (also known as
Sim-n-SAT or SNS) approach. This algorithm ('sns3') is enabled by default. Additionally, another
version ('sns4') of this algorithm is also available. If you enable 'sns4', it is expected to improve
runtime performance issues arising due to this ECG flow.

Note: Selecting the 'sns4' algorithm can impact the QoR.

• pa_set ecg_hybrid_clique_creation <true | false>

To improve the QoR for clock gate enables for ECG, an alternate mechanism exists for extracting
the weak enables among ECG candidate registers. It uses a combination of the 'sns3' and the
'greatest-common-factor'-based algorithms.

The 'sns3'-based algorithm is highly efficient for runtime performance. The

'greatest-common-factor'-based algorithm gives better QoR in terms of the number of
enhanced clock gated bits or the quality of the enable expressions but can be compute or
runtime intensive.

Use the variable 'pa_set ecg_hybrid_clique_creation true' to enable the hybrid

flow, which is a combination of the best of both approaches to get optimal QoR results with
reasonable runtime.

9.9.3. Library Modeling of Integrated Clock Cells

PowerArtist's clock gating feature takes advantage of the modeling methodology Synopsys has already
defined for integrated clock cells. PowerArtist identifies integrated clock gating cells by looking for
the 'clock_gating_integrated_cell' attribute in the '.lib' file. Ansys recommends that these
cells also have a 'max_fanout' attribute. This attribute tells the algorithm how many loads the cell
can drive.

PowerArtist searches all Liberty files specified using the '-synlib_files' option for integrated
clock gating cells. There is no special switch for specifying the libraries containing clock gating cells.

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Preparing for Power Analysis

Handling ICGC Cells without Functions

This section describes handling ICGC cells that do not contain functions in their definition in the
library. In the absence of functions and pin annotations, PowerArtist had issues in using them for
inferred clock-gating and activity propagation. Support to handle such issues is added. The details
are as follows:

• If the 'clock_gating_integrated_cell' attribute is missing in the ICGC cells in the

library, then you can define it from outside using the following command:
SetAttribute -cell <icgc_cell_name> \
-name clock_gating_integrated_cell -value latch_negedge
SetAttribute -cell <icgc_cell_name> \
-name clock_gating_integrated_cell -value latch_posedge

You do not need to edit the libraries for the above.

• If the required pin annotations are also missing then you can do the following steps:

1. Define the cell type and the pin types, using the 'DefineCell' command:
DefineCell -type icgc -name <icgc_cell_name>\
-pin {{clock <input_clk_pin>}{enable <input_en_pin>}{clock <output_clk_pin>}}

2. Define the ICGC type attribute, using the 'SetAttribute' command:

SetAttribute -cell <icgc_cell_name> \
-name clock_gating_integrated_cell -value latch_negedge
SetAttribute -cell <icgc_cell_name> \
-name clock_gating_integrated_cell -value latch_posedge

Use the first command if the ICGC is meant for a 'negedge' flop and the second command
if the ICGC is meant for a 'posedge' flop.

3. Define the polarity of the enable pin, using the 'SetPolarity' command:
SetPolarity -pin <input_en_pin> -value active_low -cell <icgc_cell_name>
SetPolarity -pin <input_en_pin> -value active_high -cell <icgc_cell_name>

Use the first command if the ICGC passes the clock when enable is '1'b0' and the second
command if the ICGC passes the clock when enable is '1'b1'.

9.10. Setting up Clock Gating for Power Reduction

Clock gating is performed entirely by the reduction engine controlled by the 'ReducePower' command.
No other command is involved in the process. To perform clock gating, PowerArtist must be told which
nets need to gate and the type of clock gating cells to use for the gating. The clock nets to gate are
not limited to a particular module hierarchy. This is because PowerArtist is not limited to synthesizing
a portion of your design, but can process the entire chip as a whole.

9.10.1. Clock Gating Flow for Power Reduction

If you want PowerArtist to perform clock gating during power reduction, you must perform the
following steps:

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 Setting up Clock Gating for Power Reduction

1. Define your integrated clock cells in your power libraries.

2. Include the following commands in your PowerArtist command file or on the command line:

• SetClockNet

This command defines which clock nets should be gated among other things.

• SetClockGatingStyle

This command defines the attributes that control how clock gating is performed.

3. Run the 'ReducePower' command to perform power reduction.

9.10.2. Clock Gating Algorithm

During clock gating, PowerArtist performs the following steps, in the following order.

1. Reads in the libraries specified using the '-synlib_files' option.

2. Reads in the clock-related commands from your command file.

3. Searches the libraries for all cells containing the 'clock_gating_integrated_cell' attribute
whose value matches that supplied by the 'SetClockGatingStyle -clock_cell_attribute'
command.

Note: If the library does not contain output maximum fanout information, you can specify it using
the 'SetCellDefaultFanout' command in the clock nets file.

4. Identifies the elements that are suitable for clock gating. To be suitable:
• An element must be an 'SFL' type of register. Register files cannot be clock gated.
• The clock name must match that specified using the 'SetClockNet' command (in the clock
nets file) or is traceable from such a clock.
• The 'd_in' of the register must be the output of a 2-1 feedback mux and the 'd_out' of
the register must be an input to the same mux.
• All registers sharing the same clock, enable, and reset pins are gathered together. If the
number of bits is greater than or equal to the 'min_bit_width' value, they are clock
gated. However, if you specified a list of instances with the '-instance' or
'-hierarchical' options of the 'SetClockNet' command, only those instances are
gathered together and clock gated. For more information, see 'Hierarchical Clock
Gating (p. 196)'.

5. Gates the selected registers using the following process:

• Identifies the best fitting integrated clock gating cell (ICGC) to drive the register bank. The ICGC
depends on three attributes/options:
– The '-gating_cells' and '-clock_cell_attribute' options of the
'SetClockGatingStyle' command.
– The 'max_fanout' attribute in its cell description in the technology file.
– The '-max_bit_width' option in the 'SetClockGatingStyle' command.

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Preparing for Power Analysis

• If the '-gating_cells' or '-clock_cell_attribute' options are specified, then the

choice of ICGC is limited to those specified in the option values. These options establish the
candidate ICGCs.
• If the '-max_bit_width' option is not specified then the best fitting candidate ICGC is identified
based on the value of the 'max_fanout' attribute to drive the total number of bits in the
register bank.
– If an ICGC to drive all the bits is not identified, PowerArtist builds a fanout tree based
on the clock buffers specified in the clock nets file. Then, the ICGC drives the fanout tree.
– The load on the net driving the ICGC is reduced by the number of bits in the register
bank. The load is then increased by one due to the added ICGC.
• If the '-max_bit_width' option is specified, PowerArtist chooses an ICGC that best fits the
specified value.
– PowerArtist adds as many ICGCs in parallel that are required to drive the register bank
load.
– A buffer is not inferred in this case.
– The load on the net driving the ICGC is reduced by the number of bits in the register
bank. The load is then increased by the total number of ICGCs added.
• If your technology library uses 'max_capacitance' rather than 'max_fanout' attribute for
its ICGCs, then the 'max_capacitance' value is translated into a 'max_fanout' value by
dividing the 'max_capacitance' value by the 'input_capacitance' of the default flip-flop
clock pin.

6. Performs an RTL average power analysis:

a. Determines the duty cycle of the select pin on the 2-1 mux driving the bits as the duty
cycle of the enable pin on the integrated clock cell.

b. Uses the gate-level power model for the integrated clock cell to calculate the power
consumed by the integrated clock cell.

c. Calculates power for the register bits that are clock gated. The clock activity for these
register bits is derated by the duty cycle for the enable pin in the clock gating cell. The
power for the feedback mux bits is reduced to zero, because these feedback components
are eliminated from the circuit.

7. Generates clock gating information in the power report (activities.rpt). It uses this
information while performing various reductions. Clock tree and clock gating information is
displayed in the PowerCanvas main window just above the tree display. If you display the clock
tree, which comes up in a separate window, you can move your cursor over the different elements
in the clock tree and the dynamic display in the main window changes as you move along. This
provides information such as Activity, Duty Cycle, Frequency, and Net Capacitance.

9.10.3. Hierarchical Clock Gating

This feature gives you control over where the integrated clock gating cells are to be inferred. By
default, PowerArtist attempts to clock gate the entire design at one time. Any inferred register that
shares the same clock net and enable signal controlling a feedback mux is clock gated using the same
integrated clock gating cell. A buffer tree then handles the potentially high fanout load.

However, if you are using a logic synthesis tool that performs clock gating and that has a capacity
limitation, clock gating for the entire design cannot be implemented at one time. Instead, only the

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 Ideal Clock Network Modeling

large blocks in the design that form the boundaries beyond which integrated clock gating cells cannot
be shared are clock gated. You can use the 'SetClockNet -hierarchical' command to overcome
this particular situation. Assume the following design:

In this design, to synthesize and clock gate block 'b2' separately from the remainder of the design,
use the following command:
SetClockNet -name top.clk -hierarchical top.b2 -gate_clock yes

In addition, PowerArtist can perform clock gating on selective blocks in a design using the 'SetClockNet
-instance' command.

Using the example of the same design, if you want to clock gate block 'b2' but not block 'b1', then
use the following command:
SetClockNet -name top.clk -instance top.b2 -gate_clock yes

Refer to the 'SetClockNet command in the PowerArtist Reference Manual for details.

9.10.4. Inferring Buffer Trees for Nets with High Fanout

PowerArtist can infer buffer trees for nets with high fanout. To use this feature, specify the following
commands in the command file:

• SetMaxFanout

PowerArtist infers a buffer tree for any net with at least the given number of fanounts.

• SetBuffer

Use this command to specify the buffers used when inferring a buffer tree for these high
fanount nets.

If you do not use this feature, during inferencing, you can get a tremendous capacitive load on a
driving pin, which can lead to the inferred element.

9.11. Ideal Clock Network Modeling

Ideal clock network modeling is required to enable post-synthesis power correlation in PowerArtist. In
this mode, clock tree optimizations (such as inferring a clock tree and balancing the load) are not
performed. Use one of the following commands to set a clock in the ideal mode:

• SetClockNet -name <clk_name> -mode ideal -gate_clock yes

or

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Preparing for Power Analysis

• pa_set clock_tree_mode ideal

SetClockNet -name <clk_name> -gate_clock yes

Note: You can change the mode by using the following command:
SetClockNet -name <clk_name> -gate_clock yes -mode infer

Since the clock is 'ideal', the transition time in the clock network is set to '0', but you can override it
by using one of the following commands:

• SetClockNet -transition_time <double>

or
• pa_set default_clock_transition_time <double>

Note: If the load capacitance of an instantiated clock tree cell exceeds the specified 'max_capacitance',
the wire capacitance is set to '0'.

9.12. Event-based Analysis

PowerArtist provides higher power estimation accuracy by using event-based analysis to calculate the
duty and activity of nets that are critical for accurate power analysis instead of statistical activity
propagation. This support is available in the following flavors:

• Event propagation for inferred clock gate enables, inferred signal buffer nets, and memory enables
where an FSDB activity file is available.

This support is available in the power analysis ('CalculatePower') and power reduction
('ReducePower') flows with and is enabled by using the following variable:
pa_set event_based_analysis_signal_type <cg_enable | inferred_buffer | mem_enable>

• Event propagation during simulation activity processing ('GenerateGAF'), where PowerArtist

propagates events to the input pins of instantiated instances if the simulation data is available
for all the nets in the cone of the logic driving the macro pins. Propagating events to the input
pins of instantiated instances improves the accuracy of the arc-based power estimation for
memories and instantiated instances when the simulation file does not have activity on some
pins and nets.

This support is enabled by default for the FSDB, VCD, and Veloce emulator native format files.

Event-based analysis support is available only for the following cell types in the fanin cone of
the enable/input net:
– Basic RTL-type elements such as connect, and, nand, or, nor, xor, xnor, aoi, oai, or decoder.
– Instantiated cell elements such as ICGC, isolation cells, or any cell with the function type
similar to the basic RTL-type elements.

• Event propagation for nets without simulation data

PowerArtist supports event propagation through inferred instances in RTL design providing
improved RTL power accuracy. This feature provides two benefits:

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 Event-based Analysis

– Power estimation for simulation data having only power critical signals activities
PowerArtist can read a simulation activity file with power critical signals only and propagate
events to missing named and inferred signals in the design for accurate RTL power analysis.
In this flow, simulators/emulators need to write the simulation data for power critical
signals only. This improves the turnaround time for simulation/emulation and reduces
the size for simulation file.
– Improved RTL power accuracy
Micro-architectural inferencing of RTL designs results in inferred signals in the design
which are not present in RTL FSDB. PowerArtist traditionally performs statistical activity
propagation. Event propagation offers more accurate logic propagation through this
inferred logic and improves RTL power accuracy.

To enable this enhancement, set the following variable to 'true':

pa_set generate_missing_sim_data <true | false>

By default, the variable is set to 'false'.

Notes:
– The enhancement is enabled for both RTL and gate-level instances. For gate-level instances,
only simple cell types (such as: and / or / nand / nor / mux21 / aoi21 / oai21 / aoi22 /
oai22) are supported. The complex cell types (such as: adder or decoder cell) are not
supported.
– If some design nets cannot be evaluated for activity/duty using event-based signal
propagation, the activity/duty of such nets continues to be estimated via activity
propagation.
– For event propagation to work reliably, the input simulation file should contain activity
data for the primary input/output ports, registers, latches, and memory output signals.
– The enhancement is supported for the 'CalculatePower', 'GenerateGAF', and
'ReducePower' commands and is not supported for 'CalculateToggleCoverage',
'CreateRPM', 'GenerateActivityWaveforms', and 'ProfilePower' commands. For the
enhancement to take effect, you must specify this variable 'before' specifying the
'CalculatePower' or 'GenerateGAF' commands.
– The enhancement supports multiple activity file formats including FSDB, VCD, STW (Veloce
flow), and ZTDB.
– The activity source of nets evaluated in this flow is reported as 'EVENT_PROPAGATED'
in the GUI and 'get_property' container command. If you do not enable this feature, the
activity source of nets missing in simulation is reported as 'PROPAGATED / SIMULATION'.
– The GAF flow is enhanced to ignore the nets in the following cases:
Some nets maintained their 'X-state' because the initial input value was not
available from simulation.
Some nets reported the duty value as '0.5' and toggle count as '0' because there
was no event/activity during simulation.
Ignoring such nets ensures that such nets are considered as candidates for activity
propagation during power analysis ('CalculatePower').

The activity/duty of named and inferred design nets calculated using event-based signal
propagation can change when this flow is enabled. You can view the new numbers in section

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Preparing for Power Analysis

'9. Net Frequencies' of the average or time-based power analysis reports. To generate this section
after average power analysis, use the following variable:
pa_set average_report_options g

Computing Activity/Duty of Clock Gates

The activity/duty of some clock gates (whose simulation data is missing) may not be calculated and
PowerArtist uses activity propagation to calculate the gated clock activity/duty. By default, PowerArtist
uses the frequency of the local clock net as input to calculate the output gated clock activity/duty of
the inferred clock gate. You can also specify the root clock net (instead of the local clock net) as input
by using the following variable:
pa_set inferred_cg_activity_source <root_clock | local_clock>

The default value of the variable is 'local_clock'.

Note: The variable 'pa_set inferred_cg_activity_source root_clock' calculates the

activity/duty of only those inferred clock gates whose activity/duty was not calculated by using 'pa_set
event_based_analysis_signal_type cg_enable'.

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Chapter 10: Analyzing Simulation Activity
10.1. Introduction
PowerArtist has the ability to perform flexible activity analysis on time slices as small as a clock cycle.
This is called vector analysis. Analyzing your simulation activity before you perform a power analysis
allows you to:

• Determine if your test bench exercises your design correctly. A test bench for average power differs
from a test bench for peak power.

• Potentially detect functional flaws that are difficult to see by looking at simple waveforms. For example,
if your design should be in an "idle mode" and yet you see significant activity, this might signal a
design error.

The primary method PowerArtist uses to achieve these goals is to provide you with a graph of activity
over time. PowerArtist calculates activity data using the following equation:

You run each simulation once while collecting activity data. Each run provides a graph for a specific
slice of the simulation time, showing the activity for selected portions of the design on the Y axis and
time on the X axis. The portions of the design are called groups.

Each group corresponds to one line waveform on the graph, and can consist of any number of hierarchical
instances of your design. The activity analysis includes the children of the defined instance. It averages
the activities of all nets in the design below the top level (as defined in the group). While activity is
only an indicator of power, displaying the average activity for each of the top-level blocks highlights
test suites that fail to access all blocks on the chip at once, resulting in artificially low power results.

The term 'activity' is used to describe the average activity of named nets in the group. Named nets are
nets that have been explicitly specified in a simulation and appear in a simulation dump, which would
include the boundary pins.

PowerArtist's vector analysis tool has two modes of operation:

• Simulation time-based
In simulation time-based mode, the average activity of the group is graphed over time.
• System clock-based

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Analyzing Simulation Activity

In system clock-based mode, the ratio of the average frequency of the group to that of the clock
is reported.

Chapter Organization
The following topics are covered in this chapter:

• Defining Different Groups at Each Design Phase (p. 202)

• Understanding the Design Flow with Vector Analysis (p. 202)
• Creating Analysis Graphs (p. 203)

10.2. Defining Different Groups at Each Design Phase

As described in the introduction, vector analysis allows you to define arbitrary groups of hierarchical
instances in the chip. PowerArtist computes the activity for each group, and displays the groups as
individual lines in a graph. During different design phases, you might want to define different kinds of
groups:

• System design

You may want to know the activity for all the memories on the chip, for overall clock activity, or for
overall I/O pad activity.

• RTL design

You may want to define each top-level block as its own group. In this way, the tool can display graphs
of activity-over-time for each block. You can raise the activity coverage of your RTL test suite by
making sure that the simulation patterns exercise all the blocks at once. You should also capture the
activity of the primary inputs of your chip. You can compare these against similar activity graphs
from your gate-level design to make sure you have the same testbench driving both. This is a useful
check if you are doing RTL-to-gate correlation studies or comparisons.

• Gate-level design

Define activities on the primary inputs of your chip. Verify that the activity is the same at the gate-level
as at the RT-level.

10.3. Understanding the Design Flow with Vector Analysis

Vector analysis fits seamlessly into your existing RTL design flow, which would consist of the following
steps:

1. Simulate your design to create a simulation activity file in any of the supported formats.

2. Elaborate the design to create a PowerArtist scenario file.

3. Perform vector analysis to create analysis graphs of activity over time for specific groups of instances.
See Creating Analysis Graphs (p. 203) for more information.

4. Use the Waveform Viewer to display the activity graphs.

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 Creating Analysis Graphs

At this point, you may want to use the tool's feedback to improve the simulation test suite for better
coverage of high-activity conditions. See Creating Analysis Graphs (p. 203) for more information.

5. Once you have confidence that your testbenches exercise the design completely, you can use
additional tools to find power peaks and graph power-over-time. See Analyzing Time-Based
Power (p. 255) for more information.

10.4. Creating Analysis Graphs

Before using the analysis tools, you should verify that your testbenches have good power coverage.
Often, testbenches are designed for functional verification or fault coverage, and might not represent
typical operation or worst-case power situations. PowerArtist's vector analysis flow can show you portions
of the design where your testbenches do not produce enough activity. You can tune your testbenches,
by adding tests or exercising more blocks in each test, so that your testbenches adequately cover all
situations. This can prevent real power problems.

Before you begin to find low-activity modules, you should already have a PowerArtist scenario file and
a simulation file. See Acquiring Simulation Data (p. 207) for information on how to capture simulation
data. You can run vector analysis using a command-based (Tcl-script) flow, which is explained in the
next section.

10.4.1. Determining the Type of Vector Analysis to Run

There are two different types of vector analysis:

• clock-cycle mode
• time-based mode

The type of analysis is determined by the value of the following option:

-activity_waveform_graph_type <activity_per_cycle | frequency_per_interval>

You can choose from:

• For 'clock-cycle' mode: activity_per_cycle

• For 'time-based' mode: frequency_per_interval

When you perform a vector analysis, you should align your intervals so that the dominant clock edge
of your choice is at the first interval start time and that each interval is some multiple of the clock
period. If you choose the 'activity_per_cycle' option this happens automatically. If you choose
the 'frequency_per_interval' option, you have to choose the interval start time and the interval
size carefully. The benefit of the 'frequency_per_interval' option is that it offers more flexibility
if you do not want to align your intervals with a clock edge.

10.4.2. Running Vector Analysis Using Command Files

Use the following process to run vector analysis and create your analysis graphs using a command
file (Tcl script):

1. Specify the 'DefineGroup' command to define groups of hierarchical instances in the chip, as
shown in the example below:

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Analyzing Simulation Activity

DefineGroup top "top"

DefineGroup core "top.core1"
DefineGroup pci "top.core1.p1"
DefineGroup rxchan "top.core1.r1"

This example defines four groups named 'top', 'core', 'pci' and 'rxchan' whose activity graphs
are generated for their associated instances.

2. Specify the 'GenerateActivityWaveforms' command to run the vector analysis. You can use
different options depending on the type of vector analysis you want to run:

• Apply the following syntax to run 'clock-cycle' based activity analysis:

GenerateActivityWaveforms -activity_file file_name
-scenario_file file_name -top_instance inst_name
-activity_waveform_clock_name clock_name
-activity_waveform_clock_edge (pos | neg | auto)
-activity_waveform_cycles_per_interval int
-activity_waveform_graph_type activity_per_cycle
-activity_waveform_group_list group_list
-activity_waveform_log file_name
-activity_waveform_number_of_intervals int | all
-activity_waveform_start_clock_cycle int
-ptcl_output_file | -fsdb_output_file
-use_rtl_sim_data true | false

• Apply the following syntax to run 'time-based' activity analysis:

GenerateActivityWaveforms -activity_file file_name
-scenario_file file_name -top_instance inst_name
-activity_waveform_graph_type frequency_per_interval
-activity_waveform_group_list group_list
-activity_waveform_interval_size time
-activity_waveform_log file_name
-activity_waveform_number_of_intervals int
-activity_waveform_start_time time
-ptcl_output_file | -fsdb_output_file
-use_rtl_sim_data true | false

The following is a sample file for 'time-based' vector analysis:

GenerateActivityWaveforms \
-activity_file activities.iaf \
-scenario_file txrx.scn \
-top_instance top_instance txrx_tst.top1 \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_group_list {top core pci rxchan} \
-activity_waveform_start_time 100us \
-activity_waveform_interval_size 1ns \
-activity_waveform_number_of_intervals 1000 \
-fsdb_output_file ${topModule}_vectors_full.fsdb \
-activity_waveform_log Waveform.activity_vw.log \

3. View the resulting FSDB or PTCL file in the Waveform Viewer. A sample waveform is shown below:

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 Creating Analysis Graphs

Figure 10.1: Sample Vector Analysis Waveforms

10.4.3. Activity Waveforms per Signal Category

The 'GenerateActivityWaveforms' command analyzes the input simulation activity file and generates
activity waveforms per hierarchical instance. These waveforms display the total signal activity across
all nets versus functional debug tools that display a signal at a time. The vector analysis feature is
enhanced to also natively support the generation of activity waveforms for different signal categories.

The 'DefineGroup' command creates waveform groups by identifying the category of a net as
determined by its driving instance. This automates the 'per-category' monitoring of activity waveforms
instead of having to manually create the groups of nets.

The following example shows how to specify three groups to monitor different net categories during
activity analysis:

1. Group output nets of combinational logic and macros in the hierarchy 'top':
DefineGroup combo_macro "top" -category { combinational macros }

2. Group output nets of registers and latches in the hierarchy 'top.core1.r1':

DefineGroup reg_latch_core1_r1 "top.core1.r1" \
-category { register latch }

3. Group clock nets of registers, latches, and memories in the hierarchy 'top.core1.t1':
DefineGroup clock_core1_t1 "top.core1.t1" -category { clock }

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Analyzing Simulation Activity

4. Create waveforms for the groups created in steps #1 to #3, by using the following commands:
pa_set activity_waveform_group_list \
{ combo_macro reg_latch_core1_r1 clock_core1_t1 }
GenerateActivityWaveforms \
-log wwgaf.activity_vw.log \
-activity_waveform_graph_type activity_per_cycle

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Chapter 11: Acquiring Simulation Data
11.1. Introduction
This chapter describes how to acquire data from a simulation testbench so that power analysis can
provide the most accurate results. PowerArtist provides the three approaches to acquiring of simulation
data, all of which produce a simulation activity file. In general, the approach that you choose depends
on your design language (VHDL or Verilog), the level of abstraction, and the simulator you are using.
If you are doing RTL VHDL designs, you should choose either FSDB or IAF since these formats have the
capability to store the composite data structure information that is typical of VHDL designs. If you are
doing RTL Verilog, then any approach works. If you are doing large gate-level designs (most likely in
Verilog), the FSDB format is preferred because it more efficiently stores toggle information. In general,
if you can create an FSDB file, use that approach. It is fast, compressed, complete, and consistent across
all simulators in its naming conventions.

If you have instantiated gates in your design, you need to pay particular attention to the amount of
detail you capture in your format of choice. An instantiated gate may be as simple as a flip-flop or as
complex as a memory. If it has a power model in Liberty format, it is a gate. When your simulation runs,
it monitors and writes the nets in your design. If the monitored instance is a gate-level instance, some
simulators do not capture the nets local to the instance. Some of these local nets represent the ports
of the instance. Whether or not ports are monitored for gate-level instances is very critical to know
when performing power analysis.

To perform average power analysis, you should monitor the ports of all gate-level instances. This is not
required to perform time-based power analysis. You lose a little accuracy when trying to perform an
analysis of tri-state gates, but the improvement in performance is quite significant.

PowerArtist supports the following simulations and simulation data formats:

Simulator Supported Formats

All Cadence Simulators FSDB, VCD, IAF
Mentor ModelSim FSDB, VCD, IAF
Synopsys VCS FSDB and VCD

Chapter Organization
The following topics are covered in this chapter:

• Using an FSDB Approach (p. 208)

• Using the Standard VCD Approach (p. 211)
• Acquiring Simulation Data in Palladium Flows (p. 213)
• Troubleshooting Tips (p. 215)

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Acquiring Simulation Data

11.2. Using an FSDB Approach

Ansys recommends that you use FSDB files to get simulation data into PowerArtist. You need to generate
the FSDB (.fsdb) file using the Verdi ™ product from SpringSoft to obtain activity information from the
simulator of choice. Using standard features available with Verdi, you can capture your simulator trace
in an FSDB file.

Memory and MDA (Multi-Dimensional Arrays) value changes are captured by the following group of
Novas system tasks:
$fsdbDumpMem
$fsdbDumpMDA

You can use the '$fsdbDumpvars' task to dump all scalar, vector, and memory/MDAs on struct signals.
For example:
$fsdbDumpvars(top, "+all");
$fsdbDumpfile

dumps all scalar, vector, memory/MDA, and struct signals under the 'top' instance and all of its
hierarchical children. In contrast, VCD files cannot capture memory, MDA, or struct signal types. If these
language features are used in the RTL, a VCD has poorer signal coverage for the design, impacting the
accuracy of the RTL power analysis.

If the design is VHDL (or mixed), then you can enable variable tracing under 'process' by using the steps
listed below:

1. Set the environment variable:

setenv NOVAS_FSDB_TRACE_PROCESS 1

2. Add the '+trace_process' option to the '$fsdbDumpvars' system task:

$fsdbDumpVars(0, ":", "+trace_process");

The above works with IUS6.2, VCS 2006.06, ModelSim 6.4 onwards.

If your FSDB file contains either a larger than necessary time window or levels of hierarchy above the
top module of the power analysis, use 'fsdbextract' to create a smaller FSDB file, enabling faster
performance from CalculatePower. Consider the following exmple:
% fsdbextract my.fsdb -bt 100us -et 200us -s /testbench/top -level 0 -o my_100us-200us_top.fsdb

Once you have an FSDB file, you need to specify it using the '-activity_file' option of the
CalculatePower command.

11.2.1. Split FSDB Support

With increasing design size and simulation duration, size of simulation data dumps have grown
tremendously. Handling large FSDB files are problematic for PowerArtist (and other EDA tools).

The idea is to generate 'N' time-sliced FSDB files. The time-sliced files are smaller, and are easily
processed and re-constructed internally by PowerArtist. Generation of time-sliced FSDB files is best

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 Using an FSDB Approach

done during simulation, using the following Springsoft system tasks to dump multiple FSDB files of
specified size:

• For ModelSim/NCSim:
$fsdbAutoSwitchDumpfile

Example:
$fsdbAutoSwitchDumpfile(10, "slice.fsdb", 3);

• For VCS:
$fsdbAutoSwitchToFile

Example:
$fsdbAutoSwitchToFile("signal.list", "slice.fsdb", 10, 3);

The above example commands generate 3, 10MB FSDB files with same hierarchy, but different time
slices. The file names are: 'slice_000.fsdb','slice_001.fsdb', and 'slice_002.fsdb'. These
files can be processed by PowerArtist for power analysis (average and time-based) and power reduction
as shown below:

• Average power analysis:

CalculatePower -activity_file "slice_000.fsdb" -to_fsdb_index 2

• Time-based power analysis:

CalculatePower -analysis_type time_based -activity_file "slice_000.fsdb" -to_fsdb_index 2

• Power reduction:
ReducePower -activity_file "slice_000.fsdb" -to_fsdb_index 2

11.2.2. FSDB Version

The table below lists the version of FSDB supported in PowerArtist releases:

PowerArtist Release Supported FSDB Version

2024R1.2 Reader: FSDB 6.1 (V-2023.12), Writer: 2015.09
2024R1.1 Reader: FSDB 6.1 (U-2023.03.03-SP2-1), Writer:
2015.09
2023R2.5 Reader: FSDB 6.1 (V-2023.12), Writer: 2015.09
2023R2.4 Reader: FSDB 6.1 (U-2023.03.03-SP2-1), Writer:
2015.09
2023R2.1 Reader: FSDB 6.0 (U-2023.03), Writer: 2015.09

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Acquiring Simulation Data

11.2.3. Virtual FSDB (VF) Integration

PowerArtist now supports Synopsys' proprietary Virtual FSDB format for reading in design activity
from emulation. Support for Virtual FSDB is available in the following PowerArtist flows:

• CalculatePower (average and time-based)

• CreateRPM
• ProfilePower
• ReducePower

Prerequisites for reading Virtual FSDBs are:

• Access to Synopsys NPI libraries, version 'M-2017.03-SP2-6' or higher.

• Path to the NPI libraries in the LD_LIBRARY_PATH environment variable. An example is shown
below:
<Synopsys_Installation>/M-2017.03-SP2-6/share/NPI/lib/LINUXAMD64

• Availability of Verdi licenses. A license is required for each process that reads a Virtual FSDB.

If the FSDB you supply to PowerArtist is not a Virtual FSDB, PowerArtist uses the 'FFR API' by default.
The generated log file indicates whether the 'FFR API' or the Synopsys 'NPI API' was used.

PowerArtist issues an error and exits if you attempt to use the FFR interface to read Virtual FSDB files.
An error is also reported if NPI libraries are not provided for Virtual FSDB files. However, you can use
the FFR API to read virtual FSDB files of type 'NONE'.

The table below lists the Virtual FSDB types, and the API supported in PowerArtist:

Virtual Description API/Adapter

FSDB
Type
NONE FFR
SPLIT Has the same time window but the design scope is NPI
different.
STITCH Is a combination of 'SPLIT' and 'SWITCH' styles. NPI
STREAMLINE Is generated in the emulation flow. NPI
SWITCH Has the same design hierarchy but the time windows are NPI
different.

11.2.4. Support for Multiple FSDB Readers

PowerArtist allows designers to choose between FFR or NPI adapters for the FSDB reader. This support
is enabled through the following variable:
pa_set fsdb_reader_method <ffr | npi>

By default, PowerArtist uses 'FFR API' to process regular FSDBs and 'NPI API' for virtual FSDBs.

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 Using the Standard VCD Approach

Important Note: You can choose the FSDB reader by using the 'pa_set' variable only. Specifying it
as an option on the command line does not work. For example, the following command does not
change the FSDB Reader to NPI:
CalculatePower -analysis_type time_based -fsdb_reader_method npi

11.2.5. Honoring the FFR FSDB Reader in User Environment

The FFR FSDB reader used for reading FSDB files is shipped with PowerArtist. Support is added to
give precedence to the FFR FSDB reader version available in your environment.

To enable this support, add the path to the Verdi installation to the 'LD_LIBRARY_PATH' environment
variable. An example is shown below:
setenv LD_LIBRARY_PATH = /<Synopsys_Installation>/verdi/<version>/FsdbReader/LINUX64

Note: The file 'linbffr.so' must be present in the 'LD_LIBRARY_PATH'.

11.3. Using the Standard VCD Approach

In the standard VCD (Value Change Dump) approach, commands provided with the simulator are used
to create a VCD file. The standard VCD approach uses standard simulator facilities. No special commands
or options are required for Verilog designs. While Verilog simulators have standardized on one set of
commands to create VCD files, each VHDL simulator is slightly different.

Also, because this approach creates a large file, Ansys recommends that you compress the resulting
VCD file while the simulation is executing using a named pipe. To do this, see Creating a Named Pipe
to Manually Compress VCD Files (p. 212).

11.3.1. Writing a VCD File from a Verilog Simulator

The easiest way to write a VCD file is to add the following two lines to your Verilog testbench:
$dumpvars;
$dumpfile ("your_vcd_filename");

11.3.2. Writing a VCD File from ModelSim

Use the following procedure to write a VCD file using the Mentor (MTI) ModelSim simulator:

1. Execute the following commands before beginning simulation:

vcd file your_vcd_file_name
vcd add -r *

2. Execute the following command when the simulation is finished to ensure that all data has been
written to the VCD file:
vcd flush

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Acquiring Simulation Data

11.3.3. Writing a VCD File from the Cadence NC-Sim Simulator

Use the following procedure to write a VCD file using the Cadence NC-Sim simulator:

1. Execute the following commands before beginning simulation, either from the command-line or
as s part of a Tcl input file:
database -open your_vcd_file_name -vcd
probe -database your_vcd_file_name -all -depth all

2. Execute the following command when the simulation is complete:

database -close your_vcd_file_name

11.3.4. Creating a Named Pipe to Manually Compress VCD Files

If you are a UNIX user, you have most likely used a pipe to pass data from one tool to another. For
example, the following command passes data from the first tool to the second using a pipe:
ls | more

This method does not work if the first tool requires the name of a file to write data into or if the
second tool requires the name of a file to read data from.

UNIX provides a slightly different method for that case called a 'named' pipe. You can execute a UNIX
command to create a special file that is actually a pipe. As the first tool writes data to this file, it is
buffered and sent to the second tool, just as if the pipe were specified on the command-line. The
'named' pipe lets you run the simulator and a file compression program (such as 'compress' or
'gzip') at the same time, passing data using a pipe.

Ansys recommends using 'gzip, because it is automatically detected by the wwgaf conversion utility.

Use the following process to create a compressed VCD file using named pipe:

1. Edit the .v files to direct output to a file to be used as a named pipe:

$dumpfile("my_pipe")

2. Compile the various files.

3. In the simulation directory, execute the following UNIX command:

mknod my_pipe p

The 'mknod' command is located in a system directory (such as '/etc' or '/usr/sbin') that may
not be in your execution path.

4. Execute the simulator and start your compression program. Both must be done in the background:
mysim -f startup_file &
gzip < my_pipe > dump.vcd.gz &

In this example, 'mysim' is the simulator executable and 'gzip' is the compression program. The
characters '<' and '>' are UNIX redirection characters. Using these characters redirects the output

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 Acquiring Simulation Data in Palladium Flows

of 'my_pipe' to the input of 'gzip'. The output of 'gzip' is directed into a file called
'dump.vcd.gz'. You can delete 'my_pipe' when the compression program is finished.

Note: The 'wwgaf' utility automatically recognizes 'gzip' files, therefore, you do not need to pipe
gzipped files in 'wwgaf'. If you use any other compression program, you have to pipe data into
'wwgaf', as shown in the example below:
uncompress -c my_vcd_file.vcd | wwgaf -iaf -

11.3.5. Support for Processing Multi-dimensional Nets in the VCD Flow

Support for multi-dimensional nets in VCD files was missing from the 'GenerateGAF' command due
to which such nets were missing from the GAF file and were reported as nets missing simulation data
via the 'SCN-51' warning. Support is added to handle such nets in the VCD flow for certain simulators.

For example, nets identified as multi-dimensional (A[3:0][2:0]) by PowerArtist during elaboration,

but defined as a compact single dimension (such as A[0:12]) by simulators in VCD, were not
processed. As support is added, PowerArtist can identify such cases during 'GenerateGAF'.

Notes:

• Due to this support, if the design has multi-dimensional nets, there may be more entries in
the GAF file, which may cause the power numbers to change.
• Certain simulators define multi-dimensional nets that are recognized by PowerArtist as
'A[3:0][2:0]' as 'A(3:0)[2:0]' in the VCD file. Such nets are still not processed by
PowerArtist and miss simulation activity. One approach to handle these nets is to post-process
the VCD file and convert 'A(3:0)[2:0]' to 'A[3:0][2:0]' as input to PowerArtist.

11.4. Acquiring Simulation Data in Palladium Flows

Many of today's largest designs create tens of Gigabytes of simulation data. Even when capturing the
data in the FSDB file format, the data size can be enormous. When a simulator generates this much
data, it not only creates huge files that need to be stored on disk, but it significantly decreases the
performance of the simulator. Hardware emulators and accelerators exacerbate this problem because
you can run much larger test patterns on hardware than you can with a software simulator.

The Palladium ™ series of accelerators/emulators from Cadence has the ability to output toggle
information in FSDB or VCD file formats. They also have the ability to take a list of nets that should be
monitored and record only the toggle information for those nets in the resulting FSDB or VCD file.
PowerArtist requires critical nets to be monitored to perform an accurate average power analysis. The
Elaborate command accepts the following option:
-list_required_traces <filename>

The specified file contains the nets to monitor. This file is formatted so that it contains one net name
per line. The net name contains its hierarchical instance name path in the design. Consider the following
example:
Elaborate -list_required_traces trace.dat

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Acquiring Simulation Data

In this example, the file 'trace.dat' is created in your current working directory and has the following
format:
top.in[1]
top.in[2]
top.clk

You need to write a simple script that post-processes this file into the format your Palladium hardware
requires and include the resulting file as part of your Palladium setup environment. The resulting FSDB
or VCD file contains only the toggle information for those nets.

This flow works for both RTL, mixed RTL and gate, and pure gate-level designs. The following nets are
monitored in your design:

• Nets connected to all of the primary ports (inputs and outputs) of the design.
• Nets connected to all of the ports of instantiated gates that are recognized as:
– Memories
– IO cells
– Flip-flops
– Latches
– ICGCs (Integrated Clock Gating Cells)
– Macro cells with pin counts greater than 10 and that are not flip-flops
– Macro cells with bussed pins
– Tri-states
– MUX select line (not output or input ports)
• Nets connected to all the ports of inferred elements (RTL components) that are recognized as:
– Registers
– Latches
– Tri-states
– Regfiles
– Latchfiles
– MUX/UNMUX select line (not output or input ports)

If your design contains RTL code, then perhaps the net to be monitored is an inferred net that is not
present in your design source code. Therefore, all the named nets that form the immediate fan-in cone
of logic for the inferred net need to be monitored. Therefore, Elaborate traces back from an inferred
net through inferred combinational logic instances (and, or, nand, nor, xor, xnor, connect and connect_inv)
until it reaches the set of named signals that are needed to capture the toggling activity for that signal.

Palladium converts everything to uppercase so you need to run Elaborate with the
'-case_insensitive' and the '-list_required_traces' options. The output list contains IOs,
state points and clock enable signals for monitoring in the Palladium simulation. You need to convert
the output list to uppercase. You can do this by using the 'tr [a-z] [A-Z]' command. The resulting FSDB
output from Palladium is 15-20X smaller in size without sacrificing accuracy. The additional advantage
for Palladium is that the simulations are now much faster and there is no need to maintain terabytes
of data. After running Elaborate, run CalculatePower with default pin-based estimation (that is,
'-arc_based_estimation' is set to 'false').

For additional information, see Analyzing Average Power Using a SAIF File (p. 243).

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 Troubleshooting Tips

11.5. Troubleshooting Tips

11.5.1. Missing 'timescale in Verilog

The most common error in using Verilog to acquire simulation data is leaving out the timescale
specification for the simulator. The first line of your Verilog testbench should set the simulation time
scale, as shown in the following example:
'timescale 1 ns / 1 ns

If your Verilog file does not include a specification of the simulation time, the simulator uses a default
value. For some simulators, the default is one second per clock cycle. If your signal changes every
clock cycle but the simulator time step defaults to one second, when you import this data and run
an analysis with a clock of 10 Mhz, the simulation data for the signal indicates that it changes only
once per 10 million clocks. This results in a very low estimate of power for that net and the modules
it drives.

11.5.2. Zero Length 'activities.iaf' File

If you are performing a small simulation using the Intermediate Activity File (IAF) approach and the
'activities.iaf' file contains no data, exit the simulator. The simulator might not be closing the
'.iaf' file until it exits. This means that there is still buffered data in the 'gzip' process, which is not
written until its input file is closed.

11.5.3. Problems with ModelSim

ModelSim uses an internal environment variable '$MODEL_TECH' to point to the binary executables
for its tools. The environment variable is maintained by ModelSim and should not be manually reset
(as noted in the ModelSim documentation). If you were to set it, you could have problems trying to
use ' make_mti_mapfile' because the 'modelsim.ini' in the ModelSim installation uses this
environment variable to point to other 'modelsim.ini' files.
others = $MODEL_TECH/../modeltech/modelsim.ini

Therefore, if you had set '$MODEL_TECH', it is possible that the above path does not resolve to the
correct location. If you run into this situation, simply unset the environment variable:
unsetenv MODEL_TECH

The make_mti_mapfile executable then uses ModelSim utilities to return a value for '$MODEL_TECH'.

11.5.4. Zero Delay Simulation

If you are performing a mixed RTL/gate simulation (for example when pads are instantiated in your
design) you need to know if a zero delay simulation run created your simulation results. There are
three reasons for this:

1. It causes inputs and outputs of cells with power models to change in the same time step.
Simulators often do not ensure that when they create simulation traces either via PLI routines
or VCD files, input changes always appear before output changes.

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Acquiring Simulation Data

When PowerArtist executes the 'CalculatePower -analysis_type average' command

when performing arc-based analysis, it checks to see if certain transition sequences happen
in the VCD file and matches those to power vectors in your .lib libraries. It does not sort all
of the changes that happen in a time step to ensure that inputs change before outputs-doing
so for most gate-level designs is prohibitively expensive. Taking this method into account,
it's possible in this scenario for an output to toggle but have no corresponding vector.
Therefore, power is underestimated.

If you perform unit delay simulation or back-annotate delay information to your simulation,
the output changes in a later time step and a power vector is matched, assuming that one
is present in your library files. This problem does not occur when you specify the
'CalculatePower -analysis_type time_based -zero_delay true' command.
The '-zero_delay true' option forces the time-based power calculator to try to re-order
events that happen in each time step so output changes follow input changes. This switch
improves your results but you incur increased run time due to the sorting of signal toggles
for every time step in your simulation file.

2. Zero-duration glitches occur. These are multiple toggles on nets that occur during the same
time cycle. These may result in too many power arcs being matched and power being over
estimated. This problem is also addressed if you specify the 'CalculatePower
-analysis_type time_based -zero_delay true' command.

To accurately analyze power, you must at a minimum use unit delay simulation and at best
back-annotate delays and simulate your design. The following example is a section of a VCD
file that exhibits both problems:
#40551
0T"
0S"
#136520
1S"
1T"
0S"
0T"

In this example, 'S"' represents an input to a buffer. 'T"' is the output.

Note: At timestep #40551, the output toggles before the input so a potential power arc
match is missed. Timestep #136520 shows the same net toggling multiple times in one time
step. In this case, the arc missed in #40551 is actually recognized twice.

3. Using VCS, the function simulator from Synopsys. VCS eliminates simple buffers like those
found in the clock network. The generated VCD file has all nets in the clock network sharing
the same VCD id code, which causes poor performance when running 'CalculatePower
-analysis_type average'. When this happens, the 'CalculatePower.log' file
contains an error message that all nets are not monitored.

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Chapter 12: Analyzing Simulation-Based Average
Power
12.1. Introduction
You can run PowerArtist average power analysis on RTL, gate-level, and mixed RTL and gate designs.
Before you run average power analysis, Ansys recommends that you read Preparing for Power
Analysis (p. 167), which describes prerequisite steps you need to perform before you begin a power
analysis. Ansys also recommends that you run through PowerArtist Tutorial Part I: Power Analysis (p. 19)
to learn how to run the command-line flow for average power analysis.

Chapter Organization
The following topics are covered in this chapter:

• Overall Design Flow (p. 217)

• Running a Power Analysis in Full Simulation Mode (p. 218)
• Controlling the Analysis of Simulation Data (p. 220)
• Running Analysis with Incomplete Simulation Data (p. 225)
• Re-Using a Stimulus File from a Previous Run (p. 225)
• Performing Power Analysis with Block-level Simulation Data (p. 226)
• Performing Gate-level Power Analysis (p. 230)
• Running Modal Analysis (p. 231)
• Understanding the Basics of the Detailed Power Report (p. 232)
• Controlling the Contents of the Power Report (p. 234)
• Analyzing Average Power Using a SAIF File (p. 243)
• Analyzing Average Power Using Partial Stimulus Files (p. 245)
• Name Mapping Flow (p. 245)
• Parallel Activity Processing (p. 247)
• RTL Glitch Power Analysis (p. 248)

12.2. Overall Design Flow

You should implement the following high-level design flow to perform average power analysis:

1. Simulate your design and generate simulation data in the FSDB, IAF, or VCD formats.

2. Build a scenario file using the 'Elaborate' command. For details, see Getting Your Design into
PowerArtist (p. 133).

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Analyzing Simulation-Based Average Power

3. Run vector analysis using the 'GenerateActivityWaveforms' command. For details, see Analyzing
Simulation Activity (p. 201).

4. Run the 'CalculatePower -analysis_type average' command. Details for this process
are documented in this chapter.

5. View the reports created by the 'CalculatePower' command in the following ways:
• Text format
• PowerArtist GUI - this is the information stored in the power database.

12.3. Running a Power Analysis in Full Simulation Mode

Running power analysis in full simulation mode is done entirely by the 'CalculatePower' command.
This command first converts simulation activity data into a global activity file (GAF) and then runs the
power analysis.

12.3.1. Controlling Your Average Power Analysis

As with all PowerArtist programs, you control the operation of your power analysis by specifying the
appropriate commands in your PowerArtist command file. To perform an average analysis in full
simulation mode, you need to specify the 'CalculatePower' command with the required arguments:

• -activity_file <your_simulation_file>

Specifies an input stimulus file generated after a functional simulator run. The file may be in
FSDB, VCD or IAF (generated by PowerArtist PLI routines) format. You must specify
'-activity_file' or '-vectorless_input_file' for average power analysis. The
'CalculatePower' command automatically determines the type of the simulation activity file.

• -gaf_file <your_gaf_file>

Specifies the name for the generated GAF file.

• -scenario_file <your_scenario_file>

Specifies the scenario file you generated using the 'Elaborate' command. For more information,
see Getting Your Design into PowerArtist (p. 133).

• -synlib_files {file_name1 file_name2 ...}

Adds the specified file or Tcl list of files to the list of Liberty library files. You can also use the
'ReadLibrary' command to specify the Liberty libraries to read.

• This option specifies the instance in the simulation hierarchy that corresponds to the top-level
instance in the scenario file. The value in the '-top_instance' option is specified as a dot
(.) separated name in which the dot is used as the hierarchical separator regardless of the
simulator used. For example: 'testbench.corelogic_0'.

You should also specify the following additional options to control your analysis:

• -start_time <string>

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 Running a Power Analysis in Full Simulation Mode

Use this option to specify the starting point. The time at which to begin power analysis.

• -finish_time <string>

Use this option to specify the stopping point. The time at which to stop the conversion of
simulation data before the point when the simulation stopped. This option is also needed if
simulation time ends long after the last signal toggle occurred. Otherwise, the average power
numbers are incorrect.

By using '-start_time' and '-finish_time', you can perform a variety of 'what-if' scenarios
without having to recreate the simulation activity file.

• -gate_level_netlist <true | false>

Use this option if you have a gate-level design. For details, see Performing Gate-level Power
Analysis (p. 230).

• -mixed_sim_prob_estimation <true | false>

Use this option if you have an IAF, VCD, or FSDB file that does not match your scenario file.
For details, see Running Analysis with Incomplete Simulation Data (p. 225). You will also need
to specify this option if you have a partial stimulus file. For details, see Analyzing Average
Power Using Partial Stimulus Files (p. 245).

• -mode_file <filename>

Use this option to perform mode-dependent power analysis. For details, see Running Modal
Analysis (p. 231).

• -allowed_x_time <string>

Simulations of large designs can result in a significant number of signals never leaving the 'X'
state. This is particularly true for gate-level designs. This can severely compromise the accuracy
of your results. The section 'Transition Counting on Nets' in the PowerArtist Reference Manual
describes how to control some of the effects for RTL designs. The 'X' states in gate-level designs
cause power to be underestimated since power vectors modeled in your power library do not
match transitions to and from 'X' states.

The 'CalculatePower' command reports the following warning:

SIM-50: wwgaf encountered 54102 signal(s) that were in an X state
for more than 10ns amount of time.

This means that an 'X' state of duration greater than '10ns' occurred '54,102' times during
the simulation run. The message can be interpreted as:
– 'one' signal in the 'X' state '54102' times.
or
– '54102' signals, 'one' time.

If you see this message with an unexpectedly large number of signals, it is an indication that
your test bench is not sufficiently robust for performing power analysis. Use the
'-allowed_x_time' option to control the duration of 'X' state.

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Analyzing Simulation-Based Average Power

12.3.2. Sample CalculatePower Specification for Full Simulation Mode

To run a power analysis in full simulation mode, you can use the following sample 'CalculatePower'
command:
set design top
CalculatePower -analysis_type average \
-activity_file ../design_data/rtl_sim/activities.vcd \
-average_report_file $design.AverageBatch.rpt \
-average_report_options agip \
-average_write_power_db true \
-compress_gaf true \
-default_output_load 3.9e-11 \
-detailed_vertical_report true \
-finish_time 12135580ps \
-gaf_file $design.AverageBatch.gaf \
-calculate_log CalculatePowerAverageBatch.log \
-mode_file txrx.mode \
-power_db_name $design.AverageBatch.pdb \
-scenario_file $design.Batch.scn \
-start_time 6014730ps \
-top_instance txrx_tst.top1 \
-use_non_scan_flops false \
-vertical_report_instances $design \
-wireload_library hvt

12.4. Controlling the Analysis of Simulation Data

To perform a simulation-based average power analysis, use the following command:
CalculatePower -analysis_type average

By default, the 'CalculatePower' command checks if a Global Activity File (GAF) file exists. If the GAF
(.gaf) file does not, it automatically runs the processes to analyze your simulation data as part of the
activity analysis phase. If the GAF (.gaf) file exists, it then checks to see if any options (or option values)
have changed since the last time you ran the 'CalculatePower' command. If they have changed, it
analyzes the simulation data. If they have not changed, it skips the simulation data analysis phase and
proceeds directly to the power analysis phase.

You can use the following options to control power analysis:

• -force_stimulus_processing <true | false>

If you use '-force_stimulus_processing true', PowerArtist performs stimulus processing

even if the dependency management indicates that stimulus processing is not needed.

• -use_existing_gaf <true | false>

If you use '-use_existing_gaf true', PowerArtist uses the existing GAF file for power
analysis even if it determines that it is out of date.

12.4.1. Controlling GAF File Creation Explicitly

The 'GenerateGAF' command resolves problems with dependency management and enables multiple
testbench support by giving you very explicit control.

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 Controlling the Analysis of Simulation Data

Command-Line Flow
To use 'GenerateGAF' in the command-line flow, run the following steps:

1. Run the 'GenerateGAF' command to generate the GAF file:

GenerateGAF -activity_file <sim_filename> -gaf_file <filename>

2. Run the 'CalculatePower' command to read the GAF file and calculate average power:
CalculatePower -analysis_type average
-use_existing_gaf true
-gaf_file <filename>

Example
GenerateGAF -activity_file top.fsdb -top_instance tb.top
-scenario_file top.scn -start_time 1000ns -finish_time 2000ns
-gaf_file top.gaf

CalculatePower -analysis_type average -gaf_file top.gaf

-scenario_file top.scn -use_existing_gaf true

The commands read the FSDB and scenario file, generate the GAF file, and then calculate average
power using the GAF file just created. Remember to specify '-use_existing_gaf true, otherwise
dependency management may force the recreation of the GAF file with many default options.

Syntax of the GenerateGAF

The 'GenerateGAF' command takes all the same activity analysis options supported by the
'CalculatePower' command. Refer to the PowerArtist Reference Manual for the complete syntax.

12.4.2. Determining Weights for a GAF File

Since PowerArtist cannot automatically determine the purpose of the different GAF files, you can
optionally assign a 'weight' to each one. The simplest way to assign weights is to use the 'AddGAF'
command. You need to specify the following information:

• The GAF file name.

• A mode name designation for the particular operational mode of the GAF file.
• The weighting factor for the GAF file.
• A report file name to write the average power estimation data for the GAF file.

Refer to the PowerArtist Reference Manual for the complete syntax of the 'AddGAF' command.

Examples
This section illustrates three examples that can help you determine the best way to assign weights
for a GAF file:

• Example 1: Two Different GAF Files

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Analyzing Simulation-Based Average Power

For this example, assume that you have two GAF files, 'A.gaf' and 'B.gaf', that represent
the design running in two different modes. In addition, you know that the design is in mode
'A' '90%' of the time and in mode 'B' the remaining '10%' of the time. In this case, you can
assign a weight of '0.9' to 'A.gaf' and a weight of '0.1' to 'B.gaf'. Use the following
'AddGAF' commands to assign the weights:
AddGAF -file A.gaf -mode mode_A -percent 0.9
AddGAF -file B.gaf -mode mode_B -percent 0.1

• Example 2: Four GAF Files with Equal Simulation Run Times

For this example, assume you have four different GAF files of the same simulation run time
(that is, simulation duration) and that none of them represent a specific mode. In this case,
you can set the weight for each GAF to '0.25'. Use the following 'AddGAF' commands to
assign the weights:
AddGAF -file A.gaf
AddGAF -file B.gaf
AddGAF -file C.gaf
AddGAF -file D.gaf

As you have not specified the '-percent' option, it is calculated as '0.25'. You can also
specify them individually as shown in the previous example.

• Example 3: Four GAF Files with Different Simulation Run Times

If you have four GAF files for different lengths of time, you can assign weights based on their
simulation run times. For example, assume their run times are '500ns', '350ns', '100ns', and
'50ns'.

In this case, you can specify the weights as '0.5', '0.35', '0.1', and '0.05' respectively. These
weights represent the percentage of the run time each GAF took. In this example, the total
run time is '1000ns'.

Note: There is no specific recommendation for the values you should use for assigning weights.
The value you assign depends on the nature of the various '.gaf' files and the purpose of
the simulation that created the VCDs.

12.4.3. Multiple Testbench Support

PowerArtist supports average power analysis using the weighted sum of multiple testbenches. The
benefit of this feature is that it allows you to efficiently determine the overall average power
consumption for a design that is simulated over several runs. You can have multiple simulation files
for the following reasons:

• When you simulate a very large design or for a long duration, one activity file is created. Large
FSDB files are known to cause significant performance problems. Therefore, you can split the
run into multiple FSDB files.
• When you have a variety of simulation scenarios, you may want to combine them into a single
power analysis run.

The simulation files may have different durations or their relative importance may be different. But,
you may want to weigh the impact of a particular simulation run more highly than others. In both

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 Controlling the Analysis of Simulation Data

cases, the same top-level design unit must be specified for each run. This is because the same scenario
file must be used for all the runs and the top module must be the same in each resulting GAF file.

The simplest way to assign weights is to use the 'AddGAF' command. The purpose of this command
is to allow you to specify all the information 'CalculatePower' needs to run multiple testbench analysis.

Command-Line Flow
To use this feature, perform the following steps:

1. Generate a GAF for each testbench using the following command:

GenerateGAF <options_for_stimulus_file>

2. Specify the 'AddGAF' command with optional percentage weights for each file:
AddGAF <arguments_for_GAF_file>

3. Include the GAF file(s) in a single power analysis:

CalculatePower -analysis_type average <options>

Note: If you have three stimulus files, the 'CalculatePower' command reads the results of all three
GAF files and generates a 'Multiple Testbench Control File (p. 223)' that is stored in your current working
directory as 'pashell.mtcf'.

Refer to the PowerArtist Reference Manual for the complete syntax of all the commands.

Multiple Testbench Control File

When you execute the 'CalculatePower' command, it recognizes if you have supplied one or more
'AddGAF' commands. This is because the 'AddGAF' command creates a variable, which is a Tcl list
of lists, with the following syntax:
multiple_GAFs {
{-file {file_name}
-percent {percentage}
-mode {mode_name}
-report {report_name}}
...
}

One such list is generated for each GAF file. It records the data exactly as you specified using the
'AddGAF' command. Therefore, you can also specify the variable 'multiple_GAFs' instead of the
'AddGAF' command. For example, you can specify the following command:
pa_set multiple_GAFs {
{-file inputs1.gaf -report inputs1.rpt}
{-file inputs2.gaf -report inputs2.rpt}
{-file inputs3.gaf -report inputs3.rpt}
}

This 'multiple_GAFs' command is converted into commands in a 'Multiple Testbench Control File'
named 'pashell.mtcf'. For the above 'multiple_GAFs' command, the following 'pashell.mtcf'
is generated:

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Analyzing Simulation-Based Average Power

$mode inputs1 0.2

$gaf inputs1.gaf
$report inputs1.rpt
$mode inputs2 0.3
$gaf inputs2.gaf
$report inputs2.rpt
$mode inputs3 0.5
$gaf inputs3.gaf
$report inputs3.rpt

12.4.4. Using the Multiple Testbench Feature to Control FSDB File Size
While the Synopsis Verdi™ product is able to generate large FSDBs, their utilities are not optimized
to handle them. An FSDB file is considered to be 'large' if its size is at least 500 MB. If you attempt
to run the 'fsdb2vcd' or 'fsdbmerge' commands and the process appears to hang or starts to swap
due to limited memory, you need to reduce the size of your FSDB file.

There are two techniques to accomplish this goal and they are documented in the 'Verdi Reference
Manual':

• Capture the FSDB file for only the simulation duration absolutely needed.
• Split the one FSDB file into multiple FSDB files during your simulation run.

This section applies to the second technique. It describes how you can use PowerArtist's multiple
testbench feature to process multiple FSDB files to get an average power number.

You can control the size and number of output FSDB files by using the following PLI command to
generate them:
$fsdbAutoSwitchDumpfile (max_fsdb_filesize,"root_fsdb_filename", total_num_fsdb_files)

An example of using this command is shown below:

initial begin
$fsdbAutoSwitchDumpfile(2,"activities.fsdb",3);
$fsdbDumpvars(0,tb.t1);
#1e9 $finish;
end

As per this example, the size of the generated FSDB files is not greater than 2MB, the root name is
'activities.fsdb', and a total number of three FSDB files are generated.

Note: If the design cannot be managed with only three FSDB files, the '$fsdbAutoSwitchDumpfile'
command appends to the previously generated files-beyond the maximum size you set in the
command.

Recommended Flow
You should use the following flow:

1. Use the following command to start recording simulation value changes to the FSDB file at
the point at which you want to perform a power analysis:
$fsdbDumpvars

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 Re-Using a Stimulus File from a Previous Run

2. Use the following command to temporarily stop recording to the FSDB file. This command
does not set the finish time of the FSDB file:
$fsdbDumpoff

3. Use the following command to stop and finish recording to the FSDB file. This command sets
the finish time of the FSDB file:
$fsdbDumpfinish

4. Use the testbench control file methodology to run the power analysis:

a. Run the 'GenerateGAF' command on the FSDB files and generate the GAF files
'1.gaf', '2.gaf', and '3.gaf'.

b. Specify the following information for each of the resulting GAF files:
• Set the simulation time to '20', '20', and '60'.
• Add the simulation times to ensure that the total is 100 (20+20+60=100).
• Specify the percentage/weightage of the total simulation time for each GAF
file as '.2' for '1.gaf', '.2' for '2.gaf', and '.6' for '3.gaf'.

c. Write the 'AddGAF' commands that capture this information for each GAF:
AddGAF -file 1.gaf -percent .2 -report 1.rpt
AddGAF -file 2.gaf -percent .2 -report 2.rpt
AddGAF -file 3.gaf -percent .6 -report 3.rpt

d. Run power analysis using the 'CalculatePower' command:

CalculatePower -analysis_type average
-average_report_file fulltest.rpt
-power_db_name fulltest.pdb <options>

This flow generates 'Multiple Testbench Control File' named 'pashell.mtcf', the 'fulltest.rpt'
file contains the correctly scaled, final power numbers, and the 'fulltest.pdb' contains the correctly
scaled, final power numbers annotated to the design netlist.

12.5. Running Analysis with Incomplete Simulation Data

If you have an IAF, VCD, or FSDB file that does not match your scenario file in some way (such as an
instance in the scenario file is missing in the design you simulated because the source files have changed),
you must run the 'CalculatePower' command with the '-mixed_sim_prob_estimation <true
| false>' option.

Note: When you run with this option, only some nets have '.gaf' data associated with them, as opposed
to the full simulation mode in which all nets are assumed to have '.gaf' data available.

12.6. Re-Using a Stimulus File from a Previous Run

Stimulus file processing typically takes a significant amount of time for any design of substantial size.
If you want to do some 'what-if' experiments without re-reading your stimulus file, you have to indicate
this to the 'CalculatePower' command. By default, during a simulation-based, average power analysis,

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Analyzing Simulation-Based Average Power

your stimulus file gets re-read. If you want to prevent that from happening and you want to re-use the
existing GAF file created by a previous run, you must specify the following option:
-use_existing_gaf true

12.7. Performing Power Analysis with Block-level Simulation Data

12.7.1. Performing Top-level Power Analysis

During the RTL design power analysis process, while the complete (top-level) RTL design may be
available early in the design flow, the simulation data (FSDB/VCD files) may not be available for the
top-level. The simulation data may be available only for multiple block-level instances.

In such a scenario, you have two options for estimating power:

• Generate individual SCN files (via the 'Elaborate' command) for each such
hierarchical/block-level instance and estimate power for the block(s) using the corresponding
block-level activity/simulation file(s).

• Generate the top-level SCN file once and use it to perform block-level power analysis for the
block of interest. You can enable this flow using the following variable:
pa_set block_design_instance <hierarchical_instance_name>

The GAF file generated with the 'GenerateGAF' command has entries starting with the top
name. For example, the GAF file generated by the command 'pa_set
block_design_instance top.core1.t1', contains the following entries:
top.core1.net1
top.net2
...

Similarly, the report generated after 'CalculatePower -analysis_type average' is as

shown below:
...
2. Internal power consumption
=============================
Note: (G) after either a register or 2-1 mux means this instance is affected by clock gating.
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top user 3.98mW 19.5mW 23.5mW
#b0 auto 0W 0W 0W
core1 user 3.98mW 19.5mW 23.5mW
t1 user 7.1nW 0W 7.1W
...

Note: In this flow, when power is estimated for the top-level (while the simulation data is available
for only one hierarchical block/instance), there may be loss of accuracy for the top-level (when
compared with the case where simulation/activity file is available for the top-level). This is because
the activity information for the remaining blocks is not available, and the activity calculation for those
blocks relies on the probabilistic activity propagation (or the vectorless flow, if used).

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 Performing Power Analysis with Block-level Simulation Data

12.7.2. Performing Block-level Power Analysis

To estimate block-level power from block-level simulation/activity data, use the following two variables:

• pa_set block_design_flow <true | false>

Default: 'false'

• pa_set block_design_instance <hierarchical_instance_name>

In this flow, power is estimated for the hierarchical/block-instance specified in the 'pa_set
block_design_instance', even when the .scn file is generated for the top-level and the GAF file
generated with the 'GenerateGAF' command has entries starting with the block name. For example,
when the following commands are specified:
Elaborate -top top
pa_set block_design_instance top.core.t1

A GAF file with the following entries is generated:

t1.block_net1
t1.block_net2
...

Similarly, the report generated after 'CalculatePower -analysis_type average' is as shown

below:
...
2. Internal power consumption
=============================
Note: (G) after either a register or 2-1 mux means this instance is affected by clock gating.
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
t1_mod user 3.98mW 19.5mW 23.5mW
#b0 auto 0W 0W 0W
block1 user 3.98mW 19.5mW 23.5mW
a1 user 7.1nW 0W 7.1W
#d1 decoder 7.1nW 0W 7.1W
block2 user 3.98mW 19.5mW 23.5mW
a2 user 7.1nW 0W 7.1W
#d2 decoder 7.1nW 0W 7.1W
...

Behavior of 'block_design_instance' without 'block_design_flow'

When the simulation file is for the top-level design, then you do not need to specify any variable. If
the simulation file is for a block, you must specify the following variable:
pa_set block_design_instance <hierarchical_instance_name>

The effect of this command is:

• The generated GAF file has top-level nets/signals.

• Power is estimated for the top-level design.

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Analyzing Simulation-Based Average Power

Behavior of 'block_design_instance' with 'block_design_flow'

The behavior of 'pa_set block_design_instance', as described above, changes when you specify
'pa_set block_design_flow true'. The changes in behavior are explained below:

• The generated GAF file has block-level nets/signals.

• Power is estimated for the block-level design.

12.7.3. Performing Top-level Power Analysis with Multiple Block-level

Simulation Activity Files
Chip-level simulation activity is often available late in the design flow although block-level simulations
are available earlier. Now, top-level power can be estimated when the top-level simulation/activity
file is not available, but multiple block-level simulation files are available.

The 'MergeGAF' command combines multiple GAF files generated from the block-level simulation
activity files. This flow requires you to execute the following three commands:

1. Run the 'GenerateGAF' command separately for each block-level simulation file to generate
individual GAF files.

Note: These GAF files are generated with top-level design hierarchy.

2. Merge the GAF files using the 'MergeGAF' command to create a single top-level GAF file.

3. Run the 'CalculatePower' command for power analysis.

You can also compute top-level power with a single block-level simulation activity file. The
following variable is enhanced to enable this:
pa_set block_design_instance <hierarchical_instance_name>

For a single block-level activity file, you do not need to execute 'Step #2' above.

Flow 1
In the following example, simulation data for two hierarchical blocks and the top-level is available.

1. Generate top-level GAF file from block-level simulation data using the 'GenerateGAF
-block_design_instance' command. The nets in the GAF file refer to the instance 'top':
GenerateGAF -block_design_instance top.core1.t1 \
-top_instance testbench1.dut_top.top.core1.t1 \
-gaf_file t1.gaf \
-activity_file top_t1.vcd

GenerateGAF -block_design_instance top.core1.r1 \

-top_instance testbench1.dut_top.top.core1.r1 \
-gaf_file r1.gaf \
-activity_file top_r1.vcd

GenerateGAF -top_instance tb1.dut_top.top \

-gaf_file top_sparse.gaf \
-activity_file top_des.vcd

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 Performing Power Analysis with Block-level Simulation Data

2. Merge the generated GAF files into a single top-level GAF file using the 'MergeGAF' command:
MergeGAF -output_gaf_file top_merge.gaf \
-gaf_file_list { t1.gaf r1.gaf top_sparse.gaf }

3. Perform power analysis on the merged GAF file using the 'CalculatePower' command:
CalculatePower -analysis_type average \
-gaf_file top_merge.gaf -use_existing_gaf true

Flow 2
In the following example, simulation data (fetched at different times and conditions), is available for
the top-level through multiple simulation files.

1. Generate top-level GAF file from the top-level simulation data using the 'GenerateGAF'
command:
GenerateGAF -top_instance testbench1.dut_top.top \
-activity_file top_1.fsdb \
-start_time 6071580ps \
-finish_time 12135580ps \
-gaf_file top_v_1.gaf

GenerateGAF -top_instance testbench1.dut_top.top \

-activity_file top_1.fsdb \
-start_time 2015809ps \
-finish_time 5061350ps \
-gaf_file top_v_2.gaf

GenerateGAF -top_instance tb1.dut_top.top \

-activity_file top_all.fsdb \
-gaf_file top_all.gaf

2. Merge the generated GAF files into a single top-level GAF file using the 'MergeGAF' command:
MergeGAF -output_gaf_file top_merge.gaf \
-gaf_file_list { top_v_1.gaf top_v_2.gaf top_all.gaf }

3. Perform power analysis on the merged GAF file using the 'CalculatePower' command:
CalculatePower -analysis_type average \
-gaf_file top_merge.gaf -use_existing_gaf true

Flow 3
In this flow, you can combine multiple GAF files (with the same 'top') with contiguous and
non-overlapping time intervals to create one combined GAF file. The GAF files to be merged must
meet the following criteria:

• The file must be generated from the same block (have the same top) or top-level instance.
• The simulation time of these files should be contiguous and non-overlapping.

In the following example, the simulation time of the first GAF file is '0us-5us', the second GAF file
is '5us-10us', and the third GAF file is '10us-15us'. You can combine these GAF files into a combined
GAF file for the complete simulation time of 0-15us.

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Analyzing Simulation-Based Average Power

1. Generate top-level GAF file from the top-level simulation data using the 'GenerateGAF'
command:
GenerateGAF -top_instance testbench1.dut_top.top \
-activity_file top_1.fsdb \
-start_time 0us -finish_time 5us \
-gaf_file top_v_1.gaf

GenerateGAF -top_instance testbench1.dut_top.top \

-activity_file top_1.fsdb \
-start_time 5us -finish_time 10us \
-gaf_file top_v_2.gaf

GenerateGAF -top_instance testbench1.dut_top.top \

-activity_file top_1.fsdb \
-start_time 10us -finish_time 15us \
-gaf_file top_v_3.gaf

2. Merge the generated GAF files into a single top-level GAF file using the 'MergeGAF' command:
MergeGAF -add_non_overlap_gafs true \
-output_gaf_file top_merge.gaf \
-gaf_file_list { top_v_1.gaf top_v_2.gaf top_v_3.gaf }

3. Perform power analysis on the merged GAF file using the 'CalculatePower' command:
CalculatePower -analysis_type average \
-gaf_file top_merge.gaf -use_existing_gaf true

12.8. Performing Gate-level Power Analysis

If you have a pure gate-level design, use 'Elaborate -gate_level_netlist true' to create a new
scenario file. This tells PowerArtist that it is a gate-level design. If during scenario file creation, PowerArtist
encounters RTL components, it blackboxes them and generates warning messages.

Pin-Based Estimation for Gate-Level Instances

There are two techniques that PowerArtist can use for power estimation of gate-level instances:

• pin-based

By default, PowerArtist uses pin-based power estimation, which does not do arc monitoring. Arc
monitoring requires the ports of the instances to be output into your simulation data file, not
just the nets connected to the ports of the instance. This method is somewhat faster and
consumes less memory than the arc-based method, at the cost of some accuracy. Arcs are
monitored for the following instances:
– IO pads
– instantiated memories
– non-memory cells containing bus pins
– macro combinational cells with 11 or more pins

To enable arc monitoring for additional cells and instances, use the 'MonitorArcs' command.

• arc-based

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 Running Modal Analysis

To perform arc-based estimation for all gate-level instances, specify the 'CalculatePower
-arc_based_estimation true' command.

12.9. Running Modal Analysis

Large designs often have several operational modes, such as standby, receiving, and transmitting. The
power consumption for these modes varies as different sections of the chip may be inactive or even
powered down, in each mode. Entering data into a mode description file enables PowerArtist to perform
accurate RTL power analysis for each mode. You can print the mode analysis results or PowerArtist can
compute a weighted average. A mode file contains design-specific information that PowerArtist uses
to execute several power analyses corresponding to different operational modes of the design, and
combine the results into one or more reports.

The format for a mode file for simulation-based power analysis is shown here:
$mode " boolean_expression "
$report file_name
$result file_name

Elements Within the Mode File

Element Description
$mode This mandatory keyword assigns a name to the operational mode you are
boolean_expression defining. The 'boolean_expression' can be a single signal name or a combination
of signals in the design. The signal's hierarchical name is, in this case, with
respect to the top most scope (or testbench scope) in the VCD, not the design's
'top' name. You can use any standard boolean operator.
$report file_name This optional keyword writes a report file for this mode to the specified
file name. You can write this file to any directory by specifying a relative
or absolute file path name. The '~' symbol is not supported in file path
name.
$result file_name This optional keyword writes a result file for this mode to the specified
file name.

Examples
• Example 1: A sample mode file is shown below:
$mode top.counting_off
$report counting_off.rpt

$mode top.counting_on
$report counting_on.rpt

As per this file:

– The design is expected to be one of these modes: 'counting_off' or 'counting_on'.
– The name of the mode must be the name of a signal such that when it is asserted high, the
system is assumed to be in this mode. In this case, the design is expected to find two signals:
'top.counting_off' and 'top.counting_on'.

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Analyzing Simulation-Based Average Power

– The names of the signals must be in the VCD file and must be rooted at the topmost scope
(or testbench scope) in the VCD.

Using a mode file containing 'n' different modes, results in 'n+1' report files. One report file is generated
and named for each mode and one report file is generated for the entire simulation.

For this mode file, PowerArtist performs two analyses, one for each mode, and generates a report
file named for each of the modes: 'counting_off.rpt' and 'counting_on.rpt'. Another report
representing the entire simulation, which is named as defined by the 'CalculatePower' command.

To obtain the total power consumed during the two modes, you cannot add the power consumed
by each mode. Instead, you must:

1. Convert each power to energy.

2. Add the two energy values together.

3. Convert to power.

This is equivalent to computing a weighted sum (weighted by the amount of time spent in each
mode) of the two powers.

• Example 2: A sample mode file is shown below:

$mode top.sys_request&&top.interrupt
$report request-interrupt.rpt

$mode "top.sys_request&&(!top.interrupt)"
$report request-not_interrupt.rpt

$mode "(!top.sys_request)&&top.interrupt"
$report not_request-interrupt.rpt

$mode "(!top.sys_request)&&(!top.interrupt)"
$report not_request-not_interrupt.rpt

In this example, the design has four modes. While processing the simulation data file, PowerArtist
monitors 'sys_request' and 'interrupt'. When either of these two signals changes state,
PowerArtist evaluates the various boolean expressions, determines which one is true and allocates
the energy to that mode bucket.

There are two edge cases for this method of modal power. If the simulator enters a mode in which
none of the mode signals are in a 'logic 1' state, the simulation activity for those simulation periods
is ignored (that is, the activity does not contribute to the power of any mode). If more than one mode
signals are in the 'logic 1' state at the same time, simulation determines that the system is in the
mode that appears first in the mode file (such as 'counting_off' in the mode file of Example 1 (p. 231)).

For more information on mode files and additional samples, see Mode File Format in the PowerArtist
Reference Manual.

12.10. Understanding the Basics of the Detailed Power Report

The detailed power report is stored in an ASCII file. Although some sections in this report are always
included others are generated/formatted depending on the values you specify to the 'CalculatePower
-average_report_options' command. Major sections (often used) include the following:

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 Understanding the Basics of the Detailed Power Report

Header

The report header includes:

• Date and time report file was generated.
• Version of PowerArtist used.
• Library file used for the power calculation.
• Assumed clock frequency.
• Voltage values for the power supplies used.
• Name of the activity file.
• Names of any capacitance files.
• The power consumed in driving inter-module nets.
• Design and simulation prefix.

Total Power Consumption

This section summarizes the results of the analysis.

Internal Power Consumption

This section lists the power consumed by each leaf-level module in the design. The specific
content of this section depends, in part, on the options you specify to the 'CalculatePower
-average_report_options' command. For more information, see Controlling the Contents
of the Power Report (p. 234).

Pad Power Consumption

This section lists the power consumed by each individual IO pad in the design, along with the
capacitive load "seen" by that pad.

Clock Power Consumption

This section lists the following information:

• The hierarchical net name, the type of analysis, and the total power for the clock tree.
The analysis type is either 'Instantiated' (meaning it was 'traced') or 'Inferred' (meaning
clock inferencing was done).
• Area occupied by the net.
• Clock senses.
• Frequency of the clock net
• Transition time of the clock net
• Fanout capacitance of the clock net (divided into contributions from wire and pin
capacitances).
• Power consumed as the net toggles (divided as wire and pin components).
• The wire load model applied to the net (the first entry is the net name and the second
entry is the wire load model applied to that net). If you assigned wire load models to
sub-nets of the clock tree, they are also listed.
• Descriptions of the instances and net that were traced as part of the clock tree.
• The clock tree inferencing that occurred including buffers and integrated clock gating
cells (ICGCs) that were inferred.

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Analyzing Simulation-Based Average Power

• The clock gating summary that provides statistics on the number of gated and ungated
registers and the number of integrated clock gating cells (ICGCs) 'instantiated' or 'inferred'
in your design.
To better understand the content of this report and to see a sample, see the 'Clock
Domain Power Consumption' section in the analysis tutorial.

Total Power Per Supply

This section lists each power supply used in the design with the power consumed from each
supply but it is generated when you specify the following command:
CalculatePower -average_report_options V

To create a report where the internal and pad power are divided into their static and dynamic
components, specify the following command:
CalculatePower -average_report_options s

Power per supply is also reported as static and dynamic components.

Vertical Report

This section reports power by cell. You can generate/manipulate this section by specifying the
following options to the 'CalculatePower' command:

• -vertical_report_instances [{inst1 inst2 inst3...}]

• -detailed_veritcal_report true

• -vertical_report_sort_mode <alphabetical | power>

Available Power Report Formats

The power report is available in plain text or HTML. Plain text report is available by default. To generate
an HTML report, specify the '-average_html_report_title <filename>' option. You can view
these reports in any web browser.

12.11. Controlling the Contents of the Power Report

You can specify different values to the 'CalculatePower -average_report_options' command
to:

• control what is included in the report.

• control the format of the instance power report in the 'Internal Power Consumption' section.
• generate additional sections in the power report.

This section provides many different sample reports that are generated based on the values you specify:

• -average_report_options

• A report with 'no' values contains the following section:

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 Controlling the Contents of the Power Report

2. Internal power consumption

=============================
Component Model Power(Watts)
--------- ----- ------------
wavtab.cnt.#0 adder_rip 67.3uW
wavtab.cnt.#1 register 225uW
wavtab.dff.#0 register 194uW
wavtab.div.#0 adder_rip 246uW
wavtab.div.#1 register 851uW
wavtab.rom rom 4.03mW
Total internal power 5.62mW

• -average_report_options ip

If you specify 'ip', the non-leaf hierarchical elements are reported using indenting to indicate levels
of hierarchy, rather than repeating all the non-leaf cell names:
Component Model Power(Watts)
--------- ----- ------------
wavtab user 5.62mW
cnt user 293uW
#0 adder_rip 67.3uW
#1 register 225uW
dff user 194uW
#0 register 194uW
div user 1.1mW
#0 adder_rip 246uW
#1 register 851uW
rom rom 4.03mW
Total internal power 5.62mW

• -average_report_options mp

• If you specify 'mp', the inferred elements with names containing '#' are not reported. This makes the
report smaller and contains only the instances you have actually created in your design:
Component Model Power(Watts)
--------- ----- ------------
wavtab user 5.62mW
wavtab.cnt user 293uW
wavtab.dff user 194uW
wavtab.div user 1.1mW
wavtab.rom rom 4.03mW
Total internal power 5.62mW

• -instance_power_threshold <float>

Another way to reduce the report size is to use this option, which eliminates any instance consuming
a small amount of power, from the report. You can set this to '1' percent
(-instance_power_threshold 1). For the sample output shown below, the threshold was set
to '10' percent (-instance_power_threshold 10):
Component Model Power(Watts)
--------- ----- ------------
wavtab.div.#1 register 851uW
wavtab.rom rom 4.03mW
Total internal power 5.62mW

Notes:
– In all the above examples, the total power reported is the same. The 'values' only change the
modules that are shown in the report. They do not change the power computation.

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Analyzing Simulation-Based Average Power

– These report samples (with just one Power(Watts) column) were generated using the 'f'
reporting value. This combines the static and dynamic power values into one.

• -average_report_options a

If you specify 'a', the area estimation section is included in the report.
6. Area
=======

Component Width Height Regs Gates

--------- ----- ------ ---- -----
top.core1.a1.#241 33.8um 33.8um 0 69
top.core1.a1.#242 30.5um 30.5um 0 56
top.core1.j1.#1923 10.8um 10.8um 2 7
...

Total Counts 697 6382

Total Net Routing Area 542p(m^2)

Total Area (Gates+Routing) 106n(m^2)

• -average_report_options N

• If you specify 'N', an additional section is created. The section reports net transition time information:
6. Transition time of nets
==========================
Transition time(Sec.)
Net Rise Fall
--- ---- ----
top.Pclk 1.070e-10 1.070e-10
top.clk 1.070e-10 1.070e-10
...
top.core1.s1.#843 1.070e-10 1.070e-10
top.core1.s1.#491 1.070e-10 1.070e-10

• -average_report_options V

If you specify 'V', an additional section is created. The section reports power dissipation per power
supply and how the estimation of library voltages is determined:
2. Total power per supply
=========================

Estimation Library Power(Watts)

Supply Voltage(V) Voltage(V) Static Dynamic Total
------ ---------- ---------- ------ ------- -----
clock_gating.vdd 1.45 1.45 41.5nW 83.9uW 84uW
Estimation Voltage Source = nom_voltage
Library Voltage Source = nom_voltage

DP512x32.WW_Vdd 2.5 2.5 0W 344mW 344mW

Estimation Voltage Source = nom_voltage
Library Voltage Source = nom_voltage

std_cell_lib.vdd 2.5 2.5 142uW 2.72mW 2.86mW

Estimation Voltage Source = nom_voltage
Library Voltage Source = nom_voltage

txrxios.Vdd 3.3 3.3 2.64uW 94.8mW 94.8mW

Estimation Voltage Source = nom_voltage
Library Voltage Source = nom_voltage

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 Controlling the Contents of the Power Report

Total power 145uW 442mW 442mW

• -average_report_options e

If you specify 'e', scientific notation is used to report power numbers:

2. Internal power consumption
=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top.core1.a1.#241 decoder 1.93e-06 0.00e+00 1.93e-06
top.core1.a1.#242 mux21 1.76e-06 0.00e+00 1.76e-06

• -average_report_options P

If you specify 'P', an additional section is created. The section reports pin transition time information:
6. Transition time of pins
==========================
Transition time(Sec.)
Pin Rise Fall
--- ---- ----
top.sclk1.inpad.PAD 1.040e-10 1.040e-10
top.sclk1.inpad.C 1.040e-10 1.040e-10
top.core1.u1.#133.in[0] 1.070e-10 1.070e-10
top.core1.u1.#133.out[0] 1.070e-10 1.070e-10

• -average_report_options g

If you specify 'g', an additional section is created. The section reports net frequency and RTL glitch
information:
6. Net frequencies
==================

Net Type Glitch Edge rate

--- ---- ------ ---------
decode.metgen_top.afifo8x17.#858 Int 0.00% 31.7MHz
decode.metgen_top.afifo8x17.re_cnter Sync 0.00% 18MHz
decode.i_ry[0] PI 0.00% 4.42MHz

Possible net types include: Int (internal), Sync (synchronous), and PI (primary input).

• -average_report_options G

If you specify 'G', glitch power numbers are reported at the top level:
1. Total power consumption
==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 4.24uW 3.2mW 3.2mW
Internal latch power 0W 0W 0W
Internal memory power 3.97mW 16.3mW 20.3mW
Other internal power 4.04uW 61.7mW 65.7mW
Total internal power 3.98uW 19.6mW 23.6mW
IP Core power 0W 0W 0W
Pad power 44.2uW 103mW 103mW
Clock power 75.3nW 70.7umW 70.7uW

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Analyzing Simulation-Based Average Power

Total power 4.03mW 122mW 126mW

Total glitch power 0W 3.62uW 3.62uW

Total glitch power % 0.0000% 0.0030% 0.0029%

Glitch power numbers are reported as an absolute value and as a percentage of total power. They
are printed separately after 'Total power'. Categories, such as register, clock, that constitute 'Total
power' do not include glitch power.

• -average_report_options t

If you specify 't', the combined static and dynamic instance power is reported. This is applicable to
all sections in the report file.
2. Internal power consumption
=============================
Component Model Power(Watts)
--------- ----- ------------
top.core1.a1.#241 decoder 1.93uW
top.core1.dpmem.m2.m2 DP512x32 1.43mW

• -average_report_options v

If you specify 'v', the gate name is replaced by the 'vendor_gate' in the report as shown in the
following sample:
2. Internal power consumption
=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top.core1.a1.#241 decoder 1.93uW 0W 1.93uW
top.core1.p1.#1918 register 7.33uW 821uW 828uW
top.core1.r1.dpmem.m1.m1 vendor_gate 0W 47.9mW 47.9mW
...

• -vertical_report_instances and -detailed_vertical_report

If you specify both these options, the report includes entries for each model type:
Power dissipation by model/gate type:
=====================================
Cell
Component Model Count Power(Watts)
--------- ----- ---- -------------
top.core1 8 24mW
Register power 2 4mW
Latch power 0 0mW
Memory power 0 0mW
Other power 6 20mW

adder_pg 2 8mW
comparator 1 1mW
decoder 1 5mW
mux21 2 6mW
register 2 4mW
========================================================
top.core2 12 36mW
Register power ...
...

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 Controlling the Contents of the Power Report

Notes:
– Vertical reports do not include instances that are reported as part of clock tree power.
– The 'Cell Count' column reports the number of instances and not the number of bits. If there
is 'one' register instance in the design that is 64-bit wide, the cell count is '1' not '64'. If you
performed clock gating in your design, you can obtain the number of register bits from the
'Clock Gating Summary' as shown here:
Clock Gating Summary:
---------------------
Clock net: top.clk
Number of inferred clock gating cells: 10
Number of registers gated by inferred clock gating cells: 376
Number of registers enhanced gated by inferred clock gating cells: 0
Number of instantiated clock gating cells: 0
Number of registers gated by instantiated clock gating cells: 0
Total number of gated registers: 376
Total number of ungated registers: 77

• -average_report_options u

If you specify 'u', 'vendor_gates' are excluded from power and area reports. Using this option
reduces the size of the gate-level power report. If you do not use this option, every standard cell
instantiation in your design is reported, which can add up to millions of lines. Excerpts of the reports
with and without '-average_report_options u' are shown below (the power variations are in
red):

Sample report 'with' '-average_report_options u'

2. Internal power consumption
=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
...
top.core1.a1.#241 decoder 1.93uW 0W 1.93uW
top.core1.p1.#1918 register 7.33uW 821uW 828uW
...

Sample report 'without' '-average_report_options u'

2. Internal power consumption
=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
...
top.core1.a1.#241 decoder 1.93uW 0W 1.93uW
top.core1.p1.#1918 register 7.33uW 821uW 828uW
...
top.core1.dpmem.m2.m1 DP512x32 0W 14.3mW 14.3mW
...

• -average_report_options c

If you specify 'c', the power associated with clock switched-cap for registers or latches is moved into
the clock report. Excerpts of the reports with and without '-average_report_options c' are
shown below (the power variations are in red):

Sample report 'with' '-average_report_options c'

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Analyzing Simulation-Based Average Power

1. Total power consumption

==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 921uW 959uW
Internal latch power 3.53uW 0W 3.53uW
Internal memory power 0W 344mW 344mW
Other internal power 100uW 964uW 1.06mW
Total internal power 142uW 346mW 346mW
IP Core power 0W 0W 0W
Pad power 0W 88.7mW 88.7mW
Clock power 2.69uW 7.1mW 7.1mW
Inferred Buffer power 139nW 4.9uW 5.04uW

Total power 145uW 442mW 442mW

2. Internal power consumption

=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
...
top.core1.t1.s1.#970 register 496nW 318nW 814nW
...
Total internal power 142uW 346mW 346mW

5. Clock power consumption

==========================
Power(Watts)
Net Type Static Dynamic Total
--- ---- ------ ------- -----
...
top.clk Inferred 2.46uW 5.97mW 5.97mW
...

Sample report 'without' '-average_report_options c'

1. Total power consumption
==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 1.76mW 1.8mW
Internal latch power 3.53uW 0W 3.53uW
Internal memory power 0W 344mW 344mW
Other internal power 100uW 964uW 1.06mW
Total internal power 142uW 347mW 347mW
IP Core power 0W 0W 0W
Pad power 0W 88.7mW 88.7mW
Clock power 2.69uW 6.26mW 6.26mW

Total power 145uW 442mW 442mW

2. Internal power consumption

=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
...
top.core1.t1.s1.#970 register 496nW 31.1uW 31.6uW
...
Total internal power 142uW 347mW 347mW

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 Controlling the Contents of the Power Report

5. Clock power consumption

==========================
Power(Watts)
Net Type Static Dynamic Total
--- ---- ------ ------- -----
...
top.clk Inferred 2.46uW 5.69mW 5.69mW
...

• -average_report_options C

If you specify 'C', the clock switched-cap power for memories and IP blocks is included in the report.

• -average_report_options 0

• If you specify '0', an additional section is created. The section reports internal driver power (the power
required to toggle the net). Excerpts of the reports with and without '-average_report_options
0' are shown below (the power variations are in red):

Sample report 'with' '-average_report_options 0'

1. Total power consumption
==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 999uW 1.04mW
Internal latch power 3.53uW 0W 3.53uW
Internal memory power 0W 344mW 344mW
Other internal power 100uW 143uW 243uW
Total internal power 142uW 345mW 345mW
IP Core power 0W 0W 0W
Pad power 0W 88.7mW 88.7mW
Clock power 2.69uW 6.26mW 6.26mW
Internal load power 0W 1.62mW 1.62mW

Total power 145uW 442mW 442mW

2. Internal power consumption

=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top.core1.r1.a1.#1721 xor 55.1nW 61.7nW 117nW
top.core1.r1.a1.#1722 xor 55.1nW 61.7nW 117nW
...
Total internal power 142uW 347mW 347mW

6. Internal load power consumption

==================================
Power(Watts)
Net Estimator Cap(F) Static Dynamic Total
--- --------- ------ ------ ------- -----
top.rx_rq Point to point 71fF 0W 13.2nW 13.2nW
top.updout[0] Point to point 79.1fF 0W 6.94uW 6.94uW
top.core1.s1.#309 Point to point 6.9fF 0W 0W 0W
top.core1.s1.#310 Point to point 6.9fF 0W 0W 0W

Note: Point to Point = Wireload model estimation.

Exact = SPEF or Capacitance file input

Notes:
– The internal load power is not reported as internal power consumption.

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Analyzing Simulation-Based Average Power

– The following nets are filtered out of the report:

Nets that are traced as part of a clock network defined in your clock file.
Nets that do not have any capacitance value attached to them.
Nets that do not have any drivers or are driven by a 'connect' or 'connect_inv'
instance.
Nets that are the output of IO pads.
Nets with no output pins (that is, primary inputs).

Sample report 'without' '-average_report_options 0'

1. Total power consumption
==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 1.76mW 1.8mW
Internal latch power 3.53uW 0W 3.53uW
Internal memory power 0W 344mW 344mW
Other internal power 100uW 964uW 1.06mW
Total internal power 142uW 347mW 347mW
IP Core power 0W 0W 0W
Pad power 0W 88.7mW 88.7mW
Clock power 2.69uW 6.26mW 6.26mW

Total power 145uW 442mW 442mW

2. Internal power consumption

=============================
Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
...
top.core1.r1.a1.#1721 xor 55.1nW 1.15uW 1.21uW
top.core1.r1.a1.#1722 xor 55.1nW 1.15uW 1.21uW
...

Total internal power 142uW 347mW 347mW

• -average_report_options d

• If you specify 'd' and provide a power diff file, the new delta on parents in the power diff is reported
for each section:
5. Internal Power difference to abc.res
=======================================

Component This(W) Ref(W) Diff(W)

--------- ------- ------ -------
top.core1.a1.#241 1.93uW 1.93uW -1.27E-21W
top.core1.a1.#242 1.76uW 1.76uW -1.27E-21W

6. Pad Power difference to abc.res

==================================

Component Pad type Cap(F) This(W) Ref(W) Diff(W)

--------- --- ---- ------ ------- ------ -------
top.sclk1.inpad PDI 2.09pF 1.91mW 1.91mW 200pW
top.sclk2.inpad PDI 1.94pF 1.91mW 1.91mW -7.24uW

7. Clock Power difference to abc.res

====================================

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 Analyzing Average Power Using a SAIF File

Net Estimator Cap(F) This(W) Ref(W) Diff(W)

--------- --------- ------ ------- ------ -------
top.clk Point to point 742fF 533uW 533uW -207pW
top.pci_clk Point to point 594fF 425uW 427uW -1.62uW

• -average_report_options r

• If you specify 'r' provide a power diff file, the relative percentage delta on parents in the power diff
is reported for each section:
5. Internal Power difference to abc.res
=======================================

Component This(W) Ref(W) Diff(%)

--------- ------- ------ -------
top.core1.a1.#241 1.93uW 1.93uW +0.000%
top.core1.p1.#1917 3.53uW 3.53uW +0.000%
top.core1.p1.#1918 842uW 844uW -0.207%

6. Pad Power difference to abc.res

==================================

Component Pad type Cap(F) This(W) Ref(W) Diff(%)

--------- --- ---- ------ ------- ------ -------
top.sclk1.inpad PDI 2.09pF 1.91mW 1.91mW +0.000%
top.sclk2.inpad PDI 1.94pF 1.91mW 1.91mW -0.379%

7. Clock Power difference to abc.res

====================================

Net Estimator Cap(F) This(W) Ref(W) Diff(%)

--------- --------- ------ ------- ------ -------
top.clk Point to point 742fF 533uW 533uW +0.000%
top.pci_clk Point to point 594fF 425uW 427uW -0.379%

12.12. Analyzing Average Power Using a SAIF File

PowerArtist can perform an RTL, mixed RTL and gate, or pure gate-level average power analysis using
a SAIF file, instead of a VCD or FSDB activity file. SAIF is a well-defined ASCII format defined as part of
the IEEE 1801 standard. SAIF files capture toggle information directly from simulators. Since a basic SAIF
format contains only toggle counts, rather than value change sections as supplied by VCD or FSDB files,
using SAIF files has the following benefits:

• Faster simulation time since far less data is created by a simulator.

• Less disk space is required for simulation.
• The SAIF file is smaller than an equivalent VCD file and therefore takes less time to read during power
analysis.

Despite these benefits, there are some drawbacks to using this format:

• You cannot analyze power over time. This is because specific signal transitions and the time
steps at which they occur are not captured, even though toggle counts are captured.
• Signal correlation is not possible, because only toggle counts are stored. Therefore,
state-dependent static power and dynamic power calculations require heuristics to determine
which conditions are matched in your technology library. This results in less accurate power
numbers when compared to a full arc power analysis. This is especially true for large macros like
compiled memories that have many pins and may have relatively complex power modeling.

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Analyzing Simulation-Based Average Power

The following two SAIF formats are supported:

• The basic format captures signal toggle information and duty cycles.
• The State-Dependent/Path-Dependent (SDPD) format captures information equivalent to the
PowerArtist arcs in the GAF file.
For most accurate power analysis, you should use the SDPD format. Support for the SDPD format
is in beta. This is especially true for a gate-level analysis. However, be aware that power arc
matching done while running the 'CalculatePower' command is done during your simulation
run. This simulation is therefore slower than if you generate the SAIF file in basic format.

PowerArtist supports both the formats and automatically detects when the given SAIF file uses the
SDPD format and performs arc-based estimation. For basic SAIF files, PowerArtist automatically performs
pin-based analysis for RTL designs (and most gate-level designs).

To use a SAIF file, specify the following option in addition to all the other options:
CalculatePower -analysis_type average -saif_file design.saif <options>

PowerArtist reads multiple time-sliced SAIF files and generate an RTL power waveform, with each data
point representing a SAIF file. This output can be directly read in Ansys RedHawk-SC Electrothermal for
early thermal analysis using RTL power as an input, thereby enabling early design decisions such as
thermal sensor placement.

To use time-sliced SAIF file, specify the index of the first time-slice and last time-sliced index using the
following variables:
pa_set saif_file <first time-slice>

pa_set to_saif_index <integer value>

Note: The SAIF format is supported in average power analysis (CalculatePower -analysis_type
average) only.

Understanding Power Value Fluctuations between SAIF and Other Formats

You should expect subtle differences in power numbers for instances in your design if you compare a
SAIF-based power analysis with an equivalent VCD- or FSDB-based analysis.

Duty cycle is defined as follows:

duty_cycle = T1 / (T1 + T0)

where:

• 'T1' = the total time in which the signal remains in the '1' state
• 'T0' = the total time in which the signal remains in the '0' state.

Any 'X' or 'Z' values generated during simulation are translated into duty cycle information. The equations
used in the SAIF flow are:
duty_cycle = (T1 + (TX / 2) + (TZ / 2)) / (T1 + T0 + TX + TZ)
TCnew = TCSAIF + IG

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 Name Mapping Flow

In this equation, the following apply:

• 'T1', 'T0', 'TX', and 'TZ' are fields from a line in the SAIF file.
• 'TX' and 'TZ' represent the total time in which the signal remains in the 'X' or 'Z' state, respectively.
• 'TCnew' represents the new calculated toggle count.
• 'TCSAIF ' represents the original toggle count in the SAIF file.
• 'IG' represents the internal glitches.

12.13. Analyzing Average Power Using Partial Stimulus Files

PowerArtist can perform an RTL, mixed RTL and gate, or pure gate-level average power analysis without
requiring that every user net name be available in an FSDB, IAF or VCD file with its associated toggle
information. If a net is not present in the stimulus file but it is in the design, PowerArtist estimates the
activity of the net while performing an average power analysis. Once it has estimated activity values
for all nets in the design, it then performs the power calculation.

Note: The higher the number of nets 'missing' from the stimulus file, the less accurate the power analysis
results are. PowerArtist's activity analysis allows you to trade-off the simulation time and stimulus file
size with the accuracy of the power analysis.

There are three possible flows:

• RTL design using a partial RTL stimulus file.

• Mixed RTL and gate or complete gate-level design using a partial RTL stimulus file.
See Name Mapping Flow (p. 245).
• Gate-level design using a partial gate-level stimulus file.
Use the '-mixed_sim_prob_estimation true' option.

In the first and third flows, nothing special is required. If you are implementing the Palladium flow, the
'CalculatePower' command checks to ensure that the nets tagged as selected in the scenario file are
present in your stimulus file. If the nets are not present, a warning message is reported. See Acquiring
Simulation Data in Palladium Flows (p. 213), for more details. The second flow is described in the next
section.

12.14. Name Mapping Flow

In this flow, you need a synthesized portion of a design (or the complete design) to perform an average
power analysis using an RTL stimulus file. You may find that simulating designs at the gate-level is
becoming more difficult, but you still have to perform a power analysis. 'Name mapping' is a very
important step that must be done before this type of analysis is possible.

During gate-level synthesis, the RTL design hierarchy is often flattened and the RTL nets that are inferred
as registers are transformed into gate-level instances. Therefore, you must map as many RTL net names
as possible, into gate-level equivalent names. The activity of every successfully mapped gate-level net
is determined by the 'CalculatePower' command using its RTL toggles. This toggle information is then
written out to the GAF file. RTL nets in the design are mapped automatically assuming that you have
not changed either your RTL design hierarchy or your RTL modules between simulating the design and
starting the power analysis run. The activity of the missing nets is calculated during average power
analysis as in flows 1 and 3.

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Analyzing Simulation-Based Average Power

Currently, PowerArtist does the gate-level mapping automatically using a mapping file generated by
Conformal ™ from Cadence. Consider the example scenario where the original design that you simulated
is an RTL design and you need to perform power analysis on a fully synthesized gate-level design. To
enable this, do the following steps:

1. Simulate your RTL design and create a stimulus file.

2. Synthesize your design to gate-level.

3. Create a 'do' file that runs Conformal in its 'compare' mode.

Running Conformal in the 'compare' mode instead of the 'full equivalency check'
mode has two notable benefits:
• You can perform the mapping on your full-chip design. There is no need for a hierarchical
equivalence checking methodology so the mapping step is much simpler to perform.
• The performance in the 'compare' is significantly better. In the 'full equivalency
check' mode, one of the first steps is a compare operation that does the name mapping.
Verifying the actual equivalence between your RTL and gate-level netlists is what takes
the most time.

The following sample 'do' script shows how a compare run is performed:
vpxmode
// preserve original RTL register names
set naming rule "%s_reg" -register -golden
// preserve hierarchical block names in RTL signal naming
set naming rule %s %L[%d].%s %s -instance
set system mode lec
remodel -seq_constant -repeat
add compare point -all
// compare
usage
report unmapped point > DESIGN.lec.unmapped
report compare data -class abort > DESIGN.lec.abort
report compare data -class noneq > DESIGN.lec.noneq
report mapped points > mapfile.dat
diag -sum
diag -all > DESIGN.lec.diag
exit -f

Notes: The key points in this script are:

• The 'set naming rule' command is specified to preserve the original names of the RTL
signals in the conformal mapping report.
• The 'compare' line is commented out. This tells Conformal to perform name mapping
only, without equivalency checking.
• The name mapping file PowerArtist needs is generated using the 'report mapped points'
command. The 'CalculatePower' command processes the file 'mapfile.dat'.

4. Create the gate-level scenario file and specify the 'SetNameMapFile' command. The syntax of
this command is:
SetNameMapFile -map_file <conformal_do_filename> -format conformal

Use the output of the 'do' script created in step #3 as the '<conformal_do_filename>'.

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 Parallel Activity Processing

5. Run the 'CalculatePower' command in its name mapping mode to generate a GAF file and
perform average power analysis by using '-use_rtl_sim_data true'. This option indicates
that the GAF file is generated by a name-mapped run.

A sample command file for steps #4 and #5 is shown below:

Elaborate -top top \
-gate_level_netlist true \
-scenario_file design.scn \
-verilog_startup_file design.vc

SetNameMapFile -map_file mapFile.dat -format conformal

CalculatePower -analysis_type average \

-top_instance testbench.top1 \
-average_report_file design.rpt \
-scenario_file design.scn \
-activity_file ../designData/design_rtl.vcd \
-gaf_file activities.gaf \
-synlib_files ../designData/flop.lib \
-use_rtl_sim_data true \
-gate_level_netlist true \

Notes:
• To force name mapping to occur, you must specify the '-use_rtl_sim_data true'
option.
• The '-use_rtl_sim_data true' option, in turn, sets the following options to 'true':
– -mixed_sim_prob_estimation
If you do not specify this option, missing nets are flagged as errors.
– -pin_based_estimation
This option indicates that many nets are missing from the design, so a complete
arc-based power analysis is not possible.

Advanced Flows
Currently, PowerArtist supports name mapping files created by Conformal. If you have Formality ™ or
can create your own name mapping files, contact your Application Engineer who can answer questions
about how to handle such flows.

12.15. Parallel Activity Processing

PowerArtist supports parallel activity processing for the average power analysis flow (CalculatePower
-analysis_type average). Multiple parallel processes can analyze activity from different time
windows in an FSDB file providing linear speed-up in the runtime for activity processing. This flow is
similar to the parallel analysis support in the time-based power analysis (Distributed Processing in
Time-based Power Analysis (p. 272)) and PAVES (The Streaming (PAVES) Flow (p. 533)) flows.

To enable this flow, use the following command and specify the number of parallel processes to run:
ConfigureParallelAnalysis -processes <>

Refer to the PowerArtist Reference Manual for complete details of the 'ConfigureParallelAnalysis'
command.

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Analyzing Simulation-Based Average Power

12.16. RTL Glitch Power Analysis

Power due to glitching can be a significant contribution to overall power consumption at the gate-level
so it is important to be able to estimate its contribution during RTL power analysis. PowerArtist has
enhanced its capability to estimate glitch power for glitchy elements, such as unregistered arithmetic
components, xor gates, and multiplexers, and then propagate glitch activity through downstream logic.

You can enable this feature by setting the following variables to 'true' during average power analysis:
# Enable glitch propagation
pa_set disable_glitch_propagation <true | false>

# Enable glitch analysis

pa_set enhanced_glitch_analysis <true | false>

You can also use the following variables:

• pa_set enhanced_glitch_max_activity <double>

• pa_set enhanced_glitch_toggle_scaling <double>

Refer to the PowerArtist Reference Manual for complete details of all the variables.

Glitch Power Debug Metrics

Glitching can have a significant impact on the power consumption of a design. Identifying potentially
glitchy elements early at RTL can help you to make design decisions to minimize glitch activity. The
following columns are added to the GUI power table to facilitate interactive debug:

• The 'Glitch Pwr' and '%Glitch Pwr' columns report potential glitch power and % of total glitch
power, respectively, for large hierarchical blocks. Sorting the power table on these columns can
help you to identify blocks with high potential glitching:

Note: The estimated RTL glitch power is intended to identify glitch-prone design elements and
not for absolute accuracy given that parasitics, timing, and detailed implementation data is not
available at RTL design stage.

• The 'Glitch Factor' and ' Glitch Depth Factor ' provide an estimate of the glitch activity on a net.
Use these metrics to identify glitch-prone logic early at RTL:
– Glitch Factor

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 RTL Glitch Power Analysis

Glitch Factor is an indication of how much glitch toggling might occur at a net.
– Glitch Depth Factor
The amount of glitching that occurs at the output of a gate is related to the difference
in the depth factor of nets connected to the inputs of the gate.

These metrics are also available as PDB properties, which can be accessed through the
'get_property' container command:
get_property <net | instance> glitch_factor
get_property <net | instance> depth_factor
get_property <instance> glitch_power

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Chapter 13: Analyzing Vectorless Average Power
13.1. Flow Overview
Vectorless power analysis is a convenient way to quickly generate 'what-if' scenarios that give you a
good idea of what your power may be in various situations. Accurate power numbers come from
simulation-based analysis.

Use PowerArtist to run vectorless power analysis by using the following flow:

1. Run the 'Elaborate' command to build a scenario file.

2. Create a Vectorless Activity File (VAF) that contains the activity information.

3. Run the 'CalculatePower -vectorless_input_file <filename.vaf>' command.

Chapter Organization
The following topics are covered in this chapter:

• Creating the VAF File (p. 251)

• Using the 'SetStimulus' Command (p. 251)
• What-if Power Analysis with User-specified Signal Activity (p. 253)

13.2. Creating the VAF File

The VAF is used to specify activity and duty cycle information for critical signals in the design. This
section describes the commands used in the VAF. For complete syntax and examples for all the commands
in this section, see the PowerArtist Reference Manual.

You can use wild cards for net names and port names in the commands used in the VAF. It may be
easiest to create an OADB script that automatically generates the commands. You can start with the
sample scripts available in the following directory:
$POWERARTIST_ROOT/examples/OpenAccess

13.3. Using the 'SetStimulus' Command

Use the 'SetStimulus' command to perform the following tasks:

• Setting the Frequency and Duty Cycle for Clock Nets

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Analyzing Vectorless Average Power

You must specify the frequency or activity and duty cycle information for every clock net in the
design, as shown in the example below:
SetStimulus -net top.clock -frequency 1e+08 -duty 0.6

This example sets the 'frequency' of the net 'top.clock' to '100 MHz' and the 'duty
cycle' to '0.6'. The default value of '-duty' is '0.5'.

If you performed clock gating using integrated clock gating cells, you should also set the gated
clock output frequency.

• Setting the Frequency for Primary Inputs

You must specify the frequency or activity for all of the primary inputs of the design. If a net is
connected to a module, you can set the frequency by specifying the hierarchical path to the net,
as shown in the example below:
SetStimulus -net {top.we} -frequency 1e+6 -duty .8

This example sets 'frequency' of net 'top.we' to '1 MHz' and 'duty cycle' to '.8'.

You may want to set the same frequency for all your primary inputs and doing so may be fine,
depending on the goals you are trying to achieve. However, you should give this careful
consideration as setting all the primary inputs to one value impacts accuracy.

• Setting the Duty Cycle of Critical Control Signals

If critical signals are tied to a particular value that you want to maintain as constant, then the
constant values can be controlled by specifying duty cycles of '0' (constant 0) or '1' (constant
1).
SetStimulus -net {top.alu.globalEn} -duty 1

This example sets the 'duty cycle' of 'top.alu.globalEn' to a constant '1'. Using the
'SetStimulus' command in this way accomplishes what case analysis does for static timing
analysis.

• Setting the Activity and Duty Cycle for Buses Driven by Tri-Stated Signals

If a signal has multiple drivers that are tri-states, you should set the desired activity and duty
cycle for the bus that represents the combination of all the tri-stated signals.

• Setting the Frequency and Duty Cycle on Leaf-Level Instances

Use the 'SetStimulus' command to set the frequency and duty cycle on all the input and output
nets of a specified leaf-level instance, as shown in the example below:
SetStimulus -instance inst.m1 –port * –frequency f –duty d

• Setting the Frequency for Ports of a Specific Type on Leaf-Level Instances

Use the '-signal_type' option to set the frequency (and duty cycle) on ports of a specific
type: 'input', 'output', or 'both'.

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 What-if Power Analysis with User-specified Signal Activity

SetStimulus -instance top.m1

-port b*
-signal_type input
-frequency 1e+08

This example sets the 'frequency' of all 'input' ports that start with 'b' to '100 MHz'.

• Setting the Frequency for Memories

You must specify the port frequencies for critical ports on your memories. Setting the port
frequencies is critical because memories account for a significant portion of the power of your
chip. You must set the output port frequencies because the 'CalculatePower' command cannot
propagate activities and duty cycles through memories and instances in the downstream cone
of logic from a memory need these values to compute their power correctly.
SetStimulus -instance rxchan.dpmem.m0
-port *
-instance_type memory
-frequency 2.76e+7

This example sets the average 'frequency' of all ports of the memory instance
'rxchan.dpmem.m0.m1' to '27.6 MHz'.

• Handling Black-boxed Instances

During power analysis, PowerArtist cannot propagate activity or duty cycles on any instances
that are black-boxed during elaboration (Elaborate). Therefore, you must specify the activity,
frequency, and duty cycle for every output port of the instance as shown in the example below:
SetStimulus top.myblackbox
-port *
-signal_type output
-frequency 1e+5
-duty .7

This example sets 'frequency' of all output ports in the black-boxed instance
'top.myblackbox' to '.1 MHz' and 'duty cycle' to '.7'.

13.4. What-if Power Analysis with User-specified Signal Activity

PowerArtist RTL power analysis runs fast and enables quick what-if analysis. You can over-ride the
simulation data by setting the activity of any net. You can set the desired activity/duty (or frequency)
on any signal and can also forcefully propagate the desired activity. The activity source for such nets
is marked as 'Forced' and 'Force Propagated' respectively. The activity source of the nets is stored
as a property in the PowerArtist power database (pdb) and can be viewed in the GUI.

Use the '-override <true | false>' option of the 'SetStimulus' command to do this quick
what-if analysis. The default value of this option is 'false'.

PowerArtist supports both vectorless (VAF) and simulation data together as input. Simulation data is
given higher priority. If there is a common net in the VAF and simulation data, then the activity/duty
given in the simulation data is set on the net. However, the net with '-override true' has a higher
priority than the activity from the simulation source.

Limitation: This is not enabled in the ' mode' and 'multiple-gaf' based flows.

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Analyzing Vectorless Average Power

You can also use the 'Net Activity' dialog in the GUI to do quick what-if power analysis. After adding
nets and changing activity/duty you can perform a what-if power analysis by exporting the data in the
format supported by the 'SetStimulus' command. You can then process this file during power analysis
by using one the following variable:
pa_set activity_override_file <filename>

Note: When you use this method, the commands in the file specified by the
'-activity_override_file <filename>' option take higher priority vis-a-vis other activity
sources such as simulation or VAF.

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Chapter 14: Analyzing Time-Based Power
14.1. Introduction
PowerArtist allows you to obtain power and current waveforms as a function of time for RTL, gate-level,or
mixed RTL and gate designs. Before you run time-based power analysis, you must read Preparing for
Power Analysis (p. 167), which describes the prerequisite steps you need to perform before you begin
any power analysis.

Chapter Organization
The following topics are covered in this chapter:

• Overall Design Flow (p. 255)

• Understanding the Inputs for a Time-Based Power Analysis (p. 256)
• Controlling Your Time-based Power Analysis (p. 256)
• Setting Timing Windows for Time-based Power Analysis (p. 258)
• Running the Analysis (p. 258)
• Understanding and Reviewing Outputs and Results of the Time-based Analysis (p. 260)
• Monitoring Flop Clock Activity (p. 266)
• Monitoring Signals (p. 269)
• Multi-threading in Time-based Power Analysis (p. 270)
• Power Normalization (p. 271)
• Distributed Processing in Time-based Power Analysis (p. 272)

14.2. Overall Design Flow

You should implement the following high-level design flow to perform time-based power analysis:

1. Simulate your design and generate simulation data in the FSDB, IAF, or VCD formats.

2. Build a scenario file using the 'Elaborate' command. For details, see Getting Your Design into
PowerArtist (p. 133).

3. Run vector analysis using the 'GenerateActivityWaveforms' command. For details, see Analyzing
Simulation Activity (p. 201).

4. Run the 'CalculatePower -analysis_type time_based' command. Details for this process
are documented in this chapter.

5. View the reports created by the 'CalculatePower' command in the following ways:
• Text format

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Analyzing Time-Based Power

• PowerArtist GUI - this is the information stored in the power database.

14.3. Understanding the Inputs for a Time-Based Power Analysis

To perform time-based power analysis you will need the following inputs:

• The 'CalculatePower -analysis_type time_based' command with other options required for
a time-based analysis. For complete syntax, see "Syntax for Time-Based Power Analysis".
• A scenario file representing the design generated by the 'Elaborate' command. For details, see Getting
Your Design into PowerArtist (p. 133).
• Libraries in Liberty format.
• Simulation traces stored in either FSDB, IAF, or VCD formats.
• Power-aware Tcl commands, such as 'SetClockGatingStyle' and 'SetClockNet' to control your power
analysis. These commands and their functions are described in this chapter.
• Y can also use the 'MonitorInstances' and 'MonitorToggleInstances' commands to monitor various
design elements. This chapter describes how to use these commands in your time-based power
analysis.

14.4. Controlling Your Time-based Power Analysis

As with all PowerArtist flows, you control the operation of your power analysis by specifying the
appropriate commands in your PowerArtist command file or on the command line. To perform either
an RTL, mixed, or gate-level time-based analysis, you must specify the 'CalculatePower' command with
the required options for the type of analysis you want to perform. Some options are required for all
time-based analyses, some for gate-level only, and some for RTL only.

14.4.1. Mandatory Options for all Time-based Analyses

Use these options to specify the various types of mandatory inputs:

• -activity_file <your_simulation_file>

Use this option to specify an input stimulus file generated by a functional simulator run. The file
may be in FSDB, VCD, or IAF (generated by Ansys PLI routines) format. You must specify either
'-activity_file' or '-vectorless_input_file' for an average power analysis.
CalculatePower automatically determines the type of the simulation activity file.

• -scenario_file <your_scenario_file>

Use this option to specify the scenario file you generated using the 'Elaborate' command. For more
information, see Getting Your Design into PowerArtist (p. 133).

• -synlib_files {file_name1 file_name2 ...}

Use this option to add the specified file or Tcl list of files to the list of Liberty technology files.

• -top_instance <top_simulation_instance>

Use this option to specify the full hierarchical name of the top-level module in the simulation
hierarchy.

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 Controlling Your Time-based Power Analysis

• Although not required, you may also want to use the '-start_time' and '-finish_time'
options. For details see, Setting Timing Windows for Time-based Power Analysis (p. 258).

14.4.2. Additional Options for Gate-Level Designs Only

In addition to the options in the previous section, you must specify the following arguments if you
are performing time-based power analysis on a gate-level design:

• -gate_level_netlist true

Use this option to analyze a gate-level design.

• -interval_size <time_in_seconds>

Use this option to specify the minimum time interval in seconds for which power is reported. Power
calculation by the time-based analyzer depends on this value.

If you specify an interval of size 'T >= 1 ns', the time-based analyzer:

1. Breaks up the time-steps in your activity file into buckets of width 'T'.

2. Calculates the total dynamic energy for every arc that matches during all time steps
processed for that interval.

3. Divides the dynamic energy by 'T'.

4. Adds the static power. This is the total power that is reported for the interval.

If you do not specify an interval, then PowerArtist performs an instantaneous analysis. For each
time step in the activity file, PowerArtist:

1. Calculates the total dynamic energy for every arc that matches during that time step.

2. Divides the energy by '1 ns' to get power.

3. Adds the static power. This is the total power that is reported for that time step.

Note: If you specify an interval of size 'T < 1 ns', PowerArtist generates a warning and performs
an instantaneous power analysis.

14.4.3. Additional Arguments for RTL and Mixed Designs Only

In addition to the required options for all analyses, you must specify the following options if you are
performing time-based power analysis on an RTL or mixed RTL-gate design:

• -reference_clock < clock_name>

Use this option to specify the reference clock that controls when a clock starts and the length of
its period.

• -active_edge <auto | positive | negative>

Use this option to specify the edge of the clock that defines the start point for the first interval.

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– positive: starts the clock when the first clock transition goes to 1.
– negative: starts the clock when the first clock transition goes to 0.
– auto: starts clock when the first clock transition goes to either 0 or 1.
Default: auto

• -num_clock_cycles <integer>

Use this option to set the interval size as the number of clock cycles. The interval size is the period
of the block into which PowerArtist splits the simulation. You should choose an interval greater
than 1% of the total simulation time.

Default: 0

For additional options, see the 'CalculatePower' entry in the PowerArtist Reference Manual.

14.5. Setting Timing Windows for Time-based Power Analysis

When performing a time-based power analysis, you must ensure that:

• the '-start_time' and '-finish_time' options are set to be the leading edge of a clock
and the trailing edge of a clock, respectively.

• the 'interval size' used in your analysis is set.

– For gate-level netlists, use the '-interval_size' option. The size should not be less
than one clock cycle.
– For RTL and mixed RTL designs, use the '-reference_clock_active_edge' and
'-num_clock_cycles' options. The size should not be less than one clock cycle. Every
interval requires an average power analysis of the entire design.

In general, the 'interval size' should be a multiple of the clock period. The number of clock
periods impacts the performance and granularity of your analysis. Smaller intervals take longer
but give you more data.

The resulting waveforms look more realistic when you do not use arbitrary values for
'-start_time', '-finish_time', and '-interval_size'.

14.6. Running the Analysis

You should use a PowerArtist command file to run your time-based power analysis. This analysis is
controlled by the 'CalculatePower' command.

14.6.1. Gate-level Time-based Power Analysis

Sample Command File
CalculatePower -analysis_type time_based \
-activity_file design.vcd \
-clock_file clocks.tcl \
-finish_time 20ns \
-gate_level_netlist true \
-scenario_file design.scn \
-start_time 10ns \

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 Running the Analysis

-synlib_files ../libs/memories.lib ../libs/core.lib ../libs/ios.lib \

-time_based_report_file design.rpt

You can also run this command from the 'pa_shell' prompt.

The following three examples assume that you are running with '-gate_level_netlist true'
and that the 'top_instance', scenario file, and Liberty files are specified:

• Example 1
CalculatePower -analysis_type time_based -interval_size 1e-9

This command performs time-based analysis breaking your simulation time into '1 ns' buckets.
The command generates a report 'design.rpt' and a power waveform file
'CalculatePower.ptcl'. The 'design.rpt' contains a simple report for the top-level
instance in the design.

• Example 2
CalculatePower -analysis_type time_based -interval_size 1e-9 \
-fsdb_output_file design.fsdb -ptcl_output_file design.ptcl -output_current true

This command performs the same time-base analysis as 'Example 1', but generates current
over time waveforms that are stored in 'design.fsdb' (FSDB format) and 'design.ptcl'
(PTCL format).

• Example 3
MonitorInstances -name top.core1
CalculatePower -analysis_type time_based -interval_size 1e-9 \
-fsdb_output_file design.fsdb -ptcl_output_file design.ptcl -output_current true

These two commands perform a similar time-based analysis as 'Example 2', but the report
and the waveform files include only the hierarchical instance 'top.core1'.

Note: The values of all the child instances are included in the information generated for
'top.core1'. This is controlled by the 'MonitorInstances' command. For additional control,
use the 'MonitorFast' and 'MonitorArcs' commands.

14.6.2. RTL Time-based Power Analysis

Sample Command File
CalculatePower -analysis_type time_based \
-active_edge positive \
-activity_file ../design_data/rtl_sim/activities.vcd \
-calculate_log CalculatePowerTimeBasedBatch.log \
-default_output_load 3.9e-11 \
-finish_time 12135580ps \
-fsdb_output_file $design.TimeBasedBatch.fsdb \
-num_clock_cycles 20 \
-power_db_name $design.TimeBasedBatch.pdb \
-reference_clock top.clk \
-save_clock_trees_netlist true \
-scenario_file $design.Batch.scn \
-start_time 6071580ps \
-time_based_report_file $design.TimeBasedBatch.rpt \
-time_based_write_power_db true \

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Analyzing Time-Based Power

-top_instance txrx_tst.top1 \
-use_non_scan_flops false \
-wireload_library hvt

This is an example of how to perform a time-based analysis on an RTL design. In this case, you do
not specify the '-gate_level_netlist true' option.

14.6.3. Cycle-based Power Analysis for GHz+ Designs

PowerArtist issues warning 'TBE-62' if the value of '-interval_size' was very small, such as less
than '1 ns', during time-based power analysis. To resolve the warning, PowerArtist automatically
sets the following variable to 'true', in cases where the value of '-interval_size' is less than '1
ns':
pa_set unlimit_interval_size true

This enhancement enables analysis of cycle-based power for designs running at GHz+ frequencies.

Notes:

• The runtime for time-based power analysis is a function of the number of intervals. Setting
'-interval_size' to a very small value for a long analysis duration can lead to an increased
runtime due to a large number of intervals.
• The variable is applicable for power analysis of gate-level designs only.

14.7. Understanding and Reviewing Outputs and Results of the

Time-based Analysis
After the analysis is complete, the following outputs are generated:

• A log file whose name you can set by using the 'CalculatePower -log' option.

• A report file containing an ASCII representation of the power analysis results.

• Waveforms in the FSDB format or PowerArtist Tcl-based format that holds the current and power
over time information you requested. Waveforms are not stored in the report file.

14.7.1. Contents of the ASCII Report File

If you specify '-time_based_report_file <filename>', 'CalculatePower' generates a text
file that contains the following information:

• A 'header' section that provides the following information:

– The date of the power analysis run.
– The version of PowerArtist used to perform the analysis.
– The options applied during this run.
– Summary information on the simulation run including simulation duration, and start and
finish times.
– The power supply values that were used.
– The initial input transition time.

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 Understanding and Reviewing Outputs and Results of the Time-based Analysis

– Monitor file name.

– Wire load mode and model information.

• Section 1: Power Contribution.

This section is divided into the following sub-sections:

– Category Power Summary
This group power section lists for each group:
The category name
Average power for all elements in the category split into static, dynamic, and total power
The maximum power in Watts
One or more time steps in your simulation at which the maximum power occurred.
– Instance Power Summary
This section lists the following for each monitored instance:
Average power for all children of the instance (or just the instance itself if it is a cell in a
library) split into static, dynamic, and total power
The maximum power in Watts
One or more time steps in your simulation that the maximum power occurred
The instance name at the end of the line because this field can be arbitrarily long.

• Section 2: Detailed Instance Power

This section provides a per instance power consumption report.

• Section 3: Clock Power Consumption

For details of this section, see Clock Power Consumption (p. 55).

• Section 4: Inferred Buffer Tree Power

If your design required that buffer trees be generated for high fanout nets, then this section
describes the affected nets and how the buffer tree was created.

For a sample time-based power report, run the analysis tutorial and generate a time-based analysis
report.

14.7.2. Generating and Viewing Waveforms

The 'CalculatePower -analysis_type time_based' command generates waveforms of current
and power over time for the categories and instances that you specified using the 'MonitorInstances'
command. These graphs are generated in two formats: 'FSDB' and/or 'PTCL'.

If you specified the FSDB format (by specifying the 'CalculatePower -fsdb_output_file
<filename>' command), you can load and display the waveforms in PowerArtist by using the Ansys
Waveform Viewer available in the PowerCanvas (select 'Tools > Waveform Viewer'). A sample
waveform is shown below:

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Figure 14.1: Sample Power-Over-Time Waveform

14.7.3. Measuring the Distance Between Two Data Points

When you are viewing a waveform of interest, you can measure the distance between two data points
on the waveform. To do so, use the ruler feature as follows:

1. Place your cursor over an area on the waveform and press the 'r' key to start the ruler.

2. Drag the ruler to any data point on the waveform and mark it using the 'm' key.

A colored box (same color as the waveform) appears at the marked data point. This box
includes the coordinates of the data point and the 'delta x (dx)' and 'delta y (dy)'
values from the first data point to second data point. The formulas are:
dx = 'X of the end point' - 'X of the start point'
dy = 'Y of the end point' - 'Y of the start point'

A copy of the ruler is also recorded on the plot.

3. You can continue measuring the distance to additional data points, or if you are done, press
the 'r' key again to disable the active ruler. Marked ruler(s) stay on the plot.

The following figure shows one measurement from a single data point:

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 Understanding and Reviewing Outputs and Results of the Time-based Analysis

Figure 14.2: Measuring Distance between Data Points

This feature is useful for presenting data in a presentation or in printed form. If you want to present
waveform data in printed form, you should change the background color to white (to save ink when
printing) by selecting 'Options > Toggle background color'.

For more information on using the Waveform Viewer, see Using the Waveform Viewer (p. 429).

Note: If the value of '-interval_size' is less than '1ns' for a gate-level design, PowerArtist performs
an instantaneous power computation. The following figure a sample waveform:

Figure 14.3: Sample Waveform in PTCL Format for Instantaneous Analysis

14.7.4. Generating Power Waveforms for Custom Groups

Power versus time waveforms are generated when the 'MonitorInstances' command is used in
time-based power analysis. The command supports pre-defined group names, such as 'registers',

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Analyzing Time-Based Power

'memory' (via the '-group' options) and user-specified instance names (via the '-name' option). The
following enhancements are added in this flow:

• The 'DefineGroup' command supports the creation of custom/user-defined groups.

• The 'MonitorInstances' command can generate a single power waveform for the
custom/user-defined groups.
• The power information of the custom/user-defined groups is reported in the power analysis
text report.

Use Model
You can enable this flow by performing the following steps:

1. Create a custom group using the following command:

DefineGroup <group_name> -instance <instance_list>

2. Specify this custom group with the following command:

MonitorInstances -group <group_list>

where, '<group_list>' accepts user-defined/custom group names as input. This is in

addition to predefined groups, such as 'registers', 'memory', 'latch', and 'clock'.

This generates a combined single power waveform and adds an entry to the time-based
power analysis text report for the group.

The following enhancements in 'DefineGroup' and 'MonitorInstances' commands enable this support:

• Enhancements to the 'DefineGroup' command:

– Support for pattern matching or wild card matching is added to the '-instance' option
to enable you to specify a pattern. All the instances matching that pattern are included in
the group.
– The '-levels' option is ignored and a warning is issued.
– Support is added to report the instance names that match the wildcard specified with the
'DefineGroup' command. These instance names are passed to the 'MonitorInstances'
command for creating power waveforms.
– Support is added to allow instance names to be specified without the design top as prefix.
– Inferred buffer power and clock power are excluded from groups that are created using the
'-category' option. Only instance power is reported for such groups.
– Wildcard support is improved. You can now specify multiple wildcards, as shown in the
following example:
DefineGroup myGrp { top.*.r* }

– You can create groups using cell names, by using the '-module' option. An example is
shown below:
DefineGroup myGrp { top.core1 } -module { DP256x32 }

In this example, the 'DefineGroup' command creates a group of all the instances whose
cell type matches 'DP256x32' within the hierarchy 'top.core1'.

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 Understanding and Reviewing Outputs and Results of the Time-based Analysis

• Enhancements to 'MonitorInstances' command:

– The '-levels' option is ignored and a warning is issued.
– Support is added to allow instance names to be specified without the design top as prefix.
– Wildcard support is added, as shown in the following example:
MonitorInstances -name { top.core*.r* }

Example
DefineGroup myGrp1 -instance {top.core1.t1 top.core1.r1}
MonitorInstances -group {memory register myGrp1}

Outputs
The 'DefineGroup' and 'MonitorInstances' commands are specified as inputs in a tcl file. The power
waveform saved in an FSDB or PTCL file and a text report to enable any post-processing are the
outputs in this flow.

• A sample power waveform is shown below:

• A new sub-section is generated in the 'Power contribution' section of the time-based power
analysis text report. It contains information about the custom/user-defined group(s). A sample
report is shown below:
1. Power contribution
=====================
CATEGORY POWER SUMMARY
Average Power(Watts) Maximum At Time
Category Static Dynamic Total Power(Watts) (s)
-------- ----- ------- ----- ------------ ---
Register 4.1363uW 3.2191mW 3.2232mW 3.955mW 10.62us
Latch 0W 0W 0W 0W 0s
Memory 3.9747mW 16.317mW 20.292mW 21.111mW 9.1036us
Other 4.8438uW 90.282uW 95.125uW 140.8uW 8.194us
IO 43.734uW 102.66mW 102.7mW 129.57mW 10.62us
11.529us
Clock 7.6726nW 21.064uW 21.071uW 22.012uW 10.013us
10.316us, 10.62us, 10.923us, 11.226us, 11.529us, 11.832us, 12.136us
InferredBuffer 668.08nW 0W 668.08nW 668.08nW 6.3748us
6.678us, 6.9812us, 7.2844us, 7.5876us, 7.8908us, 8.194us, 8.4972us, 8.8004us, 9.1036us
...
----- ------- --------
Total Average 4.0281mW 122.3mW 126.33mW

CATEGORY POWER SUMMARY

Group Average Power(Watts) Maximum At Time
Name Static Dynamic Total Power(Watts) (s)
---- ------ ------- ----- ------------ ---

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Analyzing Time-Based Power

myGrp1 4.0275mW 122.28mW 126.31mW 154.57mW 10.62us

myGrp2 1.989mW 7.7089mW 9.6979mW 14.711mW 10.62us
<snip>

14.7.5. Using Results

You can use the results from a time-based power analysis in a number of ways:

• Use the peak power and current information during the physical design process to size your
power busses. By selecting various hierarchical instances in your design that correspond to
physical blocks, you can get a good idea of the power grid needs on a block-by-block basis.
• Use the total peak power and current values to estimate the power supply needs of your chip.
• Examine areas of the waveform that have large swings in power or current from one time step
to the next, to get an idea of any di/dt issues.

14.8. Monitoring Flop Clock Activity

Flop clock activity (FCA) is a measure of the efficiency of the clock gating in your design and can be
monitored using time-based power analysis. The FCA flow monitors the activity of clock pins on registers
in your design. A low FCA number implies that clocks are well gated. Conversely, a high FCA number
indicates that the clocks are not well gated (due to inefficient enables or non-enabled registers) or the
mode captured in the simulations requires clocks to toggle.

The FCA flow works at the RT level of abstraction only for feedback MUX topologies and for instantiated
clock gates. The reports are in the form of:

• '.ptcl' graphs

The graphs report flop clock activity and average flop clock activity as a function of time.

• Text file

The text file includes minimum, maximum, and average counts of flops whose clocks toggled
during an interval expressed as a number and a percentage. It also includes the total flop count
per hierarchical instance per clock domain.

You can enable this flow in the following two ways:

• By using the 'CalculateFlopClockActivity' command

When this command is specified, PowerArtist calculates flop clock activity for your design and
generates the report and graphs mentioned above. If you are interested in only flop clock activity
information, it is better to use the 'CalculateFlopClockActivity' command.

For details of this command, refer to the PowerArtist Reference Manual.

• By using the 'CalculatePower' command:

CalculatePower -analysis_type time_based -flop_clock_activity <string>

When this command is specified, PowerArtist calculates flop clock activity for your design,
performs time-based power analysis, and generates the report and graphs mentioned above.

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 Monitoring Flop Clock Activity

You must specify the following options while using this method:
-num_clock_cycles <integer>
-reference_clock <clock_name>
-clock_file <filename>

The interval size is the same across all clocks and determined by the values of the
'-reference_clock' and '-num_clock_cycles' options.

The sample waveforms and text file in the next sections are generated by using the analysis
tutorial with the following 'CalculatePower' options:
-num_clock_cycles 1
-reference_clock top.clk
-clock_file txrx.clk
-flop_clock_activity fca

For details of this command, refer to the PowerArtist Reference Manual.

Use the 'MonitorToggleInstances' command to specify a list of hierarchical instances that to monitor
in the FCA flow. An example usage is shown below:
MonitorToggleInstances
-instances {top top.core1 top.core1.u1 top.core1.t1 top.core1.r1}

This example tells PowerArtist to monitor the five specified instances and generate results for each
hierarchical instance you specified per clock domain as a waveform in either the 'PTCL' or 'FSDB' file
you specify.

14.8.1. Sample Flop Clock Activity Graphs

The following figure shows both the average flop clock activity graph (on top) and the absolute graph
(bottom).

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Analyzing Time-Based Power

Figure 14.4: Sample Waveform in PTCL Format for Instantaneous Analysis

Looking at the average flop clock activity in the top graph, you can see that the transmit clock domain
(t1_top.clk) in brown is active when the receive clock domain (r1_top.clk) in green is inactive and
vice-versa. You can also see that the pci clock domain (top.pci_clk) is always on, indicating that this
could be a good candidate for clock gating. To determine whether it's worth your time to clock gate
the pci clock, you would need to check the absolute waveforms (displayed on the bottom half of this
figure). Looking at them here, you can see that there are approximately 20 flops being clocked in the
receive block (ut0|top.core1.r1_top.pci_clk) and even more in the transmit block
(ut0|top.core1.t1_top.pci_clk). Therefore, this could indicate a power bug. To see the exact values,
you can either hover your mouse on the waveforms or read the text report (as shown on the next
page).

14.8.2. Sample Flop Clock Activity Report

Flop Clock Activity Report
==========================
Date : Wed Apr 13 11:21:15 2011
Program : PowerTheater Time Based Engine (64 Bit Linux) 2010.2.3PreAlpha (11 Apr 2011)

Interval Size : 303 ns

Reference Clock : top.clk
Number of clock cycle(s) : 20 clock cycle(s)

Min, Max, Average Clocked Flop Statistics

=========================================

Instance: top
Clock: top.clk There are 453 flops defined in hierarchical instance “top” and its
Number of Flops : 453 children that are driven by top.clock. top and its children.
Flop Clock Activity: There existed one or more intervals where:
Minimum : 206 (45.4%) the minimum # of registers whose clock toggled was 206; the maximum
Maximum : 249 (55%) was 249;
Average : 230 (50.8%)

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 Monitoring Signals

Average Flop Clock Activity:

Minimum : 0.454 (45.4%) On average over all of the intervals, the minimum of # of clocks that
Maximum : 0.408 (55%) toggled was 45.4%; the maximum was 55%; and the average was 50.8%.
Average : 0.368 (50.8%)
<snip>

Instance: top.core1.r1
Clock: top.clk
Number of Flops : 77
Flop Clock Activity:
Minimum : 1 (1.3%)
Maximum : 13 (16.9%)
Average : 5.98 (7.77%)
Average Flop Clock Activity:
Minimum : 0.013 (1.3%)
Maximum : 0.169 (16.9%)
Average : 0.0777 (7.77%)

Clock: top.pci_clk
Number of Flops : 19
Flop Clock Activity:
Minimum : 19 (100%)
Maximum : 19 (100%)
Average : 19 (100%)
Average Flop Clock Activity:
Minimum : 1 (100%)
Maximum : 1 (100%)
Average : 1 (100%)
<snip>

Instance: top.core1.t1
Clock: top.clk
Number of Flops : 77
Flop Clock Activity:
Minimum : 1 (1.3%)
Maximum : 13 (16.9%)
Average : 7.12 (9.25%)
Average Flop Clock Activity:
Minimum : 0.013 (1.3%)
Maximum : 0.169 (16.9%)
Average : 0.0925 (9.25%)

Clock: top.pci_clk
Number of Flops : 87
Flop Clock Activity:
Minimum : 87 (100%)
Maximum : 87 (100%)
Average : 87 (100%)
Average Flop Clock Activity:
Minimum : 1 (100%)
Maximum : 1 (100%)
Average : 1 (100%)
<snip>

14.9. Monitoring Signals

PowerArtist allows you to monitor a register output net as a signal. You can specify RTL signal names
for time-based power analysis by using the following command:
MonitorInstances -signal <signal_name>

Inputs
The '-signal' option takes a register output net as input and monitors it.

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Analyzing Time-Based Power

Outputs
The '-signal' option has the following outputs:

• Detailed time-based power report

The power of the driver instance of the register output net is reported in section '1. Power
contribution' in the sub-section titled 'INSTANCE POWER SUMMARY', which also includes a new
column titled 'Signal Name'. A sample report is shown below:
1. Power contribution
=====================
CATEGORY POWER SUMMARY
<snip>

INSTANCE POWER SUMMARY

Average Power(Watts) Maximum At Time Instance Signal
Static Dynamic Total Power(Watts) (s) Name Name
------ ------- ----- ------------ --- ---- ----
11.984mW 138.85mW 150.83mW 179.85mW 10.62us TOP -
854.19nW 107.52uW 108.37uW 152.18uW 6.3748us top.u1.#r4 top.core1.txdin[0]
6.678us, 6.9812us, 7.2844us, 7.5876us, 7.8908us, 8.194us, 8.4972us, 8.8004us,
9.1036us
5.9653mW 15.381mW 21.346mW 31.395mW 10.62us top.r1 -
<snip>

Notes:
– A column is added to the sub-section only if the '-signal' option is specified. A '-' is
added for an empty entry in the 'Signal Name' column as a placeholder.
– The text in red represents the other time stamps when maximum power is achieved by
instance 'top.u1.#r4'.

• Waveforms corresponding to the specified signals are also generated for the driver instance in
the generated FSDB file.

14.10. Multi-threading in Time-based Power Analysis

PowerArtist performs time-based power analysis at user-specified intervals and provides detailed results
including peak power consumption and temporal power waveforms. The higher the number of intervals,
the longer is the time taken for time-based power analysis.

To resolve this runtime issue, time-based power analysis is enhanced to use multi-threading so that
time-consuming tasks are done concurrently giving it a significant performance boost. To enable
multi-threading, set the following variable to 'true':
pa_set threads <true | false>

The following message is issued when multi-threading is enabled:

Note TBE-165: Enabled multithreading

You can view the number of threads run during time-based power analysis in the following output files:

• As Note 'TBE-187' in the log file:

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 Power Normalization

<snip>
Note TBE-187: Number of threads being used = 2
<snip>

• As the thread count in the header of the time-based analysis text report as shown below:
<snip>
Number of threads used = <integer>
<snip>

You can also control the number of threads used by PowerArtist in an LSF setup or any other load
sharing system. Use the following variable to specify an upper limit for the number of threads and
ensure compliance to your organization's LSF policy:
pa_set num_threads <integer>

The valid values for 'pa_set num_threads' are:

Value Description
0 This is the default value, which means that no limit is set. The following message is issued
in this case:
Note TBE-187: Number of threads being used = <integer>

1 Only a single thread is allowed, which means that multi-threading is disabled and the
following variable is set:
pa_set threads false

The following warning is issued in this case:

TBE-189: Maximum number of threads specified = 1;
disabling multithreading.

<> Any integer value. The following message is issued in this case:
Note TBE-190: Maximum number of threads specified =
<integer>

Note: If you specify a value that is higher than the maximum number of threads supported
by the system, PowerArtist ignores the specified value, sets the value to the maximum
number of threads allowed by the system, and emits the following message:
Note TBE-187: Number of threads being used = <integer>

14.11. Power Normalization

Power normalization is intended to improve RTL power accuracy by mitigating the activity propagation
errors caused by probabilistic activity propagation, leading to improved power correlation between RTL
power and gate-level power.

Power normalization analyzes the gap between the propagated activity values and simulation activity
values at a net or pin, and scales the power of logic upstream. This helps to mitigate the effects of

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Analyzing Time-Based Power

activity propagation error, thereby, improving RTL power accuracy. You can enable this flow by setting
the following variable to 'true':
pa_set enable_power_normalization <true | false>

The default value of the variable is 'false'. When this is set to 'true', PowerArtist normalizes the
dynamic power of the instances between two simulated nets. For each simulated net, a normalization
factor is computed using the formula defined below:
Normalization factor = simulated activity / propagated activity

The power of the instances in the fanin cone of the simulated net is scaled with the normalization
factor, leading to improved power accuracy.

Power normalization also includes scaling buffer dynamic power according to the Normalization factor
(greater or less than 1) computed for the driving net of the buffer. Dynamic power of instances in the
fanin cone of the clock pin of sequential elements is not normalized based on the simulated activity of
output of sequential elements. Dynamic power of instances in the fanin cone of the data input pin of
sequential elements can be normalized if the simulated activity at the output of sequential element is
more than the tool calculated activity. This may correctly lead to a change in dynamic power of the
sequential element.

The resulting normalized instance power is accessible from the GUI and Tcl interface. The normalized
power (on instances and nets) and normalized activity (on nets) is also annotated in the power database
(PDB). This enables you to match total dynamic power of instances with the dynamic power reported
in power analysis text report, view the normalized frequency and activity value for nets in the GUI, and
use container commands to obtain normalized activity and power from the PDB.

14.12. Distributed Processing in Time-based Power Analysis

Time-based power analysis ('CalculatePower -analysis_type time_based') is increasingly
important for peak power and thermal concerns. However, this analysis can take significant time to run
for a high number of intervals.

Time-based power analysis is enabled for distributed processing for a significant improvement in runtime.
In this flow, multiple processes are run in parallel to perform power-over-time analysis. The input activity
data is distributed among multiple processes and the result is combined at the end to provide the
complete power over time profile. You can use the 'ConfigureParallelAnalysis -processes <>'
command to enable this flow and use '-script <>' to specify an executable script that enables you
to submit jobs to multiple machines in your environment.

Note: Distributed processing is supported in the FSDB flow only.

Command
The 'ConfigureParallelAnalysis' command defines the options for distributed processing. Refer to the
' PowerArtist Reference Manual' for complete details of the command.

The Script
The script file that you specify must fulfill the following criteria:

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 Distributed Processing in Time-based Power Analysis

• It must accept the PowerArtist commands as-is, and message quotes, as needed.
• It must submit the job to the appropriate server (or multiple machines), with the appropriate
environment configuration.
• It must echo the commands' output to stdout.

A sample script is show below:

:
set -x
# use -I to echo job's stdout
# use 'exec' to replace this shell with the running bsub job's process identifier
# use 'pa_shell' if the LSF server can distribute jobs to other machines, as
# pa_shell must be the parent process for all PowerArtist binaries
eval exec bsub -I pa_shell -cmd \""$@"\"

Use the following command to make this script executable:

chmod +x <script_name>

Notes:

• If you do not specify a script, the parallel processes are executed on the local machine.
• If you do not run the 'ConfigureParallelAnalysis' command, time-based power analysis defaults
to a single process.

Outputs
There are four outputs in this flow:

• FSDB file

A single FSDB file with a consolidated power waveform is generated after parallel analysis. You
can specify the name of the file by using the following variable:
pa_set fsdb_output_file <filename>

• PTcl files

Multiple PTcl files (one for each process) representing power waveforms are generated after
parallel analysis. Compared to FSDB, '.ptcl' files are textual and are generated incrementally
so you can open them in the 'Waveform Viewer' for each segment, after time-based analysis is
complete. The '.ptcl' files are generated only if the following variable is specified:
pa_set ptcl_output_file <filename>

If '<filename>' is specified, and it ends in '.ptcl', then '<start_time>_<finish_time>'

is inserted before '.ptcl'. Otherwise, '<start_time>_<finish_time>' is appended to the
'<filename>'.

Consider the following examples:

– Example 1:
pa_set ptcl_output_file foo.ptcl

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Analyzing Time-Based Power

The file is renamed and the following multiple files are generated:
foo_start1_finish1.ptcl
foo_start2_finish2.ptcl

– Example 2:
pa_set ptcl_output_file foo.myExtension

The file is renamed and the following multiple files are generated:
foo.myExtension_start1_finish1.ptcl
foo.myExtension_start2_finish2.ptcl

• Log file

A single log file is generated after parallel analysis. You can specify the name of the file by using
the following variable:
pa_set calculate_log <filename>

• Consolidated text file

There are two methods of generating a consolidated report:

– Manual

Each process or run of the parallel time-based flow generates a report ('.rpt') file. You
can combine the multiple reports into a single report ('.rpt'). The start/finish header for
the report file from each process is printed in the combined report noting the start/end
time slice for that report. A sample header is shown below:
(Report from -start_time 2400 to -finish_time 11000)

– Automatic

A single consolidated power report for all the slices processed in parallel is generated
automatically. A sample of the merged report is shown below:

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 Distributed Processing in Time-based Power Analysis

Note: Power database ('.pdb') generation is disabled in this flow.

14.12.1. Handling Network Delay in Distributed Processing Flow

In the parallel activity or time-based analysis flow, sometimes some file/s generated by remote
machines/processes are not immediately visible to the master machine due to network/NFS delays.
You can control the wait time (the time the main process waits for these file/s to become visible) by
using the following variable:
pa_set network_delay_timeout <time_in_minutes>

The default value of the variable is '30'.

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Chapter 15: Examining and Implementing Power
Reduction Opportunities
15.1. Introduction
You can use PowerArtist to determine your power bottlenecks. After changing your design to significantly
reduce power, you can use PowerArtist and tools later in the design flow to further reduce your chip's
power. The tree display in PowerArtist's PowerCanvas user interface allows you to quickly see where
the power in your design is going.

PowerArtist contains power reduction modules called 'PowerBots'. These PowerBots scan your design
looking for a specific design feature, such as an enable signal that can be constructed to turn off
unobserved register toggles. A PowerBot performs an analysis of the topology of your design and
activities on nets and then makes recommendations on potential changes you should make to your
design. It reports either power savings numbers or power wastage numbers to help you make your
decision. If it can determine an example change to make, it provides code snippets too. Each of the
available PowerBots are discussed in detail in this chapter.

For a hands-on example of running power reduction, you should read the PowerArtist Tutorial Part II:
Power Reduction (p. 71) chapter.

Chapter Organization
The following topics are covered in this chapter:

• PowerBot Overview (p. 277)

• Power Reduction PowerBots (p. 279)
• Power Linter PowerBots (p. 325)
• Power Reduction Technique Summary (p. 339)
• Running PowerArtist Clock PowerBots (p. 345)
• Generating Synthesis Constraints (p. 346)
• Recommended Flow for Implementing Power Reductions (p. 349)
• Viewing Reduction Results (p. 351)
• Parallel Activity Processing (p. 375)
• Fine-Grain Switch Cell Support (p. 375)

15.2. PowerBot Overview

The following diagram explains how the PowerBots fit into PowerArtist:

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Examining and Implementing Power Reduction Opportunities

Figure 15.1: Overview of PowerBots

The following table lists the PowerBots that are described in this chapter. There are two types of
PowerBots:

• Power Reduction PowerBots (p. 279)

• Power Linter PowerBots (p. 325)

Table 15.1: Overview of PowerBots

PowerBot Acronym
Power Reduction PowerBots (p. 279)
Low-Activity Non-Enabled Register (LNR) (p. 279) lnr
Low-activity Enabled Registers (LER) (p. 281) ler
Datapath Operator Isolation (DOI) (p. 282) doi
Local Explicit Clock Enable (LEC) (p. 283) lec
Split Memory Words (SMW) (p. 287) smw
Gate Memory Clock (GMC) (p. 293) gmc
Prism (p. 298) prism
Observability Don't Care (ODC) (p. 304) odc
Strengthened Observability Don't Care (SODC) (p. 315) sodc
Enhanced ODC-based Clock Enable Identification (p. 319) odc
Enable Signal-based Stability Constraints (STC) (p. 322) stc
Power Linter PowerBots (p. 325)
Memory Power (MEM) Linter (p. 326) mem
MUX Power (MUX) Linter (p. 327) mux
Register Power (REG) Linter (p. 334) reg
Clock Enable Condition (CEC) Linter (p. 336) cec
Memory Sleep Mode (MSM) Linter (p. 337) msm
Macro Power Linter (MPL) (p. 338) mpl

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 Power Reduction PowerBots

15.3. Power Reduction PowerBots

This section describes, in detail, each of the power reduction PowerBots that are available to you.

15.3.1. Low-Activity Non-Enabled Register (LNR)

Design Parts: datapath, clock

The Low-Activity Non-Enabled Register (LNR) PowerBot finds registered buses in the design that
change infrequently and are not enabled, and estimates the savings gained if a clock enable is
generated by detecting changes on the bus.

Definition
The following schematic and timing diagram shows a register where the data input is active during
one phase of operation only, and does not change for a long period of time:

Figure 15.2: LNR - Schematic and Timing Diagrams

15.3.1.1. Usage
This PowerBot is enabled by default. To disable it, specify the following command:
ReducePower -skip_reduction_list lnr

Note: This PowerBot works in vectorless mode.

15.3.1.2. Implementation
In this circuit, power is wasted by the clock driver as well as by circuitry inside the register because
most of the clock toggles are not needed. That is, driving the clock to this register when the data
is not changing does not change the circuit behavior.

One way to construct an enable signal is by detecting actual changes on the bus. In the following
circuit, an XOR is used to determine whether the next state of each bit is the same as the previous,
and then a single N-bit OR is used to determine if any bits changed. If no bits on the bus are about
to change state, then there is no reason to enable the clock. The clock gate at the top of the
schematic safely disables the clock without allowing any glitches on the detector output to reach
the register clock:

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Examining and Implementing Power Reduction Opportunities

Figure 15.3: LNR - Circuit Diagram

For example, if the original code for which LNR is flagged is as follows:
always @(posedge clk)
q <= d;

You can generate an enable 'en' by modifying the code as shown below:
en = | (q ^ d);
always @(posedge clk)
if (en)
q <= d;

15.3.1.3. Trade-offs
A large area can be impacted by adding XORs and ORs for a wide bus. The levels of logic between
the data and the enable can also impact timing. If a change arrives late at the data inputs, it requires
some time to propagate into the enable to allow the clock through.

Several variations of this technique are used to reduce the area and delay impact:

• The first variation is using human knowledge to locate an existing enable. For example, if a
register is only active in one particular mode, there is no need to build a bus-specific enable.
You can use the mode control signal as the enable.
• A second variation involves selecting bits to detect changes. PowerArtist selects bits based
on an activity threshold, which may result in the selection of only a few bits out of a bus.
Depending on the actual activity of the bus, it may be profitable to enable fewer of the bits,
or it may be simpler to understand the result if more of the bits are enabled.

15.3.1.4. Shared LNR

Reduction PowerBots usually consider a single instance as a candidate. In some cases, there might
be some small registers, with bit-width smaller than the value of 'reduction_min_bit_width'.
These small registers are skipped by PowerBots, but the LNR PowerBot has a variant 'Shared LNR'.
This variant groups small registers in the same hierarchical module to obtain additional power
savings.

In shared LNR analysis, small registers in the same hierarchical module are grouped based on their
power savings.

This PowerBot is enabled by default. To disable it, specify the following command:
ReducePower -skip_reduction_list slnr

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 Power Reduction PowerBots

15.3.2. Low-activity Enabled Registers (LER)

Definitions
Low-activity Enabled Register (LER) is a variant of the LNR PowerBot. The difference between LNR
and LER is that LER candidates have existing enables. The LER PowerBot tries to generate an LNR style
enable signal to intersect with and existing enable. This improves the dynamic CGE and saves more
power.

15.3.2.1. Usage
The LER PowerBot is enabled by default when you perform a reduction run (using the 'ReducePower'
command) and works in a vectorless mode. To disable it, specify the following command:
ReducePower -skip_reduction_list ler

15.3.2.2. Reporting Results

Improved LER Help Text in Reduction GUI
The help text reported for LER reduction technique in the reduction GUI and the detailed CSV report
generated by the 'ReportReductions' command is modified to show:

• The XOR of register input and output nets, making it more readable. Additionally, bus nets
in the LNR/LER help text are merged into a bus operation, instead of a bit operation. Consider
the sample updated help text:
// Generate enable signal
wire myTmp;
assign myTmp = | (d[7:0] ^ q[7:0]);
// Use the above and the pre-existing enable signal to gate the register
always @(posedge clk)
if (myTmp && (pre-existing enable)) begin
q[7:0] <= d[7:0];
end

• The pre-existing enable condition instead of the inferred names from the enable condition.

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Examining and Implementing Power Reduction Opportunities

15.3.2.3. Shared LER

Similar to Shared LNR, this is a variant of LER.

This PowerBot is enabled by default. To disable it, specify the following command:
ReducePower -skip_reduction_list sler

15.3.3. Datapath Operator Isolation (DOI)

Design Parts: datapath

When there is a clock enable in the RTL and there are datapath operators such as a 'multiply' or
an 'add' in front of the enabled register, the Datapath Operator Isolation (DOI) PowerBot estimates
the power savings gained from latching the datapath inputs when the output is not read.

Definition
The following schematic shows datapath operators going into a register that has an explicit clock
enable. When the enable is off, the datapath output is ignored. In this situation, the datapath is
consuming power to compute a result that is not used:

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 Power Reduction PowerBots

Figure 15.4: DOI - Schematic Diagram 1

15.3.3.1. Usage
The DOI PowerBot is enabled by default when you perform a reduction run (using the 'ReducePower'
command) and works in a vectorless mode.

To disable the PowerBot, specify the following option:

ReducePower -skip_reduction_list doi

15.3.3.2. Implementation
The following schematic shows a way to reduce power for the datapath operators. When the
datapath result is not used, the datapath is kept quiet by isolating it from its inputs with a latch.
The power savings are due to lowered activity in the datapath operators:

Figure 15.5: DOI - Schematic Diagram 2

15.3.3.3. Trade-offs
When this change is made, the power dissipated in the datapath goes down. There is a penalty
due to the latches that are added. These latches consume a small amount of power and area, and
they also add some delay to the combinational path. If the datapath is on a critical path, this extra
delay might not be acceptable.

15.3.4. Local Explicit Clock Enable (LEC)

Design Parts: control, clock, datapath

For clock enables already present in your HDL, the Local Explicit Clock Enable (LEC) PowerBot estimates
the power savings gained by using a gated clock rather than a mux in a feedback loop.

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Examining and Implementing Power Reduction Opportunities

Definition
The following schematic shows a local explicit clock enable. The 'q' output is updated on a rising
edge of 'clk', but only when the signal 'en' is high:

Figure 15.6: LEC - Schematic Diagram

Examples
• Verilog Example:
module enable_example (d, clk, en, q);
input d, clk, en;
output q;
reg q;
always @(posedge clk)
if (en)
q = d;
endmodule

• VHDL Example:
entity enable_example is port (
d, clk, en: in std_logic;
q: out std_logic);
end enable_example;
architecture rtl of enable_example is begin
process (clk) begin
if (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;

15.3.4.1. Usage
By default, this PowerBot simulates clock-gating by building a cell from your power libraries using
an 'AND' and a 'LATCH' as a clock gating cell. You get this behavior if you do not specify clock
gating commands in the Tcl script of the reduction analysis runs.

To perform clock gating using an ICGC, apply the following guidelines:

• Use the 'SetClockGatingStyle' command to specify your selected clock gating cell type.
Note: The LEC PowerBot ignores the '-min_bit_width' option.

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 Power Reduction PowerBots

• Use 'SetClockBuffer' commands to define the clock buffers to build a buffer tree. The tree is
used to reduce the load on the gated clock output of the ICGC. If 'SetClockBuffer' commands
are not specified, then buffer tree is not created.
• Do not specify 'SetClockNet' commands. Or specify the '-gate_clock false' option with
each 'SetClockNet' command to ensure that the LEC PowerBot is not disabled. Consequently,
you must be careful when using the same clock file for the LEC PowerBot while you are doing
power analysis with automatic clock gate prediction.

Note: This PowerBot also works in vectorless mode.

15.3.4.2. Implementation
Logic synthesis implements the circuit with a '2:1 mux' or a 'muxed D flip-flop' if one is available in
the target technology. If the enable is low for a significant percentage of the circuit operation, and
if 'd' and 'q' are multi-bit buses, then a substantial amount of power dissipated by the clock driver
is wasted. That is, driving the clock to this register when the enable is low does not change the
circuit behavior.

Another way to implement this circuit is to gate the clock. Replacing the clock input to the flip-flop
with an AND gate whose inputs are the clock and the enable is not safe. Consider a situation when
the clock is high and transitions occur on the enable, edges appear on the register clock input,
possibly causing incorrect circuit behavior.

To avoid these edges, an 'Integrated Clock Gating Cell' (ICGC) must also be inserted so that when
the clock is high, activity on the enable is not transferred to the clock input. The following schematic
illustrates the needed additional circuitry:

Figure 15.7: LEC - Circuit Diagram

Many logic synthesizers have the ability to insert ICGCs into your logic and automatically replace
the feedback multiplexor. Use PowerArtist to predict that style of clock gate insertion using the
'SetClockGatingStyle' command in the clock file.

If you want to control clock gate insertion, then you have two choices:

• Manually insert the clock gates.

The following two code fragments illustrate the required changes for Verilog and VHDL, each
showing the instantiation method where it is assumed that the required gate is 'CLKGATE':
– Instantiated Verilog Code Sample:
module enable_example (d, clk, en, q);
input d, clk, en;
output q;
reg q;
wire local_clk;

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Examining and Implementing Power Reduction Opportunities

CLKGATE cg1 (clk, en, local_clk)

always @(posedge local_clk)
q = d;
endmodule

– Instantiated VHDL Code Sample:

architecture rtl of enable_example is
component CLKGATE ...
signal local_clk, en: std_logic;
begin
cg1
CLKGATE (clk, en, local_clk);
process (local_clk) begin
if (local_clk'event and local_clk = '1') then
q <= d;
end if;
end process;
end rtl;

• Constrain the synthesizer to clock gate only the chosen registers.

Caution
This type of zero-delay adjustment of the clock can lead to simulation differences, especially in
VHDL. Consider register 'A' driving register 'B', where 'B' has a clock gate. In the original non-gated
version, 'A' and 'B' are activated on the same simulator delta, and data requires two clock cycles to
flow from the input of 'A' to the output of 'B'. In a zero delay environment, if 'B' is gated, the clock
to 'B' appears one delta after the clock to 'A', and data may accidentally flow from the input of 'A'
to the output of 'B' in a single cycle only.

To avoid this problem, use a unit delay environment, where each assignment includes a delay:

• In Verilog:
q = #1 d;

• In VHDL:
q <= d after 1 ps;

15.3.4.3. Trade-offs
When this type of design change is made, the power dissipated on the clock edge goes down. Part
of this power decrease occurs in the register itself and part occurs in the clock driver. At the same
time, the new clock gating circuitry consumes power. PowerArtist estimates the power due to both
these factors. If the power of the new circuit is higher, no change is suggested. In general, for mostly
active enables and small bus widths, the power of the clock gating circuitry outweighs the possible
savings. PowerArtist suggests this change usually for wide registers that are frequently disabled.

Other trade-offs involve area and timing. The area trade-off is similar to the power trade-off. The
clock gating circuitry is added, but offset by the savings in either a simple flop instead of the larger
mux-ed flop, or the removal of the mux for libraries without mux-ed flop cells. The key trade-off is
delay. This design change can actually improve the delay along the path of data, because the mux
is removed. However, it can impact the clock distribution.

Advanced software tools should be able to incorporate this logic into the clock tree with little
impact on clock skew. However, there is a risk that some clock buffer insertion methods might not

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 Power Reduction PowerBots

be able to hide the effect, resulting in additional clock skew. Ansys recommends that you perform
static timing analysis after clock buffer insertion to ensure that timing problems do not appear.

15.3.4.4. Reporting Results

The power savings achieved due to the LEC PowerBot are reported in the following two ways:

• Text Report

The LEC PowerBot reports the following as savings achieved in the reduction report:
– Mux Instance savings include:
savings due to '2-1 multiplexor removal' and
savings in the power of the net from the mux to data pin of the register
– Register Instance savings include the gating logic power. This is different from the
'ReducePower' flow where it becomes a part of the clock power of the design.
– Top Component savings include the savings in the clock power and the load power.
– The power due to the load on the output of the inserted ICGC is considered as part of the
clock power of the design.

• Graphical User Interface

The graphical user interface displays the following information for every savings opportunity
reported by the LEC PowerBot:
– Parent Module

Is the name of module containing the clock-gated register.

– Enable Net

Is the clock-enable signal name. If it is a user-defined RTL net name, then it is the boolean
expression showing the enable expression.
– Clock Net

Is the clock signal name.

– Duty Cycle

Is the ratio of the new clock duty cycle to the original clock duty cycle.
– Gated Nets

Are the gated register net names.

– Clock Gate Used

Is the cell name and the library containing the chosen ICGC.

15.3.5. Split Memory Words (SMW)

Design Parts: memory

In today's memory circuits, a memory array is usually partitioned into several segments. Only one
segment of the array is active at a given point in time, thereby reducing the overall power consumption
of that memory. This means that only a few addresses in memory are frequently accessed. Therefore,

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splitting these frequently executed sequences of memory references into smaller-sized, low-power
memories reduces the total energy of the memory.

The Split Memory Words (SMW) PowerBot is designed to reduce dynamic memory power by splitting
a memory into smaller symmetrical parts and asymmetrical parts when the 'ReducePower
-reduction_max_memory_split' command is set to an odd value. To be considered as a potential
candidate for memory splitting, the smaller memories must have identical power rail definitions as
the original large memory. The following schematic shows a memory with a large number of words
split into two smaller memories, each with half the number of words:

Figure 15.8: Split Memory Words - Schematic Diagram

Calculations
• Power Calculations
If the dynamic power of the full-size memory is 'Fd' and static power is 'Fs' (static), the total power
'Pf' of the full-size memory is:

Pf = Fd + Fs

The SMW PowerBot looks for a memory in the '.lib' that is half the size of the original memory
and calculates the dynamic ('Hd') and static ('Hs') power of this half-size memory. It assumes that
only one of these half-size memories is active at any time so that the total power 'Ph' of both
memories is:

Ph = Hd + 2 * Hs

This means that the total power of both memories is one half-size dynamic power plus two times
the leakage of the half-size memory. If the SMW PowerBot does not find a half-size memory in the
'.lib', it uses the values defined using the 'DefineHalfMemScalingFactor' command to scale the
static and dynamic power values of the full-size memory to approximate a suitable 'Ph'.
PowerArtist also accounts for the power consumed by the additional circuitry 'Pc'. The total power
'Pt' consumed by the additional circuitry and the split memories 'Ph' is:

Pt = Ph + Pc

SMW accepts the memory substitution only if 'Pt < Pf'.

• Area Calculations
If SMW finds the half-size memory in the '.lib', the new memory area is '2 * the area of
the half-size memory'. The total area includes the area of the smaller memories plus the
area of additional instances like a MUX, gates or a register, which are a part of the additional circuitry
that replace the original memory instance. If SMW does not find the half-size memory in the '.lib',

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the area penalty scaling factor (defined using the 'DefineHalfMemScalingFactor' command) is
used to approximate a suitable new area value.
• Memory Architectures
The power of a read or write to the half-size memory is far less than the power of a read or write
to the full-size memories. Even though the same number of reads and writes are occurring in the
new architecture, the power is reduced because each read or write is on only one of the smaller
memories.

15.3.5.1. Implementing Memory Partitioning/Splitting

The following criteria is used to partition a memory:

• The activity on the Most Significant Bit (MSB) and the Least Significant Bit (LSB) of the address
bus.
Of the MSB or LSB of the address bus, the one with the lower activity is selected. In
Figure 15.8: Split Memory Words - Schematic Diagram (p. 288), bit '0' can be either the MSB
or LSB of the address bus.
The selected MSB/LSB address bit should be in a stable state (that is, the signal maintains
the state of '0' or '1') for more than a specified number of clock cycles (as defined by the
'DefineMemActivityThreshold' command).
• The state of the chip enable must be active.
• There must be some activity on other address bits of the memory.

To reduce power, SMW splits memories in a tree-like manner. It internally performs analysis for all
combinations of memory splits. By default, the 'ReducePower' command splits the original memory
into two half-size memories. You can increase the number of splits allowed using the
'-reduction_max_memory_split' option. If you set this option to '3', then one of the half-size
memories is further split into two parts, resulting in a total of three smaller-size memories.

For example, if you set '-reduction_max_memory_split to '3' for a memory with an original
size of '2048x32', it is split into the following smaller-size memories: '1024x32', '512x32', and
'512x32'. SMW tries two possible split combinations and recommends the one that results in the
maximum power reduction. It also reports the area overhead, due to the placement of instances
and additional nets in the added circuitry, associated with the recommended split.

15.3.5.2. Usage
Use the following commands to run reduction using the SMW PowerBot:

1. The SMW PowerBot is disabled by default. To enable it, specify the following command:
ReducePower -skip_reduction_list {}

Note: To disable other PowerBots and the SMW PowerBot, you need to list all of them explicitly:
ReducePower -skip_reduction_list {smw odc}

2. Create a '.tcl' script that includes the following commands:

• Use the 'DefineMemory' command to define your memory properties.

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• Use the 'DefineHalfMemScalingFactor' command to define scaling factors for memory

splitting. This is optional and required only if you do not have a predefined memory
library that includes a variety of memory sizes.
• Use the 'DefineMemActivityThreshold' command to specify the number of clock cycles
during which a memory (of a given type and size) must maintain a stable state ('1' or
'0') for memory splitting. In addition to the MSB/LSB of a memory address maintaining
a stable state, some activity must also happen on other address bits. Therefore, this count
is the count of clock cycles where there is activity on other address bits. For example, if
the MSB/LSB address is in state 0 for 100 clock cycles, but in those 100 cycles, there is
activity on other address bits for 10 cycles, the threshold value should be set to 10.

Note: If you do not specify the last two commands, PowerArtist uses their default values.

3. Create a '.tcl' script that includes the 'ReducePower' command with the appropriate options
specified. Two critical options are:
• -activity_file
Specifies the file containing your simulation vectors (VCD or FSDB).
• -synlib_files
Specifies your Liberty libraries. You should specify memories of varying sizes. In absence
of half-size memories, PowerArtist computes a half-size memory using the value of
'DefineHalfMemScalingFactor' (specified in step #2).

4. Run the Elaborate' command to generate the scenario file.

5. Source the '.tcl' script created in step #2.

6. Run/source the reduction script created in step #3. Internally the script performs the following
steps:
a. Analyzes the simulation input file and generates a '.gaf' file by using the information in
the 'DefineMemory' commands to:
• Monitor the clocks of all recognized memory instances in your design.
• Collect a variety of data for your memories.
• Write statistics on your memories into a side Tcl file ('.stcl'), which is read in the next
step. SMW entries in the '.stcl' file begin with 'splSMWLint'.
The '.gaf' file is required because memory splitting happens only when the memory
activity profile indicates that a particular memory instance is a candidate for memory
splitting. 'ReducePower' then runs the SMW PowerBot, along with the other PowerBots,
with the parameters you specified in step #2.
b. Performs power reduction analysis:
• Reads the data from the '.stcl' file you created in step #6.1.
• Identifies memory splitting opportunities.
• Calculates power savings based on the memory splitting opportunities.
• Writes reduction data into a text report and the power database.

7. Review the reduction data either by reading the text report or viewing it in the 'Simple Reduction
Viewer.

8. Run subsequent 'ReducePower' commands with the '-use_existing_gaf true' option.

This option tells PowerArtist not to re-run the GAF generation process, thereby reducing the

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run time. You can apply different combinations of the SMW-related parameters for each reduction
run to see the effects of different types of memory splitting. These parameters include:
• '-max_mem_split <integer>' option
• 'DefineHalfMemScalingFactor' command
• 'DefineMemActivityThreshold' command

15.3.5.3. Trade-offs
From an area and layout perspective, this power reduction technique can increase the routing
congestion. Since memories tend to be large and often do not allow routing above them, increasing
the number of memory blocks in the design can make the routing more difficult.

From a delay perspective, the mux on the output adds some delay to the path from address change
to data output. However, the actual memory access time for the smaller memory decreases. Generally,
the access time savings is more than the delay of a mux, so the path becomes faster. However, if
this path is timing critical, you should review the change for its impact on timing.

15.3.5.4. Understanding the Output of the SMW PowerBot

The SMW PowerBot automatically generates a text file named 'smw.reduction.analysis.red'.
This file reports SMW reduction information for all possible memory split combinations. It contains
information for all memory instances in the design that are candidates for splitting. If a memory is
a good candidate for a split, the following note:
Power saved. Selected as a reduction opportunity.

appended to the end of the Total Power line. If not, you will see the following note:
No power saved. Not selected as a reduction opportunity.

A sample 'smw.reduction.analysis.red' file is shown below:

SMW Reduction Report
--------------------

SMW analysis for memory instance: 'top.core1.r1.dpmem.m0b.m1'

------------------------------------------------------------

1. Original Memory Cell Name : DP256x32

Original Memory Size : 256x32
Original Memory Inst Total Power : 2.51mW
Original Memory Inst Total Area : 161029
Original Memory Library Name : Memories
Chip Enable Pin Name : CENB
Number of Memory Splits : 2
Memory Activity Threshold : 1
Total Power : 2.49mW (Power saved. Selected as a reduction opportunity)
Total Dynamic Power : 2.27mW
Total Static Power : 217uW
Total Area : 264445
Design Net Area : 18760.1
Design Insts Area : 245685

Memory Clock Specific Details:

------------------------------
Index Clk Port Name Clk Polarity Avg Cnt Addr MSB Name Clk Net Name Addr MSB Net Name
==============================================================================================
1 CLKB Pos Edge 1.0 33 AB[7] CLKB1 AB1[0]
2 CLKA Pos Edge 1.0 28 AA[7] CLKA1 AA1[0]

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----------------------------------------------------------------------------------------------

In the above table,

'Avg' refers to average consecutive cycles (above threshold) for which memory is accessed from
either half.
'Cnt' refers to total num of such cycles (above threshold) mentioned above.

Split Memory Details:

---------------------
Index Split Mem Cell Memory Size Enable Expression
==============================================================================================
1 DP128x32 128x32 CENB1 | ~AB1[0]
2 DP128x32 128x32 CENB1 | AB1[0]

SMW analysis for memory instance: 'top.core1.r1.dpmem.m0b.m2'

------------------------------------------------------------

2. Original Memory Cell Name : DP256x32

Original Memory Size : 256x32
Original Memory Inst Total Power : 2.51mW
Original Memory Inst Total Area : 161029
Original Memory Library Name : Memories
Chip Enable Pin Name : CENB
Number of Memory Splits : 2
Memory Activity Threshold : 1
Total Power : 2.49mW (Power saved. Selected as a reduction opportunity)
Total Dynamic Power : 2.27mW
Total Static Power : 217uW
Total Area : 264445
Design Net Area : 18760.1
Design Insts Area : 245685

Memory Clock Specific Details:

------------------------------
Index Clk Port Name Clk Polarity Avg Cnt Addr MSB Name Clk Net Name Addr MSB Net Name
==============================================================================================
1 CLKB Pos Edge 1.0 33 AB[7] CLKB2 AB2[0]
2 CLKA Pos Edge 1.0 28 AA[7] CLKA2 AA2[0]
----------------------------------------------------------------------------------------------

In the above table,

'Avg' refers to average consecutive cycles (above threshold) for which memory is accessed from
either half.
'Cnt' refers to total num of such cycles (above threshold) mentioned above.

Split Memory Details:

---------------------
Index Split Mem Cell Memory Size Enable Expression
==============================================================================================
1 DP128x32 128x32 CENB2 | ~AB2[0]
2 DP128x32 128x32 CENB2 | AB2[0]

Note: The formatting in this sample report is modified to fit the available area.

Example of Additional Circuitry

In this example, additional circuitry is introduced when the original memory 'ra2shd_4kx32' is
split into two smaller 'ra2shd_2kx32' memories:
module submod (
OA,IA,AA,CLKA,CENA,WENA,
OB,IB,AB,CLKB,CENB,WENB
);
parameter DATMAX = 31;
parameter ADRMAX = 11;
output [DATMAX:0] OA, OB;
input [DATMAX:0] IA, IB;

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 Power Reduction PowerBots

input [ADRMAX:0] AA, AB;

input CLKA, CLKB;
input CENA, CENB;
input WENA, WENB;

wire [204:0] net;

reg sel1, sel2;

assign net[0] = ~AA[0];

assign net[1] = net[0] | CENA;

assign net[2] = AA[0] | CENA;

always @ (posedge CLKA) begin

sel1 <= AA[0];
end

assign net[4] = ~AB[11];

assign net[5] = net[4] | CENB;

assign net[6] = AB[11] | CENB;

always @ (posedge CLKB) begin

sel2 <= AB[11];
end

ra2shd_2kx32 mem1(.CLKA(CLKA), .CENA(net[1]), .WENA(WENA), .AA(AA[11:1]), .DA(IA),

.QA(net[41:10]), .CLKB(CLKB), .CENB(net[5]), .WENB(WENB), .AB(AB[10:0]),
.DB(IB), .QB(net[73:42]));

ra2shd_2kx32 mem2(.CLKA(CLKA), .CENA(net[2]), .WENA(WENA), .AA(AA[11:1]), .DA(IA),

.QA(net[107:76]), .CLKB(CLKB), .CENB(net[6]), .WENB(WENB), .AB(AB[10:0]),
.DB(IB), .QB(net[139:108]));

assign net[171:140] = (sel1) ? net[41:10] : net[107:76];

assign net[203:172] = (sel2) ? net[73:42] : net[139:108];

assign OA = net[171:140];
assign OB = net[203:171];

endmodule

To implement this change, replace the single memory with two memories, each having half the
number of words. The enable expressions identified in the 'smw.reduction.analysis.red'
file define the select signal that operate as a bank select. This bit should also be used as the select
input to a new multiplexer on the memory outputs. This multiplexer selects the appropriate memory
bank.

15.3.6. Gate Memory Clock (GMC)

Design Parts: memory

The GMC (Gate Memory Clock) reduction technique identifies redundant memory accesses. GMC also
identifies redundant write cycles for memories with byte write enables. The byte write enable pins
mask one or more bytes when writing data to the memory. In certain SRAMs, these pins can be
different from the standard Write Enable (WE) pin.

The GMC PowerBot performs one of two methods of power reduction for memories. It first applies
Method 1 (p. 294) and then applies Method 2 (p. 294).

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Method 1
For this method, GMC determines a way to disable the clock in a redundant read/write access mode.
A read/write access is redundant when:

• The read/write data at the memory output does not change, or

• The read/write data is not observed in the downstream cone of logic. This is an example of
an observability-don't-care condition identical to what the ODC PowerBot finds for registers.

For this method to apply, the memories must fit into one of the following architectures:

• Single clock/multi port SRAM

• SRAMs with bit-write support
• Single port register file
• A two-port register file with memory and write enables
• ROM

In addition, a memory must meet the following constraints:

• At least one clock must support a read interface.

• The memory must be synchronous.
• ROMs must be single port
• The memory Liberty model has the required dynamic energy arcs.

If the cell does not meet these criteria, this method is not applied. GMC attempts Method 2 (p. 294).

Method 2
For this method, GMC examines your Liberty files and locates models that lack internal clock gating.
It then turns off the clock when the memory is not accessed. This happens when the memory select
signal is not asserted.

Setting the Type of Memory Gating

PowerArtist can gate memories using either an integrated clock gating cells (ICGCs) or a discrete
circuit. Most applications use explicit ICGCs, which you can define in one of two ways:

• You can use the 'SetMemoryGatingCell' command to define a list of cells from specific libraries
that should be used.
• If you do not specify one or more 'SetMemoryGatingCell' commands, PowerArtist uses the
ICGCs identified by any 'SetClockGatingStyle' commands that you specify.
The ICGC are used as part of the algorithms to estimate power savings and to rewrite as
instantiated cells in your RTL.

If you do not specify either 'SetMemoryGatingCell' or 'SetClockGatingStyle', PowerArtist uses a

discrete gating circuit for estimation and rewrite.

15.3.6.1. Usage
Use the following process to run power reduction using the GMC PowerBot:

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1. Run the 'Elaborate' command to generate the scenario file.

2. Use 'DefineMemory' commands to define critical ports for the memories used in your
design.

3. Optionally, use 'SetMemoryGatingCell' commands to define the clock gating cells to use
for memory clock gating. Alternatively, you can specify the 'SetClockGatingStyle' command
to define your integrated clock gating cells (ICGCs).

4. Set options for the 'ReducePower' command. The two critical options are:
• Specify a list of memory cell names that you do not want to analyze:
-reduction_dont_touch_modules {module_name1 module_name2 ...}

• Set the following option to 'true' if you do not want GMC to generate address
stability checking logic:
-reduction_memory_disable_edge_detection <true | false>

The detection circuit created is similar to the XOR-OR based circuit used by the
Low-Activity Non-Enabled Register (LNR) (p. 279) PowerBot. In addition, registers are
added to remember the previous address.

5. Run the 'ReducePower' command. Internally this performs the following steps:

a. Analyzes your simulation input file by using the information in your 'DefineMemory'
commands to:
• Monitor the clocks of all recognized memory instances in your design.
• Collect a variety of data for your memories.
• Write statistics on your memories into a side Tcl file ('.stcl'), which is read
in the next step.

b. Performs the power reduction analysis:

• Reads the data from the side Tcl file.
• Identifies power reduction opportunities.
• Calculates power savings using the ICGCs specified using the
'SetMemoryGatingCell' or 'SetClockGatingStyle' commands.
• Writes reduction data into a text report and the power database.

6. Review the reduction data either by reading the text report or viewing it in the 'Simple
Reduction' dialog as a potential GMC opportunity.

15.3.6.2. Calculations Performed

The power saving calculations depend on the memory architecture found by the GMC PowerBot.
A redundant memory read analysis performs the following critical calculations:

• Estimates the power saved by implementing the potential reduction.

• Estimates the penalty power to implement the potential reduction. This includes the circuitry
needed to generate the enable, the clock tree for the additional registers required for an
address line stability check, and clock gating circuitry
• Estimates area penalty.

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If the memory architecture does not meet the criteria for a redundant memory read analysis, as
described earlier, GMC predicts power savings by gating the memory clock when the memory is
inactive. In this case, the savings are the internal power consumption due to the clock switching
in the memory disabled state. If power is saved, then the memory cell enable signal(s) are used to
gate the actual clock signal(s). The enabled clock(s) then drive the clock input(s) of the memory.

Reduction is performed using the ICGCs specified using the cells defined by the
'SetMemoryGatingCell' or 'SetClockGatingStyle' commands. If these commands are not specified,
the gating logic is modeled using a more traditional circuit consisting of a latch and an 'AND'.

15.3.6.3. Reporting Results

A text report named 'mpl.analysis.red' is generated to report reduction opportunities identified
by the GMC technique. The report is generated by default if the 'DefineMemory' command is
specified in the power reduction flow.

Conditions
Note the following conditions:

• The report is generated if the 'DefineMacroMode' and 'SetMacroPowerLinterReportFile'

commands are specified.
• If 'DefineMemory' is specified, but 'DefineMacroMode' is not specified, then PowerArtist
internally creates different modes with appropriate port information for the memory cells
and generates the report.
• If both 'DefineMacroMode' is specified, but 'DefineMemory' are specified for the same
memory cell, 'DefineMacroMode' takes precedence and the default setup of the memory
cell is overwritten.
• If both 'DefineMacroMode' is specified, but 'DefineMemory' are specified, but for different
memory cells, a combined report is generated.

Notes:

• In all the above cases, the name of the report depends on the filename specified by the
'SetMacroPowerLinterReportFile' command. If it is not specified, the report is saved by
default as 'mpl.analysis.red'.
• Refer to the PowerArtist Reference Manual for details of these commands.

A sample report is shown below:

<snip>
1. Summary

1.1 Redundant Clock Cycles

-------------------------------------------------------
Redundant Total Pin Mode Instance
Cycles Cycles Name Name Name
-------------------------------------------------------
9 15 clk disabled top.mem01.memInst
-------------------------------------------------------

1.2 Redundant Input Toggles

2. Detailed Report

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Instance Name : top.mem01.memInst

Cell Name : sram_123
Library Name : sram_123_SVT
Mode Name : disabled
When Condition : !(ce_b)
Clocked on : clk
Clock Edge : posedge
Total Clock Cycles : 15

(absolute start time, # of clock cycles)

----------------------------------------------------------------------------
Clock Pin | clk (top.mem01.memInst)
----------------------------------------------------------------------------
Redundant Period | 170ns, 9
----------------------------------------------------------------------------
Total Wasted Cycles | 9, 60%
----------------------------------------------------------------------------

Mode Name : write

When Condition : (we)
Clocked on : clk
Clock Edge : posedge
Total Clock Cycles : 7

Mode Name : read

When Condition : (we)
Clocked on : clk
Clock Edge : posedge
Total Clock Cycles : 7

For GMC analysis, you can specify enable conditions as Boolean expressions using the
'DefineMemory' command. The enable conditions are used to generate MPL reports with redundant
activity periods.

The following table shows how PowerArtist interprets lists of memory ports to create conditions
to generate the MPL report:

Associations established through Corresponding condition expressions

'DefineMemory' commands in GMC
Read Enable Ports = {r1, r2, r3, ....} Read Enable Condition (RE) = r1&r2&r3&...
Write Enable Ports = {w1, w2, w3, ....} Write Enable Condition (WE) = w1&w2&w3&...
Memory Enable Ports = {m1, m2, m3, ...} Memory Enable Condition (CS) =
m1&m2&m3&...

Note: The expressions are self-evident when specified explicitly through 'DefineMemory'.

The following table shows the relationship between modes, conditions, and input pins for memories:

Mode(s) Conditions input_pins redundant_pins

read (RE&!WE&CS) read address data input pins
write (!RE&WE&CS) write address
read_write (RE&WE&CS) read+write addresses and data
pins
disabled (!CS) all data input pins and
address

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Mode(s) Conditions input_pins redundant_pins

unknown (ME&!RE&!CS) all data input pins and
address

Note: All the mode conditions must be exclusive among themselves and complete together.

Limitation
A redundant access that spans multiple modes that are similar but not identical are not reported.
For example, a 'read+write' access at an address followed by a 'read' access at the same address is
not identified as redundant in the MPL report but is flagged by GMC.

15.3.6.4. Ignoring Test Clocks

Liberty descriptions for memory cells can lack attributes that identify the cells as memories or
identify the functionality of memory ports such as chip select, read and write enable, etc. Use the
'DefineMemory' command to augment this missing information in Liberty files which is then used
by the GMC power reduction technique. The 'DefineMemory command is enhanced to enable
GMC to skip the test clocks of memories and focus on the functional clocks instead.

To enable this enhancement, use the following command:

DefineMemory <other_options> -ignore_clk_pins { <list of clocks to be skipped> }

The '-ignore_clk_pins' option accepts one or more clock pins and regular expressions.

Note: Using this option may impact the total power reduction opportunities found through GMC
because test clocks are ignored to analyze the functional clocks of the memory.

15.3.7. Prism
Design Parts: registers

The Prism PowerBot looks for chains of registers where a register early in the chain is enabled. Registers
later in the chain are not enabled, and the enable can be used to gate later registers.

Definitions of Terms
To efficiently use the Prism PowerBot, you should be familiar with the following terms:

• Clock Gating

A power efficient implementation where register banks are disabled during some clock cycles.
The register feedback loop and the multiplexer are removed. The clock gating circuitry is
inserted into the clock path, creating a derated clock that reduces unnecessary register clock
activity.

• Gated Register

A register bank with all its bits enabled through a feedback multiplexer or its clock is driven
by an instantiated integrated clock gating cell.

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• Candidate Register

A register bank for which both the following conditions are true:
– none of its bits have a mux feedback path.
– its datapath width is greater than or equal to user-defined datapath width specified
using the 'SetDatapathWidth' command.

• Un-Gateable Register

A register bank for which both the following conditions are true:
– none of its bits have a mux feedback path.
– its datapath width is less than the user-defined datapath width. This is not the same
as the minimum bit width required for clock gating.

15.3.7.1. Usage
The Prism PowerBot uses the following flow:

1. It tries to find candidate registers in the design that are downstream to gated registers.

2. For such a candidate register, it then tries to determine if the upstream gated register
enable signal can be used to gate it.

3. It estimates power savings and penalties to determine the effectiveness of the gating.

4. It writes the results into the OpenAccess database for later viewing.

During inferencing, vectored registers are broken out into their own registers. This makes for easy
visualization of data paths. It also recognizes that data paths are often manipulated the same way
across all bits.

Prism creates enables for non-enabled registers that feed other registers downstream. Chains of
registers that had ungated registers as the first register in the chain are enabled using XOR enable
generation and all subsequent register stages use a propagated enable. This XOR enable generation
capability is the same used by the Low-Activity Non-Enabled Register (LNR) (p. 279) PowerBot. In
addition, Prism strengthens power-inefficient (weak) enables so that clocks are turned off for longer
durations saving more power. It does this by reusing existing enables of upstream registers. This
enable quality analysis is the same used by the Clock Enable Condition (CEC) Linter (p. 336) PowerBot.

Before running power reduction with Prism, you can define the analysis conditions by providing
specific inputs using the '-tcl' option or using the PowerArtist command file. You can set the
following conditions:

1. Set the data path width. As previously mentioned, a data path is a vectored signal inferred
as a register instance. You can specifically indicate how many bits wide a data path must
be before it should be considered a candidate register. You do this using the
'SetDatapathWidth' command. The default width is '8' bits.

2. Specify the names modules you do not want to analyze. To do this use the
'SetExcludeModules' command (which is similar to the 'Elaborate -black_box_modules
{string_list}' command).

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3. Control the 'min' and 'max' bit widths for XOR enable creation as part of Prism. This is
controlled using the '-min_bit_width' and '-max_bit_width' options of the
'ReducePower' command.

Registers that are not part of a Prism chain and have acceptable power savings:
• Any register < '-min_bit_width' wide are completely ignored as an LNR
opportunity
• Any register >= '-min_bit_width' are written to the reduction database as an
LNR opportunity.
• Any register >= '-min_bit_width' and <= '-max_bit_width' are automatically
accepted as an LNR opportunity in the reduction database.

The behavior of registers that are part of a Prism chain remains the same:
• Prism generates an enable for registers <= '-max_bit_width'.
• If the register is >= '-min_bit_width', Prism clock gates it.
• If the register is < '-min_bit_width', Prism does not clock gate it.

If the savings are reasonable, Prism automatically accepts the changes.

The Prism PowerBot is enabled by default when you perform a reduction run (using the
'ReducePower' command) and works in a vectorless mode. To disable the PowerBot, specify the
following option:
ReducePower -skip_reduction_list prism

15.3.7.2. Reporting Results

The 'Forward_ {$DataPathWidth}.red' file enables you to perform what-if experiments with
different datapath widths, saving the results in different '.red' files.

The Prism output is organized into the following five sections:

• Section 1: Design Summary

This section summarizes the impact that making the changes suggested by Prism have on
your design and your development schedule. It tells you the number of register bits in your
design, how many of those bits are gated and how difficult it is to make changes to reduce
power. See the following sample section for details on the information it provides.
1. Design Summary
------------------
Total number of register bits : 758
Number of gated register bits : 481
Number of gated register bits forming the head of a Prism chain : 224
Number of candidate register bits: 128
Easy bits (only gated upstream) : 32
Medium bits (no ungateable count upstream) : 32
Hard bits (everything else) : 64

• Section 2: Forward Chains

This section presents all the chains starting from the gated registers of the design. A chain
describes the gated register and the downstream candidate registers. The candidate register
description captures the following upstream counts:

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– gated count (g)

This is the number of upstream gated register links in the chain. They are sources of
enables that stand a very high probability of being useful.

– candidate count (c)

This is the number of upstream candidate register links in the chain. These have at
least one gate register upstream link.

– ungateable count (u)

The following upstream links are include in the count:

Primary inputs: If the primary input is a bus, its count is '1'.
Ungateable registers: These are ones that have no mux feedback path, have
fewer bits than required, and whose clock is not driven by a clock gate.
Complex vendor gates: A vendor gate gets counted once.
Upstream links to a candidate register that do not have a gated register link.

Consider the following forward chain sample:

G0 : top.upper.upReg.#13
-> C1(top.upper.downReg.#15) |<- 1g, 0c, 0u
-> C4(top.CReg.#15) |<- 0g, 2c, 0u
G2 : top.lower.upReg.#13
-> C3(top.lower.downReg.#15) |<- 1g, 0c, 0u
-> duplicate C4(top.CReg.#15) |<- 0g, 2c, 0u

In this example,
– There are two chains: 'G0: top.upper.upReg.#13' and 'G2:
top.lower.upReg.#13'.
The 'G#' means that 'G' is a gated register and '#' is the index number such that the
chain can be easily referred to when Prism analyzes a large block.
– The 'C1' line, which is indented below 'G1', represents 'top.upper.downReg.#15'
and it has:
'1g' means 1 gated register upstream and that is 'G0'.
'0c' means no upstream candidate registers.
'0u' means no upstream ungated registers.
– Similarly, 'C3' has 'G2' as its only upstream dependency.
– Lastly, 'C4', represents 'top.CReg.#15' and it has 2 upstream candidate
dependencies: 'C1' and 'C3'. So, unless 'C1' and 'C3' are gated, it cannot be gated.

• Section 3: Register Details

This section presents information about the participating instances in the chains described
in 'Section 2'.

For a 'G-type (gated)' instance, the report tells you its width, clock, and enable. Consider
the following detailed sample data for a gated register:
G5: core1.s1.#646
-----------------
Register core1.s1.wdtmr[0:31] is in module stats

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Width: 32
Clock Net: top.clk
Local Clock: clk
Enable Net: top.core1.en_wdtmr, Local Expression: en_wdtmr
Clock Enable duty: 1, Optimal: 0.0512821
Percent clock-gated: 0%, Optimal: 94.8718%
CDC: false
It drives 1 candidate registers in 1 module

For this example, PowerArtist provides the following information:

– Register

The full path to the register and the module in which it is defined - 'G5:
core1.s1.#646'.

– Width

The number of bits in the register, which is '32'.

– Clock Net

The full path name to the register clock net - 'top.clk'.

– Local Clock

The net name of the clock using its local scope name so you can find it more easily
in the source file - 'clk'.

– Enable Net

The full path to the enable net 'top.core1.en_wdtmr' and the local expression
for this enable net is 'en_wdtmr'.

– Clock Enable Duty

These are the 'normal' and 'optimal' duty cycles of the enable signals. The normal
duty cycle is the percentage of time the existing enable is at '1'. The optimal value
is calculated when the data inputs to the register are changing and algorithmically
determining how long the enable must be '1' to ideally match the data changes. In
this example, the normal duty cycle is '1' and the optimal is '0.0512821'.

– Percent Clock Gated

These are the 'normal' and 'optimal' clock gating percentages. This represents the
percentage of clock cycles the clock is disabled. The optimal is calculated based on
the percentage of clock cycles that data changed and the register is enabled. In this
example, the normal value is '0%' and optimal value is '94.8718%'.

– CDC

The value 'false' means this register does not cross clock domains and it is in one
clock domain. The value 'true' would mean that the register is in more than one
clock domain.

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– For this instance, the last line in the report says that there is only one upstream
enable.

For a 'C-type' instance, the report tells you its clock and the enable information that can
be used to gate the clock of the instance. It also tells you the bits of the data path that can
be gated. Consider the following sample data for a 'C-type' instance:
C10: core1.s1.#645
-----------------
Register core1.s1.dout[0:31] is in module stats
Width: 32
Clock Net: top.clk
Local Clock: clk
Clock Enable duty: 1, Optimal: 1
Percent clock-gated: 0%, Optimal: 0%
CDC: false
It could be gated by OR'ing 5 enable(s).
5 enables are available locally.

The information given for this C-type instance is similar to that given for the gated register.
The details for instance 'C10: core1.s1.#645' indicate that it can be gated by OR'ing
5 enable(s), which are available locally.

• Section 4: Reduction Report

The reduction report summarizes each opportunity from a power savings point of view.
Consider the following sample report:
Analysis type = Normal

Reg Power Saved Total Saved Reg Saved Clock Ideal Reg Ideal Clock Instance Name
--------- ----------- --------- ----------- --------- ----------- -------------

16.2uW -4.92uW -592nW -4.33uW 0W 26.9uW core1.s1.#645(C10)

16.9uW -4.05uW -591nW -3.46uW 0W 27.7uW core1.s1.#644(C11)
78.7uW 124uW 68.5uW 56uW 69.1uW 56.3uW core1.p1.#1847(C36)

Analysis type = Optimal

Reg Power Saved Total Saved Reg Saved Clock Ideal Reg Ideal Clock Instance Name
--------- ----------- --------- ----------- --------- ----------- -------------

16.2uW -4.92uW -592nW -4.33uW 0W 26.9uW core1.s1.#645(C10)

16.9uW -4.05uW -591nW -3.46uW 0W 27.7uW core1.s1.#644(C11)
78.7uW 124uW 68.5uW 56uW 69.1uW 56.3uW core1.p1.#1847(C36)

The columns in this report are described below:

– Reg Power: Reports the power of the register bits before clock gating.
– Saved Total: Reports the total power (register + clock - penalty) saved by gating the
clock to the register.
– Saved Reg: Reports the register power saved by gating the clock to the register. It
includes the penalty due to enable generation and propagation.
– Saved Clock: Reports the clock tree power saved by gating the clock to the register.
It includes the gating circuitry penalty.
– Ideal Reg: Reports the register power saved by gating the clock to the register. It
does not include the penalty due to enable generation and propagation.
– Ideal Clock: Reports the clock tree power saved by gating the clock to the register.
It does not include the penalty due to the gating circuitry.

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This section is categorized by analysis type:

– Normal: This section represents the power savings you can achieve given the
simulation vectors used to perform the reduction analysis.
– Optimal: This section represents the power savings you can achieve if your enable
was 'optimal'.

You can switch between these values in the Prism dialog in the PowerArtist GUI.

• Section 5: Cumulative Savings

This section provides the cumulative power savings using existing enables and new enables.
It also is categorized by analysis type: Normal and Optimal. A sample is shown below:
5. Cumulative Savings
---------------------

Analysis type = Normal

Using existing enables : 0W

Using new enables : 124uW

Analysis type = Optimal

Using existing enables : 0W

Using new enables : 124uW

15.3.8. Observability Don't Care (ODC)

Design Parts: registers

The Observability Don't Care (ODC) PowerBot generates enable signals by examining the topology
of your circuit and determining the conditions under which the outputs of your registers are not
observable by downstream registers. These conditions are then used as clock enable signals on the
upstream register. Depending on your design, this may save a significant amount of dynamic power
at the cost of increased area and slight timing impacts (see Trade-offs (p. 306)).

15.3.8.1. Usage
The Observability Don't Care (ODC) PowerBot goes through the following process.

1. Locates register banks that are not clock gated. These are the candidate registers.

2. Locates all the registers in the downstream cone of logic, if the candidate register meets
user supplied constraints.

3. Locates all 2-1 muxes, unencoded muxes, and tri-states in the paths connecting a candidate
register to all downstream registers. These instances form the critical steering logic that
determines if a register output can be observed by downstream registers.

4. Examines the select lines for each steering logic instance to determine the conditions under
which the register output is not observable by any downstream register.

5. If such a condition exists, it becomes a potential enable for the candidate register. If the
signals in the enable expression are all direct outputs of registers and not boolean
combinations of other signals, this means that the enable signal can easily be made available

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'one clock cycle earlier' with no penalty to precompute the logic. If the signals do not meet
this 'no precompute required' constraint, the opportunity is discarded as a potential ODC
candidate.

6. If you are performing ODC analysis with 'ReducePower -reduction_topology true',

then it automatically selects the candidate register and records it in the power database
('.pdb'). Otherwise, it computes the power savings and power penalties to determine if
the opportunity ultimately save power. If it does save power, it automatically accepts the
candidate register and records it in the power database.

You can review the results in the 'Simple Power Reduction' dialog in the PowerArtist GUI to see if
you agree with the automatic selections and deselect those that you do not want to accept. ODC
also recognizes opportunities for enable strengthening, but it does not automatically accept them.

This PowerBot is enabled by default and it works in the vectorless mode.

Disabling ODC
ODC is enabled by default when you perform a reduction run. You can disable ODC by doing any
of the following:

• To disable the ODC PowerBot, specify the following option:

ReducePower -skip_reduction_list odc

• To exclude all clock-related PowerBots, specify '-reduction_classes' and exclude the

'clock' class:
ReducePower -reduction_classes linter logic memory

This disables the ODC, LEC, LNR, and Prism PowerBots.

• To exclude certain registers from consideration by ODC, specify the following option:
ReducePower -reduction_min_bit_width_clocks {min_value}

The ODC PowerBot ignores the registers whose bit-widths do not meet the specified minimum
bit width constraint and the '-reduction_max_bit_width' constraint.

15.3.8.2. Understanding Power Savings and Penalty Calculations in ODC

The ODC enable expression is the OR of all the select signals along one path ANDed with the enable
expressions for all other paths. The penalty power includes:

• The boolean expression required to implement the enable signal.

• The ICGC required to implement the actual clock gate.
• Any buffers required to meet the ICGC fanout.
• Increased capacitive load on the signals in the enable expression.

The power savings comes from:

• Decreased buffers in the clock tree that were driving the candidate register bits directly.
• Reduced clock power in the candidate register due to the reduced number of times the
clock pin toggles on all the candidate register bits.

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• The savings in the cone of logic downstream from the candidate register due to fewer toggles
appearing at the outputs of the candidate register.

Area impacts primarily occur due to the extra circuitry needed to implement the new clock enable
and the clock distribution network due to the additional ICGC that is synthesized.

15.3.8.3. Trade-offs
As with any clock gating technique, there are area and delay trade-offs you have to make versus
the power saved. Area and delay may both increase due to the combinational logic that must be
added to your circuit to create the enable signal. In general, as long as the number of clock gated
bits is reasonable, which is probably 3 or more, the savings outweigh the area impact.

15.3.8.4. Handling Overlaps Between ODC and Other PowerBots

The ODC PowerBot finds some of the same registers that other PowerBots may also find. Therefore,
when an overlap occurs PowerArtist must select one PowerBot as the final implementation
methodology. In making this selection, the following rules apply:

• An ODC reduction takes priority over an LNR reduction. In general, the LNR reduction XOR
tree has a higher power penalty. Also, ODC works on register banks of any size while it is
recommended that register banks > 16 bits wide are not considered by LNR due to a high
power and timing penalty.
• Different PowerBots work together to provide more savings than you may otherwise expect.
For example, Prism may detect a large savings opportunity but there is no enable signal for
the first register in one of the chains. In such situations where Prism needs to generate an
enable, it uses LNR.
• If the register being enabled is the last register in a chain, PowerArtist compares the power
savings between the two implementation choices and chooses the one that saves more
power.

15.3.8.5. Increased Clock Gating Using Weak Enables

Stronger ODC expression enabled bits of a register can be merged with weaker ODC expression
enabled bits for more clock gating coverage. See the following two examples:

• Example 1:
module top(clk, en1_nxt, en2_nxt, d, qout1, qout2);
input clk;
input en1_nxt, en2_nxt;
input [7:0] d;
output [6:0] qout2;
output qout1;

reg [0:0] en1, en2;

reg [7:0] q;
always @(posedge clk) begin
q <= d;
en1 <= en1_nxt;
en2 <= en2_nxt;
end
wire [7:0] q_int = en1 ? q : 'b0;

reg [6:0] qout2;

always @(posedge clk) begin

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qout2 <= q_int[6:0];

if (en2) qout1 <= q_int[7];
end
endmodule

The strict and realizable ODC expression for the bits 'q[6:0]' is '(en1 == 1'b0)' and for the
bit 'q[7]' is '((en1 == 1'b0) || (en2 == 1'b0))'. The gating on bit 'q[7]' is missed
upon using these condition. Instead, the ODC expression '(en1 == 1'b0)' can be used for all
the bits 'q[7:0]'.

• Example 2:
module top(clk, en1_nxt, en2_nxt, d, qout1, qout2);
input clk;
input en1_nxt, en2_nxt;
input [7:0] d;
output [6:0] qout2;
output qout1;

reg [0:0] en1, en2;

reg [7:0] q;
always @(posedge clk) begin
q <= d;
en1 <= en1_nxt;
en2 <= en2_nxt;
end
wire [7:0] q_int = en1 ? q : 'b0;

reg qout1;
reg [6:0] qout2;
always @(posedge clk) begin
qout1 <= q_int[7];
if (en2) qout2 <= q_int[6:0];
end
endmodule

The strict and realizable ODC expression for the bit 'q[7]' is '(en1 == 1'b0)' and for the bits
'q[6:0]' is '((en1 == 1'b0) || (en2 == 1'b0))'. Upon using these conditions, 'q[7]'
is missed from clock gating because the bit width is '1'. The bit 'q[7]' can be combined with
bits 'q[6:0]' by using a weaker ODC condition '(en1 == 1'b0)'.

15.3.8.6. Optimized Enable Expression by Pruning Don't Care Variables

The size of an ODC or enable expression can be reduced by avoiding variables that do not affect
its efficiency. Reduction in the size of the clock gating expression leads to reduction in area and
power penalty. Consider the following example design:
module top(clk, d, s1_nxt, s2_nxt, qout);
input clk, s1_nxt, s2_nxt;
input [7:0] d;
output [7:0] qout;

reg [7:0] q;
reg [0:0] s1, s2;
always @(posedge clk) begin
q <= d;
s1 <= s1_nxt;
s2 <= s2_nxt;
end
wire [7:0] q1, q2;
assign q1 = s1 ? q : 'b0;
assign q2 = s2 ? q1 : 'b0;

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assign qout = q2;

endmodule

The ODC expression for the bits 'q[7:0]' is '((s1 == 1'b0) || (s2 == 1'b0))'. The
enable expression is '((s1_nxt == 1'b1) && (s2_nxt == 1'b1))'. If the simulation
activity is such that 's2' is 'always logic 1', then the ODC expression can be reduced to '(s1
== 1'b0)' and the enable to '(s1_nxt == 1'b1)'.

Pruning is disabled by default. You can enable it by using the following variable:
pa_set reduction_odc_prune_dont_care_variables true

15.3.8.7. Discrete Gating Logic Support for Enable Derivation

'ReducePower' can extract ODC conditions from the existing clock control logic in the RTL to further
gate the clock of additional flops. This feature is enhanced to recognize and use discrete clock
gating logic while extracting ODC conditions. This is especially applicable for processor designs.

You can enable it by using the following variable:

pa_set reduction_odc_clock_tree_source true

15.3.8.8. Reset Handling for Functionally-safe ODC

ODC based clock-gating a register can be unsafe under reset conditions. Consider the following
example design:
module top(clk, nrst, s_nxt, din, qout);
input clk, nrst, s_nxt;
input [7:0] din;
output [7:0] qout;
reg [7:0] q;
always @(posedge clk) begin
q <= din;
end
reg [0:0] sel;
always @(posedge clk or negedge nrst) begin
if (~nrst) sel <= 1'b0;
else sel <= s_nxt;
end
assign sel ? 'b0 : q;
endmodule

The ODC condition for bits 'q[7:0]' is '(sel == 1'b1)'. The flop 'sel[0]' has an active low
asynchronous reset ('nrst') that sets the value of the flop to '1'b0' making the flop bits 'q[7:0]'
observable. Thus, the ODC gating is not safe here.

The ODC analysis is improved to consider the observability of the flop under reset conditions in
deciding whether to gate the flop or not. Consider the following example design:
module top(clk, nreset, sel_next1, sel_next2, sel_next3, din, qout);
input clk, nreset;
input sel_next1, sel_next2, sel_next3;
input [7:0] din;
output [7:0] qout;
reg [7:0] q;
always @(posedge clk) begin
q <= din;

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end
reg sel1, sel2, sel3;
always @(posedge clk or negedge nreset) begin
if (~nerest) begin
sel2 <= 1'b0;
sel1 <= 1'b0;
sel3 <= 1'b1;
end
else begin
sel2 <= sel_next2;
sel1 <= sel_next1;
sel3 <= sel_next3;
end
end
wire [7:0] qout1 = (sel1) ? 8'd0 : q;
wire [7:0] qout2 = sel2 ? qout1 : 8'd0;
assign qout = sel3 ? 8'd0 : qout2;
endmodule

Even though the flop bits 'q[7:0]' are missing the reset, they can be safely gated using the
following enable expression:
(~sel_next1 & (sel_next2 & ~sel_next3))

15.3.8.9. Controlling ODC Precompute Logic

The ODC powerbot traces the upstream cone of ODC net to flop start-points to identify the cycle-early
version of the ODC condition, which can be used as a clock enable. The logic between the ODC
net and flop start-points is called precompute logic. The levels of precompute logic to trace in order
to identify the cycle-early enable can be specified using the following variable:
pa_set reduction_odc_max_precompute_level <integer>

The default value of this variable is '3'.

The following variable provides additional user control on the maximum number of allowed flop-start
points for precompute logic to trade-off runtime and QoR:
pa_set reduction_odc_max_precompute_inputs <integer>

By default, this limit is set to '256'. This limits the amount of precompute logic processed to improve
runtime. Reducing the value of this variable may reduce the number of ODC opportunities.

The following figure illustrates precompute levels and logic:

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There are three levels of logic and three inputs. The inputs are counted only after the final level of
logic is traced.

15.3.8.10. Reporting Results

• Text Report

The '.rpt' file contains an entry in section '4. Power Reduction by Technique' that looks like the
following file excerpt:
4. Power Reduction by Technique
===============================
<snip>
Core Core
Core Techniques Dynamic Saving Total Saving
----------------------------------------------------------------------------
Potential : 93.6uW 11.51% 93.3uW 11.35%
Observability Don't Care :
Auto-accepted : Topology based auto-accept#
Potential : 92.5uW 6.60% 92.4uW 6.54%

Note: This output was attained by performing a topology-based analysis.

• GUI - Simple Reduction Viewer

The 'Simple Reductions' dialog displays ODC opportunities. To display only ODC opportunities,
filter on 'Reductions contain ODC'. If you select 'Show Downstream Cone' on an ODC candidate
register in the 'Simple Reductions' dialog, the schematic shows the downstream cone of the
candidate register and the downstream cones of the flops that participate in the ODC expression.

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15.3.8.11. Performing Downstream Clock Tracing in ODC

Downstream tracing in the 'Simple Reductions' dialog for ODC is slightly different than the other
reductions. For the other reductions, right-clicking on an instance of a reduction and selecting
Show Downstream Cone shows the downstream cone from the instance pins in the schematic.
For ODC you can also see the upstream cones from 'steering logic'. Steering logic instances include
2-1 muxes, unencoded muxes, and tri-states. Their enable or select pins are used in ODC expressions
to generate clock gating expressions. The schematic 'zoom fits' to the gates in the steering logic
cones to focus your attention on this information. The following figure shows this for the ODC
reduction in the tutorial.

In this figure, gate '#843' is the candidate register to which ODC gating can be applied. The steering
logic is mux '#1845' and it's select pin upstream cone terminates at instance '#760'.

15.3.8.12. Displaying Cones of Logic during ODC Analysis

During ODC analysis, when displaying cones of logic from the reduction dialogs, the cone display
request occasionally contains many individual bits. These individual bits cannot be displayed
collectively, as is the case for an entire bus.

The PowerArtist GUI is enhanced so that when a cone is requested for more than a single entity,
the designer is given the opportunity to observe each bit of the operation and cancel it once they
observe enough information about the cone.

When a cone request is determined to be complex, the following dialog is displayed:

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The dialog has three choices:

• Continue with a single operation.

This choice is accurate, but potentially takes a long time.

• Display each object individually.

This updates the graphics for each element of the cone. It takes longer but gives earlier
visual feedback.

• Display the full bus of each bit.

This is faster, but contains more bits than requested, and is therefore less accurate.

Irrespective of the choice, the following progress meter is displayed:

Use this dialog to cancel a potentially long operation instead of waiting for it to complete.

15.3.8.13. Observability Don't Care Notes

Each ODC opportunity has a detailed explanation for the derivation of ODC enable expressions.
The explanation includes the initial ODC expression, pruned expression, merged expression, final
ODC expression and the cycle early ODC expression that is the enable for clock gating. Steering
logic and dynamic clock gating efficiency (DCGE) values are also provided for each of these
expressions. You can view this information in the 'Notes' pane of the 'Simple Reduction' dialog of
the PowerArtist GUI.

When you select an ODC (or SODC) candidate, the 'Notes' pane below the reduction candidate list
shows the detailed explanation for that candidate. The Notes for a sample ODC opportunity is
shown below:

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To control the generation of ODC notes, use the following variable:

pa_set reduction_odc_enable_notes <true | false>

The default value is 'false'. Setting this variable to 'true' generates the 'ODC Notes' but can
increase the runtime of ODC analysis and the size of the reduction power database.

15.3.8.14. Understanding ODC-based Reductions

The Notes pane in the GUI reduction window is enhanced to better describe to RTL designers how
each PowerArtist ODC reduction opportunity has derived the clock enable. The following figure
shows the ODC analysis notes in 'Notes' pane of the 'Simple Reduction' dialog:

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The following information is available in the 'Notes' pane:

• ODC condition in each stage of the derivation process: original, pruned, optimized, merged,
untimed enable, and timed enable.
• The clock gating efficiency (CGE) of the ODC condition (if it is used to generate an enable
signal).
• The supplied instance list, which lists all the steering gates and registers that provide the
ODC condition. Registers in this instance list drive steering gates in the next sequential stage
that affect the candidate register's observability.

A sample of the ODC analysis notes is shown below:

Original:
ODC(top.#r3.din[7]) = (~top.#n26 | top.#n27)
CGE: 99.999969
Supplied by: top.#m0, top.#r1;
ODC(top.#r3.din[6]) = (~top.#n26 | top.#n28)
CGE: 99.999969
Supplied by: top.#m0, top.#r1;
...
Pruned:
ODC(top.#r3.din[7]) = (~top.comp2 | ~top.en2)
CGE: 99.999939
Supplied by: top.#m0; Pruned: top.#r1;
ODC(top.#r3.din[6]) = (~top.comp2 | ~top.en2)
CGE: 99.999939
Supplied by: top.#m0; Pruned: top.#r1;
...
Optimized:
ODC(top.#r3.din[7]) = (~top.comp2 | ~top.en2)
CGE: 99.999939
Supplied by: top.#m0;

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 Power Reduction PowerBots

ODC(top.#r3.din[6]) = (~top.comp2 | ~top.en2)

CGE: 99.999939
Supplied by: top.#m0;
...
Merged:
ODC(top.#r3) = ~top.comp2|~top.en2
CGE: 99.999939
Untimed enable:
En_untimed(top.#r3) = ~ODC(top.#r3) = top.comp2&top.en2
CGE: 99.999939
Timed enable:
En_timed(top.#r3) = top.#n16&top.en1
CGE: 100.000000

Notes:

• Due to the performance cost of calculating CGE for ODC conditions that contain more than 20
operators ('&', '|', '^'), CGE is calculated and the expression is not presented.
• If an ODC candidate has CGE of '0' after merging, its analysis note is not presented in the 'Notes'
pane.

15.3.9. Strengthened Observability Don't Care (SODC)

Under certain conditions, the outputs of registers are not observable by downstream registers. The
boolean expressions that capture these conditions can sometimes be used to improve the efficiency,
or 'strengthen', the enable condition of an upstream register that is already clock gated. The
Strengthened Observability Don't Care (SODC) PowerBot identifies such power reduction opportunities
and automatically generates the enable conditions, as shown in the following figure:

Figure 15.9: Strengthened Observability Don't Care - Schematic Diagram

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In this figure, the observability of the outputs of registers 'R1' and 'R2' is a function of the downstream
mux select. Only one register output is observable downstream for a given logic value of the mux
select. If the mux select signal is available a clock cycle earlier, at the input of the register 'R3', then
that cycle-early mux select signal is used to strengthen the clock enable conditions for registers 'R1'
and 'R2', which are already clock gated with enables 'EN1' and 'EN2' respectively.

Definitions of Terms
To use the SODC PowerBot effectively, you should be familiar with the following terms:

• Clock Gating

A power efficient implementation where register banks are disabled during some clock cycles.
The register feedback loop and the multiplexer are removed. The clock gating circuitry is
inserted into the clock path, creating a lower frequency clock that reduces unnecessary register
clock activity.

• Gated Register

A register bank where some or all of its bits are enabled through a feedback multiplexer or
has its clock driven by an instantiated integrated clock gating cell.

• Candidate Register for SODC

A register bank for which both the following conditions are true:
– Some or all its bits have a mux feedback path.
– Its data path width is greater than or equal to the minimum bit threshold required for
clock gating. For example, a register instance with scalar bits is not considered.

15.3.9.1. Usage
The SODC PowerBot is enabled by default when you perform a reduction run (using the
'ReducePower' command) and works in a vectorless mode. Before running power reduction with
SODC, you can define the analysis conditions that determine when SODC is applied by providing
different options to the 'ReducePower' command:

• To exclude all clock-related PowerBots, you can specify the '-reduction_classes' option
and exclude the 'clock' class:
ReducePower -reduction_classes linter logic memory

This disables the SODC, ODC, LEC, LNR, and Prism PowerBots.

• To exclude certain registers from consideration by SODC, specify the following option:
ReducePower -reduction_min_bit_width_clocks {min_value}

The SODC PowerBot ignores the registers whose bit-widths do not meet the specified
minimum bit width constraint and the '-reduction_max_bit_width' constraint.

• To exclude specific modules from reduction analysis, specify the 'SetSkipReduction'

command:

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SetSkipReduction -instance top.blk1 -reduction sodc

When this command is specified, PowerArtist does not perform SODC analysis on the instance
'top.blk1', but ODC analysis is performed.

• By default, reductions cannot cross hierarchical boundaries. To enable hierarchical reduction,

specify the following option:
ReducePower -reduction_hierarchy full

• To disable the SODC PowerBot, specify the following option:

ReducePower -skip_reduction_list sodc

15.3.9.2. Implementation
When you run reduction, SODC goes through the following process:

1. Locates candidate registers in the design.

For candidate registers, it searches for 2-1 muxes, unencoded muxes, and tri-states that
steer logic results to downstream registers. The select lines for those devices can be
combined with existing enables for the upstream register if the select line is directly
generated as an output of a register. The SODC PowerBot does not support pre-computation
of the enable strengthening expression.

2. Estimates power savings and penalties to determine the effectiveness of the gating.

3. Writes the results into the power database for later viewing. You can view the results in
the 'Simple Reduction Dialog' in the GUI.

During inferencing, vectored registers are broken out into their own registers. This enables easy
visualization of data paths. It also recognizes that data paths are often manipulated the same way
across all bits.

15.3.9.3. Understanding Power Savings and Penalty Calculations in SODC

The SODC enable strengthening expression is the OR of all the select signals along one path ANDed
with the enable expressions for all other paths. This enable strengthening expression is then
combined with the existing enable condition.

• The penalty power includes the boolean expression required to implement the enable signal
strengthening expression.
• The power savings are due to:
– Reduced clock power in the candidate register due to the reduced number of times
the clock pin toggles on all the candidate register bits.
– The savings in the cone of logic downstream from the candidate register due to fewer
toggles appearing at the outputs of the candidate register.
• Area impacts primarily occur due to the extra circuitry needed to implement the clock enable
strengthening expression.

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15.3.9.4. Trade-offs
As with any clock gating technique, there are area and delay trade-offs you have to make versus
the power saved. Area and delay may both increase due to the combinational logic that must be
added to your circuit to create the enable signal. In general, as long as the number of clock gated
bits is reasonable, which is probably 3 or more, the savings outweigh the area impact.

15.3.9.5. Reporting Results

• GUI - Simple Reduction dialog

The Simple Reduction' dialog displays SODC opportunities, as shown in the following figure:

To display only SODC opportunities, filter on 'Reductions contain SODC'. If you select 'Show
Downstream Cone' on an ODC candidate register in the Simple Reduction Viewer, the schematic
shows the downstream cone of the candidate register and the downstream cones of the flops
that participate in the SODC expression.

The 'What's This?' (tool tip) text for the 'Gating Power' column in the 'Details' pane is updated.

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The text explains that SODC candidates have zero value, because the SODC reduction technique
tries to strengthen existing enables and does not insert a clock gating circuit.

• Text Report

In addition, the '.srpt' file contains an entry in section '4. Power Reduction by Technique' that
looks like the following file excerpt:
4. Power Reduction by Technique
===============================
<snip>
Core Core
Core Techniques Dynamic Saving Total Saving
----------------------------------------------------------------------------
Potential : 93.6uW 11.51% 93.3uW 11.35%
Observability Don't Care :
Auto-accepted : Topology based auto-accept#
Strengthened : 7.96uW 0.98% 7.94uW 0.97%
Potential : 7.96uW 0.98% 7.94uW 0.97%

The SODC results are reported in the 'Strengthened' category (highlighted in red) in the
Observability Don't care section shown here. In this example, the total savings (if you implemented
the suggested SODC reduction opportunities) would be '7.94uW'.

Note: The SODC reduction opportunities are never automatically accepted but you can schedule
all changes manually.

15.3.9.6. Optimizing Enable Expressions in ODC/SODC PowerBots

Designers can use the results of ODC/SODC reduction PowerBots, because the following
enhancements are available:

• The inferred net names in the enable expressions are replaced by the optimized driving
expression for the inferred nets, which allows further optimization on the new enable
expression.
• The optimized driving logic of such inferred nets is reported in the 'Note' tab of the 'Simple
Reduction Viewer'.
• The value reported in the 'En Depth' and 'En Literals' columns is calculated based
on the new enable expression.

15.3.10. Enhanced ODC-based Clock Enable Identification

The Observability Don't Care (ODC) PowerBot examines the topology of the design circuit to determine
the conditions under which the outputs of the registers are not observable by downstream registers.

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These conditions are then used as clock enable signals on the upstream register. A new variant of
the ODC algorithm is now available, which gives better performance and power savings, especially
on large designs.

15.3.10.1. Usage
Do the following steps to enable the new ODC PowerBot algorithm:

1. Set the following variable to 'true' to run the algorithm during elaboration:
pa_set elaborate_enable_advanced_enable_extraction <true | false>

This step generates an enable file. By default, the enable file name is 'enable.xml.gz'.
Use the following variable to change the default name:
pa_set reduction_clock_gating_enable_file <filename>

2. Specify the enable file using the following variable:

pa_set reduction_clock_gating_enable_file <filename>

Note: Specifying the enable file is optional.

3. Define memory cells:

DefineMemory -cell {RR128*} -data {{CLK {{Q*} {D*}}}}

4. Define the clock gating cells:

DefineCell -name SEQTLATNTSCAX2MTH -type icgc -pin {{enable E}}

5. Run elaboration and power reduction:

Elaborate <options>
ReducePower <options>

Note: If you do not specify 'pa_set

elaborate_enable_advanced_enable_extraction true', the legacy ODC analysis
is enabled.

Use the following variable to ignore the generation of the ODC data:
pa_set skip_reduction_list reduction_type {odc}

15.3.10.2. Reporting Results

The following reports are available after running the new ODC PowerBot algorithm:

• The 'ODC-by-enable' report

ODC generates enable signals by examining the topology of the circuit and determining the
conditions under which the outputs of the registers are not observable by downstream

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registers. These conditions are then used as clock enable signals on the upstream register
to save significant amount of dynamic power at the cost of area penalty.

The report contains information about the clock enable expressions. The report provides
details on ODC reduction opportunity for each enable expression and how much power can
be saved with how much area penalty. The 'ODC-by-enable' report also groups the ODC
suggested register bits by their clock enable logic. The report is sorted in descending order
of power savings. In case of similar power savings, sorting is based on the number of register
bits, area overhead, and CGE improvements.

A sample report is shown below:

===============================================================================
Note: The results might be filtered by the following settings:
pa_set reduction_report_negative_reductions (current value : False)
===============================================================================

Clock Gate Groups:

1. Enable Expression : (((((e299 & e300) & (e302 & e303)) | ((e299 & e300) &
(e303 & ~(e302)))) | ((e299 & e300) & e302)) | ((e299 & e300) & (~(e302) & ~(e303))))
e299: orpsoc_top.wb_ctrl0.fifo.#n1
e300: orpsoc_top.wb_ctrl0.delay1.#n2
e302: orpsoc_top.wb_ctrl0.fifo.#n7
e303: orpsoc_top.wb_ctrl0.fifo.#n8

The inferred signal names and related expressions are as follows:

orpsoc_top.wb_ctrl0.fifo.#n1=(((we_i | clear) & ((clear & 0) |
(~(clear) & ~a0))) | (~((we_i | clear)) & a0))
orpsoc_top.wb_ctrl0.delay1.#n2=((clear & 0) | (~(clear) & dffs[2][0]))
orpsoc_top.wb_ctrl0.fifo.#n7=((((a0 & we_i) | clear) & ((clear & 0) |
(~(clear) & adr_i_next[1]))) | (~(((a0 & we_i) | clear)) & adr_i[1]))
orpsoc_top.wb_ctrl0.fifo.#n8=((((a0 & we_i) | clear) & ((clear & 0) |
(~(clear) & adr_i_next[0]))) | (~(((a0 & we_i) | clear)) & adr_i[0]))

Total Candidate Flops : 16

Candidate Flop List :
wb_ctrl0.fifo.tmp[15:0]

Details Per Flop :

Parent Module: wb_ctrl_fifo

Candidate Flop : w_cl0.fifo.tmp[15:0] (File: ../../vlog/../../w_c_fifo.v, Line: 34)

Bit Width : 16
Dynamic CGE : 0 -> 100 (Improvement: 100)
Power Saved : 20.9uW (Logic:17.5uW, Clock:3.4uW)
Area Penalty : 84.87
Auto-accept : yes

<snip>

By default, the 'ODC-by-enable' report is saved as 'ReducePower_odc_by_enable.rpt'.

Use the following variable to save the file with a different name:
pa_set reduction_odc_by_enable_report <filename>

• ReportReductions

The 'ReportReductions' command reads the reduction power database and generates a
CSV file of the reductions in the design:
ReportReductions -pdb ** -csv ** -reds {odc}

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15.3.10.3. APSH/Containers Support

The reduction power database generated after running the new ODC PowerBot algorithm contains
the ODC data and can be queried by using the APSH 'get_reductions' container command:
get_reductions -filter {reduction_type == ODC}

15.3.10.4. GUI Support

The figure below shows the ODC candidates in 'Simple Reduction' dialog:

15.3.10.5. Limitations of the New ODC Algorithm

The new ODC algorithm has the following limitations:

• Enable extraction for latches and instantiated registers are not supported yet.
• Technology libraries are not automatically parsed for memory and ICGC information.

15.3.11. Enable Signal-based Stability Constraints (STC)

Stability Condition (STC) is the condition when a register's input is maintained stable (unchanging
value) over several consecutive cycles by upstream logic.

15.3.11.1. Usage
Do the following steps to perform STC analysis:

1. Set the following variable to 'true' to run the algorithm during elaboration:

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pa_set elaborate_enable_advanced_enable_extraction <true | false>

This step generates an enable file. By default, the enable file name is 'enable.xml.gz'.
Use the following variable to change the default name:
pa_set reduction_clock_gating_enable_file <filename>

2. Specify the enable file using the following variable:

pa_set reduction_clock_gating_enable_file <filename>

Note: Specifying the enable file is optional.

3. Define memory cells:

DefineMemory -cell {RR128*} -data {{CLK {{Q*} {D*}}}}

4. Define the clock gating cells:

DefineCell -name SEQTLATNTSCAX2MTH -type icgc -pin {{enable E}}

5. Run elaboration and power reduction:

Elaborate <options>
ReducePower <options>

Note: When STC analysis is enabled, the Prism PowerBot is disabled.

Use the following variable to ignore the generation of the STC data:
pa_set skip_reduction_list reduction_type {stc}

15.3.11.2. Reporting Results

The following reports are available after running the STC analysis:

• The 'STC-by-enable' report

The report contains information about the STC enable expressions. A sample report is shown
below:
Clock Gate Groups:

1. Enable Expression : e4440

e4440: ~(~(~(~(delay(delay(e251)) & ~(delay(delay(delay(e475)))
& ~(~(delay(delay(delay(e475))) & delay(delay(e251))) & ~(delay(delay(delay(e475))))
& ~(delay(delay(delay(e475))) & delay(delay(e251))))) & ~(e4194 & ~(delay(delay(e251))
& ~(delay(delay(delay(e475))) & ~(~(delay(delay(delay(e475))) & delay(delay(e251)))
<snip>
e251:
e475: i_or1k.i_top.or1200_cpu.or1200_ctrl.#n68
e4194: i_or1k.i_top.or1200_cpu.or1200_fpu.fpu0.fpu_op_r2[1]
e4258: i_or1k.i_top.or1200_cpu.or1200_fpu.fpu0.fpu_op_r2[2]
e4299: i_or1k.i_top.or1200_cpu.or1200_fpu.fpu0.fpu_op_r2[0]

The inferred signal names and related expressions are as follows:

Total Candidate Flops : 17

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Candidate Flop List :

i_or1k.i_top.or1200_cpu.or1200_fpu.fpu0.fract_i2f[16:0]

Details Per Flop :

Parent Module: fpu

Candidate Flop : i_or.or_cpu.fpu[16:0] (File: ../../vlog/../fpu.v, Line: 363)

Bit Width : 17
Dynamic CGE : 0 -> 87.5 (Improvement: 87.5)
Power Saved : 5.39uW (Logic:2.31uW, Clock:3.09uW)
Area Penalty : 429.442
Auto-accept : yes

<snip>

By default, the 'STC-by-enable' report is saved as 'ReducePower_stc_by_enable.rpt'.

Use the following variable to save the file with a different name:
pa_set reduction_stc_by_enable_report <filename>

• ReportReductions

The 'ReportReductions' command reads the reduction power database and generates a
CSV file of the reductions in the design:
ReportReductions -pdb ** -csv ** -reds {stc}

15.3.11.3. APSH/Containers Support

The reduction power database generated after running the new ODC PowerBot algorithm contains
the ODC data and can be queried by using the APSH 'get_reductions' container command:
get_reductions -filter {reduction_type == STC}

15.3.11.4. GUI Support

The figure below shows the STC candidates in Simple Reduction window:

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15.4. Power Linter PowerBots

If increased power consumption is the cost of achieving certain logic functionality and meeting timing
in a design, then the goal of a low-power design is to achieve the required functionality and timing
while consuming the least amount of power. In this case, power dissipation that does not add to
functional completeness or aid in meeting (or exceeding) the timing budget is wasted power.
PowerArtist's power linter PowerBots help you identify the areas in your design where power is wasted.

Since power analyses at the RT level of abstraction are made through net toggles, monitoring wasted
power is equivalent to monitoring extraneous net toggles, and estimating the amount of power saved
if the unneeded toggles were eliminated. The PowerBots in this section find the amount of wasted
power at the inputs of three very common design components. They determine whether a certain
toggle at the input of the device was used, or ignored. Based on the wasted toggle data collected
during the reduction analysis process, it generates the wasted power numbers. You can then use the
PowerCanvas to display the wasted power results and then decide what changes you may want to
make to your design. These results include: an estimate of the amount of power wasted in each case,
the kind of wasted power, the instance in which the power is getting wasted, and which nets form the
input of that instance. The Mux Power Linter provides some critical additional information. It traces
'cones of logic' for the inputs that have wasted power and presents this information in the PowerCanvas.

Limitations of the Linter PowerBots

The power linter PowerBots do not recommend a means of recovering the wasted power, as the method
of recovering power depends heavily on the design and test pattern. For example, if the input net to
a multiplexor toggles much more frequently than the frequency of its selection, you could reduce the
number of toggles using one of several methods-gating the input with the select, changing some
upstream logic so that the input data changes only before it will be selected, etc. However, there is no
fixed 'optimal' solution.

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Input Nets with Multiple Instances Connected

If the instance being monitored by a power linter PowerBot is not the only instance connected to an
input net, that input net will not be monitored for wasted power because that net's activity could be
used by another device. In short, only nets with one source and one sink are considered for extraneous
activity monitoring.

The next sections describe the available power linter PowerBots in detail.

15.4.1. Memory Power (MEM) Linter

Design Parts: memory

The Memory Power Linter (MEM) PowerBot finds the memories in the design and monitors the data
input to the memories to see if changes in the data input ports were wasted because the memory
was not selected for a write access. This PowerBot also estimates the amount of power lost due to
the wasted activity on the input data bus.

Definition
If the input data bus to a memory changes one or more times and that memory is not selected for
a write access before the input data line toggles again, the toggles on the input data bus of the
memory are considered as extraneous toggles, which cause power to be wasted. The following
schematic shows data changing at input 'DATA' to the memory. However, the write enable ('WE') to
the memory is not valid during the data change and is not written into the memory at 'ADDR'.
Therefore, this extraneous transition of the data causes power to be wasted.

15.4.1.1. Implementation
Unused toggles on the memory input data bus can be desirable or undesirable. Depending on your
design, there are several ways to implement more efficient circuitry to reduce extraneous activity
on the input data bus for the memory. This PowerBot is essentially an analysis tool that points out
the potential areas of concern. The analysis is very much design and simulation dependent. The
PowerBot monitors the input data bus of the memory only if the bits of the input data bus and the
write enable are monitored by your simulator. Inferred nets are not monitored for extraneous
activity/wasted power.

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15.4.1.2. Usage
The MEM PowerBot is enabled by default. Use the following command to disable it:
ReducePower -skip_reduction_list {mem}

15.4.1.3. Reporting Memory Power Wastage

Memory Power Linter (MEM) reports the power wasted in non-clock pins/buses of the memories
in a Memory Linter Report (p. 369). The algorithm to detect wasted toggles is enhanced to cover
various scenarios, such as gated clock, and disabled memory, where the activity on memory
pins/buses can be redundant. The power wastage is reported at pin/bus level and at instance level.
The wasted power does not include the cone power of the pin/bus.

MEM analyzes memory input pin/bus toggles per clock cycle and redundant toggles and the
corresponding wasted power is identified as follows:

• If clock is gated, Greater than one toggle on pins/buses is wasted.

• If chip select (CS) is disabled, greater than one toggle on any input pins/buses except clock
is wasted.
• If clock is enabled, chip select (CS) is enabled, and memory is in 'read' mode, any toggle
on pins/buses associated with the 'write' operation are wasted. Such ports include data input
(DI), write address (WA), or byte write enable (BYTE).

15.4.2. MUX Power (MUX) Linter

Design Parts: multiplexors

The MUX Power Linter (MUX) PowerBot locates all multiplexors in the design and monitors their inputs
to see if certain input toggles are unnecessary due to the input not being selected. It also estimates
the power in the cones of logic leading up to the inputs with the wasted power. This estimate allows
you to determine whether you see a significant benefit from reducing the power upstream in the
cone.

Definition
If the input net to a multiplexor toggles one or more times and that input is not selected by the
multiplexor before it toggles again, the toggles on that input of the multiplexor are considered wasted.
This means that there is activity that consumes power on that pin of the multiplexor, but that activity
is meaningless. The following schematic shows a multiplexor which initially selects the 'B' input. The
power consumed by the transitioning that appears on 'A' during the 'B' select period is considered
wasted power as it is not relayed to any other part of the design.

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15.4.2.1. Implementation
The unused toggles on the multiplexor can be desirable or undesirable. Depending on your design,
there are many ways of implementing more efficient circuitry upstream from the multiplexor which
can reduce wasted activity at the multiplexor. This PowerBot is essentially an analysis tool that
points out the potential areas of concern. The analysis is very much design and simulation dependent.

The PowerBot monitors an input of a multiplexor only if the associated net is monitored by your
simulator. Inferred nets are not monitored for extraneous activity/wasted power.

15.4.2.2. Usage
The MUX PowerBot is enabled by default. Use the following command to disable it:
ReducePower -skip_reduction_list {mux}

15.4.2.3. Understanding the PowerCanvas Data for the MUX Linter

The PowerCanvas displays two different types of information related to the MUX Power Linter, as
shown in the following figure:

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Figure 15.10: Linter Reduction Dialog Showing MUX Results

• The 'Linter Reductions' dialog contains special columns in the upper pane that provide data that
can help you determine whether the power savings would be worth the effort to implement the
power reduction opportunity revealed by the technique. For details, see section 'Information in
the Upper Pane (p. 329)'.
• In the tabbed pane within the 'Detail' tab, there is detailed information that can help you
determine the specific changes you need to make. For details, see section 'Information in the
Tabbed Pane (p. 331)'.

After reviewing the dialog data, if you determine that there is a reduction opportunity worth
investigating further, you can display logic cones in the 'Schematic Viewer' that help you to better
understand the scope of the changes required. To do this, select and right-click an input pin in the
'Detail' tab to display the logic cones. For details, see section 'Schematic Display for the Mux Power
Linter (p. 331)'.

15.4.2.3.1. Information in the Upper Pane

The following information is available in upper pane:

• Wasted Power

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The Mux Power Linter (MUX) points out power that is wasted in muxes due to toggles on
mux data inputs that are not passed to the mux output because the select line is selecting
other data inputs when those toggles happen. There is certainly wasted power in the mux
itself. However, the cone of logic that generates the ignored toggles is a potential source
of far more wasted power. The data provided in the Mux Power Linter shows you the
magnitude of the power that is wasted.

• Cone Power

One of the columns in the upper pane is 'Cone Power'. This represents the power of all
the instances and nets in one or more exclusive logic cones associated with the instance.
An exclusive logic cone is the cone of logic that drives a particular pin on a 2-1 or
unencoded mux instance that does not fanout to any other pin.

The cone of logic stops when it reaches a sequential instance (register, latch, register file,
latch file, memory), a blackbox instance, a bus pin of vendor gate instance, a primary input
to the design or an inferred instance whose input pin is driven by an instance that fans
out outside the cone. The cone of logic is traced through the select pins of 2-1 and
unencoded muxes and tri-state enable pins.

Larger cone power numbers normally represent excellent opportunities to reduce power.
If you are able to suppress toggles entering the exclusive cone, then those toggles do not
ripple through the cone and do not cause excessive dynamic power.

• Exclusive Cone Power

The 'exclusive' cone power is the sum of the power of all of the nets and instances in the
cone except for instances that are vectored. For vectored instances, the instance total
power number is divided by the number of output bits of the device and it is added to
the exclusive cone power. Examples of vectored instances are registers, latches, register
files, latch files adders, multipliers, tri-states, buffers, nots, unencoded muxes, and 2-1
muxes.

• Start Points

Another column is 'Start Points'. This represents a count of the number of entry points
into the exclusive cone of logic. These are the places that logic should be inserted to
suppress toggles in the exclusive cone. Generally. the smaller the number of 'Start Points',
the easier it is to determine logic to suppress excess toggles. The start points are
determined as follows:
– For inferred registers, latches, register files and latch files, the start point is the 'din'
pin that generates the 'dout' value. Therefore, if the exclusive cone is traced back to
'dout[i]', tracing stops at this instance and 'din[i]' is listed as a start point. For
sequential vendor gates, all the input pins are listed as a start point.
– For a blackbox, tracing stops at those instances and no start point is listed.
– For a combinational vendor gate, tracing stops at the vector pin, if any, of the instances
and all the input pins are listed as start point. In an RTL design, it should be rare that
you see these instances.
– For a primary input, it is the input pin of the instance driven by the primary input.
– For all other 'Start Points', it is the input pin of the instance reached where exclusivity
stops.

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In short, you need to consider both the 'Cone Power' number (whether it is high) and the number
of 'Start Points' when you determine the reduction opportunities to pursue first.

15.4.2.3.2. Information in the Tabbed Pane

Once you select an instance in a mux linter opportunity in the upper pane and then click the
'Detail' tab, you see much more information. You see two side-by-side sub-panes. The left-side
sub-pane controls the right-side sub-pane display. The four columns in the left-side sub-pane
are:

• Input_pins: This is the list of pins on the 2-1 or unencoded mux that have wasted power.
It can be a single pin or a vector.
• Cone Power: The power of the exclusive cone of logic leading to that pin.
• Start Points: The number of start points associated with the exclusive cone of logic for
that point.
• Pcnt Idle: The percentage of time that the inputs pins were idle. Therefore, it represents
potential wasted power.

If you add the 'Cone Power' and the 'Start Points' for all the pins, they match their corresponding
accumulated number in the upper pane. If you select an 'input pin', the following columns in the
right-side sub-pane are populated:

• Input Nets: This is a list of nets attached to the selected 'input pin'. This can be a scalar
net, a vector, or a combination of the two.
• Start Pins: This is the list of 'Start Pins' for the exclusive cone leading to this pin. The
number of Start Pins is equal to the Start Point count.
• Select Nets: These are the select lines that control the 'input pin'.

Each of the above has an associated sub-item:

• Input Pin: If you select an input pin and right-click, you can display the full logic cone or
the exclusive logic cone for that pin in the 'Schematic Viewer'.
• Input Net: If you select an input net and right-click, you can display a logic waveform.
• Start Pin: If you select a start pin and right-click, you can display the full logic cone or
the exclusive logic cone for that pin in the 'Schematic Viewer'.
• Select Net: If you select a select net, you can display a logic waveform.

15.4.2.4. Schematic Display for the Mux Power Linter

You can generate a logic cone or an exclusive cone for a pin. The following figure shows an exclusive
cone of logic that includes select paths and datapath coloring.

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Figure 15.11: Exclusive Cone of Logic in Schematic (Colored by Connectivity)

If you select Schematic > Colorized By > Connectivity, the following color scheme is applied to
exclusive cones in the 'Schematic Viewer':

• Green: Indicates a 2-1 or unencoded mux from which the exclusive cone of logic is traced. All
the instances in the exclusive cone generate logic for an input pin of this instance.

• Magenta: Indicates that these are data path logic elements.

• Red: Indicates that these are the 'stop at' instances. These are instances that have one or more
'start pins'. They are registers, latches, register files, latch files, black-boxes, sequential vendor
gates, and instances where the exclusive cone stops.

• Blue: Indicates that these instances are 'next to last stop at' instances. You must insert logic
between the 'stop at' instance and the 'next to last' instance to suppress wasted toggles.

• Yellow: Indicates that these are elements in the select path that were not colored as a 'start',
'end', or 'next to last stop at' instance.

The View > Schematic Legend menu displays the coloring. If you select the Schematic > When
Tracing menu options, then datapaths logic or select logic is displayed and colored uniquely.
Additional colors are also explained in the legend. The legend uses the word 'penultimate' which
means 'next to last' and applies to the 'next to last stop at' instance.

Tracing Exclusive Cones

When the tracer reaches the output of an instance while tracing upstream for an exclusive cone,
it continues from the corresponding input point. The choice of continuation point depends on the
type of instance:

• adders and multipliers: If 'out[i]' is reached, then:

– 'a_in[0]' to 'a_in[i]' is a continuation point.
– 'b_in[0]' to 'b_in[i]' is a continuation point.
• decoders and comparators: All inputs are continuation points.
• buffer, not, connect, connect_inv: If 'out[i]' is reached, then 'in[i]' is a continuation point.
• OR, NOR, AND, NAND, XOR, XNOR: All inputs are continuation points.

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• 2-1 mux and unencoded mux: If 'out[i]' is reached, then 'a_in[i]', 'b_in[i]', and 'c_in[i]',
are continuation points. The select pins for a 2-1 mux and an unencoded mux are also continuation
points.

15.4.2.5. Reporting Wasted Power for Multiplexer Inputs/Cones

The Mux linter technique can highlight and quantify the reduction opportunities associated with
cones of logic feeding into unselected multiplexer inputs. For every Mux linter reduction candidate:

• The total power is the sum of the mux instance's total power and its exclusive fanin cone power.
• The total wasted power is the sum of mux instance power and cone power multiplied by the
proportion of time that the input is idle.
• Mux input pins that do not have an exclusive fanin cone are not displayed in the 'Details' tab in
the 'Reduction Viewer'. When displaying the exclusive fanin cone of a mux input in the 'Schematic'
from the ' Detail' pane of the mux linter, the cone is traced for all of the bits of the input port
instead of just those shown in the 'Detail' pane.
• Mux input pins that do not have unused data toggles are displayed in the 'Details' tab in the
'Reduction Viewer'.

GUI Enhancement
The tooltip descriptions in the GUI, launched by the 'What's This?' button are modified to reflect
the changes described above:

• Total power for the multiplexer linter candidate includes exclusive fan-in cone power in addition
to instance power.
• Wasted power of multiplexer linter candidate includes estimated wasted cone power, in addition
to wasted candidate instance power.

15.4.2.6. Reporting Wasted Power for Inferred Select Nets

For PowerArtist to recognize and process multiplexers with wasted activity, a multiplexer instance
must meet the following two requirements:

• Simulation activity on the select net.

• Simulation activity on one or more data input net.

When the select line of a multiplexer instance does not have simulation activity, as in the case of
inferred select nets, the multiplexer activity linter traces the select net upstream to find an expression
composed of nets with simulation activity. To avoid adverse performance impact, the expression
tracing has limits on depth and total variables in the tracing expression. The default depth limit is
set to '8' and the default variable count is set to '32'.

You can use the following variables to change the default values:

• To set the depth of tracing expressions for select lines:

pa_set reduction_mux_max_expression_depth <integer>

• To limit the number of variables in the tracing expression for select lines:
pa_set reduction_mux_max_expression_literals <integer>

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15.4.3. Register Power (REG) Linter

Design Parts: registers/flip-flops, clock

The Register Power Linter (REG) power linter PowerBot finds registers in the design and monitors the
inputs to see if certain toggles were unnecessary because the clock did not cycle. It also estimates
the amount of power lost due to the extraneous activity on the inputs.

Definition
If the input net to a register or a flip-flop toggles two or more times before the clock of the register
completes one cycle, the toggles on the inputs could all be wasted. This means that there is activity
that consumes power on the input of the register, but that activity is meaningless. The following
schematic shows a register that is clocked infrequently ('CLK') compared to the data changing at its
'D' input. The transitioning occurring on the 'D' input between the clocking of the register is considered
extraneous because power is wasted.

15.4.3.1. Implementation
The unused toggles on the register input can be desirable or undesirable. If it is undesirable, there
may be many ways of implementing a more efficient circuitry upstream from the register, which
reduces wasted activity of the register. This PowerBot is essentially an analysis tool that points out
the potential areas of concern. This analysis is very much design- and simulation-dependent. This
PowerBot monitors the input of the register only if the associated net is monitored by your simulator.
Inferred nets are not monitored for extraneous activity/wasted power.

Threshold for Register (REG) Power Linter

The Register (REG) Power Linter PowerBot finds registers in the design and monitors the data and
clock inputs to see if certain data toggles are redundant because the clock did not toggle. It also
estimates the amount of power wasted due to the redundant activity on the data inputs.

You can specify a threshold for the REG linter to filter out candidates that do not have enough
wasted toggles.

The ratio (for inferred and instantiated clock gated registers) is cycle counts when clock is disabled
but data is toggling to cycle count when clock is disabled. If the ratio is lower than the specified
threshold, then the candidate register is not considered as a reduction opportunity.

You can enable this support by using the following variable:

pa_set reduction_reg_linter_threshold <integer>

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The default value of the variable is '0.05' and the valid range is '0.0' to '1.0'.

15.4.3.2. Usage
The REG PowerBot is enabled by default. Use the following command to disable it:
ReducePower -skip_reduction_list {reg}

15.4.3.3. Reporting Results

This PowerBot reports the exclusive fan-in cone power and the wasted exclusive fanin cone power
based on the clock gating efficiency. You can view these values in the GUI, the reduction report,
and the CSV report generated by the 'ReportReductions' command.

To calculate the exclusive fan-in cone power of potential candidates, set the following variable to
'true':
pa_set reduction_calculate_register_fanin_cone_power <true | false>

You can view the 'Cone Power' and 'Start Points' (both of which are related to the fanin cone) of the
REG power linter candidates in the 'Linter Reductions' dialog of the PowerArtist GUI as shown
below:

You can control the performance impact by limiting the fan-in cone size by using the following
variable:
pa_set reduction_max_start_points <integer>

The default value of the variable is '256'.

Feedback multiplexers are also analyzed by the REG power linter. The initial power and saved power
is higher for the REG power linter and lower for the MUX linter as the MUX opportunities are
changed to REG opportunities.

New columns are added in the 'Detail' tab of the 'Linter Reductions' dialog to report the 'wasted
timestamps' and the 'cycle' information:

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15.4.4. Clock Enable Condition (CEC) Linter

Design Parts: registers/flip-flops and multiplexers in a feedback loop, clock

The Clock Enable Condition Linter (CEC) PowerBot detects clock gating situations where the data
input to the register is driven by a feedback mux. The goal is to determine situations where the mux
select line, which act as the clock gate enable signal, is not optimally designed. A simple example is
where the clock is enabled but that data input is not changing.

Definition
The following schematic shows a mux-flop feedback loop topology, which is a potential candidate
for clock gating. The power benefit of clock gating is only as good as the clock enable condition
(ENABLE). If the input 'D' does not cycle when the mux is enabled, the corresponding clock toggles
are extraneous, and therefore contribute to wasted power. If this topology is replaced with a gated
clock with the same enable condition, the wasted power remains the same.

15.4.4.1. Implementation
The unused clock toggles on the register clock pin can be desirable or undesirable. If they are
undesirable, there are ways of implementing more efficient circuitry that would reduce wasted
activity of the clock. For example, you can replace the topology in the previous schematic with a
gated clock such that the gated clock enable signal is in sync with the data activity of the register.

15.4.4.2. Usage
The CEC PowerBot is enabled by default. Use the following command to disable it:
ReducePower -skip_reduction_list {cec}

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15.4.5. Memory Sleep Mode (MSM) Linter

Design Parts: memories

Memory Sleep Mode (MSM) linter, is a simulation based approach that leverages the available power
gating modes in on-chip memories, to detect the inactive and redundant periods of memory from
the simulation and suggest power savings by enabling different power gating modes.

MSM reports power penalty for entry and exit from the power gating modes, Light Sleep (LS), Deep
Sleep (DS) and Shut Down (SD). This includes setup and recovery time to enter and exit respectively
from the modes (each low-leakage mode has its own wake up overhead and leakage savings).

15.4.5.1. Use Model

Information about the sleep and power down modes are taken from the '-sleep' and
'-power_down' options of the 'DefineMemory' command. Consider the following example:
DefineMemory
-library RDP*
-access_enable { WEA WEB }
-memory_enable { CSA CSB }
-read_address { AB }
-write_address { AA }
-data { DA DB QA QB }
-sleep { LS DS }
-power_down { SD }

In this example:

• ''LS' corresponds to pin in the memory '.lib'. When active, memory goes into a low leakage
mode and there is no change in the output state.
• 'DS' corresponds to the pin in the memory '.lib'. When active, power to the periphery is
shut down and the contents are retained. But the outputs are pulled low.
• 'SD' corresponds to pin in the memory '.lib'. When active, power to both the periphery
and the core is shut down. The memory contents are not retained.

It is your responsibility to provide the correct sleep and power down pins. PowerArtist determines
their polarity automatically and handles them according to their priority.

15.4.5.2. Usage
The MSM PowerBot is enabled by default. Use one of the following methods to disable MSM for
specific blocks/instances:
SetSkipReduction -instance <> -reduction msm

or:
pa_set skip_reduction_list msm

The MSM PowerBot belongs to the 'memory' category of 'reduction classes'. If 'reduction_classes'
is defined and does not contain either 'all' or 'memory', MSM is disabled, as shown in the example:
pa_set reduction_classes {logic linters}

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15.4.5.3. Reporting Results

The MSM PowerBot generates a report named 'msm.analysis.red'.

15.4.6. Macro Power Linter (MPL)

Design Parts: macros

Macro Power Linter enables you to develop custom power linters for the macros in the design. A
macro can be any of the following:

• liberty cell instantiation.

• black boxed module or liberty cell.
• hierarchical blocks enabling wasted activity analysis for any block in the design.

Macro Power Linter allows you to specify the functionality of macros by defining functional modes
of the macro. Using this information, Macro Power Linter reports the redundant clock cycles and
redundant toggles in clock and non-clock pins in various functional modes of a macro.

Note: This implies a clean methodology for memory wrappers, in particular, as they have a clear and
consistent interface. Real memory instantiation can vary as it is typically target technology and compiler
dependent.

15.4.6.1. Use Model

You can enable Macro Power Linter using following steps in PowerArtist:

1. Run the 'Elaborate' command to generate the scenario file.

2. Define functional modes of the macros using the 'DefineMacroMode' command.

3. Specify the analysis output file using the 'SetMacroPowerLinterReportFile <filename>'

command.

If you do not specify the output file name, by default the analysis output is saved as
'mpl.analysis.red'.

4. Perform power reduction using the 'ReducePower' command.

15.4.6.2. Usage
Macro Power Linter is enabled by default. Use the following command to disable it:
ReducePower -skip_reduction_list {mpl}

15.4.6.3. Reporting Results

Macro Power Linter generates a report named 'mpl.analysis.red'. The report consists of a
header, summary, and detailed report sections. Refer to the 'SetMacroPowerLinterReportFile'
command details in the 'PowerArtist Reference Manual' for details of the report.

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15.5. Power Reduction Technique Summary

This section summarizes the power reduction techniques.

15.5.1. Precedence Rule for Optimal Power Reduction

The tool is enhanced to choose the most optimal reduction technique when reporting for designs
with overlapping reductions. This precedence rule is used for implementing the common filtering
approach for 'ReducePower' text reporting, Report Reductions, and Rewrite processes in overlapping
scenarios.

The filtering action is performed based on the following rules:

1. Ideal Power Savings

The tool looks for maximum or ideal power savings. It selects the reduction technique with a
greater total of logic and clock power savings.

2. Actual Power Savings (including gate power penalty)

If ideal power savings is equal, the tool evaluates actual power saving including gate power
penalty. It selects the reduction technique with the highest value in actual power savings.

3. CGE Improvement

If ideal power and actual power savings are equal, the tool looks for higher CGE improvement.
The tool selects the reduction technique with maximum clock gating efficiency improvement.

4. Area Overhead

If ideal power savings, actual power savings, and CGE improvement are equal, the tool evaluates
area overhead. The tool selects the technique with minimal total area required to implement the
reduction.

The precedence rule helps filter all the powerboats including SODC, ODC, Prism, GMC, LER, LNR, STC,
SMW, LEC, DOI, CEC, MUX, REG, and MEM.

Note: GMC is considered overlapping when the memory instance and clock net are the same, as GMC
could be applied to the same memory instance with different clock nets.

Report All Overlapping Reduction Techniques

By default, the 'ReportReductions' command now skips duplicate or overlapping reduction techniques
while generating CSV and text reports.

Use the new pa_set, reduction_report_overlapping_reductions, to report all overlapping

reduction techniques for an instance. By default, the value is set to false.

The following snippet shows the usage syntax:

pa_set reduction_report_overlapping_reductions <true | false>

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The following snippets shows comparison in results when the pa_set

reduction_report_overlapping_reductions is enabled and disabled:

The example contains following duplicate reduction data as explained subsequently:

1. Instance name: aReg[0:7] is covered by the following techniques:

a. Reduction: ODC

Ideal Power Savings: -6.24298e-09, Actual Power Savings: -1.2769e-09, CGE Imp: 0, Area
overhead: 7.04.

b. Reduction: Prism

Ideal Power Savings: -1.08141e-08, Actual Power Savings: -5.80826e-09, CGE Imp: 0, Area
overhead: -1e+99.

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 Power Reduction Technique Summary

2. Instance name: bReg[0:7] is covered by the following techniques:

a. Reduction: ODC

Ideal Power Savings: -6.24298e-09, Actual Power Savings: -1.2769e-09, CGE Imp: 0, Area
overhead: 7.04.

b. Reduction: Prism

Ideal Power Savings: -1.08141e-08, Actual Power Savings: -5.80826e-09, CGE Imp: 0, Area
overhead: -1e+99.

Based on the precedence rule, ODC is selected for both register instances due to higher numbers in
ideal power savings.

The following snippet shows the CSV output:

By default, when pa_set reduction_report_overlapping_reductions is false:

When pa_set reduction_report_overlapping_reductions is configured true:

15.5.2. Low Noise Register (LNR) / Low-activity Enabled Register (LER)

Registers with low data activity can have a clock enable created or strengthened with a comparison
of the data input and output. Opportunities can be viewed in the 'Simple' and 'Unified Reduction
Viewer'.

pa_shell Variable/Command Default Value

reduction_lnr_instantiated_flops false
Effect: If true, enables LNR/LER analysis on instantiated flop cells.
reduction_register_low_activity_threshold 0.05
Effect: Data input activity below which LNR/LER analysis is done for a register.

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15.5.3. Observability Don't-care Condition (ODC/SODC)

Registers whose output is not observable by any other sequential element or primary output at any
time can have a clock enable created or strengthened. Opportunities can be viewed in the 'Simple'
and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

reduction_odc_activity_optimization false
Effect: If true, uses signal activity from the given activity data to reduce enable expression size
without forfeiting the majority of enable strength.
reduction_odc_by_enable_report <design_name>_odc_by_enable.rpt
Effect: Path where the ODC-by-enable report should be written.
reduction_odc_check_same_clock false
Effect: If true, candidate and delay registers in an ODC opportunity must be driven by the same
clock net.
reduction_odc_clock_tree_source false
Effect: If true, ODC-based enable conditions are strengthened using instantiated clock gate enables.
reduction_odc_ignore_resets false
Effect: If true, reset compatibility checks for ODC candidate and delay registers are disabled.
reduction_odc_include_control_paths false
Effect:
reduction_odc_instantiated_flops false
Effect: If true, instantiated flop cells are analyzed for ODC opportunities.
reduction_odc_max_fanout 128
Effect: Maximum fanout of nets that propagate ODC conditions.
reduction_odc_max_precompute_level 3
Effect: Maximum levels of netlist logic that is duplicated for enable expression.
reduction_odc_memory_source false
Effect: If true, instantiated memories contribute to ODC conditions.
reduction_odc_precompute false
Effect: If true, logic driving multiplexer select inputs are duplicated for enable expression.
reduction_odc_precompute_comparator false
Effect: If true, comparator instances driving multiplexer select inputs are duplicated for enable
expression.
reduction_odc_precompute_decoder false
Effect: If decoder instances driving multiplexer select inputs are duplicated for enable expression.
reduction_odc_prune_dont_care_variables false
Effect: If true, enable expressions cannot contain terms that do not increase the enable strength
with the given activity data.
reduction_odc_report_constant_enables false
Effect: If true, opportunities with constant value enables are reported.

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 Power Reduction Technique Summary

pa_shell Variable/Command Default Value

reduction_odc_use_basic_gates false
Effect: If true, other types of logic and multiplexers are used to derive enable expressions
SetStaticSignals None
Effect: Specifies signals that do not need to be delayed if they are found in ODCs for use in clock
gate enables.

15.5.4. Power Reduction in State Machines (PRISM)

Registers that are downstream of enabled registers can also be enabled using a cycle-delayed version
of those existing enables. Opportunities are viewed in the 'Prism' and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

reduction_disable_manual_gating false
Effect: If true, enables for instantiated clock gating cells are not propagated to downstream
registers.
reduction_disable_prism_enable_strengthening false
Effect: If true, existing register enables are not strengthened with enables propagated from
upstream.
reduction_no_hard_prism_registers false
Effect: If true, registers smaller than the minimum data path width with no enable are not used
to propagate enable conditions downstream.
SetDatapathWidth 8
Effect: Minimum bit width of a register to clock gate.

15.5.5. Gated Memory Clock (GMC)

A clock enable can be created or strengthened for memories whose address (and data) inputs are
stable for several consecutive cycles by comparing the input’s current value with the value from a
cycle before. ODCs for the memory outputs can also be used. Opportunities can be viewed in the
'Simple' and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

DefineMemory
Effect: Specifies memory cells and their ports and enable conditions.
reduction_memory_disable_edge_detection false
Effect: If true, the suggested clock gate enable for a 1R1W memory instance does not check for
conflicting read and write addresses.
reduction_memory_odc_gating true
Effect: If true, ODC conditions are included in suggested clock gate enables for memory instances
if they exist.
reduction_memory_stability_gating true

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Examining and Implementing Power Reduction Opportunities

pa_shell Variable/Command Default Value

Effect: If true, address and data stability conditions are included in suggested clock gate enables
for memory instances.

15.5.6. Split Memory Word (SMW)

Large memories whose full address range is only partially used can be split up into smaller memories
to reduce power consumption for the unused address region. Opportunities can be viewed in the
'Simple' and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

DefineMemory
Effect: Specifies memory cells and their ports and enable conditions.
reduction_max_memory_split 2
Effect: Specifies the maximum number of times that a memory instance can be split.
DefineHalfMemScalingFactor
Effect: Specifies parameters for calculating power of smaller memory instances if no adequate
models exist in the given Liberty files.
DefineMemActivityThreshold 10
Effect: Specifies the minimum number of cycles that a memory address must be stable for the
instance to be split.

15.5.7. Memory Sleep Mode Linter (MSM)

Memories with low power enables can be put into those modes during periods of inactivity. Results
can be viewed in the 'Linter' and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

DefineMemory
Effect: Specifies memory cells and their ports and enable conditions.
reduction_msm_threshold 0
Effect: If above zero, specifies the percentage of total power that wasted power must exceed for
a memory instance to be reported.

15.5.8. Memory Power Linter (MEM)

MEM analyzes memory input pin/bus toggles per clock cycle and redundant toggles and the
corresponding wasted power is reported in the 'Memory Linter Report'.

pa_shell Variable/Command Default Value

DefineMemory
Effect: Specifies memory cells and their ports and enable conditions.
reduction_memory_linter_report <filename> memory_linter_report.csv
Effect: Specifies the user-defined report name.

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 Running PowerArtist Clock PowerBots

15.5.9. Macro Power Linter (MPL)

Macros with an interface description can be analyzed for redundant activity that may cause power
wastage. Results are reported only in the 'Macro Power Linter' report.

pa_shell Variable/Command Default Value

DefineMemory
Effect: Specifies memory cells and their ports and enable conditions.
DefineMacroMode
Effect: Specifies macro instances and their ports and enable conditions.
SetMacroPowerLinterReportFile mpl.analysis.red
Effect: Sets the path where the MPL report should be written.

15.5.10. Clock Enable Condition Linter (CEC)

Registers that are clocked when the data input is stable waste power. Results can be viewed in the
'Linter' and 'Unified Reduction Viewer'. This linter has no special 'pa_shell' variables or commands.

15.5.11. Register Linter (REG)

Registers with data activity when their clock is stable waste power. Results can be viewed in the
'Linter' and 'Unified Reduction Viewer'. This linter has no special 'pa_shell' variables or commands.

15.5.12. Multiplexer Linter (MUX)

Active logic that is unobservable because of a multiplexer that is selecting another path waste power.
Results can be viewed in the 'Linter' and 'Unified Reduction Viewer'.

pa_shell Variable/Command Default Value

reduction_max_start_points 256
Effect: Specifies the maximum number of inputs to the input cone of a multiplexer port that is
traced.
reduction_mux_max_expr_depth 8
Effect: Specifies the maximum netlist logic depth that is traced to monitor multiplexer select inputs
during activity analysis.
reduction_mux_max_expr_vars 32
Effect: Specifies the maximum number of signals that is monitored to calculate the multiplexer
select input value during activity analysis.

15.6. Running PowerArtist Clock PowerBots

Reducing clock power is one of the easiest opportunities to reduce the power of your design. This is
because:

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Examining and Implementing Power Reduction Opportunities

1. You can take advantage of tools later in your design flow to automatically insert Integrated
Clock Gating (ICGC) cells.

2. You can provide these tools constraints indicating which registers to gate.

3. If your circuit is missing enable signals or has inefficient enable signals, PowerArtist can
recommend design modifications or automatically output new RTL that contains the
recommendations.

The recommended methodology to run PowerArtist to reduce your clock power is as follows:

1. Leverage existing 'enables' to create new 'enables':

a. Set 'gate_clock yes' using the 'SetClockNet' command for the appropriate nets in the clock
file.

b. Disable the Low-Activity Non-Enabled Register (LNR) (p. 279) PowerBot and run a reduction using
Prism (p. 298), Clock Enable Condition (CEC) Linter (p. 336), and other PowerBots.

2. Generate completely new 'enables' and leverage those throughout your design:

a. Keep 'gate_clock yes' using the 'SetClockNet' command.

b. Analyze the RTL written in step #1.

c. Run a reduction analysis using both Low-Activity Non-Enabled Register (LNR) (p. 279) and
Prism (p. 298) PowerBots.

3. Generate synthesis constraints to tell PowerCompiler™ the optimal registers to clock gate:

a. Set 'gate_clock no' using the 'SetClockNet' command.

b. Run the Local Explicit Clock Enable (LEC) (p. 283) PowerBot.

c. Run the 'CreateGraph' command to generate a cumulative savings versus number of reductions
curve to determine which register should be gated.

d. Generate the constraints using the 'WriteClockGatingConstraints' command.

Synthesis constraint generation is described in more detail in the next section titled 'Generating
Synthesis Constraints (p. 346)'.

15.7. Generating Synthesis Constraints

The simplest synthesis flows can make clock gating decisions based on topological constraints such as
minimum register bank bit width. Gating decisions do not take power into consideration. Furthermore,
while some register clock gating might save power, the power saving is offset by the increased difficulty
to close timing.

In contrast, PowerArtist analyzes the power of your design (when you run the Local Explicit Clock Enable
(LEC) (p. 283) PowerBot) and determines the optimal registers to clock gate based on the activity files
you provide. PowerArtist then generates '-exclude' constraints to prevent PowerCompiler™ from

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 Generating Synthesis Constraints

gating the registers when there are little or no savings. To run this feature, apply the use model described
in the next section.

Use Model
To generate clock gating constraints, use the following flow:

1. Run power reduction with the Local Explicit Clock Enable (LEC) (p. 283) PowerBot. All clocks specified
in your clock file must have the 'SetClockNet -gate_clock false' option set. This is the default
setting for LEC to run on any clock.

When you run this PowerBot, PowerArtist identifies the registers that are likely to result in positive
savings if the register is clock gated. Before you decide to perform clock gating, you should consider
how clock gating impacts timing and physical design closure. If the savings is small, clock gating
may have a negative impact on the design as a whole. This can be an important consideration since
the bulk of the power savings from clock gating comes from a relatively small number of
opportunities. When LEC finishes running, you have a '.pdb' file that contains the reductions that
LEC considers to be worthwhile.

2. Run the 'CreateGraph' command to generate a '.ptcl' file that you can view using the Waveform
Viewer. This command has the following syntax:
CreateGraph -class clock
-power_db_name <filename>
[-graph_output_file <filename>]
[-graph_log <filename>]
[-graph_type power_savings]

Be sure to specify an output file name to make it easier to select in the Signal Viewer.

Note: You need to specify 'pa_shell' to start the shell and execute the 'CreateGraph' command.

Example
% pa_shell
pa_shell % CreateGraph -class clock -power_db_name my.pdb
-graph_output_file power_savings.ptcl

This command generates a PTCL file where the X-axis is the total number of reduction opportunities
and the Y-axis is the cumulative savings opportunity. The reduction opportunities are sorted so that
the opportunities that provide the highest savings are closest to the Y-axis. A typical graph quickly
rises and then asymptotically approach 100% of your total savings. You see quite often that 80% of
total savings are achieved in a small fraction of the total gating opportunities.

3. View the waveform using the following process:

a. Type 'PowerArtist' to bring up the GUI.

b. From the PowerArtist main menu, select Tools > Signal Viewer.

c. Delete the default '*.fsdb' in the file browser and replace with '*.ptcl' and click 'Enter'.

d. Select the '.ptcl' file you just created. The waveform loads automatically.

PowerArtist displays the effectiveness curve in the 'View' tab.

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Examining and Implementing Power Reduction Opportunities

4. Examine the graph and look for a good cut-off point where you think the additional clock gating
opportunities, while potentially saving power, are not worth the downstream design impacts. This
is typically at the 'knee of the curve'. The point on the Y-axis is the number you specify with the
'-constraints_savings' option of the 'WriteClockGatingConstraints' command.

Figure 15.12: Sample Clock Gating Effectiveness Waveform

In the sample waveform, the coordinates of the selected point are '14.0' and '618.517'. Therefore,
specify the 'WriteClockGatingConstraints -constraints_savings 618.517' command.

5. Run the 'WriteClockGatingConstraints' command to generate the constraints. The syntax is as

follows:
WriteClockGatingConstraints -power_db_name pdb_file
-top module_name
-constraints_savings float
[-constraints_bus_naming_style string]
[-constraints_log file_name]
[-constraints_output_file file_name]
[-constraints_synthesis_tool PC]

For complete descriptions of the options of this command, see the description in the 'PowerArtist
Reference Manual'.

Note: Whenever you run the 'ReducePower' command, reduction data is stored in a power database
(.pdb) file. This is the file you specify with the '-power_db_name' option.

When the 'WriteClockGatingConstraints' command runs, it creates a constraint file that can be
read by your synthesizer. For PowerCompiler™, the constraints are in the form of
'-exclude_instances' constraints to the 'set_clock_gating_registers' command.

• Example 1
WriteClockGatingConstraints -constraints_savings 30e-06
-power_db_name my.pdb -constraints_output_file my.con

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 Recommended Flow for Implementing Power Reductions

In this example, PowerArtist sorts the reduction opportunities from highest to lowest power
savings and selects 30 uW as the cut-off point. This means that once the constraints savings
value of 30 uW is reached, by the top X opportunities, all other opportunities are excluded
from the resulting constraint file. The power database to be analyzed is 'my.pdb' and the
constraints are output to the 'my.con' file.

• Example 2
WriteClockGatingConstraints -bus_naming_style %s_%d
-power_db_name my.pdb -constraints_output_file my.con

In this example, other constraints you supply to PowerCompiler™ control the

'-bus_naming_style'. The '-exclude' constraints generated by the
'WriteClockGatingConstraints' command must match the naming style. In this case, the
naming style is '%s_%d'.

Sample Output Constraint Files

• Example 1: Output using the default bus naming style for specified constraints savings
set_clock_gating_registers -exclude_instances { cnt3_reg[11] cnt3_reg[10]
cnt3_reg[9] cnt3_reg[8] cnt3_reg[7] cnt3_reg[6] cnt3_reg[5] }
set_clock_gating_registers -exclude_instances { cnt1_reg[15] cnt1_reg[14]
cnt1_reg[13] cnt1_reg[12] cnt1_reg[11] cnt1_reg[10] cnt1_reg[9] cnt1_reg[8]
cnt1_reg[7] cnt1_reg[6] cnt1_reg[5] cnt1_reg[4] cnt1_reg[3] cnt1_reg[2] cnt1_reg[1] cnt1_reg[0] }

• Example 2: Output using specified bus naming style for maximum constraints savings
set_clock_gating_registers -exclude_instances { cnt3_reg_11 cnt3_reg_10 cnt3_reg_9
cnt3_reg_8 cnt3_reg_7 cnt3_reg_6 cnt3_reg_5 }

In the constraint file, you some constraints may be commented using the '#' character, as shown in
the next example.

• Example 3: Output that includes lines that are commented

set_clock_gating_registers -exclude_instances { q3_reg_11 q3_reg_10 q3_reg_9 }
# set_clock_gating_registers -exclude_instances { q1_reg[2] q1_reg[1] q1_reg[0] }

The commented constraints are those registers that are below the '-min_bit_width'. PowerArtist
does not explicitly exclude these registers because a synthesis tool, with its better optimization, may
find them to be part of larger register bank and therefore may decide not to exclude them. If
PowerArtist excludes these registers, synthesis tools would never be able to include them. They are
present in the file only for reference. The 'uncommented' constraints are those that PowerArtist has
decided to exclude because they do not save power and their bit-width is above the
'-min_bit_width'.

15.8. Recommended Flow for Implementing Power Reductions

You should use the following flow when implementing reductions:

1. Run the 'Elaborate' command to perform logic inferencing on your design.

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Examining and Implementing Power Reduction Opportunities

2. Perform vector analysis using PowerArtist on the available RTL simulation data and inspect the
activity profiles. You can use a scripted flow that includes the 'GenerateActivityWaveforms'
command.

3. Choose a set of vectors and intervals with a reasonable level of activity that is representative of
normal device operation.

The vectors you choose for power reduction analysis are different from those you choose to stress
test the power distribution network with voltage drop analysis. For the latter, you can choose to
maximize activity. If you use the same vectors for power reduction, then there are fewer opportunities
on which to apply the LNR PowerBot to registers with normally low activity. These high-activity
vectors can also cause existing 'clock enables' to always 'be enabled'. Therefore, propagating them
forward with Prism saves little power. If you choose a vector set with too little activity PowerArtist
might insert too many clock gating opportunities, which can cause physical layout problems for
clock networks at the P&R phase or can increase power consumption.

4. Run the 'ReducePower' command with the vector set (s) you chose.

You are likely run reduction more than once. On your initial run, enable all reductions. PowerArtist
attempts to select the power reductions that provide optimum power savings. For example, it
chooses the ODC over LNR. Also, by enabling all reductions you see the power savings that are likely
in memories and, potentially, any power you might be wasting (with the linter PowerBots) due to
inefficient clock enables. After you get a profile of the potential power savings from each reduction
class, you can re-run PowerArtist and disable reduction classes you do not want to consider.

5. When you are done with your reduction runs, inspect the '.rpt' file:

a. Note the clock gate percentage.

Is it about what you expected? If it's greater than 85%, the clock-based power savings are limited.
If the clock gating percentage is very high, it indicates that you can encounter problems with
clock tree synthesis and P&R so use PowerArtist to reduce the number of gated registers with
only a minimal impact on power savings. You should use the synthesis constraint generation
feature of the LEC PowerBot (see Step 3 in Running PowerArtist Clock PowerBots (p. 345)) to
specify registers that should not be clock gated by your synthesis tool.

b. Focus on the dynamic power savings in the core to see what is worth doing. If you look for the
total power savings, you can conclude that there is nothing worth doing because real power
savings are masked by high static power or high I/O power.

c. Note which reductions PowerArtist found and which of those were auto-accepted. If you see a
lot of savings in your memories, it might be best to redesign the memory architecture and usage
rather than rewriting the RTL.

6. If you want to control which reductions are rewritten, invoke the PowerArtist PowerCanvas and use
the reduction dialogs to reject or accept reductions for rewrite. You can easily do this by filtering
on specific reductions or modules. For details, see Filtering Reduction Results (p. 87) in the reduction
tutorial.

7. Run PowerArtist again to verify the power savings.

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 Viewing Reduction Results

Controlling Clock Domains During Reduction

During reduction, you may want PowerArtist to analyze certain clock domains but not automatically
rewrite them. The 'ReducePower -reduction_dont_touch_clocks {}' command allows you to
specify a list of clock domains to be analyzed but not automatically rewritten. This option accepts a Tcl
list of hierarchical net names:
-reduction_dont_touch_clocks {clock_net1 clock_net2 ...}

The effect of this option depends on the setting of the 'SetClockNet -gate_clock <true |
false>' command:

• If you specify 'SetClockNet -gate_clock true', then:

– The LEC PowerBot is not run for any clock domain. To run LEC on any clock net, you must
set '-gate_clock false'. See section Usage (p. 284) in Local Explicit Clock Enable
(LEC) (p. 283) for details.
– All other reductions that are discovered and can be automatically rewritten are marked
as 'accepted' in the reduction dialogs.

• If you specify 'SetClockNet -gate_clock false', then:

– The LEC PowerBot runs for that clock domain assuming that all other clocks are also
marked as '-gate_clock false'.
– All reductions that are found are accepted for 'automatic rewrite' in the reduction dialogs.

• If you specify '-gate_clock true' and '-reduction_dont_touch_clocks {}' for the

same net name, then no reductions are accepted for 'automatic rewrite' in the reduction dialogs.

This behavior allows you to indicate that while synthesis-based clock gating is performed on the
net, reductions for that net are not 'automatically accepted' for rewrite.

Note: In the 'design.rpt' file, reductions that can be accepted for rewrite are marked as
'Potential' reductions. An example of a report of the LNR reduction technique is shown below:
Core Techniques Dynamic Saving Total Saving
---------------------------------------------------------------------
Low activity non-enabled register :
Auto-accepted (width <= 16bits) : 0W 0.00% 0W 0.00%
Potential : 18.8uW 89.77% 18.7uW 89.52%

In this example, the option '-reduction_dont_touch_clocks clk' was specified, which

prevented a number of LNR opportunities from being auto-accepted.

If you specify a root clock with the '-reduction_dont_touch_clocks {}' option, then
the root clock and children clocks traceable from the root clock are not processed by PowerArtist.

15.9. Viewing Reduction Results

You can review the reduction results using the PowerArtist GUI and text reports generated during a
power reduction run. These are explained in the next sections.

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Examining and Implementing Power Reduction Opportunities

15.9.1. Viewing Reduction Results-GUI

To review the reduction results using the PowerArtist GUI, select one of the last three items under
the 'View' menu:

• Simple Power Reductions

• Linter Power Reductions
• Advanced Power Reductions

15.9.2. Viewing Reduction Results-Text Reports

The next sections describe a summarized list of reports generated after a power reduction run.

15.9.2.1. Power Reduction Summary Report

This report summarizes wasted and saved power by technique:

pa_shell Variable/Command Default Value

reduction_threshold 0
Effect: If above zero, specifies the percentage of total power that an opportunity must
reduce/waste power by to be included in this report.

15.9.2.2. Power Reduction Report

The 'ReportReductions' command generates a CSV file where each row contains data for a power
reduction opportunity on a specific instance and a graph of power savings versus implementation
effort.

pa_shell Variable/Command Default Value

reduction_report_csv_file
Effect: Specifies the path where the CSV file should be written.
reduction_report_csv_separator ,
Effect: Specifies the field separator for CSV file.
reduction_report_detail false
Effect: If true, includes additional columns with detailed information in CSV file.
reduction_report_instance *
Effect: Glob-style pattern to determine which instances to include in the report.
reduction_report_log_file ReductionReport.log
Effect: Specifies the path where the report generation log should be written.
reduction_report_module *
Effect: Glob-style pattern to determine which modules to include in the report.
reduction_report_negative_reductions false
Effect: If true, includes power reduction opportunities with negative power savings in the report.
reduction_report_reduction_types all

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 Viewing Reduction Results

pa_shell Variable/Command Default Value

Effect: Specifies which power reduction techniques to include in the report.
reduction_report_type power_savings
Effect: If 'power_savings', is specified, a CSV file with wasted or saved power per instance is
generated. If 'reduction_vs_effort' is specified, a graph of power savings versus effort is
generated.

15.9.2.2.1. Reporting Total Saved Power

The 'total saved power' calculation is improved to eliminate redundant savings that occur
when multiple reduction techniques are applied to the same candidate instance. With this, a
unified total saved power calculation is implemented for both GUI and reduction report (generated
through the 'ReportReductions' command). The saved power of the reduction technique with
the highest saved power (among the overlapping reduction techniques) is added to the 'total
saved power'. There are two exceptions and they are:

• GMC and MEM reporting on the same memory instance are not considered overlapping
and therefore, the power saved by both these reduction techniques is added to the 'total
saved power'. GMC and MEM are not considered overlapping because GMC reports power
saved on memory clock pin and MEM reports power saved on data/address ports.

• A Prism candidate of 'easy' category has higher priority. This means that if an instance
is reported by Prism as 'easy' category, then the power saved from Prism is also (including
the other reduction techniques) added to the 'total saved power'.

15.9.2.3. Clock Gating Report

This is a clock gating efficiency report with metrics for each clock domain and each logical hierarchy.
Optionally, metrics can be generated for every instance if desired

pa_shell Variable/Command Default Value

reduction_clock_gating_report <design_name>_cg.srpt
Effect: Specifies path where the clock gating report is written. Refer section 'Clock Gating
Report (p. 356)' for details.
reduction_report_bitwise_clock_gating false
Effect: If true, includes clock gating data for each register bit in the report.
reduction_report_clock_gating_by_instance false
Effect: If true, includes clock gating data for each register instance in the report.
reduction_report_clock_gating_enable_efficiency false
Effect: If true, includes a separate section for CGEE and wasted clock pin power in the report.
reduction_report_hierarchical_clock_efficiency false
Effect: If true, includes a section with data for each element in the clock tree. Refer section
'Hierarchical Clock Efficiency Report (p. 367)' for details.
reduction_report_max_enable_terms 10

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Examining and Implementing Power Reduction Opportunities

pa_shell Variable/Command Default Value

Effect: If the number of terms in clock enable expressions is more than the default value, the
clock enable expression is replaced by an inferred name. Changing the value of this variable to
'0' removes the limit.
reduction_report_levels all
Effect: If the number is equal to or greater than zero, specifies the hierarchical levels below top
to include in the report.
reduction_report_use_zf_in_cgee false
Effect: If true, includes registers with zero clock frequency in hierarchical CGEE calculations.
reduction_split_clock_gating_report false
Effect: If true, generates a separate file for each section of the report.

15.9.2.4. ODC-by-Enable Report

Each unique suggested enable expression is listed in this report along with the affected instances
and their power savings and clock gating efficiency improvements:

pa_shell Variable/Command Default Value

reduction_odc_by_enable_report <design_name>_odc_by_enable.rpt
Effect: Specifies path where the 'ODC-by-enable' report is written.

15.9.2.5. STC-by-Enable Report

Contains information about the STC enable expressions:

pa_shell Variable/Command Default Value

reduction_stc_by_enable_report <design_name>_stc_by_enable.rpt
Effect: Specifies path where the 'STC-by-enable' report is written.

15.9.2.6. Redundant Reset Report

Registers can be without a reset state if they are unobservable when the reset is asserted. A report
that lists these registers can be generated if desired:

pa_shell Variable/Command Default Value

reduction_report_redundant_resets false
Effect: If true, generates the redundant reset report.

15.9.2.7. Memory Access Report

This is a CSV file where each row contains access activity and power data for each port on each
memory instance:

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 Viewing Reduction Results

pa_shell Variable/Command Default Value

memory_access_report
Effect: Specifies the path where the memory access report should be written. Refer section
'Memory Access Report (p. 367)' for details.

15.9.2.8. Memory Linter Report

This is a CSV file where each row contains wasted power data for each bus/pin on each memory
instance.

pa_shell Variable/Command Default Value

reduction_memory_linter_report memory_linter_report.csv
Effect: Specifies the path where the memory access report should be written. Refer section
'Memory Linter Report (p. 369)' for details.

15.9.2.9. Macro Power Linter (MPL) Report

This report highlights redundant activity detected on macro and memory instances:

pa_shell Variable/Command Default Value

SetMacroPowerLinterReportFile mpl.analysis.red
Effect: Sets the path where the MPL report is written.

15.9.3. Blocks Activity Ranking Report

There are many power-saving opportunities that cannot be discovered solely by iterating over leaf-level
instances. A design should also be viewed from the block level to determine if power is wasted due
to redundant activity at a block's interfaces. If this is the case, you should implement clock- and
data-gates to reduce power consumption.

Block Activity Ranking (BAR) analysis highlights redundant clock and data activity at the interfaces of
each user-defined block in a design. For each block containing sequential elements, the data includes
the activity metric for the clock signals. For each clock input, the associated data inputs (inputs that
drive sequential instances clocked by the clock input) and their activities are also listed. Asynchronous
reset inputs are not included in the report/s.

These reports are generated:

• Comma-Separated Value (.csv) Report

The CSV report contains block-specific data and includes:

– Block name
– Hierarchical level of block in design

A sample output is shown below:

Block Name,Hierarchical Level,Total Power,Percentage of Top Total Power,Total
Clock Power,Clock Activity,Data Activity
top.core1,1,0.017504,99.743,0.00025742,1.3325,0.30024
top.core1.t1,2,0.0091785,52.301,3.2215e-05,1.9988,0.4513

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top.core1.t1.dpmem,3,0.0091215,51.976,4.192e-06,1.4981,0.38417
top.core1.r1,2,0.0073569,41.921,2.0215e-05,1.9988,0.31935
top.core1.r1.dpmem,3,0.007311,41.659,3.2203e-06,1.1599,0.12807
<snip>

• Text (.txt) Report

A well formatted text report is also generated. The reports consists of two sections:

– Summary

This section is identical to the information in the '.csv' report.

– Details

This section is in addition to the 'Summary' section. A sample output is shown below:
<snip>
2. Details

Activity : Average activity of all nets connected to the port

% of Clock : Percentage of associated clock activity that the data port has
Source : Method of activity calculation

Level 1

clogic top.core1

Static Logic Power : 0.0039831

% of Top Static Logic Power : 98.879
Dynamic Logic Power : 0.013264
% of Top Dynamic Logic Power : 100
Total Logic Power : 0.017247
% of Top Total Logic Power : 99.739
Static Clock Power : 1.6722e-07
% of Top Static Clock Power : 100
Dynamic Clock Power : 0.00025725
% of Top Dynamic Clock Power : 100
<snip>

15.9.4. Clock Gating Report

The clock gating report 'reduce_power_cg.rpt' generated during power reduction provides
detailed information about clock gating in this design. It provides:

• a measure of the static and dynamic clock gating efficiency in the design.
– Static clock gating efficiency is a vector-independent measure of the clock gating coverage
of the design.
– Dynamic clock gating efficiency is a vector-dependent measure of the clock gating
effectiveness of the design.

• information on the number of bits that will be clock gated by synthesis as well as additional
clock gating identified by the PowerArtist power reduction techniques.

The report further breaks down the clock gating information on a per-clock and per-hierarchical
instance basis.

With the report providing both a high-level and a detailed view of the clock gating status in the
design, you can quickly identify the right areas on which to focus your power reduction efforts.

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The report has a header section and seven body sections. The header section includes information
such as the run date and program information (date and version). In addition, the header section
includes a Note section that defines some of the symbols and terms used in this report. It provides
information on how PowerArtist calculates certain values. A sample output is shown below:
POWER REDUCTION CLOCK GATING REPORT
===================================
<snip>
Note:
'-' : indicates unknown value
Enabled : Bits with a synchronous load-enable or a clock-enable
Inferred Clock Gating : Bits that synthesis will add clock gates for
<snip>
Clock Gating Enable Efficiency:(100 * ((data_toggle_cycles)/total_enabled_cycles))%

The top-level body sections in the clock gating report are described in the next sections.

15.9.4.1. Clock Gating Constraints

This section provides the constraint values (such as minimum register bank size, minimum register
bank size for enhanced clock gating, maximum clock gate fanout, and maximum register bank size
for LNR reduction) that were applied during reduction analysis. It also lists the corresponding
command-line option from which the constraint was defined. For example:

• SetClockGatingStyle -min_bit_width

or

• ReducePower -reduction_max_bit_width

A sample output is shown below:

1. Clock Gating Constraints
===========================
Minimum register bank size (min_bit_width) : 3
Minimum register bank size for enhanced clock gating (min_bit_width_ecg) : 6
Maximum clock gate fanout (max_bit_width) : -
Maximum register bank size for applying LNR reduction (reduction_max_bit_width):16

15.9.4.2. Clock Gating Summary

This section reports both static and dynamic components of power for the hierarchical and leaf-level
sections and is broken into three subsections:

• Clock Gating Summary for Flops

• Clock Gating for Flops by Reduction
• Clock Gating Summary for Latches

3.2.1 Clock Gating Summary for Flops

This section provides basic statistic on the flops in the design-total flops, enabled flops, and inferred
gated flops). It also lists the number of flops that were excluded from inferred gating, broken down
by the reason for the exclusion. In addition, it provides three data points (before reduction, after
reduction and improvement percentages) for clock gating efficiency and clock gating of the flops
in the design.

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Clock gating efficiency is broken into static and dynamic values, which are calculated as follows:
Static Clock Gating Efficiency = (100 * (gated_flops/total_flops))%
Dynamic Clock Gating Efficiency = (100 * (gated_cycles/total_cycles))%

A sample output is shown below:

2. Clock Gating Summary
=======================

2.1 Clock Gating Summary For Flops

Total enabled flops : 481 ( 69.41% )

Total inferred gated flops : 467 ( 67.39% )

Flops excluded from inferred gating
Lack of enable : 212 ( 30.59% )
Bank width too small : 14 ( 2.02% )
Instantiated flops : 0 ( 0.00% )
Total flops : 693

Before Reduction After Reduction Improvement

-----------------------------------------------------
Clock Gating Efficiency :
Static : ( 67.39% ) ( 68.69% ) ( 1.30% )
Dynamic : ( 63.67% ) ( 65.75% ) ( 2.08% )
Data Aware : ( 67.53% ) ( 69.61% ) ( 2.08% )

Clock Gating :
Inferred : 467 ( 67.39% ) 476 ( 68.69% ) ( 1.30% )
Instantiated : 0 ( 0.00% ) 0 ( 0.00% ) ( 0.00% )
Inferred and Instantiated : 0 ( 0.00% ) 0 ( 0.00% ) ( 0.00% )
None : 226 ( 32.61% ) 217 ( 31.31% ) ( 1.30% )

For example, in the tutorial, the static clock gating efficiency for flops before reduction was
approximately '67.39%' before reduction and '68.6%' after reduction, which is a '1.3%'
improvement.

The Clock Gating Efficiency (CGE) value for the design is computed and reported based on the total
flop count. In some cases, it was found that CGE values were reported lower than they were because
of their dependency on untraced flops in the design.

You can control the calculation method of CGE values. You can choose to compute CGE based on
all (traced and untraced) flops in the design or based only on the traced flops in the design. You
can enable this by using the following variable:
pa_set ignore_untraced_flops_cge <true | false>

The default value of the variable is 'false' (where CGE values are computed based on all flops in
the design). Setting it to 'true' enables CGE computation based only on traced flops.

3.2.2 Clock Gating for Flops by Reduction

This section provides the numbers and percentages of flops in the design that were clock-gated
by a particular reduction techniques (such as, Prism and Observability Don't Care). It further breaks
down each category by how the gating was applied (Auto-accepted, Strengthened and Potential).

A sample output is shown below:

2.2 Clock Gating For Flops By Reduction
Flops Percent

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-----------------------
Low activity non-enabled register :
Auto-accepted (width <= 16bits) : 9 1.30%
Potential : 78 11.26%
Low activity enabled register :
Auto-accepted (width <= 16bits) : 3 0.43%
Potential : 3 0.43%
Observability Don't Care :
Auto-accepted : 0 0.00%
Strengthened : 64 9.24%
Potential : 64 9.24%

3.2.3 Clock Gating Summary For Latches

This section provides basic statistics on the latches in the design (total latches, inferred latches,
instantiated latches) as well as information on clock gating efficiency and clock gating for the
latches, which is very similar to that for the flops as described earlier.

A sample output is shown below:

2.3 Clock Gating For Latches

Total latches : 0
Total inferred latches : 0 ( 0.00% )
Total instantiated latches : 0 ( 0.00% )
Clock Gating Efficiency :
Static : ( - )
Dynamic : ( - )
Data Aware : ( - )

Clock Gating :
Instantiated : 0 ( 0.00% )
None : 0 ( 0.00% )

15.9.4.3. Clock Gating by Clock

This section provides clock gating information on a clock-by-clock basis. For a given clock, this
section summarizes the status of the clock gating. The Flop and Latch Summary sections for each
clock list the total enabled flops/latches, inferred gated flops/latches, clocks excluded from inferred
gating (by reason of exclusion), and total flops/latches. The tool does not support calculation of
CGE metrics for macros with multiple clock pins.

A sample output is shown below:

3. Clock Gating by Clock
========================

3.1 Clock Root : top.clk

Clock Gating : On
Frequency : 66.5MHz
Static Power : 121nW ( 0.11% )
Dynamic Power : 111uW ( 99.89% )
Total Power : 111uW

3.1.1 Clock Gating Summary For Flops

Total enabled flops : 377 ( 83.41% )

Total inferred gated flops : 376 ( 83.19% )
Flops excluded from inferred gating
Lack of enable : 75 ( 16.59% )
Bank width too small : 1 ( 0.22% )
Instantiated flops : 0 ( 0.00% )
Total flops : 452

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Before Reduction After Reduction Improvement

-----------------------------------------------------
Clock Gating Efficiency :
Static : ( 83.19% ) ( 85.18% ) ( 1.99% )
Dynamic : ( 78.31% ) ( 80.55% ) ( 2.23% )
Data Aware : ( 83.02% ) ( 85.26% ) ( 2.23% )

Clock Gating :
Inferred : 376 ( 83.19% ) 385 ( 85.18% ) ( 1.99% )
Instantiated : 0 ( 0.00% ) 0 ( 0.00% ) ( 0.00% )
Inferred and Instantiated : 0 ( 0.00% ) 0 ( 0.00% ) ( 0.00% )
None : 76 ( 16.81% ) 67 ( 14.82% ) ( 1.99% )

3.1.2 Clock Gating Summary For Latches

Total latches : 0
Total inferred latches : 0 ( 0.00% )
Total instantiated latches : 0 ( 0.00% )
Clock Gating Efficiency :
Static : ( - )
Dynamic : ( - )
Data Aware : ( - )

Clock Gating :
Instantiated : 0 ( 0.00% )
None : 0 ( 0.00% )
<snip>

15.9.4.4. Clock Gating by Instance - Summary

This section provides clock gating information on a clock-by-clock basis and on a per-hierarchical
instance basis. For a given instance, this section summarizes the status of clock gating that instance
and then it reports how that register may or may not be clock gated. Additionally, per instance
clock gating efficiency data for non-leaf (design and instance-level) instances is reported.

The Clock Gating by Instance reporting automatically detects latches that are intended in the design
for existing clock-gating. Such latches are not considered for any clock-gating or in clock gating
efficiency calculations.

This section also reports the flop power, flop activity, latch power, and latch activity metrics
per-hierarchical instance. It also reports the root clock for every flop and latch in the design. The
full instance path is used to report the hierarchical instance names. Finally, the clock gating efficiency
numbers for leaf level instances are also reported.

The report is sorted hierarchically in the descending order of clock gating inefficiency. The clock
gating inefficiency of an instance is calculated as:
(Total_Flops * (100 - DACGE))

For same value of inefficiency, the report is sorted in descending order of 'Total_Flops' and
'Total_Power'. If none of the sorting criteria holds, sorting is alphabetical.

A sample output is shown below:

4. Clock Gating by Instance - Summary
=====================================

Note: SCGE : Static Clock Gating Efficiency

DCGE : Dynamic Clock Gating Efficiency
DACGE : Data Aware Clock Gating Efficiency

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ECG : Enhanced Clock Gating

ZF : Zero Source Clock Frequency

4.1 Clock Gating Summary for Flops

Total Flop Flop Initial Final Improvement Instance

Flops Power Activity Gated SCGE DCGE DACGE Gated SCGE DCGE DACGE Gated SCGE DCGE DACGE Name
----------------------------------------------------------------------------------------------
693 806uW 0.077 467 67.39 63.67 67.53 476 68.69 65.75 69.61 9 1.30 2.08 2.08 top
693 806uW 0.077 467 67.39 63.67 67.53 476 68.69 65.75 69.61 9 1.30 2.08 2.08 -top.core1
...
2 12.1nW 0.000 0 0.00 ZF ZF 0 0.00 ZF ZF 0 0.00 - - --top.core1.j1

<snip>

15.9.4.4.1. Reporting Toggle Numbers for Clock Gating Activity

The pa_set variable, reduction_report_clock_gating_toggles, reports clock gating
activity in terms of toggles. By default, the variable is set to false.

To report clock and data activity in terms of toggles, use the following command:
pa_set reduction_report_clock_gating_toggles true

You can also configure the setting using the ReducePower command as follows:
ReducePower -report_cg_toggles

This variable enhances the text report, reduce_power_cg.rpt, with toggle data recorded in
the Clock Gating by Instance - Summary section. The report contains clock, data in, and data
out activities in terms of toggle numbers.

The following snippet shows the difference in reports with the

reduction_report_clock_gating_toggles variable set to false and true:

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15.9.4.5. Clock Gating by Instance - Details

This section is an extension of the previous section. The details of leaf level instances are also
reported in this section. This is not generated by default and if you want PowerArtist to generate
this section, you need to specify the following option to the 'ReducePower' command:
-reduction_report_clock_gating_by_instance true

This section reports:

• the actual width and all output nets of an instantiated MBF flop.
• the enable expression besides clock and root clock name in section 5.1.
• the ECG enable expression for ECG registers, which are consistent with the ECG enable
expression reported in section 5.1.
• the wasted clock pin power for each row in section 5.1, which includes clock activity if gated
cycles are not detected.
Note: This based on the instance-based CGEE and the values can, therefore, differ from the
enable-based wasted clock pin power reported in section 6 (Clock Gating Enable Efficiency)
of this report.
• An asterix (*) is added to the DACGE numbers (CGEE and WCPP columns) if the following
variable is not specified or is set to 'false':
pa_set reduction_time_based_dacge true

Refer to the PowerArtist Reference Manual for details of this variable.

A sample output is shown below:

5. Clock Gating by Instance - Details
=====================================

Note: (U) : Sequential elements not traced as part of a clock domain

(O) : Some bits of the sequential element were optimized
* : Activity (Clock/Data) is not from Simulation

5.1 Clock Gating Details for Flops

Initial Final
Gating Technique Width Power Activity DCGE DACGE DCGE DACGE Flop Name(Clock, Root Clock)
----------------------------------------------------------------------------------------------
None 64 31.7uW 0.000 0.00 0.00 0.00 0.00 top.core1.<snip>.pci_clk)
None 64 91.8uW 0.163 0.00 8.15 0.00 8.15 top.core1.<snip>.pci_clk)
...
None 1 12.1nW 0.000 ZF ZF ZF ZF top.core1.<snip>top.tck)
None 1 12.1nW 0.000 ZF ZF ZF ZF top.core1.<snip>top.tck)

5.2 Clock Gating Details for Latches

<snip>

The meaning of the legend is given below:

• 'O' is appended to the end of line if the instance is optimized.

• 'U' is annotated for sequential elements/instances that could not be traced to a clock source,
and thereby not considered for inferred clock gating.

• '*' is annotated to clock/data I/O activities if they are not from simulation.

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15.9.4.6. Clock Gating Enable Efficiency

To display clock gating enable efficiency in the reduction power report, you need to enable it by
specifying the following option to the 'ReducePower' command:
-reduction_report_clock_gating_enable_efficiency true

The section reports the Clock Gating Enable Efficiency (CGEE) metric. CGEE identifies and quantifies
the scenarios when the data is stable over a period of time and the flop is unnecessarily getting
clocked. The intent of this metric is to enable you to quickly identify and debug hierarchies/instances
that are not power-efficient by doing a cycle-by-cycle analysis of clock, data, and enable (if present).

These are the highlights of the CGEE metric:

• A low CGEE value for a flop signifies the clock is not well gated. A high CGEE value for a flop
signifies the clock is well gated.
• CGEE applies to both gated and ungated flops in the design. For an ungated flop, the enable
condition is assumed to be always enabled.
• CGEE is reported on a per enable basis and not per register instance basis. Registers that
share the same enable have the same CGEE values.
• CGEE is extended to both leaf-level clock gating enables and instantiated gating enables.
Registers that are driven by ICGCs having common enables will have the same CGEE values.
• CGEE does not consider enhanced clock gating enables. Instead, it uses the RTL enable. The
intent is to fix the RTL and not the implementation.
• The CGEE value for an ungated register is equal to its data activity, which is calculated after
removing the overlapping toggles of its bits.
• Flop outputs are monitored by delaying the calculations by one clock cycle. This helps in
cases where the flop inputs are from inferred logic and therefore, are not present in the
simulation activity.
• Activity-based calculations are not based on averaging activities (an 'n-bit' counter results
in 'n%' of activity). Instead, CGEE adds the activities of the bits and subtracts the overlapping
toggles.
• In addition to the CGEE metric, the report includes the wasted clock pin power. The wasted
clock pin power represents the switching power of the clock pin of the registers and does
not include any other clock network component.
• You can control the CGEE, DCGE, and DACGE value of zero frequency (ZF) registers for roll-up
calculations by using the following variable:
pa_set reduction_report_use_zf_in_cgee <true | false>

The default value of the variable is 'false'. This means that Zero Frequency (ZF) flops are
ignored from instance-based CGEE calculation. Zero Frequency (ZF) and Fully Gated (FG)
tags are added to ZF and FG flops in the 'Clock Gating Details for Flops' section so they can
be identified as excluded from the calculation. Setting the variable to 'true' ensures that
the following happen for Zero frequency (ZF) flops:
– 100% CGEE is used in instance-based CGEE, DCGE, DACGE calculation.
– The report shows the actual DCGE, CGEE, and DACGE values.

A sample output is shown below:

6. Clock Gating Enable Efficiency
=================================

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Note: CGEE : Clock Gating Enable Efficiency

FG : Completely Clock Gated Flop

6.1 CGEE Summary for Gated Flops

Total Gated CGEE Wasted Clock Instance

Flops Flops (%) Pin Power Name
------------------------------------------------------------
693 467 49.11 6.79uW top
693 467 49.11 6.79uW -top.core1
<snip>
160 160 2.33 2.44uW --top.core1.s1
138 64 98.25 88.3nW --top.core1.u1

6.2 CGEE Summary for Ungated Flops

Total Ungated CGEE Wasted Clock Instance

Flops Flops (%) Pin Power Name
-------------------------------------------------------------
693 226 19.18 83.5uW top
693 226 19.18 83.5uW -top.core1
<snip>
160 0 - - --top.core1.s1
138 74 43.39 17.9uW --top.core1.u1

6.3 CGEE Details for Gated Flops

Total CGEE Wasted Clock Flop Name

Width (%) Pin Power (Clock, Root Clock)
------------------------------------------------------------
8 100.00 0W top.core1.r1.f1.wrcntr.<snip>.pci_clk)
4 8.18 270nW top.core1.r1.f1.wrcntr.<snip>.pci_clk)
<snip>
32 FG - top.core1.s1.<snip> top.clk)
64 98.25 88.3nW top.core1.u1.<snip> top.clk)

6.4 CGEE Details for Ungated Flops

Total CGEE Wasted Clock Flop Name

Width (%) Pin Power (Clock, Root Clock)
------------------------------------------------------------
8 100.00 0W top.core1.r1.f1.wrcntr.<snip>.pci_clk)
4 8.18 270nW top.core1.r1.f1.wrcntr.<snip>.pci_clk)
<snip>

The CGEE section of the report contains the following information also:

• Local enable function

This is the enable signal or function within the instance hierarchy and it is reported for both
gated and ungated flops (inferred and instantiated).

• Calculation type

CGEE calculation can be one of the following:

– Cycle-based:

CGEE is cycle-based when both the enable and flop output are present in the
simulation activity.

– Activity-based:

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CGEE is activity-based when the enable is:

present but one or more flop outputs are not present in the simulation activity.
not present but all flop outputs are present in the simulation activity.
not present and one or more flop outputs are not present in the simulation
activity.

In addition to the CGEE metric, 'ReducePower' also reports the wasted clock pin power. The wasted
clock pin power represents the switching power of the clock pin of the registers and does not
include any other clock network component.

15.9.4.7. Clock Gating by Clock Hierarchy

'ReducePower' has a comprehensive design exploration framework for clock, data, and power
efficiencies. It provides various metrics that enable easy identification of power-inefficient spots at
multiple levels of abstractions. The recommended approach is to identify the power-inefficient
block first and then move to the next level of abstraction to debug the power hotspot.

This section reports clocking efficiency per level of clock hierarchy. The clock nets are arranged in
the form of a hierarchy starting from the root. The clocking efficiency and switching activity
distribution of data is reported at every hierarchical clock element level. There are two sub-sections:

• Clock Hierarchy Summary that reports data by clock by clock hierarchy level
• Leaf Level Clock Details that reports data by flop by clock. The flops in this section are sorted
in the descending order of clocking inefficiency.

This section enables effective clock power debug by identifying the least powerefficient clocking.
You can generate this section by using the following variable:
pa_set reduction_report_hierarchical_clock_efficiency true

A sample output report is shown below:

7. Clock Gating by Clock Hierarchy
==================================

Note: (U) : Sequential elements or clocks not traced as part of a clock domain
Bus Activity : Activity of bits as a group
Clock Activity : Gated activity of clock to the group of bits
Downstream Clock Power: Downstream dynamic clock power (including clock pin power)

7.1 Clock Hierarchy Summary

Clock : top.clk2 ( clk2 ) (71.5MHz)

-------------------------------------------------------------------
Level | Type | In Freq | Out Freq | Gating | Downstream |
| | (Hz) | (Hz) | Efficiency | Clock Power|
--------------------------------------------------------------------
0 root - 71.5MHz - 26.3uW
1 mux 71.5MHz 71.5MHz 0.00 16uW
2 cg 71.5MHz 66.3MHz 7.21 6.86uW
1 cg 71.5MHz 66.3MHz 7.21 1.06uW
--------------------------------------------------------------------
----------------------------------------------------------------------
Direct Sinks | Activity |
Flop | Latch | Memory | CG | Bbox | Min | Avg | Max |
---------------------------------------------------------------------
9 0 0 1 0 0.01 0.27 0.36
16 0 0 1 0 0.01 0.13 0.23
14 0 0 0 0 0.01 0.10 0.20

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2 0 0 0 0 0.31 0.32 0.33

---------------------------------------------------------------------
------------------------------------------------------------------------------------------
Activity Distribution (%) | Clock
0 | 0-20 | 20-40 | 40-60 | 60-80 | 80-100 | 100 |
------------------------------------------------------------------------------------------
0.00 55.56 22.22 22.22 0.00 0.00 0.00 clk2
0.00 68.75 31.25 0.00 0.00 0.00 0.00 -top.muxed_clk
0.00 71.43 28.57 0.00 0.00 0.00 0.00 --top.muxed_clk_hier.gg_clk
0.00 0.00 0.00 100.00 0.00 0.00 0.00 -top.two_clock_hier0.gclk2
-------------------------------------------------------------------------------------------

7.2 Leaf Level Clock Details

Clock : top.clk2 (71.5MHz)

Root clock : top.clk2 (71.5MHz)
----------------------------------------------------------
Width | Bus | Clock | Activity |
| Activity | Activity | Min | Avg | Max |
------------------------------------------------------------
1 50.909 1.410 0.359 0.359 0.359
1 52.000 1.282 0.333 0.333 0.333
7 64.000 1.282 0.013 0.104 0.205
-------------------------------------------------------------
-----------------------------------------------------------------------------------------------
Activity Distribution (%) | Flop Name (Clock, Root Clock)
0 | 0-20 | 20-40 | 40-60 | 60-80 | 80-100 | 100 |
-----------------------------------------------------------------------------------------------
0.00 0.00 0.00 100.00 0.00 0.00 0.00 top.two_clock_hier0.ungated_flop2.dout[0]()
0.00 0.00 0.00 100.00 0.00 0.00 0.00 top.two_clock_hier0.enabled_flop2.dout[0]()
0.00 71.43 28.57 0.00 0.00 0.00 0.00 top.two_clock_hier0.inf_gated_flop2.dout[6:0]()
-----------------------------------------------------------------------------------------------

Notes:

• The column 'Downstream Clock Power' reports the clock power consumed by clock buffers,
clock gates, and flop clock pins, downstream to a clock net or a clock gate in the clock tree.
This enables you to identify clock gaters controlling large clock tree power and optimize
their enables to reduce clock power.
• The formula to calculate the downstream clock power includes clock net power, clock gate,
and inferred clock buffer power. It is calculated as the sum of the following:
sum (power of (combinational or sequential) elements from the node to clock pin) +
sum (pin power of each clock pin it is driving) + clock net power +
sum (power of all clock gates driven by clock) +
sum (power of all inferred buffers in the clock tree)

This ensures that the clock power reported in the average power report matches the
downstream clock power reported in this section.

15.9.4.8. Splitting the Clock Gating Report

By default, the clock gating report is a single file. This report can optionally be split by the various
sections in the report by using the following variable:
pa_set reduction_split_clock_gating_report true

If 'reduction_split_clock_gating_report' is used, the following report files are generated:

• Clock Gating Summary - <>_cg_summary.rpt

• Clock Gating By Clock - <>_cg_by_clock.rpt

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 Viewing Reduction Results

• Clock Gating By Instance - <>_cg_by_instance.rpt

• Clock Gating Enable Efficiency - <>_cg_enable_efficiency.rpt

15.9.5. Hierarchical Clock Efficiency Report

Power reduction in PowerArtist has a comprehensive design exploration framework for clock, data,
and power efficiencies. It provides various metrics that enables easy identification of power inefficient
spots at multiple levels of abstractions.

• Design hierarchy level

• Block interface level
• Sequential instance level (flops and latches)
• Individual sequential bit level

The recommended approach is to identify the power inefficient block first and then move to the next
level of abstraction to debug the efficiency.

Power reduction has the capability to report efficiency at the clock hierarchy level. Based on the
derivation, the clock nets are arranged in the form of a hierarchy starting from the root. The efficiency
and switching activity distribution of its data is reported at every level. You can generate the report
by using the following variable:
pa_set reduction_report_hierarchical_clock_efficiency true

15.9.6. Memory Access Report

Memories consume substantial power, and when not operated in a power-efficient manner can lead
to significant wastage of power due to redundant activity. For example, a commonly encountered
power bug is when a memory is left in the read mode by default, even if the memory is not required
to read data. A memory access report identifies such memory power inefficiencies.

The report contains all access information collected during reduction-focused activity analysis, and
is generated as a '.csv' file. Memory access analysis and report generation depend on the following
inputs:

• The activity information at memory inputs, which is available in '.vcd'/'.fsdb' file or the
emulator stream.
• The technology libraries with sufficient energy arc information.
• Any additional port descriptions for memory macros specified through 'DefineMemory'
commands.

Note: The PowerArtist GUI also reports redundant memory accesses but they are a smaller subset as
they are filtered based on power savings. If PowerArtist is unable to figure out a way to reduce
redundant activity on a memory port and save power, then the data for that port is not displayed in
the GUI.

To generate the memory access report, use one of the following sets of commands:

• pa_set memory_access_report <report-file-name.csv>

ReducePower

or

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• pa_set memory_access_report <report-file-name.csv>

GenerateGAF -gaf_enable_reduction_data true

A sample report is shown below:

The following table explains the information in the columns in the report (from left to right):

Column Name Description

Cell Name Cell type of the memory instance.
Instance Name of the memory instance.
Clock Port Clock port on the memory instance for which the access counts
(reported in the next columns) apply.
Total Clock Cycles The total number of clock cycles at the clock port.
No-Access Cycles The number of clock cycles for which the memory was disabled.
Memory Enable Expression Memory enable expression for the cell instances.
Read Cycles The total number of clock cycles for which the memory was in read
mode.
Read Enable Expression Read enable expression for the cell instances.
Write Cycles The total number of clock cycles for which the memory was in write
mode.
Write Enable Expression Write enable expression for the cell instances.
Redundant-Read Cycles The number of clock cycles for which the memory was in read mode
and the read address was stable/unchanging.
Estimated ODC Redundant The estimated number of read cycles that were unobservable. This
Read Cycles is an average-activity-based number calculated by multiplying the
total number of read cycles by the duty cycle of the memory’s ODC
expression.

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 Viewing Reduction Results

Column Name Description

Redundant-Write Cycles The number of clock cycles for which the memory was in write mode
and the write address and input data was stable/ unchanging.
Unknown Cycles The number of clock cycles for which the memory was in an
unknown/unrecognizable state.
Read+Write Cycles The number of clock cycles for which memory was in the read+write
mode.
Redundant R+W Cycles The number of clock cycles for which the memory was in the
read+write mode and the write address and input data was
stable/unchanging.
Redundant Read + Write The number of clock cycles with partially redundant Read-Write
Cycles cycles with only 'Read' as redundant data
Read + Redundant Write The number of clock cycles with partially redundant Read-Write
Cycles cycles with only 'Write' as redundant data.
Conflicting Read + Write The number of clock cycles which have conflicting 'Read' and 'Write'
Cycles addresses.
Total Initial Power The total power that is acquired initially.
Total Saved Power The total power that is saved by adding the suggested clock enable
to the memory.
ODC Detected Indicates if an ODC was detected for this memory.
Disable Power Power wastage due to unnecessary memory clock toggles in disable
mode.
Redundant Read Power Power wastage due to redundant memory clock toggles in read
mode.
Redundant Write Power Power wastage due to redundant memory clock toggles in write
mode.

15.9.7. Memory Linter Report

Memory Power Linter (MEM) generates a detailed memory power wastage report in CSV format. Use
the following variable to specify the report name:
pa_set reduction_memory_linter_report <filename>

By default, the report is saved as 'memory_linter_report.csv'.

CSV Report
The report has three sections, and they are described below:

• Summary

This section summarizes the wasted power of the pins/buses due to wasted toggles for each
memory instance in the design and includes the following columns:

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Column Name Description

Total Power Is the total power of the memory instance.
Wasted Power Is the total wasted power of a memory instance.
%Instance Wasted Power Is calculated using the formula: (Wasted Power/Total
Power) * 100
%Total Memory Wasted Is calculated using the formula: (Wasted Power/Design
Power Total Memory Power) * 100

A sample report is shown below:

• Detailed

This section lists the individual pins/buses and includes the following columns:

Column Name Description

Clock-Pin Is the name of the associated clock pin.
Bus/Pin Is the name of bus/pin.
Condition Is the condition for which this pin/bus has wasted toggles. The
possible values for this column are: 'gated_clock',
'no_access', 'read_mode'. If the chip select (CS) is disabled
and clock is gated, then 'gated_clock' is reported.

Note: The column is non-empty only when wasted power is

calculated for a memory instance.
Total Power Is the total power associated with the bus/pin.
Wasted Power Is the total wasted power of a bus/pin.
%Pin Wasted Power Is calculated using the formula: (Wasted Power/Total Power)
* 100

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Column Name Description

%Instance Wasted Is calculated using the formula: (Wasted Power/Power of a
Power particular instance) * 100

A sample report is shown below:

• Wasted timestamps

This section reports the timestamps at which the toggles of a particular pin/bus were wasted.
A sample of this section is shown below:

Graphical User Interface

The wasted timestamps are also reported in 'Detail' pane of 'Linter Reduction' dialog:

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15.9.8. Accessing Reduction Data Using APSH Containers

An APSH container-based interface is introduced to access power reduction data from PowerArtist
power database, which enables you to generate custom reports. The power database must be
generated using the 'ReducePower' command to access the reduction data. In this approach:

• a database object called 'reduction' similar to an instance or a net, is returned.

• you can use the 'get_reductions' command to retrieve a container of reductions.
• you can use the 'get_property' command to retrieve properties of the 'reduction' container
object.
• you can use the 'get_property_list -class reduction' command to return the list of
properties available on the 'reduction' container object.

The following properties are available on the 'reduction' container object:

Property Name Type Property Name Type

area_overhead double logic_saved_power double
auto_accepted boolean memory_clock_net string
bit_count long memory_clock_port string
cdc boolean memory_no_access_cycles double
cge_improvement double memory_read_cycles double
clock_enable_expr string memory_redundant_read_cycles double
clock_saved_power double memory_redundant_write_cycles double
cone_power double memory_total_clock_cycles double
cone_saved_power double memory_write_cycles double
dynamic_power_saved double reduction_instance_name string

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Property Name Type Property Name Type

ideal_total_saved_power double reduction_type string
is_gated boolean static_power_saved double
leakage_overhead double total_saved_power double
local_enable double

15.9.8.1. Syntax
Usage: get_reductions [options] [{*}]
where:
[-filter <expression>] Filters the container with expression
[-debug] Emit debug messages for this command
[-quiet] Emit no messages for this command
[-help] Emit this help text

Returns:
container

Example:
get_reductions -filter {reduction_type == GMC}
get_reductions -filter {auto_accepted == true}

15.9.8.2. Examples
• Example 1:

An example of retrieving a per-reduction property is shown below:

openPDB reduction.pdb

foreach_in_container red [get_reductions {*}] {

set red_type [get_property $red reduction_type]
puts "Reduction Type = $red_type"
set inst_name [get_property $red reduction_instance_name]
puts "Instance Name = $inst_name"
set logic_saved_power [get_property $red logic_saved_power]
puts "Logic Saved Power = $logic_saved_power"
set clk_saved_power [get_property $red clock_saved_power]
puts "Clock Saved Power = $clk_saved_power"
set total_saved_power [get_property $red total_saved_power]
puts "Total Saved Power = $total_saved_power"
set ideal_total_saved_power [get_property $red ideal_total_saved_power]
puts "Ideal Total Saved Power = $ideal_total_saved_power"
set cone_power [get_property $red cone_power]
puts "Cone Power = $cone_power"
set cge_imp [get_property $red cge_improvement]
puts "CGE Improvement = $cge_imp"
set clk_en_expr [get_property $red clock_enable_expr]
puts "Clock Enable Expression = $clk_en_expr"
set bit_count [get_property $red bit_count]
puts "Bit Count = $bit_count"
set mem_clock_cycles [get_property $red memory_total_clock_cycles]
puts "MEMORY Total Clock Cycles = $mem_clock_cycles"
set mem_no_acc [get_property $red memory_no_access_cycles]
puts "MEMORY No Access Cycles = $mem_no_acc"
set mem_read_cycles [get_property $red memory_read_cycles]
puts "MEMORY READ Cycles = $mem_read_cycles"
set mem_write_cycles [get_property $red memory_write_cycles]
puts "MEMORY Write Cycles = $mem_write_cycles"
set mem_re_read_cycles [get_property $red memory_redundant_read_cycles]
puts "MEMORY Redundant READ Cycles = $mem_re_read_cycles"
set mem_re_write_cycles [get_property $red memory_redundant_write_cycles]

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puts "MEMORY Redundant Write Cycles = $mem_re_write_cycles"

set area_ovh [get_property $red area_overhead]
puts "Area Overhead = $area_ovh"
set leak_ovh [get_property $red leakage_overhead]
puts "Leakage Overhead = $leak_ovh"
set local_en [get_property $red local_enable]
puts "Local Enable = $local_en"
set cdc [get_property $red cdc]
puts "CDC = $cdc"
set auto_accepted [get_property $red auto_accepted]
puts "Auto Accepted = $auto_accepted"
puts ""
}

• Example 2:

Use the '-filter' option of the 'get_reductions' command, to get the desired reduction objects:

– To get reductions of a type:

foreach_in_container red [get_reductions -filter {reduction_type == GMC} {*}]
{
set red_type [get_property $red reduction_type]
puts "Reduction Type = $red_type"
set red_clock_port [get_property $red memory_clock_port]
puts "Clock port = $red_clock_port"
set red_clock_net [get_property $red memory_clock_net]
puts "Clock Net = $red_clock_net"
}

– To get reductions on a specific instance:

foreach_in_container red \
[get_reductions -filter {reduction_instance_name == <name_of_instance>} {*}] \
{}

Similarly, you can apply other filters to any property listed in the table above.

• Example 3:

Use the '-class' option of the 'get_property_list' command, to get a list of reduction properties:
pa_shell> get_property_list -class reduction

15.9.8.3. PDB Properties for Querying Clock Enables

These properties help to query logic depth and number of literals in a suggested clock enable for
reduction objects returned by the 'get_reductions' command:

• enable_logic_depth

Returns the logic depth of the suggested enable expressions.

• enable_expr_literal_count

Returns the number of literals in the suggested enable expressions.

These properties are defined for reduction techniques ODC, SODC, and GMC and can help perform
trade-off between power saving and area/timing while implementing the suggested reductions.

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 Fine-Grain Switch Cell Support

These properties are also supported in the 'Unified', 'Simple', and 'By-Enable' reduction dialogs of
the GUI.

Example
Suppose enable expression suggested by a reduction technique is:
(A & B * C) | (D & B | C | E)

In this example, the 'Enable Logic Depth' is '4' and the 'Enable Expr Literal Count' is '5':
foreach_in_container red [get_reductions -filter {reduction_type == GMC} {*}]
{
set enable_depth [get_property $red enable_logic_depth]
puts "Enable Logic Depth = $enable_depth"
set enable_expr_literal_count [get_property $red enable_expr_literal_count]
puts "Enable Expr Literal Count = $enable_expr_literal_count"
}

15.10. Parallel Activity Processing

PowerArtist supports parallel activity processing in the reduction flow ('ReducePower') enabling faster
run times. This flow is similar to the parallel analysis support in time-based power analysis (Distributed
Processing in Time-based Power Analysis (p. 272)) and the 'ConfigureParallelAnalysis' command is used
to control the number of parallel processes.

To enable parallelization of reduction-focused activity analysis, use the following commands:

ConfigureParallelAnalysis -processes <number_of_processes>
ReducePower

To perform parallel reduction-focused activity analysis as a separate step from power reduction, use
the following commands:
ConfigueParallelAnalysis -processes <number_of_processes>
GenerateGAF -gaf_enable_reduction_data true
ReducePower -use_existing_gaf true

You can refer to the PowerArtist Reference Manual for complete details of the 'ConfigureParallelAnalysis'
command.

Note: Parallel activity processing supports all reduction techniques except 'Split Memory Words (SMW)',
'Memory Power Linter (MEM)', 'Memory Sleep Mode (MSM)', and 'Macro Power Linter (MPL)'.

15.11. Fine-Grain Switch Cell Support

Memory access cycle count calculation of instantiated memories with fine-grain switch cells is enhanced.
PowerArtist monitors the switching functions of Power-Ground (PG) pins associated with a clock pin in
such memory cells. If the switching functions evaluate to 'one (1)' in a cycle, the cycle is categorized
as a 'power down' cycle.

Estimated power savings may also change depending on the changed memory access cycle counts in
the various modes (read, write, read+write) of such memories.

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Examining and Implementing Power Reduction Opportunities

This support is available in the Gate Memory Clock (GMC), Memory Power Linter (MEM), and Memory
Sleep Mode Linter (MSM) PowerBots.

PowerArtist lists all the instantiated fine-grain memory cells processed in the reduction flow through
Note WBT-60. It also reports the respective 'Switch Functions'.

A sample 'Note' is shown below:

WBT-60: The following memory cells have a fine-grain switch with the
Corresponding switch functions.
These switch functions will act as power down condition for such memories.
--------------------------------------------------------------------------------
Note: These switch functions will supersede 'power_down'/'sleep' condition for
such memories.
--------------------------------------------------------------------------------
Cell: abv5p_umbr1_lvt_2048x32m4q_XXX
--------------------------------------------------------------------------------
Switch Func (CLK):
(SD||XXYY||ABCD)&&(SD||XXYY||DEFG||ABC.int_SEL[1]||ABC1.int_SEL[1])
--------------------------------------------------------------------------------

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Chapter 16: Using the PowerCanvas
16.1. Introduction
This chapter provides an overview of how to use the PowerArtist graphical user interface, called the
PowerCanvas. It describes the available menu items and how to use them. It does not take you through
a process step-by-step. For details on starting PowerCanvas, see Invoking the GUI (p. 16) and Viewing
Power Analysis Results in the PowerArtist Graphical Interface (p. 47).

To learn to use PowerCanvas, run the following tutorials:

• Analysis Tutorials — PowerArtist Tutorial Part I: Power Analysis (p. 19)

• Reduction Tutorials — PowerArtist Tutorial Part II: Power Reduction (p. 71)
• Advanced Tutorials — PowerArtist Tutorial Part III: Advanced Features (p. 95)

Refer to this chapter if there is a particular aspect of PowerCanvas that is not covered in the tutorial or
to know how a particular menu works.

Chapter Organization
The following topics are covered in this chapter:

• Overview of the PowerCanvas Initial View (p. 378)

• PowerCanvas Menus (p. 378)
• PowerCanvas Dialogs (p. 382)
– Using the Find Dialog (p. 383)
– Using the Preferences Dialog (p. 386)
– Using the Properties Dialog (p. 390)
– Using the Net Activity Dialog (p. 391)
• Using the Hierarchy Browser (p. 393)
• Using the Schematic Viewer (p. 396)
• Using the All Reductions Dialog (p. 404)
• Viewing Reductions by Category (p. 407)
– Using the Simple Reduction Dialog (p. 407)
– Using the Linter Reductions Dialog (p. 413)
– Using the Prism Dialog (p. 418)
• Viewing Reductions by Clock Enables (p. 427)
• Using the Waveform Viewer (p. 429)
• Using the Signal Viewer (p. 441)
• Using the Source Browser (p. 449)

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Using the PowerCanvas

16.2. Overview of the PowerCanvas Initial View

When you first bring up the PowerCanvas, as described in PowerArtist Tutorial Part I: Power
Analysis (p. 19), you need to load your design by selecting 'File > Load Design... and selecting your
'.pdb' file. Alternately, you can use the '-pdb <filename>' option to the 'PowerArtist' command
to automatically load the specified power database.

Note: If you are loading a large design that may take some time, PowerArtist displays an hour glass
busy indicator. When your design is loaded, the display looks like the following figure:

Figure 16.1: Initial Power Canvas Display (Tutorial Design)

The PowerCanvas has two main sections:

• Hierarchy Browser

You can use the 'Design' menu to change the look of the hierarchy browser. For more information
on the using the hierarchy browser, see Using the Hierarchy Browser (p. 393).

• Schematic Display

You can use the 'Schematic' menu to change the look of the schematic display. For details on
using the schematic display, see Using the Schematic Viewer (p. 396).

16.3. PowerCanvas Menus

A snapshot of the menus available with the PowerArtist GUI (PowerCanvas) is shown in the following
figure:

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 PowerCanvas Menus

Figure 16.2: PowerCanvas Menus

Note: Some menus are enabled only when certain conditions exist. For example, the 'Design' and
'Schematic' menus are available only if an inferenced design is loaded.

16.3.1. Using the Edit Menu

The 'Edit' menu has two menu items, as shown below:

The menu items are explained:

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Using the PowerCanvas

• 'Find...', which brings up the Find dialog. For detailed information on this dialog, see Using
the Find Dialog (p. 383).

• 'Preferences...', which brings up the Preferences dialog. For detailed information on this
dialog, see Using the Preferences Dialog (p. 386).

16.3.2. Using the Tools Menu

The 'Tools' menu has the following menu items, as shown below:

The menu items are explained:

• 'Net Activity...', which supports the what-if power analysis flow. For detailed information on
this dialog, see Using the Net Activity Dialog (p. 391).

• 'Waveform Viewer...', which enables you to view output from PowerArtist or from external
sources. For information on how to use the viewer, see Using the Waveform Viewer (p. 429).

• 'Signal Viewer...', which is a faster and an alternate waveform display tool. For information
on how to use the viewer, see Using the Signal Viewer (p. 441).

• 'Command Window...'.

16.3.3. Using the View Menu

The 'View' menu has seven menu items, as shown below:

Four of these control the display of paned windows: Schematic Legend, Hierarchy, Information,
and Schematic.

The last three items are used for viewing and manipulating power reduction analysis results. They
appear only after a power reduction analysis is complete and the power database is loaded. These
items are:

• All Power Reductions: For information on how to use the viewer, see Using the All Reductions
Dialog (p. 404).
• Power Reductions By Category: For information on how to use the viewer, see Using the
Waveform Viewer (p. 429).

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 PowerCanvas Menus

• Power Reductions By Enable: For information on how to use the viewer, see Viewing
Reductions by Clock Enables (p. 427).

16.3.4. Using the Help Menu

The 'Help' menu provides links to release notes, documentation, shortcut bindings, and version
information.

PowerArtist supports Acrobat Reader, Evince, and Xpdf document viewers.

If you select Help > Shortcut Bindings, PowerArtist displays the following dialog, which describes
various hot keys and their operations.

Figure 16.3: Schematic Viewer Shortcuts

Menu Item Keyboard/Mouse Key or Function

Key Combination
Right Arrow Right Arrow key Pans to the right by half the window
size
Left Arrow Left Arrow key Pans to the left by half the window size
Up Arrow Up Arrow key Pans up by half the window size
Down Arrow Down Arrow key Pans down by half the window size
- - key Zooms out by half the window size
+ Shift + = Zooms in by half the window size

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Using the PowerCanvas

0 0 key Zooms to fit the available window

space
Stroke-SE-Btn1 Hold down left mouse Zooms in to area in selection box
button and drag in south
east direction
Stroke-SW-Btn1 Hold down left mouse Zoom fit. Fits the current window size
button and drag in south
west direction
Stroke-NE-Btn1 Hold down left mouse Zooms out proportional to the length
button and drag in north of the stroke. The longer the stroke,
east direction the further out the zoom. As you drag
the mouse, PowerCanvas displays the
value of the zoom factor.
Stroke-Btn2 Click and hold the middle Pan. Moves around the design.
mouse button
Shift-Stroke-Btn1 Hold down Shift key and Drag selected instance. Performs a
click left mouse button and move.
drag across screen
This move is only operational for
elements that are not nested inside the
body of another instance.
Click-Btn1 Single-click left mouse Select. This focuses in the schematic
button window and selects any element that
is under the mouse cursor.
Shift-Click-Btn1 Hold down Shift key while Append to selection. Adds elements to
clicking left mouse button your current selection.
Double-Click-Btn1 Double-click left mouse Navigate. Expands the connectivity for
button the clicked object to include additional
connections.

Clicking on a net shows additional pins

for the net. Clicking on a pin shows the
net for the pin.
Shift-Double-Click-Btn1 Hold down Shift key while Shows the children of the clicked
double-clicking left mouse instance
button
Delete Delete key Removes the selected net from the
view
Ctrl-Delete Hold down the Control key Removes the selected instance from
and press the Delete key the view

16.4. PowerCanvas Dialogs

The PowerCanvas provides different dialogs that allow you to manipulate your data in a number of
ways. You can search the power database and view and edit the source lines for selected elements.

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 PowerCanvas Dialogs

You can display hierarchical paths using '/' separators instead of '.'. This enables designers to easily
copy and paste paths between APSH and GUI.

The following dialogs are available in PowerCanvas:

16.4.1. Using the Find Dialog
16.4.2. Using the Preferences Dialog
16.4.3. Using the Properties Dialog
16.4.4. Using the Net Activity Dialog

16.4.1. Using the Find Dialog

The 'Find' dialog allows you to do a number of different searches on your power database. Select
Edit > Find... to launch the dialog shown below:

Figure 16.4: Find Dialog

Note: You can also use the 'Ctrl+F' shortcut keys to launch the dialog.

This dialog allows you to search the power database for information relating to instances, pins, or
nets. You control your search choice in the following steps:

1. 'Search for:' pull-down menu.

2. Enter the search criteria, controlling how many criteria must be met using the '+' (add another
criteria to the list), '-' (delete the last criteria from the list), or 'Clear' (clear the entire list).

The criteria depend on the object you select:

• If you choose instances, you can then search by name, hierarchical name, name,
inferred name, cell name, total power, dynamic power, static power and clock gating.
• If you choose pins, you can search by hierarchical name, name, type and capacitance.

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Using the PowerCanvas

• If you choose nets, you can search by hierarchical name, name, average activity,
capacitance, duty cycle, and frequency.

3. After defining the search criteria, click the 'Search' button.

Note: The search button changes to a 'Stop' button while the search is working. To stop
the search at any time, click 'Stop'.

The following figure shows sample search criteria with results:

Figure 16.5: Find Dialog (Search with Multiple Criteria)

This sample search, which uses the power database from the average power analysis tutorial,
finds all hierarchical names (including inferred instances) that begin with 'u' or 'U' with dynamic
power greater than '7e-04W' or '.7mW'. In this example, the search criteria matched 3
elements.

The first time you search the Instance, Net, or Pin category you may see a 'busy indicator'
because 'Find' does not know how many items are in the design.

After the first search, you get a progress meter that indicates the percentage completion of
the search (if the search goes on for more than several seconds).

You can click any column (p. 386) header in the table of returned elements to sort the elements
by either increasing or decreasing order according to that criteria. The first time you select
a header, you get an arrow showing the direction of the sort. The second time you select the
header inverts the sort.

You can view the source, the schematic entry, or the hierarchy browser entry for each element.
You must select the element in the returned list and then click 'Show in Source' to see the
corresponding source.

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 PowerCanvas Dialogs

Figure 16.6: Displaying Source for Element in Returned Search List

Types of Search
The following types of search are supported:

• Name-based

For name-based searches, do not specify any wild card characters. You can type in any part
of the name and the find dialog returns all names that contain that string. You can then ask
for either a match ('==') or not a match ('!='). The name-based entries are case-insensitive.
When using this dialog, it is important that you understand the difference between a 'hierarchical
name' and a 'name'. A hierarchical name is the full hierarchical path name where levels of
hierarchy are separated by '/' or dot (.). The name is the portion of the name after the last
dot. Consider the following example of strings in your design:
a.b.c
a.bc
abc

A 'name' search using 'b' as the search string returns 'a.bc' and 'abc'. It does not match
'a.b.c' because in this example 'c' is the name, which does not match the pattern 'b' (0 or
more name elements followed by a 'b' followed by 0 or more name elements). However, a
'hierarchical name' search using 'b' returns all three because 'a.b.c' matches the given
pattern.

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Using the PowerCanvas

• Numeric Values

When you are searching for numeric values, the values are all floating point numbers but are
displayed using scientific notation. You will use the standard relational operators (<, <=, ==,
>=, >) to control your search.

If you do not specify a unit when searching for a numeric value, 'Watts (W)' is assumed.
You can specify W (default) mW, uW, or nW.

• Clock Gating

You can search for instances by their clock gating type. If you select 'Instance' and 'Clock Gating',
then you can search for instances that match (or don't match) any of the following types:
None, Inferred, Instantiated, Inferred and Instantiated, and Register
Bank.

Columns in the Find Dialog

The following columns are available in this dialog:

• Clock Traced: Search for untraced registers.

• Width: Use as criteria to filter results.

• Optimized Width: Use to report the number of bits of an instance that are optimized during
power analysis ('CalculatePower').

• Clock Gating Efficiency (CGE) Metrics: Use for sorting and filtering results.

16.4.2. Using the Preferences Dialog

The 'Preferences' dialog allows you to specify preferences for tool values and the font used in the
PowerArtist GUI. Select Edit > Preferences... to launch the dialog shown below:

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 PowerCanvas Dialogs

Figure 16.7: Preferences Dialog

You can also use the Ctrl+P shortcut to launch the dialog.

The dialog provides three preference categories:

• General

You can use this section of the dialog to perform the following activities:
– Specify whether the register clock pin power is associated with a register or with the
clock tree. All power displays (except the reduction dialogs) respond to this preference.
– Display all values in the tool in scientific notation via the check box.
– Select the precision via the spin box.
– Specify the file comparison utility using the 'File Comparison Command:' field. tkdiff'
is default utility for file comparison.
– Specify the file editor using the 'File Edit Command:' field. 'vi' (or the value in the
'$EDITOR' environment variable) is default file editor.
– Configure the color themes as Classic, Dark, or Light. By default, the theme is Classic.

You can also set the value of your choice through these fields. Once set, the value persists for
subsequent invocations of PowerArtist.

• Font

You can select the font to use for the tool or the log output:

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Using the PowerCanvas

• Schematic

This category contains the following fields:

1. Initial Display: You can set to 'Primary IOs' or 'Nothing'.

The default is 'Primary IOs', which displays the top-level ports in the currently open
power database. Setting it to 'Nothing', signifies that the initial display of the schematic
does not contain any graphics and elements must be added to the schematic using the
'show in schematic' menu from the other parts of the GUI.

2. Mouse Behaviour: To navigate the Schematic Viewer, you can configure one of the two
mouse behaviors available in the tool - Classic and Ansys.

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The Shortcut bindings table shows an asterisk mark against the keys which are always
active in the Ansys mode.

The following pan and zoom mouse controls are available:

Pan Cursor: You can use the middle mouse button to perform the pan operation. The
cursor icon changes into a hand-palm icon. The following pan controls are available:

– Pan Schematic: To pan around the whole design, click the middle mouse button and
drag the mouse in any direction.

– Pan Model: To move the schematic model in any direction, click Ctrl + middle mouse
button.

Zoom Cursor: To see the zoom cursor, click the Shift + middle mouse button. The cursor
icon changes into a magnifying glass icon. The following specifies the direction:

– Zoom In: If the direction of the cursor movement is upwards, zooms in.

– Zoom Out: If the direction of the cursor movement is downwards, zooms out.

The 'Preferences' dialog has the following four buttons:

• Defaults - Restores the preferences to the tool defaults.

• OK - Applies the changed preferences and closes the dialog.
• Apply - Applies the changed preferences. The dialog remains open and stays visible.
• Cancel - Cancels the changed preferences and closes the dialog.

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16.4.3. Using the Properties Dialog

You can launch the 'Properties' dialog in one of the following ways:

• The 'Schematic' menu (Schematic > Show Properties)

• The context menu of the 'Schematic Display'.

This dialog displays the properties (power values, frequency, transition times, average, activity, duty
cycle, wire capacitance, etc.) for nets, pins, or instances in the design. You can do the following with
this dialog:

• Select nets, pins, or instances from the Schematic or the Hierarchy Browser.

• Add tabs that allow you to save data for items you have selected and then toggle between them.
There is no limit on the number of tabs you can create. You can use the and icons to add or
remove tabs, respectively. You can also right-click the dialog title to open a menu of tab actions.
This menu has three items: New Tab, Close Tab, and Close Other Tabs.

• Suppress (hide) or change any column by right-clicking the column header and disabling/enabling
the columns from the menu that appears. To reorder the columns, click and drag the column
headers.

• Cross-probe to the 'Waveform Viewer':

1. Select 'Tools > Waveform Viewer...' to open the viewer.

2. Right-click a net/pin name and select 'Show Waveform' from the menu.

For details, see section Using the Waveform Viewer (p. 429).

• Select multiple elements to display in the same tab. The following figure has three tabs, one for
each element type:

Figure 16.8: Properties Dialog with Multiple Tabs and Instances Displayed

Each tab represents an element as indicated by the different icons in the tab headings:

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 PowerCanvas Dialogs

– The icon represents a net instance.

– The icon represents a pin.
– The icon represents an instance.

You can display multiple elements (nets, pins, or instances) of the same type using the 'Ctrl-select'
keys in a single tab. But you cannot display elements of different types in the same tab.

• Display the pins for any listed instance by right-clicking any row and selecting 'Show Instance
Pins'. If the tab is already showing the pins, you can right- click and select 'Don't Show Instance
Pins' to view the information for the parent instances only. If you check the 'Expand instances to
pins by default' box, the pins display whenever you select an instance.

• Display the upstream, downstream, or exclusive cones of logic for an instance pin by selecting the
appropriate entry from the right-click menu. The following figure shows the downstream cone of
logic for the 'Y' output pin on instance 'udi18':

Figure 16.9: Displaying the Downstream Cone of Logic for an Output Pin

• Expanding and collapsing expression views

The expressions shown in the 'Properties' dialog can be expanded to their user-defined nets. To
expand, right-click and select 'Expand All'. To collapse all expressions, right-click and select 'Collapse
All'.

16.4.4. Using the Net Activity Dialog

During RTL power analysis and debug, you can override the simulation data, for a clock enable (as
an example), and perform a quick what-if power analysis to measure the impact on power. What-if
analysis allows overriding the net switching activity from the simulation data through batch commands.

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The 'Net Activity' dialog supports the what-if power analysis flow. You can launch the dialog in one
of the following ways:

• The 'Tools' menu (Tools > Net Activity...)

• The context menu of the 'Find' or the 'Properties' dialogs, or the 'Schematic Display'.

The main area of the dialog is a table with the following columns:

Column Function
Name
Net Displays the full net path.
Export This is a check box and it allows you to determine the nets exported to the
'SetStimulus' file. You can change the what-if scenarios easily without to
deleting/adding nets in the dialog.
Activity This is the net activity. When you add a net, this value initializes to the activity
stored in the power database (PDB).
Duty This is the net duty. When you add a net, this value initializes to the duty
stored in the power database (PDB).

After the 'Net Activity' dialog is visible, you can also add nets to it by dragging from the 'Find' or the
'Properties' dialogs, or from the 'Schematic'. You can change the activity or duty of nets in the dialog
by first selecting the value with the mouse, then clicking again. The field changes to a type-in where
you can type in the new value. You can edit multiple entries at once by doing a multiple selection.
Make sure you hold the shift key down for the second click to launch the field editor.

You can perform a what-if power analysis by doing the following steps:

1. Add the nets and change the activity or duty.

2. Export the data in 'SetStimulus' format by selecting 'File > Export > SetStimulus Format...'.

You can also export the data as a CSV file by selecting 'File > Export > CSV Format...'.

3. Specify the exported file as input during power analysis:

CalculatePower -vectorless_input_file <exported_filename>

The data in the dialog is saved automatically when you close PowerArtist or you can save it anytime
by selecting 'File > Save'. Previously saved data is automatically loaded when you launch the
PowerArtist GUI on the same pdb and re-open the 'Net Activity' dialog. If the pdb you load into
PowerArtist does not have net activity data but you know that relevant data is stored elsewhere you
can load it from a different pdb by selecting 'File > Load...'.

Note: The data is always saved and associated with the current pdb.

Some additional features of the dialog are:

• The 'Filter' text box enables you to display nets filtered according to the string you type.
• The table context menu provides the following capabilities:
– 'Copy' menu items to copy values and nets.
– 'Remove All Nets' to remove all entries from the dialog.

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 Using the Hierarchy Browser

– 'Remove Select Nets' to remove the selected nets.

16.5. Using the Hierarchy Browser

This section describes the ways in which you can manipulate your design data in the hierarchy browser
in PowerCanvas.

Figure 16.10: Hierarchy Browser

The hierarchy browser has two panes:

• Hierarchy

It is the left pane of the figure shown above. You can use the button ( which by default shows
'Power') at the top right of the hierarchy view to sort the data. You can sort by 'Power', 'Power
Density', 'Instance', 'Module', or 'Area'.

• Power Table

It is the right pane of the figure shown above. It displays inferred instances, registers, and gates
that are within the hierarchical instance (module) that is highlighted in the hierarchy view in the
left pane.

16.5.1. Controlling the Hierarchy Browser From the Design Menu

The 'Design' menu controls the display of the hierarchy browser:

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Using the PowerCanvas

Figure 16.11: Design Menu

The 'Design' menu has two menu items:

• Hierarchy

For the highlighted module/instance, you can perform the following actions:

– Show in Source

Opens the smart 'Source Browser' on the source file containing the selected element. The
browser is positioned at the source line and colorized for power based on the
module/instance from which you cross-probed. For more information on using the smart
'Source Browser', see Using the Source Browser (p. 449).

– Show in Schematic

Displays the selected instance in the schematic. You can then zoom-in to get a closer look.
For more information see, Using the Schematic Viewer (p. 396).

– Show Properties

Displays the selection in the Properties dialog. For more information, see Using the Properties
Dialog (p. 390).

– Colorize by : Colors the hierarchy browser by the following:

Nothing: The default value and it adds no color.
Power: Colorizes the modules in the hierarchy by the power results. The higher the power
consumption, the hotter the color.
Clock Power: Colorizes the modules in the hierarchy by the clock power results. The
higher the power consumption, the hotter the color.
Power Density: Colorizes the modules in the hierarchy by power density (power/area) as
a percentage of the largest power density.
Note: These menu items are also available when you right-click a module in the hierarchy.

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 Using the Hierarchy Browser

• Power Table

For the selected instance, you can perform many of the same actions listed in the 'Hierarchy'
sub-menu and the following actions that apply only to selections in the power table (or apply
differently to them):

– Copy

– Copy Special

– Copy Path

– Export...: Exports data from the power table to a CSV file so that you can manipulate it in
a spreadsheet (such as MS-Excel). This is similar to the 'export' capability in other dialogs.

– Show Clock Gate Enables

– Show Downstream Cones: Displays the downstream cone of logic in the schematic for the
selected inferred instance in the power table.

– Show Upstream Cones: Displays the upstream cones of logic in the schematic for the
selected inferred instance in the power table. For upstream cones, you have the following
additional display choice. You can choose to ignore or show cones of logic for upstream
select signals for 2-1 muxes, unencoded muxes, and tri-states, by selecting Ignore Select
Cones/Show Select Cones.

– Colorize by: Colors the power table by the following:

Nothing: The default value and it adds no color.
Power: Colorizes for power as a percentage of the parent instance.
Clock Power

– You can also choose to hide the following elements in the power table by checking the
following options:
Hide Gates
Hide Inferred Instances
Hide Registers
Hide IO Pads

All elements are displayed by default.

16.5.2. Column Header Definitions for the Power Table

The power table display has the following columns:

• *Instance: This is the name of the instance inferred from the RTL.

• *Module/Cell: This is the name of the modules/cell in the design.

• Logic Stat: This is the total leakage power of the logic and inferred buffers.

• Logic Dyn: This is the total dynamic power of the logic (internal plus net power) and inferred
buffers.

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Using the PowerCanvas

• *Logic Total: This is the sum of the leakage and dynamic power of the logic. The latter includes
internal plus net power and inferred buffers.

• Clk Stat: This is the total leakage power of the clock tree enclosed by a hierarchical instance.

• Clk Dyn: This is the total dynamic power of the clock tree enclosed by a hierarchical instance.

• *Clk Total: This is the sum of the leakage and dynamic power of the clock tree enclosed by a
hierarchical instance.

• Total Stat: This is the sum of the logic and clock tree leakage power.

• Total Dyn: This is the sum of the logic and clock tree dynamic power.

• *Total Pwr: This is the sum of the logic and clock tree power.

• *Pwr Density: This is the total instance power divided by the instance area.

• *Area: This is the instance area.

• *Clk Gated: For registers, it identifies whether it is clock gated or not.

• CGE: This is the clock gating efficiency value.

• *Optimized: Indicates whether the instance can be optimized away. For example, if it has no fanout
the instance is optimized.

* indicates that the field is enabled/displayed by default.

Note on Logic Instance Values: If the instance power under Logic Stat, Logic Dyn, or Logic Total
is zero, it may be because it forms part of a clock tree. If so, its power is included there.

Note Clock Instance Values: If a leaf instance power value under Clk Stat, Clk Dyn, or Clk Total
is non-zero value, it is because it forms a part of a clock tree. Therefore, its logic power is included
here.

16.6. Using the Schematic Viewer

The schematic display allows you to browse through a schematic representation of the loaded design.
This section describes the ways in which you can manipulate the schematic view of your design in the
PowerCanvas.

Figure 16.12: Schematic Display

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 Using the Schematic Viewer

16.6.1. Controlling the Schematic from the Schematic Menu

The 'Schematic' menu controls the display of the schematic display:

Figure 16.13: Schematic Menu

The 'Schematic' menu offers several options that you can use to manipulate the schematic. This menu
has the following options/sub-menus:

• Colorize By:

Colorizes the schematic by the following:

– Power: Colorizes by the power results. The higher the power consumption, the hotter the
color. Schematic instance bodies are colorized by their power color, for better distinction
between hierarchical instances and their children, and a clearer visualization of the power
distribution.
– Activity: Colorized by the activity of a given net. The more activity, the hotter the color.
– Connectivity: This is a special 'power debug' mode that associates colors with instances
of the schematic when you are tracing cones of logic.
– ODC: Allows users to switch between the different schematic modes for an ODC item.

• Show Properties

Brings up the 'Properties' dialog. This dialog displays information on pins, nets, and instances
selected from the schematic. This is especially useful to see all instances connected to a particular

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Using the PowerCanvas

bus port. Multiple selections show as many of the selected items as possible, even if they have
different parents. You can save selection information by creating a tab. For more information on
how to use this dialog, see Using the Properties Dialog (p. 390) and Viewing Power Analysis Results
in the PowerArtist Graphical Interface (p. 47).

• Copy Path

• Redraw

Redraws the current schematic.

• Zoom In/Zoom Out/Zoom Out Full

Zooms in/out or zooms to fit the full screen.

• Zoom to Selection/Center Selection

These menus enable better identification of schematic elements. If there is an element in the design,
that you are unable to view in the schematic, you can use either of these menus and it becomes
visible.

• Views

Views can be saved and restored by name. This menu has the following sub-menus:

– Save...

Displays a dialog that allows you to specify a name for the view.

Similarly, clicking 'Schematic > Views > <view name> restores the saved view. Views are
automatically mapped to the function keys 'F1' to 'F12'. As you save a view, a function key
is automatically assigned to the saved view. You can use these function keys to restore saved
views.

When you exit the GUI, the last schematic view is saved as the 'Last' view, if a function key
is still available. You can restore this view automatically, the next time you launch the GUI,
by specifying the following command:
PowerArtist -last_view true

or by using the following variable before running the 'PowerCanvas' command:

pa_set canvas_show_last_view true

– Organize...

Use this dialog to move views up or down the function key order or delete saved views.

• Instance

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 Using the Schematic Viewer

This menu has the following sub-menus:

– Show In Hierarchy: Highlights the selected instance in the hierarchy browser.
– Show Source: Displays the selected instance source in the Source Browser. For details, see
Using the Source Browser (p. 449).
– Expand Children: Displays the schematic of all the child instances of the selected instance.
– Collapse Children: Replaces the schematic of the child instances of the selected instance
with just the block symbol representing the parent instance.
– Show Clock Trees: Displays the clock trees for the selected instance. For details, see Basic
Clock Tree Manipulation (p. 402).
– Show Downstream Cones: Displays all downstream cones of logic for the given instance.
– Show Upstream Cones: Displays all upstream cones of logic for the selected instance. You
can choose to 'Ignore Select Cones/Show Select Cones'. This option 'ignores/shows' cones
of logic for upstream select signals for 2-1 muxes, unencoded muxes, and tri-states.
– Show All Pins: Displays all pins of the selected instance.
– Remove Unexpanded Pins: Removes unexpanded pins from the schematic view. For
example, when PowerArtist traces an instance in the schematic it does not show all the pins
of the instances (to provide an uncluttered view). You can display all pins by selecting
Schematic > Instance > Show All Pins. You can then do a trace from one of those pins or
launch the pin/net dialog. If you then want to collapse the instance to reduce clutter you
can select Schematic > Instance > Remove Unexpanded Pins.

• Pin

This menu affects any pin selected in the schematic and has the following sub-menus:
– Expand Drivers/Loads: Expands the drives/loads for the selected instance pin/port.
– Collapse Driver/Loads: Removes the drives/loads for the selected instance pin/port.
– Show Clock Tree: Displays the clock trees for the selected pin. For details, see Basic Clock
Tree Manipulation (p. 402).
– Show Downstream Cone: When selected for an output pin of an instance, it generates a
schematic of the downstream cone of logic for that pin. It stops tracing at register boundaries
or primary IOs.
– Show Upstream Cone: When selected for an input pin of an instance, it generates a
schematic of the upstream cone of logic for that pin. It stops tracing at register boundaries
or primary IOs. You can choose to 'Ignore Select Cones/Show Select Cones'. This option
'ignores/shows' cones of logic for upstream select signals.
– Show Exclusive Cone: When selected for an input or output pin of an instance, it generates
a schematic for the exclusive cone of logic for that pin. You can choose to 'Ignore Select
Cones/Show Select Cones'. This option 'ignores/shows' exclusive cones of logic for select
signals.

• Net

• Bundle/Un-Bundle Net
– The schematic view bundles nets together to de-clutter the display. This makes it difficult to
initiate tracing on a scalar portion of that net bundle. The 'Schematic > Un-Bundle Net' menu
enables exploding this net into its bits for further tracing and viewing property details.
– If a net is un-bundled, it must be re-bundled before another net can be un-bundled. The menu
name changes from 'Un-Bundle Net' (when a net is not bundled) to 'Re-Bundle Net'.

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Using the PowerCanvas

• Expand Full Schematic

Generates a full hierarchical schematic for your entire design. Before you select this command,
consider the potential time this can take due to the size of the schematic that it generates. When
you do select this, the following progress meter appears:

This gives you an idea of how long it takes to display the full design. If you decide you no longer
want to display the full schematic, click the 'stop' button.

• Collapse Full Schematic

Clears the schematic view and takes you back to the original schematic, which consists of the
primary inputs and outputs.

• Auto Hide Pins

When selected, this toggle suppresses the display of unconnected pins for any subsequent schematic
display. This feature is most useful when showing cones of logic as it does not display any pins
that are not associated with the cone.

• When Tracing

This menu has two sub-menus:

– Colorize Data Path: Colorizes the data path while performing tracing.
– Colorize Select Path: Colorizes the path for select signals while tracing.

Note: You can also select these items by right-clicking the schematic.

16.6.2. Using the Mouse to Zoom In and Out on the Schematic

By pressing and holding the left mouse button and moving the mouse, you will get different zoom
operations. There are three supported directions:

• To the NorthEast (up and to the right): this zooms out by a factor that is proportional to the angle
as well as the length of the stroke. You see an annotation 'zoom <value>' on the display.

• To the SouthEast (down and to the right): this does a window zoom where the first point is the
upper left bounding box point and the second point is the lower right bounding box. You see the
annotation 'zoom in' on the display.

• To the SouthWest (down and off to the left): this does a zoom fit. You see the annotation 'zoom
fit' on the display.

16.6.3. Expanding the Schematic by Double Clicking Ports

Suppose you have pin-pointed a hierarchical instance that consumes a lot of power and you want
to see the schematic for it. You can select that element in the hierarchy browser, right-click and select

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 Using the Schematic Viewer

'Show in Schematic'. This displays the schematic symbol body in the schematic with input ports
listed on the left side and output ports on the right side, as shown in the following figure.

Figure 16.14: Hierarchical Schematic Body

Double-clicking this element in the schematic while holding the shift key down expands the body
into its equivalent schematic. You can then do a 'Zoom Fit' and see the following figure.

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Figure 16.15: Nested Schematic for a Hierarchical Block

If you have run power analysis, you can quickly find the nets with high activity because they are a
non-blue color. Other elements are displayed in different shades of the thermal spectrum indicating
that some of their powers are higher than others. To see how a port of this module is connected to
other modules, double-click the port.

16.6.4. Basic Clock Tree Manipulation

To display a clock tree, you must:

1. Define your clock trees using the 'SetClockNet' command.

2. Specify the '-save_clock_trees_netlist' option with the 'CalculatePower' or

'ReducePower' commands.

3. Perform the power analysis (you cannot view clock trees after elaboration).

After performing these requisite steps, you can use the following process to display a clock tree:

1. From the schematic display, select and highlight one of three elements to display a clock
tree:
• The clock pin of an inferred register.
• The clock pin of an instantiated gate-level instance.
• The clock net defined using the 'SetClockNet' command.

2. If you select a pin, right-click and select 'Pin > Show Clock Tree'.

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 Using the Schematic Viewer

This creates a new schematic window of either the inferred clock tree for the selected element
or the traced clock tree. If you select a pin, you get the cone of logic that leads to that
particular clock pin. If you select the clock net, the entire clock tree is generated in a new
clock schematic.

Note: You cannot use the standard 'less' and 'more' schematic techniques (described previously) to
see less or more of your clock tree. You can only traverse the clock distribution network in this view.
For example, you do not have access to enable pins of integrated clock gating cells.

The following figure shows a clock tree for inferred register 'core1.s1.rxwrd.clock[0]'.

Figure 16.16: Inferred Clock Tree

This register name is a concatenated list of scalars.

16.6.5. Displaying Observability Don't Care (ODC) Candidates

You can view the following elements when you select the 'Show Downstream Cone' option after
selecting the ODC candidate in the 'Schematic Viewer':

• ODC Candidate
• Steering Logic
• Delay Flops

The following legend shows the color coding for the elements:

There is a threshold to limit the number of elements shown in the 'Schematic Viewer' while viewing
ODC candidates.

• If the number of elements in the cone is 'below' this threshold, then all the elements in the
downstream cone are shown and the ODC elements are highlighted as per the legend. Non-ODC
elements are grayed out:

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• If the number of elements in the cone 'exceeds' this threshold, only the ODC elements in the
downstream cone are shown and the ODC elements are highlighted as per the legend:

16.7. Using the All Reductions Dialog

The PowerArtist GUI is enhanced to display all the reduction and linting opportunities in one dialog
accessible from the main window menu. You can click 'View > All Power Reductions...' to access the
'All Reductions' dialog.

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Figure 16.17: All Reductions

This dialog allows you to apply sorting and filtering on all reductions and linters at the same time and
enables you to locate the reduction that provides the most power saving across Prism, Simple, and
Linter reductions. The separate reduction dialogs are available through main window menu item 'View
> Power Reduction By Category'.

16.7.1. Column Header Definitions for the All Reductions Dialog

You can click any column header in the 'All Reductions' dialog to sort the data in ascending or
descending order by that column. The following list provides a definition of the columns that are
unique to this dialog:

• Type: The type of reduction. You can expand this item to show all instances of this type across
all instantiations of the parent module (shown in the 'Module' column).
• Label: A label is assigned to the same reduction opportunities across all instantiations of a
module. The label is not persistent across invocations of PowerArtist and is just used to identify
different reductions. The prefixes 'L-' and 'R-' identify the item as a Linter or a Reduction
respectively.
• Tag: This is an ID for a reduction provided by the engine.
• Module: This is the parent module for the reduction opportunity.
• En Depth: Displays the enable logic depth.

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• En Literals: Displays the number of literals in the enable expression.

• Target: This is the name of the gate or register that is the subject of the reduction.
• Instance: This is the inferred name of the target.

16.7.2. Context Sensitive Help

The 'What's This' functionality is available in the reduction Detail tab column headers:

16.7.3. Detecting Duplicate Reduction Opportunities

Reduction opportunities that are displayed as strikethrough italics (as shown below) indicate a target
that is part of another reduction, that it is a duplicate. It's power saving is ignored but it is included
in case you want to implement this duplicate opportunity in preference to the other one.

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16.8. Viewing Reductions by Category

You can view the power reduction opportunities in the GUI by category. You can launch the dialogs
by clicking ' View > Power Reduction By Category' and selecting a reduction dialog:

Figure 16.18: Reductions By Enable

Each of these dialogs is explained in detail in the next sections.

16.8.1. Using the Simple Reduction Dialog

There are three separate dialogs for viewing power reduction results: Simple Reductions, Linter
Reductions, and Prism Reductions. This section describes the Simple Reduction dialog.

To view the results of the GMC, LNR, LEC, ODC, and DOI PowerBots, bring up the Simple Reduction
dialog by selecting View > Power Reduction By Category > Simple Reductions.... The Simple
Reductions dialog appears as shown in the following figure:

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Figure 16.19: Simple Reductions Dialog

16.8.1.1. Column Header Definitions for the Simple Reductions Dialog

You can click a column header in this dialog to sort the data by that column. The following list
provides a high-level definition of each column:

• Module: The name of the modules containing the reductions.

• Reduction: The type of reductions discovered in the given module. The line number of the
RTL where the reduction is found is also listed in this column. The name of the
variable/instance associated with the reduction is listed in this column at the lowest level.

• Instance: The name of the instance inferred from the RTL.

• Total Power: The total of the logic and clock power of the RTL before any reduction takes
place.

• Logic Power: This is all the power that is not clock power. This includes combinational logic,
sequential logic (latches and register), and instantiated library elements.

• Clock Power: The power not including logic power. This is the power of your clock
distribution network including any inferred buffers, inferred integrated clock gating cells,
and any traced elements in your clock network.

• Saved Total: The total of the logic and clock power saved after all reductions (or the specific
reduction) are applied.

• Saved Logic: The power of the RTL logic that is saved per module or reduction.

• Saved Clock: The clock power that is saved after the reduction(s) are applied.

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• Saved Clock Pin: The power savings from the clock pin, due to named reduction techniques.
The values in this column are different from the values in the 'Saved Logic' column.

• Pcnt Saved: The total of the logic and clock power saved as a percentage of the total
top-level power.

• Ideal Saved Logic: The power of the RTL logic saved after the reductions are applied but
before subtracting the logic power required to implement the reduction.

• Ideal Saved Clock: The clock power that is saved after the reductions are applied but before
subtracting the clock power required to implement the reduction.

• En Depth: Displays the enable logic depth.

• En Literals: Displays the number of literals in the enable expression.

• Area Ovrhd: The total area required to implement the reduction(s).

• CGE Imp: The clock gating efficiency (CGE) improvement percentage, which is the CGE value
after reduction minus the CGE before reduction. This value is displayed for clock-based
reductions (LEC, LNR, and ODC) only. The CGE for each instance of a register is displayed
(see the blue text) and the 'Line' row displays the average of all its children.

• Bits: The bit-width of the register. For ODC/SODC candidates, the 'actual' bit-width is reported
after '/'.

• AA: The AA (auto-accepted) column indicates whether or not the reduction was automatically
accepted for rewrite. If a reduction is not auto-accepted, you can hover your mouse over
the word 'No' to see the tool tip that tells you why the reduction was not auto-accepted.

Note: You can also filter on what is automatically accepted. In the Simple Reductions dialog,
the PowerBots that can be auto-accepted are: GMC, LNR and ODC.

• Accept: Ticking this check box causes reductions that can be automatically rewritten to be
scheduled (when 'Automatic' is selected from the pull-down menu) and adds the power
saved by any accepted reduction to the power summary table.

• Rewrite: The word 'Scheduled' appears in this column when a reduction opportunity is
accepted for 'Automatic' rewrite.

16.8.1.2. Column Header Right-Click Menu

If you right-click any column header in the Simple Reductions dialog, you see a menu. This menu
shows you which column headers are already displayed [X] and which are not. You can enable/disable
display of these columns using this menu. The first three selections in this menu perform the
following functions:

• Auto Size Column: Extends the selected column to allow you to see the entire contents of
the column for all displayed reductions.

Note: A '...' in any column indicates that there is text that is not displayed. To see the
text, you can auto-size the column.

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• Auto Size All Columns: Extends all displayed columns to their full width or the maximum
width set in the 'Column Width' dialog for that column.

• Column Width: When you select this, you see the following dialog:

In the input field, enter a specific width (in characters) and click 'OK'. The column from which
you invoked this dialog adjusts to the specified width.

If you specify a column width and check the 'Set value as maximum auto-fit width' box, the
specified value becomes the maximum width to which the Auto Size Column feature
expands. This is useful when instance names are very long and the Auto Size Column
selection makes the columns too wide.

Note: This maximum setting persists in PowerCanvas. If you want to remove the maximum
setting, specify '0' and click 'OK'.

16.8.1.3. Simple Reduction Dialog Data Filters

You can use the 'Match' filtering mechanism to filter the data in the Simple Reductions dialog. The
available filters are described in the following table.

Simple Reductions Dialog Data Filters

Filters that compare against strings using 'contains/doesn't contain':

Module Name
Reduction Instance
Filters that compare against numbers using 'standard relational
operators':
Mod Total Power Line Saved Clock
Red'n Total Power Mod Pcnt Saved
Line Total Power Red'n Pcnt Saved
Line Logic Power Line Pcnt Saved
Line Clock Power Line Ideal Svd Lgc
Mod Saved Total Line Ideal Svd Clk
Red'n Saved Total Line Area
Line Saved Total Bits
Line Saved Logic
Filters that compare against
Auto-Accepted Accepted
Filters that compare against Scheduled, Rewritten, Failed
Rewrite

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The purpose of using these filters is to reduce the amount of data you view. For example, to display
only those reductions that were auto-accepted, you can filter on 'Auto-Accepted is yes':

1. Remove all filtering by clicking the cancel icon.

2. Select Reductions > Mark All Not Accepted.

3. Filter on 'Auto-Accepted is yes'.

4. Select Reductions > Mark All Accepted.

You can use this type of filtering to restore the auto-accepted state of the reductions after manually
accepting/rejecting reductions in the GUI and saving your changes.

16.8.1.4. Using the Simple Sorting and Filtering Features

PowerArtist provides some simple features for sorting and filtering your data. In the simple mode,
you can sort by simply clicking on any column header. If a column header does not show an arrow
to the right of the column name, you can't sort by that column.

Figure 16.20: Simple Filtering Features

In the simple mode, you can see there is only one 'Match' filter line. This allows you to filter on
one set of criteria at a time. For example, you can filter reductions that do not reduce total power
by a given amount. For additional information and an example, see Filtering Reduction Results (p. 87)
in the reduction tutorial.

16.8.1.5. Using the Advanced Sorting and Filtering Features

In addition to the simple sorting and filtering features, PowerArtist provides more advanced sorting
and filtering features. To use the advanced sorting and filtering feature, click the icon on the far
right of the Simple Reductions dialog. This expands the dialog to display new 'Sort by' buttons
and provides the ability to filter on multiple fields. For example, you can filter on 'module' and
'whether power savings are greater than a specified value', then sort your
data first by bits and then by module/reduction. To add another sort or filter field, click the icon.
You can add up to three sort fields and as many filters as you like.

In the following figure, there are two sorting fields and two filtering fields.

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Figure 16.21: Sample Multi-Level Advanced Sorting and Filtering

Note: Sorting is hierarchical and it is applied within levels. Specifically, the sort feature is applied
to the different levels in the following order:

1. Module level
2. Reduction level
3. Line level
4. Instance level

In this sort order, if you sort on bits, you may not get the instance with the highest bits first.

Sorting Total Power by Module and Reduction

The following examples show how a total power sort is applied at the different levels of hierarchy
in the Simple Reduction dialog. For example, when you sort by 'Total Power' (by clicking the
up arrow in the 'Total Power' header) PowerArtist sorts each of the various levels-Module,
Reduction, Line, and Instance, as shown in the following figure:

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 Viewing Reductions by Category

Figure 16.22: Sorting Total Power Values at Different Hierarchical Levels

16.8.2. Using the Linter Reductions Dialog

This section describes the 'Linter Reductions' dialog though many of the features described in this
section are also available, in a slightly modified form, in the other reduction dialogs.

To view the results of the Linter PowerBots, launch the 'Linter Reductions' dialog by selecting View
Power Reduction By Category > Linter Reductions.... The 'Linter Reductions' dialog appears as
shown in the following figure:

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Figure 16.23: Linter Reductions Dialog

Similar to the 'Simple Reductions' dialog, you can use the 'What's This' feature to get information
on each of the column headers and the 'Match' feature to sort the data.

16.8.2.1. Column Header Definitions for the Linter Reductions Dialog

You can click any column header in this dialog to sort the data by that column. The following list
provides a high-level definition of each column:

• Module/Linter: The name of the module/linter containing the linter reduction.

• Instance: The name of the register instance inferred from the RTL.

• Total Power: The total power, including wasted power.

• Wasted Power: The total wasted power of the RTL (per module, linter, line, or instance as
applicable).

• Pcnt Wasted: The total wasted power of the RTL in all instances (per module, linter, or line)
as a percentage of the total module power. For modules, it does not include the child
modules.

• Bits: The bit width of the instance associated with the linter.

Note: You must expand to the line-level to see this information.

• Cone Power: The total average power in the exclusive cones of all instances that experience
wasted toggles (per module, linter, or line).

• Start Points: The maximum number of start points in the exclusive cones over all instances
that experience wasted toggles (per module, linter, or line).

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• Accept: Ticking this check box causes reductions that can be automatically rewritten to be
scheduled and for all such reductions causes the power saved to be accumulated in the
power summary table.

For details on how you can use the data in this dialog to evaluate MUX power reduction
opportunities, see Understanding the PowerCanvas Data for the MUX Linter (p. 328).

16.8.3. The Menus

The 'Simple Reduction' and 'Linter Reduction' dialogs have five menu items: File, View, Reductions,
Detail, and Help. This section explains the 'View' and 'Design' menus in detail.

16.8.3.1. The View Menu

The View menu allows you to expand or collapse collections (groups) of reductions at one time.
Using this menu, you can do the following:

• Expand the view of selected items

• Expand the view of all items
• Collapse the view of selected items
• Collapse the view of all items

To expand/collapse selected items, you need to:

1. Select one or more items using 'Shift-click' or 'Ctrl-click'.

The selected items highlighted in blue.

2. Click the 'View' menu and expand/collapse the selections to your level of choice (Reduction,
Line Number, or Instances).

The following figure shows you how you can expand multiple selections down to the line number.

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The 'All' in the menu items refers to 'all' the items currently displayed in the dialog (not all items
in the database). If you previously filtered some data, that filtered data is not included in the 'All'
operation.

For example, to 'accept all LNR' reductions do the following:

1. Filter out all reductions other than LNR. In the 'Match' field, select 'Reduction contains'
and enter LNR in the text field. Click the magnifying icon to filter the data.

2. 'Shift-click' to highlight the remaining lines in the dialog.

3. Click Reductions > Mark all Accepted.

4. Select Reductions > Set All Rewrite Actions > Automatic.

5. Click the 'Save' button to schedule the reduction rewrites.

16.8.3.2. The Detail Menu

The 'Detail' menu allows you to perform several different operations on an instance selected in
the 'Detail' tab (not from the reduction list).

This menu has the same options as the menu that appears when you right-click an instance name
in the reduction list and one additional item-'Show Waveform'. You can also see these options by
right-clicking a net/instance in the 'Detail' tab.

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 Viewing Reductions by Category

Figure 16.24: Right-Click Menu from Detail Tab

The following columns are available in the 'Detail' tab:

• A column to report the 'wasted timestamps' for the REG and MUX linter PowerBots:

• Columns to report the cycle information for the REG linter:

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16.8.3.3. Help Text in Help Tab

An improved 'Help' is available in the GUI. The improvements are:

• For SODC/LER reduction techniques, the help text includes pre-existing enable expressions
for SODC/LER candidate data. In addition, the inferred nets in enable expressions are
expanded in all cases, except when the:
– inferred net expression is traced up to a complex logic gate, such as adder or
comparator, and
– expression is traced up to certain logic levels (16).

• For shared LNR/LER candidates, the help text is enhanced to indicate the registers that share
the reduction opportunity. Sample output is shown below:

16.8.4. Using the Prism Dialog

This section describes the 'Prism' dialog though many of the features described in this section are
also available, in a slightly modified form, in the other reduction dialogs.

To view the results of the 'Prism' PowerBot, launch the 'Prism' dialog by selecting View > Power
Reduction By Category > Prism Reductions.... The Prism dialog appears as shown in the following
figure:

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 Viewing Reductions by Category

Figure 16.25: Prism Dialog (Initial View)

Click the '+' signs at the beginning of each line to expand the results. You can also click a row that
has a '+' sign and click the '*' key to expand that row. You see that each line is color-coded, as shown
in the following figure:

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Figure 16.26: Prism Dialog (Expanded View)

The color key applied to the Prism results is as follows:

• White row: These are the gated registers that form the start of the potential enable propagated
chain.

• Green row: These are candidate registers that only have gated registers upstream. Green rows
fall into the easy category.

• Yellow row: These are candidate registers that have gated and/or candidate registers upstream.
These fall into the medium category. Yellow rows are always under green rows.

• Red row: The register instance in this row has unresolved dependencies, that is, the enable
logic required to clock gate this register is partially known. This may happen when a register
is driven by:
– an ungated register in addition to being driven by a white, green, or yellow register.
– a primary input in addition to being driven by a white, green, or yellow register.
– a macro (such as, a memory) in addition to being driven by a white, green, or yellow register.
– a delayed version of itself in a feedback loop in addition to being driven by a white, green,
or yellow register.

The icons at the beginning of each line indicate the type of element in the register chain. The icons
are:

• : A register gated in the RTL.

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• : A register for which an enable is generated by XORing the inputs and outputs. If the register
width is greater than 'min_width', the enable is also used to gate it.

• : A gated register with a strengthened enable.

• : A single candidate register, which indicates that the chain is a simple register.

• : Two registers whose outputs drive another register. This indicates that this register is one
of at least two other registers that drive another register. This means that two or more registers
share a common register chain. By selecting the '+' sign that precedes the icon, you can see
the next element in the chain.

• : Two stacked registers, which indicates the start of a common register chain. Somewhere
else in the display is a row that has as the icon. Instead of searching for that, you can
right-click this row and select 'Move Common Chain Here'.

16.8.4.1. Categories of Implementation of Suggested Modifications

The Prism results are categorized as:

• Easy

Creating an enable for this register from the upstream gated registers is easy. You need to
'OR' the enables and delay by a register.

• Medium

Creating an enable for these registers is not so easy since there is a candidate upstream.
However, an inspection of the schematic can uncover an easy way to create one.

• Hard

Creating an enable for these registers is probably not possible since the upstream of this
register consists of ungateable registers, macros, and primary inputs. However, by looking
at the schematic, you may be able to identify an enable. For example, the upstream
ungateable register might be an initialization flop that never changes state outside of reset.

16.8.4.2. Definitions for the Bit Counters in the Prism Dialog

In the bottom right corner of all reduction dialogs, in the status bar, there is a set of counters:

Their definitions are:

• Viable

The total number of easy or medium bits.

Note: It might not be possible to accept all of these because some might have red candidates
upstream, which can block an enable.

• Automatic

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The total number of bits that are accepted for automatic rewrite.

• Manual

The total number of bits that have been accepted for manual rewrite.

• Normal

The view mode or analysis type. You can switch modes/analysis type by using the 'View >
Analysis' menu.

• Modules

The number of Verilog modules or VHDL architectures that are displayed in the dialog.

16.8.4.3. Column Header Definitions for the Prism Dialog

You can click any column header in the 'Prism' dialog to sort the data by that column. The following
list provides a high-level definition of the column headers:

• Register: For a gated register it is the name of the register where the enable originates. For
a candidate register it is the name of the register to which the enable can be propagated.

• Instance: The name of the register instance inferred from the RTL.

• Module: The name of the module containing the register.

• Clock Net: The name of the clock driving the register.

• Reg Power: It is the power of the register before clock gating. The value in parentheses is
the total power, before clock gating, of all the registers in the chain starting from the gated
register.

• Saved Total: It is the total power (register + clock - penalty) saved by gating the clock to
the register. The value in parentheses is the total power (register + clock - penalty) saved in
the chain starting from the gated register if all the registers in the chain were clock gated.

Note: There might not be any savings if the clock gating percentage is too low, too few
register bits are gated, or the logic required to gate the clock, an ICGC, consumes too much
power.

• Saved Reg: The register power saved by gating the clock to the register. The value in
parentheses is the total register power saved in the chain starting from the gated register
if all of the registers in the chain were clock gated.

Note: There might not be any savings if the clock gating percentage is too low or too few
register bits are gated.

• Saved Clock: The clock power saved by gating the clock to the register. The value in
parentheses is the total clock power saved in the chain starting from the gated register if
all of the registers in the chain were clock gated.

Note: There might not be any savings if the clock gating percentage is too low, too few
register bits are gated, or if the ICGC consumes too much power.

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• Ideal Saved Reg: This is the total register power saved in the chain starting from the gated
register if all the registers in the chain were clock gated, but before subtracting the power
in the enable propagation logic. For a candidate register, this is the register power saved
by gating the clock to the register, before subtracting the power required to propagate the
enable from the upstream registers.

• Ideal Saved Clock: The total clock power saved in the chain starting from the gated register
if all of the registers in the chain were clock gated, but before subtracting the power due
to the ICGCs and additional clock buffers. For a candidate it is the clock power saved by
gating the clock to the register before subtracting the power due to the ICGC and additional
clock buffers.

Note: There might not be any savings if the clock gating percentage is too low, too few
register bits are gated, or if the ICGC consumes too much power.

• Pcnt Gated: The percentage of the time the clock to the register was clock gated. The value
is ('1 - duty cycle') of the feedback MUX select signal expressed as a percentage. For
a gated register, the duty cycle is calculated from the simulation data. For a candidate
register, the duty cycle is estimated by ORing the upstream enables. Sources that cannot be
gated are ignored.

• Area Ovrhd: The total area required to implement the reduction(s).

• CGE Imp: The CGE improvement percentage, which is the CGE value after reduction minus
the CGE before reduction. This value is displayed for all candidate registers. The root registers
may or may not have a CGE value. If the root register has its strengthened enables or has a
generated enable (these roots are blue/yellow or yellow icons) then the CGE improvement
is displayed due to the strengthening or new gating.

Note: If the register is a simple user-gated register, no CGE value is displayed since PowerArtist
does not attempt to improve the CGE for these registers.

• Bits: The bit width of the register.

• Opt?: Indicates (by 'yes/no' values) whether you can save more power by strengthening the
gated register enable. If there are 'yes' values in this column, you can switch to the 'Optimal'
view from the 'Normal' view to see the extra savings. To switch views, select ' View >
Analysis > Optimal'.

• Gated Regs: The number of upstream gated registers from which an enable can be
propagated.

• Candidates: The number of upstream candidate registers from which an enable can
potentially be propagated. A candidate that has a candidate upstream of it becomes a
'medium' gating opportunity.

• Ungateable: The number of ungateable sources upstream. You need to inspect these sources
to see if they prevent you from clock gating the register. Ungateable sources makes a
candidate a 'hard' gating opportunity.

• CDC: If 'false', the register does not cross clock domains and it is in a one clock domain.
If 'true', the register is in more than one clock domain.

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• Local Enable: The number of enables that are available in the same module as the candidate
register.

• Extrn Enable: The number of enables that need to be routed to the same module as the
candidate register from other modules.

• Feeds Back: Indicates whether the output from the candidate register feeds back to its input
via another register. This might prevent you from gating the clock to the register.

• Accept: Ticking this check box causes reductions that can be automatically rewritten to be
scheduled (when 'Automatic' is selected from the pull-down menu) and adds the power
saved by any accepted reduction to the power summary table.

• Rewrite: The word 'Scheduled' appears in this column when a reduction opportunity is
accepted for 'Automatic' rewrite.

16.8.4.4. Filtering Prism Dialog Data

In addition to sorting by table column, you can use 'Match to filter the data. The filters are described
in the following table:

Filters that compare against strings using contains/doesn't contain:

Any Register Any Module
Any Instance Any Clock Net
Filters that compare against numbers using standard relational
operators:
Any/Chain Reg Power Any/All Bits
Any/Chain Saved Total Any/All Gated Regs
Any/Chain Saved Reg Any/All Candidates
Any /Chain Saved Clock Any/All Ungateable
Any/Chain Ideal Reg Any/All Local Enable
Any/Chain Ideal Clock Any/All Extrn Enable
Any Pcnt Gated Chain Area Ovrhd
Any Area Ovrhd
Filters that compare against yes/no:
Any Feeds Back All Accepted
Any Accepted All Feeds Back
Any/All CDC Chain Optimized

The purpose of using these filters is to reduce the amount of data you are viewing at any point in
time. Filters starting with 'Any...' mean that if a condition matches any register in a chain, the whole
chain is visible whereas filters starting with 'All...' require that all registers in a chain match the
condition for the chain to be visible. Filters starting with 'Chain...' apply to the values associated
with the first or gated register in the chain, which are rolled-up values for the entire chain. The
goal is to reduce your power as much as possible with as little work as possible. There are several
approaches to this problem:

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 Viewing Reductions by Category

• Focus on a Module

You know by reviewing the hierarchy display that one module consumes more power
than it should. You should then use the 'Any Module' filter to examine that particular
module. If the module has multiple instantiations you see data for all the instantiations.

From the hierarchy browser again, you might realize that there is one particular
instantiation of the module that is consuming more power than the others. You can
then use the 'Any Instance' filter to locate register chains involving that instance.
For example, you can specify 'top.core1' as the 'contains' criteria to focus on all
the register chains involving that module instance.

• Focus on Clock Domains

You may be very concerned about the clock power for a particular clock. You run
PowerArtist and notice that one clock domain consumed more power than you expected.
Use the 'Any Clock Net' filter with the full clock name to locate those register chains
that are in the desired clock domain.

• Focus on the Amount Saved

If you want to see the opportunities that provide the most savings choose 'Chain
Saved Total' and look for a number greater than some value.

Another way of looking at opportunities is by 'bit width'. Generally, the wider the
register bank, the greater the opportunity for power savings. Use the 'Any Bits' filter
and specify a bit width size using the 'greater than' operand.

• Focus on Easiest First

Making a source code edit where you do not have to cross module boundaries is the
easiest alternative. This means that the enable signal you are missing is local to your
module. Choose 'All Local Enable' and then specify '0' with the 'greater than'
operand and the displayed opportunities requiring edits to just one file are displayed.

You should also focus first on registers that have no ungateable elements in their chain.
This means that enables are all immediately available. Filtering on 'All Ungateable
equals 0' is a good start because this leaves you with chains where the registers can
be gated using upstream registers. But some of these upstream registers might themselves
be more difficult opportunities.

• Focus on the More Difficult

After making the easy changes, if you still want to reduce power, you should remove all
the opportunities you have accepted from your view. Filter on 'Any Accepted No'
to remove any chain with an accepted opportunity. To focus on chains crossing module
boundaries, filter on 'Any Extrn Enable greater than 0'.

16.8.4.5. Using the Normal v s. Optimal Views

Designs often contain ineffective enables, which result in a substantial amount of wasted power.
These enables are recognized by the CEC linter, which then estimates the resulting wasted power
in the particular register they are enabling. These inefficient enables can also impact the quality of

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Using the PowerCanvas

the 'Prism' powerbot results. This is because Prism replicates existing enables to use as the enables
of candidate registers later in the chain. If these replicated enables are recognized by CEC, you may
be wasting power in both the gated register and in every register downstream that uses that enable.
Therefore, by making that one enable more efficient, you save even more power in the entire chain.

The Prism dialog has two different views:

• Normal

The 'Normal' view represents the power savings you can achieve given the simulation vectors
used to perform the reduction analysis.

• Optimal

The 'Optimal' view represents the power savings you can achieve if your enable was
'optimal'.

By examining the difference between the Normal and Optimal savings values, you can see the
impact that an inefficient enable has on multiple registers in your design. You can toggle between
the two views using the View > Analysis menu.

The 'Opt?' column in the Prism dialog means 'Optimizable?'.

If its value is 'yes' then this chain has an inefficient enable, which you can optimize to further reduce
power. If its value is 'no' then this chain has the best enable possible given the simulation vectors
used to perform the reduction analysis.

The 'Prism' dialog displays this field for the root (gated) register because this is the enable signal
that is leveraged through the chain. As with other columns in the dialog, you can filter data using
this column's value. For example, to see only 'Prism' opportunities with enables that are inefficient
and can be optimized, filter the data using 'Chain Optimized is yes'.

Note: When you switch views between 'Normal' and 'Optimal', PowerArtist recalculates all the
values in the dialog, including roll-up values, using the appropriate data. It also updates the summary
pane.

Using the Optimized Results to Improve the Power in your Design

To view the optimal results in the Prism dialog, run a reduction analysis with the 'Prism' PowerBot
using the 'ReducePower' command. Use the following flow to generate and view optimal results:

1. Run the 'ReducePower' command with the 'Prism' PowerBot enabled and open the 'Prism'
dialog in PowerCanvas.

2. Ensure that the display is set to 'Analysis: Optimal' mode by selecting View > Analysis
> Optimal. Verify that you are in the 'Optimal' mode by checking the status bar at the
bottom right of the dialog.

3. Filter chains that need optimizing and chains with small bit width registers by applying
the following filters:
a. Chain Optimized is no
b. Any Bits greater than 2

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 Viewing Reductions by Clock Enables

4. Accept all the easy chains by selecting Reductions > Mark All Chains Accepted > Just
Easy Candidates.

5. Note how much power is saved in the summary table.

6. To see just these chains set a single filter to 'Any Accepted is yes'.

7. Sort on 'Saved Total' column by clicking the column header. You now have a list of
register chains with readily available efficient enables that can be implemented easily.

8. Repeat the process on chains that would benefit from more efficient enables. To do this,
first define the following filters:
a. Chain Optimized is yes
b. Any Bit greater than 2

9. Accept all the easy chains by selecting Reductions > Mark All Chains Accepted > Just
Easy Candidates.

10. Note how the total savings have increased in the summary table. If this amount is substantial,
then modify the previous filter to:
a. Chain Optimized is yes
b. Any Accepted is yes

11. Sort on 'Saved Total' column by clicking the column header. You now have a list of
register chains with inefficient enables. If implemented, these provide extra power savings.

12. If there are many chains like these, it might be useful to see if it is worth the effort to create
better enables to achieve the extra savings. To do this toggle the display to 'Normal' by
selecting View > Analysis > Normal.

Note how the total savings in the summary table decrease. Based on this decrease, you
can decide whether you want generate better enables or just use the existing enables.

13. At this point, you are left with things that are potentially more difficult to implement. Follow
your previously established methodologies.

16.9. Viewing Reductions by Clock Enables

The 'All Reductions' dialog shows the power reduction opportunities detected during power reduction
(ReducePower) and how to implement them. Additionally, clock-gating opportunities per instance
(multi-instance opportunities are broken up into individual instances) are shown in the 'Simple Reduction'
dialog.

These viewers are not efficient for clock-gating opportunities that cover multiple instances. Additionally,
clock-gating techniques can also identify a single enable condition that can be used for all registers in
a group. To show this information, a new reduction dialog is added to the GUI. It is similar to the 'Simple
Reduction' dialog, but organizes the opportunities by enable condition (similar to the 'by-enable'
text report), instead of being module-centric.

You can launch the new dialog by clicking ' View > Reductions By Enable...':

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Figure 16.27: Reductions By Enable

You can use this viewer to view the full enable expression, by one of these methods:

• Click the 'Enable ID' and the full text expression is available in the 'Help' tab below.

• Right-click the 'Show Enable Expression' menu to bring up the 'Enable Expression' dialog.

The GUI can also display the clock gating expression for ECG opportunities in addition to regular clock
gating. To view the ECG enable expression, right-click a register in the power table and select ' Show
Clock Gate Enables'.

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 Using the Waveform Viewer

If this item is disabled (grey color), then the register is not clock gated. If this item is not disabled (black
color), it launches the 'Properties' dialog, which shows the clock gating enable expression.

16.10. Using the Waveform Viewer

This section focuses on how to use the 'Waveform Viewer'. You can use the waveform viewer to view
output from PowerArtist or from external sources. You can use the 'Tips' tab at anytime to see some
tips on performing common functions using the waveform viewer.

16.10.1. Supported Waveform Sources

You can view waveforms from the following sources:

• From an FSDB file.

The waveform viewer supports all FSDB files that PowerArtist supports. The waveform viewer
also supports ETCL and PTCL files.

As a PowerArtist user, you use FSDB files and potentially PTCL files. There is very little reason
to use PTCL files since PowerArtist has the capability of generating power waveforms in the
FSDB format. These will be much faster and take less disk space than their .ptcl equivalents.

• From an HSP ICE (CSDF or PSF) or a Spectre PSF file.

For details, see Displaying Waveforms from an HSPICE or Spectre Simulation (p. 434).

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16.10.2. Finding and Displaying Waveforms from an FSDB File

Do the following steps to view waveforms stored in an FSDB file.

1. Select 'Tools > Waveform Viewer...' from the main PowerCanvas window.

This launches the 'Waveform Viewer' as a separate window with the 'Add Waveform Source' dialog
open.

Figure 16.28: Selecting an FSDB File with the Waveform Viewer

2. From the 'Add Waveform Source' dialog, select an FSDB file (or PTCL file). For demonstration
purposes, you can use the FSDB file in the PowerArtist analysis tutorial. Navigate to the
'$POWERARTIST_ROOT/tutorial/analysis/reports' directory and select
'activity_waveform.fsdb'.

3. Click the 'OK' button.

The following figure shows the 'Search' tab with a list of available waveforms:

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 Using the Waveform Viewer

Figure 16.29: Waveform Viewer with a List of Available Waveforms

4. To locate a signal name to view as a waveform, you have three choices.

• Type in a search pattern in the 'Waveform Name:' field. The pattern is case-insensitive and
can contain the '*' wild card character.

• Cross-probe instances from the 'Schematic' or the 'Properties' dialog.

When you select an instance in the 'Schematic', the name is transferred to the 'Waveform
Name:' field with two modifications. The syntax is:
*.full_path_to_instance.*

The '*.' is added to the beginning of all cross-probed nets/instance. This is due to the
top-level hierarchy of the testbench that is reflected in the FSDB file. Adding a '*' wild card
at the beginning of the name matches any top-level string that begins the hierarchical net
names such as, 'testbench.top0'.

The '.*' is added to the end of the hierarchical name so that the waveform viewer finds
all the nets defined in the selected instance. It recursively matches all the nets defined by
its children instances also. For the sample screen shot in Figure 16.28: Selecting an FSDB
File with the Waveform Viewer (p. 430), if you select 't1/txchan' the following name is
added to the 'Waveform Name:' field in the 'Search' tab:
*.core1.t1.*

• Cross-probe wires from the 'Schematic' or the 'Properties' dialog.

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Using the PowerCanvas

If you select a wire, the name of the associated net appears in the 'Waveform Name:' field
as:
*.full_path_to_net

Since there is a single net associated with the wire, there is no need for the '.*' at the end
of the name. If you select a bus, the generated name is:
*.full_path_to_bus[*]

If you select an inferred instance or net, then no cross-probing is done to the waveform
browser since there can be no possible match in the FSDB file.

5. After the 'Waveform Name:' field is specified, click the 'Search' button to perform the search.
Cross-probing performs an automatic search for you. The waveforms that are found, in the selected
waveform source, are listed in the box below the entry field.

In this figure, the search pattern is '*.clk', which locates 30 waveforms. If your search returns
more than 100 matches, the browser displays the first 100 matches and generates a warning that
the remaining matches are not displayed.

The 'Search History:' field contains a log of all searches in the current session. As you keep searching,
this menu is updated, allowing you to quickly go back and forth between different search results.
This eliminates the need to re-invoke a search for a given pattern. For any of the listed searches,
the first number indicates the waveform source for which the search was executed, followed by
the pattern that was entered, and finally the number of matches.

6. From the list of available waveforms, select the waveforms to display and click the 'Add waveforms
to plot area' button. To select all the listed waveforms, right-click and select 'Select All'. If the
external file size is large, it may take some time for the waveforms to appear.

Note: Although the option appears available, you cannot place more than one digital waveform
in a single plot (it does not look right). The following figure shows three waveforms in individual
plots that were selected from the 'Properties' dialog:

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 Using the Waveform Viewer

Figure 16.30: Waveform Display with Three Plots

7. Right-click any plot to bring up a menu of available operations. You can manipulate the display
using the 'Display Options' menu. For easier viewing, the plots in this figure were increased in
width by 20% using the 'Display Options > Increase height of all plots by 20%' option. For
more information on options, see Using the Waveform Viewer Options (p. 435).

Understanding the Waveform Name

There are four distinct elements in a waveform name:

• The first element indicates the type of waveform: 'u' (unknown), 'p' (power), 's' (state), or 'v'
(voltage).

• The second element represents the domain: 't' (time) or 'f' (frequency).

• The third element is the index number assigned to the source of the waveform. This index is
listed next to the source name on the 'Waveform Source:' drop-down list. The '0' index is used
for the first waveform source. This index is increased by '1' for each additional source.

• The fourth element follows the pipe and indicates the name of the waveform as it exists in
the waveform source. The following figure breaks-down a sample waveform name:

Figure 16.31: Break-Down of a Waveform Name

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Using the PowerCanvas

In this figure, the waveform is a 'state' waveform in the 'time' domain for a waveform called
'txrx_tst.clk' in the 'first' listed source (source index '0').

16.10.3. Manipulating the Waveform Display

To delete the waveform, double-click a waveform name.

To zoom-in on particular area of interest on a waveform, click the middle mouse button and hold it
down while dragging the mouse to form a rectangle around the area of interest.

16.10.4. Displaying Waveforms from a PTCL File

The Waveform Viewer can display waveforms from a PTCL file. If a '.ptcl' file is available to you,
you can view the file by adding it to the waveform source, as described in 'Step 2' of section Finding
and Displaying Waveforms from an FSDB File (p. 430). Replace '*fsdb' in the 'Filter:' field with '*ptcl'
to see the available PTCL files.

16.10.5. Displaying Waveforms from an HSPICE or Spectre Simulation

The Waveform Viewer can display waveforms from an HSPICE or Spectre simulation.

• For HSPICE, the simulation output can be in 'CSDF' or 'PSF' format:

– To generate the output in 'CSDF' format, you must include the following setting in
your HSPICE simulation input file:
.options CSDF

Other output format options must not be specified after this CSDF specification. For
example, specifying '.options POST' overrides the 'CSDF' setting. Since a CSDF file
is an ASCII file, displaying waveforms from very large CSDF files is slow. However, you
can speed up this process by using '.PROBE v(XXX)' statements in your HSPICE
simulation input file to limit the number of reported waveforms.

– To generate the output in 'PSF' format, you must include the following setting in your
HSPICE simulation input file:
.options psf=2

Specifying '2' creates an ASCII PSF file, which the waveform viewer supports.

Note: The Waveform Viewer does not support binary PSF files.

• For Spectre, you need to set the following option:

psfascii

Finally, load the HSPICE or Spectre output files as you would any source file.

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 Using the Waveform Viewer

16.10.6. Using the Waveform Viewer Options

When a waveform is in the plot area, you can right-click anywhere on the plot to bring up the options
menu. You must continue to hold the right mouse button to see the menu as shown below.

Note: Some menu items have single-character shortcuts.

This menu allows you to:

• Take a snapshot

To take a snapshot of the current waveform view, press 's' or right-click and select 'Snapshot' from
the options. You can save the snapshot in '.png' or '.gif' format. The default format is '.png'
due to its small file size.

• Navigate — For more information, see Using the Navigation Sub-menu (p. 435).

• Measure and annotate — For more information, see Using the Measurement and Annotation
Sub-menu (p. 436).

• Delete a plot, Delete all plots, and Delete other plots (other than the current plot).

• Display options — For more information, see Using the Display Options Sub-menu (p. 436).

16.10.6.1. Using the Navigation Sub-menu

The following sub-menu appears when you select 'Navigation':

Using this sub-menu, you can do the following:

• Select a Zoom Style (Zoom x only, y only or x & y (default)).

• Zoom-in, Zoom-out, and fit area
• Pan a waveform in different directions.

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Using the PowerCanvas

16.10.6.2. Using the Measurement and Annotation Sub-menu

The following sub-menu appears when you select 'Measurement and Annotation':

Using this sub-menu, you can do the following:

• Mark a data point. Simply hover the cursor over any area on a waveform and press the 'm'
or select 'Mark data point' from the option.
• Delete all data point markers on plot or on all plots.
• Add a note. For more information, see Adding Notes to a Plot (p. 437).
• Delete notes on a plot.
• Toggle the ruler feature. For more information on using the ruler, see Measuring the Distance
Between Two Data Points (p. 262).

16.10.6.3. Using the Display Options Sub-menu

To make changes to the way the waveforms display, select 'Display Options'. The following sub-menu
appears when you select 'Display Options':

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 Using the Waveform Viewer

Using this sub-menu, you can do the following:

• Increase/decrease height of one/all plots by 20 percent.

• Increase/decrease waveform thickness.
• Toggle grid, which displays/hides a grid on the plot.
• Toggle background color, which switches the background from black to white and back
again.
• Toggle x-axis linear vs. log (Beta), which allows you to look at the x-axis in linear values vs.
log scale. For example, ticks are 1,2,3,4 vs 1,10,100,1000.
• Transform Y axis to decibel (Beta). This is useful for generating bode plots from some analog
signals.
• Set the units for X/Y axis.

16.10.6.4. Adding Notes to a Plot

At some point, you may want to share a snapshot of a waveform, either through e-mail or as a
slide in a presentation. To save a snapshot of a particular waveform, You may want to explain the
details about the plot or highlight a particular area of interest.

Use the following process add notes to a waveform and take a snapshot:

1. Bring up the desired waveform view.

2. Press 'n' or right-click the plot to launch the note window.

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Using the PowerCanvas

You can also right-click any waveform and select 'Measurements and Annotation > Add a
note'.

3. Type the note content and click 'OK'.

The note is added at the point where you originally clicked the waveform.

Additional 'Note' Manipulations

• To move a note to a different location, click and drag it.
• To edit the contents of a note, double-click it. Deleting all contents in a note, deletes the note.
• To delete a single note, double-click an existing note to bring up the note window and click the
' Delete Note' button. To delete all notes from a plot, select 'Measurements and Annotation
> Delete all notes on plot'.

16.10.7. Comparing Waveforms in the Same Plot

To put multiple waveforms in the same plot, select the 'Place in one plot' check box on the 'Search'
tab before clicking the 'Add waveforms to plot area' button.

If you already have individual plots, you can drag one waveform into the plot of another. To do so,
click anywhere on a waveform and drag it to the other plot.

16.10.8. Opening Tabs in a Separate Window

To open a tab in a separate window (also referred to as a tearing tab), click the '------' perforation
lines in the tab titles. This opens the tab in a separate window. Closing the separate window brings
it back to its tab. This feature allows you to view the 'Search' and 'View' tabs side-by-side and see
the waveform additions immediately as you click the Search button. This is more efficient than
clicking back and forth between tabs.

If you are a new user, you might want to tear the 'Tips' tab for quick reference while you are viewing
the waveform tab. This is also useful for comparing 'time-domain' waveforms against the 'frequency
spectrum' waveforms.

16.10.9. Reporting Activity and Duty

The GUI reports the activity/duty cycle pairs of 0.0/0.5 translated to X/X, instead of their activity and
duty values.

16.10.10. Clock Gating Efficiency Metrics in the Power Table

Several clock gating efficiency metrics are displayed in the power table for interactive power debug.
The following is a list of all clock gating efficiency metrics available in the power table:

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 Using the Waveform Viewer

CGE Description
Metrics
SCGE Static Clock Gating Efficiency. A metric that captures the percentage of gated flops
in the design. This is a static metric and is independent of the stimulus or mode
of the design. This is defined as a percentage of clock gated flops in the design.
It is calculated using the following formula:

SCGE = (100 * (total_gated_flop_bits/total_flop_bits))

DCGE Dynamic Clock Gating Efficiency. A metric that captures the reduction in clock
toggles at the clock pin of the register compared to the toggles at the clock source.
In general, the fewer the clock toggles, the lower will be the clock dynamic power.
Any improvement in DCGE (due to the clock-gating reductions) will mean a
reduction in clock switching and therefore power savings. This is defined as a
percentage of gated clock cycles in the design. It is simulation based and is
calculated using the following formula:

DCGE = (100 * (total_gated_clock_cycles/total_clock_cycles)

DCGE This formula is based on the 'actual clock activity' (which is the clock activity 'before'
(roll-up) clock gating) and 'effective clock activity' (which is the clock activity 'after' clock
gating):

DCGE(top) = (total actual clock activity - total effective

clock activity) / (total actual clock activity)
DACGE Data Aware Clock Gating Efficiency. Is a measure of how efficient the clock gate
enables are. Or of how effectively a flop is utilized. Every cycle of the flop's root
clock should either be gated or used to pass new data to the flop's output. If this
is not the case, then DACGE will be less than 100% or cycles that waste power. It
is calculated using the following formula:

DACGE = (100 *
((gated_cycles+data_toggle_cycles)/total_cycles))
CGEE Clock Gating Enable Efficiency. A metric that captures the scenarios where the
data is stable over a period of time and the flop is unnecessarily getting clocked.
It applies to both gated and ungated flops in the design. In case of an ungated
flop, the enable condition is assumed to be always enabled. A low CGEE value for
a flop signifies the clock is not well gated. A high CGEE value for a flop signifies
the clock is well gated.

CGEE = (100 * (data_toggle_cycles/ungated_cycles))

CGEE This formula is based on the proportion of a register's (data/enabled) activity to
(roll-up) total (data/enabled) activity:

CGEE(top) = (total data activity) / (total enabled

activity)

The GUI shows these clock gating efficiency metrics in the power table for interactive power debug:

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Using the PowerCanvas

16.10.11. Analyzing Clock Tracing in the GUI

The GUI provides feedback on clock tracing of sequential elements. The power table is enhanced in
the following ways:

• The 'Clk Traced' column has one of these values — 'Yes', 'No', or '--'. The 'Yes/No' values
occur on sequential elements and indicate whether they are traced or not.

• Dynamic CGE values can now have the following four possible states:
– A value between '0' and '100%' to indicate the usual efficiency.
– 'U' to indicate an untraced sequential element.
– 'ZF' to indicate that the clock to the element is zero.
– '--' to indicate that CG does not apply to the gate.

• The icon for untraced elements is different. Refer to the highlighted icon in the screen shot:

16.10.12. APSH Support in GUI

The PowerArtist GUI console supports APSH (Ansys Power SHell). All APSH commands and utilities
can be run from the GUI console.

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 Using the Signal Viewer

• All APSH utilities are enabled (run 'oadbInit' first).

• All commands, such as 'Elaborate' and CalculatePower are enabled.
• All native Tcl commands are included.
• Rich set of keyboard shortcuts (such as line edit and cut/paste) is supported

Note: The PDB loaded in the APSH console is not automatically loaded in the GUI. To load the PDB
in the GUI, run run 'oadbInit' in the APSH console to attach the PDB to the APSH console.

16.11. Using the Signal Viewer

PowerArtist supports another waveform display tool called Signal Viewer. Signal viewer has several
usability advantages over the current waveform viewer, including but not limited to faster performance,
better window layout, and drag-n-drop support.

16.11.1. Launching the Signal Viewer

To launch the Signal Viewer, do the following:

1. Open the GUI by using the following command:

PowerArtist

2. Select 'Tools > Signal Viewer...'. The Signal Viewer is launched as a separate window, as
shown below:

Figure 16.32: Signal Viewer

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Using the PowerCanvas

16.11.2. Additional Features

Some additional features of the dialog are:
16.11.2.1. Drag-Drop Support
16.11.2.2. Viewing Reduction Opportunities
16.11.2.3. Highlight Accumulated Reduction Data
16.11.2.4. Naming Nets
16.11.2.5. Selecting the Signal Name Style
16.11.2.6. VCD Stimulus File Support
16.11.2.7. Auto Loading the Activity File in Signal Viewer
16.11.2.8. Cross-probing Support for Linter Reductions

16.11.2.1. Drag-Drop Support

Drag-n-drop support in the Signal Viewer is extended to ODC and SODC expressions. These
expressions can be dragged from either the 'Details' pane or the 'Expression' dialog to the Signal
Viewer, which displays the waveform of the selected expression.

16.11.2.2. Viewing Reduction Opportunities

You can use the Signal Viewer to view the waveforms for important signals of power reduction
opportunities. To display the waveforms, right-click a power reduction opportunity in the 'Reduction
Viewer' and select 'Show Waveforms'.

The Signal Viewer is launched as a separate window, as shown below:

Figure 16.33: Viewing Wasted Power in the Signal Viewer

The waveform is highlighted to indicate the duration when power is wasted. This is supported for
the following types of opportunities:

• Observability Don't-care Conditions (ODC/SODC)

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 Using the Signal Viewer

• Gated Memory Clock (GMC)

• Low-activity Non-Enabled or Enabled Register (LNR/LER)

16.11.2.3. Highlight Accumulated Reduction Data

Waveforms of multiple ODC opportunities can be displayed simultaneously. The wasted power
duration is then highlighted by intersecting the individual ranges.

The waveforms of the first ODC opportunity 'top.selBlk[1].inReg[7:0]' are displayed in

the Signal Viewer shown below:

The waveforms of the second ODC opportunity 'top.selBlk[0].inReg[7:0]' are displayed

in the Signal Viewer shown below:

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Using the PowerCanvas

Note: The enable for the new candidate gates clock for higher number of cycles, but the highlighting
is based on the common cycles in which the clocks of both registers are disabled, so there is no
change to the highlighted area.

The waveforms of the third ODC opportunity 'top.selBlk[2].inReg[7:0]' are displayed in

the Signal Viewer shown below:

Note: The highlighted region is smaller now to reflect the common cycles, which are gated using
the three different enables.

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 Using the Signal Viewer

16.11.2.4. Naming Nets

The nets of expression literals in the Signal Viewer waveform list are represented by the full
hierarchical names and leaf-level names:

By default the leaf-level names of expression literals are shown in the Signal Viewer:

16.11.2.5. Selecting the Signal Name Style

You can select the naming style for a signal by right-clicking the signal and selecting the style, as
shown in the figure below:

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Hierarchical Name
The signal names shown at the 'hierarchical' naming style:

Unique Name
The signal names shown at the 'unique' naming style:

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 Using the Signal Viewer

Leaf Name
The signal names shown at the 'leaf' naming style:

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16.11.2.6. VCD Stimulus File Support

Waveform cross-probing (to the Signal Viewer) from a VCD stimulus file for the average power
analysis and power reduction flows is integrated.

16.11.2.7. Auto Loading the Activity File in Signal Viewer

PowerArtist stores the stimulus file path specified by the '-activity_file' option during power
analysis ('CalculatePower') and power reduction ('ReducePower') in the respective power databases.
The Signal Viewer, upon launching automatically loads the stimulus file, if it exists. The stimulus
file is used for cross-probing enable signal waveforms.

16.11.2.8. Cross-probing Support for Linter Reductions

The MUX, REG, CEC, and MEM linter reduction PowerBots support waveform cross-probing to the
'Signal Viewer'. There are two ways to cross-probe the linter reduction data:

• Select a linter reduction candidate, right-click, and select the 'Show Waveform(s)' option.
This launches the 'Signal Viewer' with the signals related to the candidates.

or

• Drag and drop the linter reduction candidate to an open 'Signal Viewer' window. The
following figure shows the MUX linter candidate's waveform in the Signal Viewer:

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 Using the Source Browser

The waveforms of 'data[7:0]' enabled at '~sel' and 'data1[7:0]' enabled at 'sel' are
all plotted.

Note: A section of the waveform for 'data1[7:0]' is highlighted in blue color, which
represents a wasted toggle.

16.12. Using the Source Browser

PowerArtist enables you to view the source for an element in the 'Hierarchy' display. You can view the
source in one of the following ways:

• Click the element and then select 'Design > Hierarchy > Show in Source'.
or
• 'Show in Source' from the right-click menu.

The 'Source Browser' appears as shown in the following figure:

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Figure 16.34: Smart Source Browser

You can perform a similar operation from the 'Schematic' display.

16.12.1. Features
The following enhancements are implemented:

• Drag-n-Drop

Drag-n-drop support enables you to drag-n-drop instances from the source browser to
other areas, such as the 'Schematic Viewer' or the 'Signal Viewer'. You can also drop
instances from anywhere within PowerArtist and view the corresponding design file.

• Multiple Tabs

You can open multiple design files simultaneously as multiple tab support is implemented.
Each design file is opened in a new tab, preserving scroll locations as you change the view
between source files. Tabs may be removed or deleted using the 'x' button on each tab.

• 'Property' columns

The line number and power color are displayed in the property columns.

• Power Colorization Relative to the Parent

Power of each instance is colorized relative to the power of the parent instance.

• Active Connection to 'info' Pane

If you hover your mouse over an instance or module, its properties are displayed in the
Info pane of PowerArtist GUI.

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 Using the Source Browser

• Search

The search capability is bi-directional. The direction of the search is controlled by the arrow
buttons to the right of the search entry field. Searches automatically wrap around to the
opposite of the file once the top or bottom is reached. Additionally, the search history is
maintained.

• Location-independent Source Viewing with Symbolic Link Resolution

The Source Browser can locate source files regardless of where PowerArtist is invoked.

Note: You need to regenerate the .scn (scenario database) and the .pdb (power
database), to use this feature as the Source Browser uses the invocation directory
remembered during elaboration ('Elaborate').

• Modern Look and Feel

The updated Source Browser has a modern look.

16.12.2. Additional Features

Some additional features of the dialog are:
16.12.2.1. Highlight Important Signals of ODC Opportunities
16.12.2.2. Highlight the Exact Tokens for Bundled 'Delay Flops'
16.12.2.3. Highlight Intermediate Elements
16.12.2.4. Highlight Steering Logic

16.12.2.1. Highlight Important Signals of ODC Opportunities

The source code browser automatically highlights important signals for ODC (Observability Don't
Care) related power reduction opportunities. The browser helps designers understand how registers
are rendered un-observable by downstream steering logic.

To launch the browser, right-click an ODC opportunity in the 'Reduction Browser' and select 'Show
Source':

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16.12.2.2. Highlight the Exact Tokens for Bundled 'Delay Flops'

When 'Delay Flops' are bundled during optimization, the flop is renamed as
'{<name1>,<name2>,...}', where the 'nameN' represents the individual element in the bundle.
The reduction 'Source Browser' is enhanced to highlight such bundled 'Delay Flops'.

In the following example, the 'Delay Flop' is named '{selC1,selD1}'. While

highlighting/selecting the signal name, PowerArtist highlights the exact individual signal-names,
namely 'selC1' and 'selD1':

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 Using the Source Browser

16.12.2.3. Highlight Intermediate Elements

The following intermediate elements are also highlighted:

• Candidate segment — Between 'Candidate' and 'Steering Logic'

• Delay segment — From 'Steering Logic' to 'Delay Flops'
• Literal segment — From 'Enable Literals' to 'Delay Flops'

The following diagram shows an example, where there is an intermediate net 'out' between the
delay flop and the steering logic where the net is the output of the intermediate 'AND' logic:

The color scheme of the highlight is as follows:

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Using the PowerCanvas

• The elements in the 'candidate segment' are highlighted with the color of the candidate
(Green).
• The elements in 'delay segment' are highlighted with the color of the delay flops (Blue).
• The elements in 'literal segment' are highlighted with the color of the enable literals (Yellow).

Such nets are also highlighted in the reduction Source Browser:

16.12.2.4. Highlight Steering Logic

The steering logic is now shown in 'magenta' color when viewed in the 'Source Browser'.

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Chapter 17: Analyzing the Effects of Power Gating
with Proprietary Commands
17.1. Introduction
Defining voltage domains and performing power gating can help to aggressively reduce power. Early
visibility into design trade-offs involving these techniques at the RT level of abstraction are valuable.
There are two methods for exploring multiple voltage domains and performing power gating in
PowerArtist:

• Using only PowerArtist proprietary commands

This chapter describes a method for exclusively using PowerArtist proprietary commands to
explore multiple voltage domains, define power domains, and perform simulation-based or a
vectorless analysis of power domains.

• Using a combination of proprietary commands and UPF commands

For information on using UPF file format, see the section titled The UPF File Format in the
PowerArtist Reference Manual. The section describes only a portion of the overall flow that UPF
can replace. The remaining steps in the flow are described in the following sections in this
chapter.

Chapter Organization
The following topics are covered in this chapter:

• Required Inputs for Power Gating (p. 457)

• Special Option to the 'Elaborate' Command (p. 460)
• Setting up Your Command File for Power Gating (p. 460)
• Performing Simulation-Based Power Analysis with Power Gating (p. 462)
• Performing Vectorless Power Analysis with Power Gating (p. 462)
• Understanding the Output Reports for Power Gating Analysis (p. 463)

17.2. Required Inputs for Power Gating

The following inputs are required for this flow:

• Libraries in Liberty format with the required power gating attributes.

See Defining Libraries (p. 458) for more information.

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Analyzing the Effects of Power Gating with Proprietary Commands

• RTL source files with named begin blocks (for Verilog designs) and named process (for VHDL designs)
to control the default cell selection of retention flops and latches.

See Creating Source Files (p. 459) for more information.

• A PowerArtist command file

The command file contains all the Tcl commands used to specify inputs such as clocks, defines libraries
for use in various portions of your design, virtual supplies, voltage and power domains, and wire load
models.

For vectorless analysis, while defining a virtual supply, the 'ON' condition must be a constant '0' or
constant '1'. For simulation-based analysis, that condition is any legal boolean expression of the
design nets in the target language.

• A scenario file representing the RTL or mixed RTL and gate design

Use the 'Elaborate' command to create the scenario file.

For vectorless power analysis, the instantiated gate-level logic should be small (to almost
non-existent) to minimize any problems with propagating activity through gates. For complete details
on creating a scenario file, see Getting Your Design into PowerArtist (p. 133). See Special Option to
the 'Elaborate' Command (p. 460) for information specific to power gating. You may also analyze an
entire gate-level design.

For simulation-based power analysis, you need an activity file in either FSDB, VCD, or IAF file formats.
The VCDe format is generated by Ansys PLI routines. See Acquiring Simulation Data (p. 207) for more
information on activity file formats.

• The reference clock name

For simulation-based power analysis, you must specify a reference clock. This is the fastest clock
in the design. It is used to calculate activity factors. All other signals are assumed to be toggling
slower than this signal.

• The number of clock cycles per calculation interval

For simulation-based power analysis, once the number of clock cycles is reached, the time-based
power analyzer performs average power analysis for that interval. This process is repeated from the
'-start_time' to the '-finish_time' giving you a power-over-time curve.

• Vectorless input file

For vectorless power analysis, see Performing Vectorless Power Analysis with Power Gating (p. 462)
for more information.

17.2.1. Defining Libraries

To use the power gating feature, add the following attribute to the appropriate Liberty library:
power_gating_cell

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 Required Inputs for Power Gating

This is a cell-level attribute that indicates that the given cell is a retention flop or latch. Use the
'MapRetentionCell' command to map a type of retention cell specified by the value of this attribute
to a particular always block.

A sample of a typical Liberty retention flip-flop cell definition is shown below:

cell (retflop) {
rail_connection (PVDD, VDD);
rail_connection (PVDDC, VDDC);
power_gating_cell : LOW;
leakage_power () {
value : 2.72E+01;
when : "RET";
power_level : VDDC;
}
leakage_power () {
value : 5.91E+03;
when : "RET";
power_level : VDD;
}
leakage_power () {
value : 2.89E+01;
when : "!RET";
power_level : VDDC;
}
leakage_power () {
value : 5.89E+03;
when : "!RET";
power_level : VDD;
}
pin (RET) {
internal_power () {
power_level : VDDC;
...
}
internal_power {} {
power_level : VDD;
...
}
}
...
}

17.2.2. Creating Source Files

PowerArtist has established a convention that allows you to control how and when retention flops
and latches are selected when doing default cell selection. This convention relies on the use of 'named
begin blocks' for Verilog or 'named process statements' for VHDL.

There can be a variety of retention cells in your library. By understanding how your design operates,
you may want to control which latches or flops from your power libraries are chosen at a very fine
level of granularity. In Verilog, the level of granularity is the 'always @' block-level and in VHDL it
is the 'process' level. The Verilog and VHDL sample fragments demonstrate this use.

Sample Verilog
module top(....);
...
always @(posedge clock)
begin : tag1
out1 = in1;
end

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Analyzing the Effects of Power Gating with Proprietary Commands

always @(posedge clock)

begin : tag2
out2 = in2;
end

always @(posedge clock)

begin : tag3
out3 = in3;
end
endmodule

Sample VHDL
architecture synth of top is
...
begin
tag1: process (clock)
begin
if (clock = '1' and clock'event) then
out1 = in1;
end if
end process

tag2: process (clock)

begin
if (clock = '1' and clock'event) then
out2 = in2;
end if
end process

tag3: process (clock)

begin
if (clock = '1' and clock'event) then
out3 = in3;
end if
end process
end synth;

Note: Later sections show how to control default cell selection so that 'out1', 'out2', and 'out3' are
different types of retention flops.

17.3. Special Option to the 'Elaborate' Command

To use power gating, specify the '-tag_blocks true' option to the 'Elaborate' command in your
Tcl file. The resulting tags are used later in the 'MapRetentionCell' command to control retention cell
default cell selection.

17.4. Setting up Your Command File for Power Gating

When running any type of power analysis, you need to do the following:

• Define how you want the clocks inferred using the 'SetClockNet' command.
• Ensure that the wire load models are selected correctly to ensure that interconnect capacitance
is estimated correctly.
• Define output loads. See Using Default Wire Load Models for Capacitance Analysis (p. 173) for
more information.

For the power gating flow, you need to the following additional steps:

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 Setting up Your Command File for Power Gating

• Define Library Associations

For the power gating flow, you need to define which libraries are used for power analysis for
various hierarchical instances using the 'SetLibrary' command. Assigning one or more libraries
to an instance controls the following:
– Default cell selection for the RTL power models.
– Wire load model selection for use in estimating interconnect capacitance for the instance (if
the libraries contain wire load models).
– Gate-level power models for instantiated cells.
– Power rail names that are available for use by voltage and power domains.

See Handling Designs with Multiple Libraries (p. 175) for complete details.

• Define Virtual Supplies

Virtual supplies (design rails) are associated with library power rails and are used to perform
'what-if' experiments with respect to voltage islands or derating the voltages in libraries. They
are also used for power gating applications. To define virtual supplies, use the
'CreateVirtualSupply' command. See Creating a Virtual Supply (p. 176) for complete details.

• Define Power Domains

To define power domains, you need to:

– Define the virtual supplies associated with a hierarchical instance.
– Define the power gating condition that controls the virtual supply.

Use the 'CreateDomain' command to create voltage and power domains. See Assigning a Virtual
Supply to a Hierarchical Instance (p. 176) for complete details.

• Define the mapping for retention cells

To define the assignment of retention flops and latches to particular inferred register and latch
instances, create named Verilog begin blocks or VHDL process statements (described in Creating
Source Files (p. 459)). Then specify the 'MapRetentionCell' command for the named begin blocks
or process statements.

Sample Command File for a Power Gating Flow

# Power Gating Settings #
SetLibrary -instance top -library {hvt RETENTION_EXAMPLE_LIB Memories}
#SetLibrary -instance {top.core1.u1 top.core1.a1 top.core1.s1} -library {hvt lvt}

# Power gating specific settings #

CreateVirtualSupply -supply vdd -virtual_supply VDDRX -on top.rx_rq
CreateVirtualSupply -supply vdd -virtual_supply VDDTX -on top.tx_rq
...
CreateDomain -instance top.core1.r1 -virtual_supply {VDDRX RX_VDDNWS RX_VRET}
CreateDomain -instance top.core1.t1 -virtual_supply {VDDTX TX_VDDNWS TX_VRET}

MapRetentionCell -instance {top.core1.r1} -attribute CK_LOW

MapRetentionCell -instance {top.core1.t1} -attribute CK_LOW -tag NoMap -notag true

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Analyzing the Effects of Power Gating with Proprietary Commands

17.5. Performing Simulation-Based Power Analysis with Power Gating

To run time-based power analysis with power gating, create a command file that contains the
'CalculatePower' command and the appropriate options. An example is shown below:
# Power analysis for simulation-based power gating flow #
CalculatePower -analysis_type time_based \
-time_based_upf_in_file my.upf \
-activity_file my_file.iaf \
-synlib_files {my_lib1.lib my_lib2.lib} \
-top_instance top \
-start_time 607158ps \
-finish_time 12135580ps \
-num_clock_cycles 20 \
-reference_clock myclock.clk \
-time_based_report_file time_based.rpt \
-time_based_write_power_db true

Note: To perform time-based power analysis with power gating, you can:

• Add this sample command specification to the command file you created in the previous section
(Sample Command File for a Power Gating Flow (p. 461) that includes the SetLibrary' and
CreateVirtualSupply' commands.
or
• Source that command file from this one using the 'source' command.

17.6. Performing Vectorless Power Analysis with Power Gating

To perform a vectorless power analysis with power gating, you need all the inputs listed in the section
Required Inputs for Power Gating (p. 457) except those specific to time-based analysis. In addition, you
need to create a vectorless activity file that you then specify to the 'CalculatePower' command using
the '-vectorless_input_file <filename>' option. An example is shown below:
# Power analysis for vectorless power gating flow #
CalculatePower -analysis_type average \
-vectorless_input_file my_file.vaf \
-synlib_files {my_lib1.lib my_lib2.lib} \
-top_instance top \
-average_report_file average.rpt \
-average_write_power_db true

Creating a Vectorless Activity File

Vectorless power analysis requires a Vectorless Activity File ('.vaf'). The '.vaf' file is an ASCII format
file than can be created using your favorite text editor. The format is described in section Analyzing
Vectorless Average Power (p. 251).

To get reasonable power analyses, the '.vaf' file must:

• Accurately define the frequency and duty cycle for your clocks and primary IOs of your design.
• Specify the frequency and duty cycles of enable signals for clock gating.
• Specify the read/write frequencies for the memories in your design.

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 Understanding the Output Reports for Power Gating Analysis

17.7. Understanding the Output Reports for Power Gating Analysis

Reports generated when analyzing the effects of power gating include additional sections over the
basic power report.

17.7.1. Sample Report for Simulation-Based Analysis

The time-based power report contains the following additional information:

• The 'Detailed Instance Power' section

This section that identifies the power and voltage domains with the type name 'domain'.
2. Detailed Instance Power
==========================

Average Power(Watts) Type Model Instance

Static Dynamic Total Name Name Name
------ ------- ----- ---- ---- ----
236.97uW 26.314mW 26.551mW domain domain_0
0W 0W 0W user -inst1
0W 0W 0W user -inst2
0W 0W 0W CELL1 --inst_imp
0W 0W 0W user -inst_switch
0W 0W 0W SWITCH1 --inst2_switch
275.01nW 0W 275.01nW user -io_inst
33pW 0W 33pW and --#381
< snip >

• The 'Power Per Domain' section

This section provides power numbers for each defined power domain - for 'average power'
and 'On Power'.
4. Power Per Domain
===================

Average Power (Watts) On Power (Watts) Domain

Static Dynamic Total Static Dynamic Total Name
------ ------- ----- ------ ------- ----- ----
118.74uW 24.841mW 24.96mW 118.81uW 24.856mW 24.975mW domain_0

The 'average power' is the overall average, which includes power consumption for times when
the power domain is 'on' and 'off'. The 'On Power' is the average power consumed only when
the power domain is switched 'on'.

• The 'Power Domain Summary' section

This section provides information on the power domains set up for this design. Information
includes library names and details of the virtual supplies (including On condition setting,
analysis voltage, and static and dynamic power numbers).
5. Power Domain Summary
=======================

Domain domain_0
----------------------
Library typical
File: ../typical.lib
Library typical1

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Analyzing the Effects of Power Gating with Proprietary Commands

File: ../typical1.lib
Library typical2
File: ../typical2.lib
Virtual Supply: VDDSW_0
Library Supplies:
typical1.VDD
typical2.VDD
typical3.VDD
typical4.VDD
typical.VDD
Estimation Voltage: 1.2 V (from Tcl file)
On condition: domain1_on & ! domain2_on
Average Static Power: 116.33uW
Average Dynamic Power: 23.404mW
On Static Power: 116.41uW
On Dynamic Power: 23.419mW
Virtual Supply: VDDSW_1
Library Supplies:
typical4.VDDNW
typical.VDDNW
Estimation Voltage: 1.2 V (from Tcl file)
On condition: domain1_on & domain2_on
Average Static Power: 799.43nW
Average Dynamic Power: 1.253mW
On Static Power: 799.93nW
On Dynamic Power: 1.2538mW

17.7.2. Sample Report for Vectorless Analysis

The vectorless analysis report contains the following additional information:

• The 'Internal Power Consumption' section

This section highlights the power for each domain by setting the model to 'domain', as shown
in the following excerpt:
3. Internal power consumption
=============================
Power(Watts)
Component Model Supply Static Dynamic Total
--------- ----- ------ ------ ------- -----
instance_1 user VDD_typ 26.9nW 226mW 226mW
#48 and VDD_typ 35.9pW 1.64nW 1.68nW
#55 comparator VDD_typ 506pW 3mW 3mW
#56 comparator VDD_typ 502pW 2.92mW 2.92mW
ra1 domain VDD_typ 3.56nW 40.5mW 40.5mW
#1 latch VDD_typ 568pW 13.9mW 13.9mW
#2 latch VDD_typ 1.14nW 17.3mW 17.3mW
<snip>
Total internal power 26.9nW 226mW 226mW

• The 'Power Domain Summary' section

This section provides information on the power domains defined for this design. Information
includes library names and details of the virtual supplies (including On condition setting,
analysis voltage, and static and dynamic power numbers associated with the supply):
6. Power Domain Summary
=======================

Domain instance_1.ra2
-----------------------
Library typical
File: typical.lib

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 Understanding the Output Reports for Power Gating Analysis

Library typical2.db
File: typical2.small.lib
Virtual Supply: VDD_typ
Library Supplies:
typical.vdd
Estimation Voltage: 2.5 V (from Tcl file)
On condition: 1
Static Power: 26.9nW
Dynamic Power: 226mW
<snip>
Virtual Supply: VDDNSW
Library Supplies:
typical2.db.VDDNW
Estimation Voltage: 2.5 V (from Tcl file)
On condition: On
Static Power: 0W
Dynamic Power: 0W

Domain instance_1.ra1
-----------------------
Library typical
File: typical.lib
Library typical2.db
File: typical2.small.lib
Virtual Supply: VDD_typ
Library Supplies:
typical.vdd
Estimation Voltage: 2.5 V (from Tcl file)
On condition: 1
Static Power: 26.9nW
Dynamic Power: 226mW
<snip>
Virtual Supply: VDDNSW1
Library Supplies:
typical2.db.VDDNW
Estimation Voltage: 2.5 V (from Tcl file)
On condition: 1
Static Power: 0W
Dynamic Power: 0W

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Chapter 18: Generating and Using PACE Technology
Files
18.1. Overview
PACE is an acronym for PowerArtist Calibrator and Estimator. It is a technology that improves power
accuracy. The goal of PACE is to enable out-of-box power analysis accuracy at RTL and pre-layout gates.
PowerArtist reads a post-layout, post-CTS reference-design and generates a PACE model. This PACE
model can be used for RTL power analysis with improved capacitance characterization and clock tree
modeling information.

When the PACE analyzer runs, it inspects the characteristics of a given gate-level design and builds a
model of those characteristics that can be used to analyze the power of other designs that share the
same fabrication technology. The gate-level design used for the model must be fully placed and routed
and have a synthesized clock tree.

There are two steps to the PACE process:

1. A library developer, potentially a CAD team member, runs the PACE analyzer on an existing
design and generates the PACE model. The library developer then publishes that model by
placing it in a generally accessible file location.

2. An end user runs PowerArtist using this model by specifying the PACE technology file as input
to either the 'CalculatePower' or the 'ReducePower' command. The power analyzer reads and
takes advantage of the PACE model.

A PACE model contains two types of information-capacitance models and clock tree distribution network
models.

Chapter Organization
The following topics are covered in this chapter:

• Need for PACE (p. 468)

• Types of PACE Models (p. 468)
• Capacitance Models (p. 469)
• Clock Distribution Network Models (p. 470)
• RTL Cell Selection (p. 470)
• Generating a PACE Model (p. 471)
• Using a PACE Model (p. 475)
• PACE Model Version (p. 479)
• PACE Technology Migration (p. 479)
• Useful APSH Utilities for PACE (p. 480)

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Generating and Using PACE Technology Files

• Performing Correlation Studies (p. 481)

• Multi-bit Flip-Flop (MBFF) Mapping in PACE Flow (p. 482)
• PACE Model per Hierarchy (p. 482)
• Merge Multiple PACE Models (p. 483)
• Using Incremental VT Settings for Cell Assignment/Selection (p. 483)

18.2. Need for PACE

There are a number of factors that impact RTL power analysis accuracy. Some of them are:

1. Physical attributes like capacitance estimation, clock tree modeling, and transition time inputs.
2. Low power structure modeling using CPF/UPF.
3. Micro-architectural inferencing and cell selection.
4. Algorithms internal to the tool like activity propagation and power calculation.

The inputs in factors 1-3 impact power analysis accuracy. PACE addresses out-of-box modeling of physical
inputs such as, capacitance and clock tree.

Traditionally, wire-load models are used for RTL power analysis. Wire-load models are sometimes too
pessimistic or unavailable. This limits the availability of accurate capacitance data for RTL power analysis.

To estimate clock tree power at RTL, you must specify the type of clock gating cell to use, a set of root,
branch and leaf clock buffers and their fanouts. RTL designers are often not familiar with this information,
and inaccurate information provided for clock tree inferencing results in inaccurate power numbers.

PACE model accurately models the capacitance profile of the design and you do not need to deal with
a number of switch settings for capacitance and clock tree modeling.

18.3. Types of PACE Models

PowerArtist supports the following types of PACE models:

• Capacitance Models (p. 469)

PACE capacitance model is a statistical model, which models the capacitance on a per category,
per fanout basis. Capacitance estimation using PACE overrides capacitance estimation using wire
load models, but other capacitance annotation methods override capacitance estimation using
PACE.
• Clock Distribution Network Models (p. 470)
PACE clock tree model consists of the electrical and physical characteristics, such as slew
degradation and 'max_fanout', which are used for buffer and fanout selection during power
analysis.
• RTL Cell Selection (p. 470)
• Statistical Cell Distribution Model Design-specific PACE (p. 499)
Design-specific PACE aims to maximize out-of-the box RTL power accuracy for register and clock
power using exact instance-to-instance cell mapping between RTL and gate. The model, when
applied at the RTL-level, helps to improve the accuracy of cell selection.

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 Capacitance Models

18.4. Capacitance Models

PACE models contain information to improve capacitance estimation accuracy. This has become
increasingly necessary for the following two reasons:

• Liberty files for smaller geometry sizes may not contain wire load model information.
• Wire load models are traditionally designed to help close timing and, as such, are more pessimistic
than what is most likely available in the real design.

You can use one of these commands to generate the model:

WriteTechnologyFile -generate_pace_model_category cap
WriteTechnologyFile -generate_pace_model_category all

You can use one of these commands to apply the model:

CalculatePower -use_pace_model_category cap
CalculatePower -use_pace_model_category all

Linear Capacitance Modeling

PACE capacitance models can improve RTL dynamic power predictability versus post-layout power by
applying a piecewise linear modeling approach. To enable linear capacitance modeling, use one of the
following methods:
pa_set pace_use_linear_cap_model <true | false>
CalculatePower -pace_use_linear_cap_model <true | false>

The default value of the variable 'false'.

Wire Capacitance Modeling

PowerArtist can categorize the net into a long or a short net, by using the coordinate information of
the pins for each fanout of net as obtained from the SPEF file. During RTL modeling, net wire capacitance
is estimated accordingly. Wire capacitance modeling is controlled by the following variable:
pa_set pace_cap_enhanced_variation_mode <true | false>

The default value of the variable is 'false'.

Note: To use this feature, ensure that pin coordinates are available in the input SPEF file.

To enable wire capacitance modeling, use the following commands:

pa_set pace_cap_enhanced_variation_mode true
pa_set spef_file <spef_file_name>.spef

or:
pa_set pace_cap_enhanced_variation_mode true
WriteTechnologyFile -spef <spef_file_name>.spef

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Generating and Using PACE Technology Files

18.5. Clock Distribution Network Models

Power correlation studies reveal that clock power represents a significant percentage of the total power
of a design. This clock power is due to the topology of the clock distribution network, the selection of
integrated clock gating cells (and their impact on reducing the clock frequency in the design) and the
power due to clock pins toggling on registers and memories. Each of these areas contributes to reduced
RTL power analysis accuracy.

A large percentage of the correlation problems encountered involve approximating the distribution
network topology that is ultimately chosen during clock tree synthesis and optimization. Key parameters
include the selection of clock buffers for branch, root and leaf buffers and the fanout that each buffer
drives. PACE may choose different buffers based on the frequency of the associated clock net. It makes
similar decisions for the ICGCs in the design.

Use one of these commands to generate the model:

WriteTechnologyFile -generate_pace_model_category clock
WriteTechnologyFile -generate_pace_model_category {cap clock}
WriteTechnologyFile -generate_pace_model_category all

Use one of these commands to apply the model:

CalculatePower -use_pace_model_category clock
CalculatePower -use_pace_model_category {cap clock}
CalculatePower -use_pace_model_category all

18.6. RTL Cell Selection

To improve the accuracy of cell selection, a statistical cell distribution model is implemented. Both the
generation and application of the model is transparent to the user. You can use one of these commands
to generate the model:
WriteTechnologyFile -generate_pace_model_category cell
WriteTechnologyFile -generate_pace_model_category {cap cell clock}
WriteTechnologyFile -generate_pace_model_category all

If the PACE model contains a cell model, it is automatically applied to the RT-level. You can choose to
selectively apply the cell model, by using one of the following commands:
CalculatePower -use_pace_model_category cell
CalculatePower -use_pace_model_category {cap cell}

Cell distribution from the PACE model is ignored if you have specified 'SetVT' commands.

18.7. Cell Mapping in PACE

To enable Enhanced Cell Mapping (p. 157) in the PACE flow, you must regenerate the PACE model using
the 21R2.X release. The regenerated PACE model includes data for the 'AND'/'OR'/'NOR'/'XNOR' gates
and their VT information. If data for 'AND'/'OR'/'NOR'/'XNOR' cells is not available in the PACE model or
the PACE model is generated using an older release, mapping is performed as per the older flow (using
'NAND'/'XOR' cells).

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 Generating a PACE Model

If 'pa_set map_original_gates' is set to 'true' and PACE model is regenerated using 21R2.X version,
cell mapping is based on the following rules:

• If a cell exists in the library and the mapping information is available in the (regenerated) PACE
model, then the PACE cell model is used.
• If a cell does not exist in the library and the mapping information is available in the (regenerated)
PACE model, cell mapping as per the non-PACE flow is used.
• If a cell exists in the library but the mapping information is not available in the (regenerated)
PACE model, cell mapping as per non-PACE flow is used.

Note: To enable cell mapping, the PACE model version is updated. You should regenerate the PACE
model if you see warning 'UTL-246'.

18.8. Generating a PACE Model

PACE file, aka the '.tech' file is an encrypted file generated using the 'WriteTechnologyFile' command
on a gate-level reference design. You have to execute this command within the 'pa_shell'. You cannot
specify this command directly on the UNIX command line. You can run this command using a Tcl script.

18.8.1. Selecting the Reference Design

Selecting the sample design that forms the basis for a PACE model is straightforward. First you need
to identify the technology node that needs the PACE model. Then select a design that has a SPEF
file, an SDC file, and a gate-level netlist. The design should be representative of an average design
in your application. If you have radically different design styles, you might want to generate a PACE
model for each style. While the analyzers only take one PACE model as input, you can create a library
of PACE models.

The reference design must meet the following criteria:

• Should be a post-layout, post-CTS design.

• Have the same technology as RTL.
• Be a similar design application as RTL.
• Preferably be the largest block routed flat.
• Have memories and other macros for capacitance of all types of logic.
• Have similar frequency clock domains.

18.8.2. Data Requirements

The design you choose must also meet the following constraints:

• Gate-level netlist
• SPEF file
80% or more of the nets in the design must be successfully back-annotated from your SPEF
file. Poorer back-annotation does not result in a representative PACE model.
• Library files in liberty format, including .libs for memories and other macros instantiated in the
design
• SDC file

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Generating and Using PACE Technology Files

The SDC file must successfully identify at least one placed and routed clock network in your
design. The SDC file must include the frequency for each of your clocks in order to generate
the PACE model. The SDC file assists in specifying 'SetClockNet' commands:
– For capacitance model, only clock root nets are needed.
– For clock tree model, clock frequencies are also needed.
• 'SetClockNet' commands with frequency information
• 'DefineMemory' commands for identification for memories
• The design must also contain registers and remaining combinational logic. IO pads and
instantiated memories are not required, but it is best if your design contains these logic
elements too.

18.8.3. Using a Tcl Command File

You should use a Tcl command script to generate your PACE technology file. This script should include
all required commands and input/output options. Save the script with a meaningful name, such as
'WriteTechnologyFile.tcl', and run it from within the 'pa_shell' as shown below:
pa_shell % source WriteTechnologyFile.tcl

or, execute it using the following command:

pa_shell -tcl WriteTechnologyFile.tcl

The following inputs are required:

• SPEF parasitic files

Specify these using the 'ReadParasitics' command.

• A Verilog startup file

Specify this using the '-verilog_startup_file' option to the 'WriteTechnologyFile'

command or the 'ReadVerilogStartupFile' command.

• The top module name

Specify this using the '-top' option to the 'WriteTechnologyFile' command.

• Technology library files

Specify these using the '-synlib_files' option to the 'WriteTechnologyFile' command

or the 'ReadLibrary' command.

• Clock definitions

These are captured in SDC files using the '-sdc_files' option to the 'WriteTechnologyFile'
command. This is the preferred input. If you do not have one that matches your design, you
can create one that is good enough to supply clock definitions or use SetClockNet' commands
to define the clocks.

• User-defined information

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 Generating a PACE Model

You can optionally use the 'SetPowerTechComments' command to add user-defined

information to your PACE model file.

• The PACE technology file name

Specify the '-power_tech_file' option to the 'WriteTechnologyFile' command. This is

the name that PowerArtist gives to the generated PACE technology file. This value can be an
absolute name or a relative path.

Note: If you do not specify a path, the output file is created in the run directory.

For the complete command syntax, see the 'WriteTechnologyFile' command in the PowerArtist
Reference Manual.

18.8.4. Resource Tracking During PACE Generation

The tool tracks resources as it reads each SPEF input file.

The following snippet shows messages from a sample log file:

Note UTL-276: Started Reading SPEF file <..filepath/filename.spef>.
Resource usage: Total(0:00:00 elapsed, 0:00:00 cpu, 382Mb used, 532Mb peak).

Note UTL-277: Finished Reading SPEF file <..filepath/filename.spef>.

Resource usage: Total(0:00:00 elapsed, 0:00:00 cpu, 386Mb used, 532Mb peak),
Incr(0:00:00 elapsed, 0:00:00 cpu, 3.67Mb used, 0b peak).

18.8.5. Sample PACE Generation Script

You can use the following script as a template to generate a PACE model:
# Sample WriteTechnologyFile.tcl
# Read library files
ReadLibrary -name ../lib/mylib.lib

# Specify memories
DefineMemory -library {}

# Read gate level netlist and elaborate the design

pa_set top top
pa_set gate_level_netlist true
pa_set scenario_file top.scn
pa_set power_db_name top.pdb
Elaborate \
-verilog_startup_file top.f
-verilog_2001 true
-elaborate_write_power_db true

# Specify default transition time

pa_set default_transition_time 100e-12

# Disable capacitance estimation for nets missing in SPEF

pa_set no_module_net_capacitances true

# Read SPEF. There are several ways to make

# this happen depending on the complexity of your design. Follow
# the methodology established by Synopsys.
ReadParasitics -path top -file top.spef

# Read SDC file

ReadSDC -sdc_files ../sdc/top.sdc -sdc_out_file top.scr
source top.scr

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Generating and Using PACE Technology Files

# Or Specify SetClockNet commands with –frequency and –mode trace

# SetClockNet –name top.clk –frequency 100e+06 –mode trace

# Define multi-bit cells if design contains multi-bit cells

DefineMultiBitCell -name cell_names \
-library logical_library_names

# Add user-defined comments to the PACE model

SetPowerTechComments "Design= txtop\n Lib= typical\n SPEF= txtop.poly.spef"

# Generate PACE Model

WriteTechnologyFile \
-power_tech_file top.tech \
-generate_pace_model_category [cap | clock | all]
-tech_file_log WriteTechnologyFile.log

Notes:

• The '-default_transition_time' option

While this is optional, it is best to specify this if it cannot be extracted from the SDC file. If you
do not specify this value, 100ps is assumed. If you do not specify this option and PACE could
not determine if from your SDC file, the following message is issued:
Warning ENG-598: Absence of a default slew or transition time file limits the
accuracy of the generated PACE model. Please consider supplying
default slew (pa_set default_transition_time) or transition
time file (pa_set transition_time_file). Using 100ps as the
default slew for PACE model generation.

• 'SetClockNet' commands

If you are not using an SDC file, you need specify the '-frequency' option to the 'SetClockNet'
command. PACE generates clock models as a function of clock frequency. If you do not specify
'-frequency' and PACE is unable to determine the clock frequencies from the SDC file, the
following message is issued:
Warning ENG-92: Absence of frequency on Clock "foo" limits the accuracy of
the generated PACE model. Please consider supplying frequency
for all clocks.

The design for which you choose to create the PACE model should use a reasonable number
of different clock frequencies. The clock nets, when traced, should also have a reasonable
number of sub-nets (at least 50). PowerArtist generates a summary for each net traced using
messages 'ENG-532' and 'ENG-533':
Note ENG-532: Below are clock subnet counts for all clock nets
in the design. The design should be a post CTS netlist
and all subnet counts should be high. The counts are the
number of traced nets in the clock distribution network.

Clock Subnet Count Clock Name

2758 top.clk1
6 * top.clk2
60 top.clk3

Warning ENG-533: Some of the clocks mentioned in Note 9922 above

have very low subnet count. Please check clock
definitions.

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 Using a PACE Model

Note: Nets that do not have at least 50 sub-nets are flagged with an '*' in message 'ENG-532'.
In addition, the design should use clock gating cells. If there is no clock gating in the design,
the resulting PACE model cannot be used in subsequent analysis runs where clock gating is
requested.

• Adding comments to the PACE model

The 'SetPowerTechComments' command is specified in the sample script. This command

allows you to add user information/comments to your PACE model file when you generate it.
You simply specify a string to this command, which could include the new line ('\n') and tab
('\t') characters. For the example line in the script, PowerArtist generates the following
information while reading the PACE file:
Note UTL-3: reading pace file power.tech
power tech information: Design = txtop
power tech information: Lib = typical
power tech information: SPEF = txtop.poly.spef

In addition, it prints Note 'UTL-7' to indicate the types of models in the PACE file:
Note UTL-7: found following power models:
capacitance model
clock network model

18.8.6. Understanding the Internal Process

When the 'WriteTechnologyFile' runs, it goes through the following process:

1. Performs HDL Inferencing on your design. It runs the 'Elaborate' command using the Verilog
startup file, the Liberty libraries, and the top-level module name. By default, this process
creates a scenario file called 'top.scn'. For the sample script, it is 'top.scn'.

2. Performs the first phase of the power analysis. It reads the scenario, Liberty, and SPEF file(s)
and builds the capacitance model and the clock distribution network model.

3. Writes the PACE model file. For the sample script above, the PACE model is saved in
'power.tech'.

As with all commands that perform extensive processing, you can specify the '-wait_for_license
true' option. Specify wait_for_license_timeout <int> to wait for the specified number of
seconds while checking for license availability.

18.9. Using a PACE Model

You can use the PACE model or '.tech' file for power analysis of RTL or pre-layout gate design using
following options:
CalculatePower -power_tech_file top.tech \
-use_pace_model_category [cap | clock | all]

By default, all models present in the pace file are used for power analysis. A PACE model file contains
capacitance models, clock distribution network models, and cell models. The capacitance models improve
capacitance estimation accuracy. Similarly, the PACE clock distribution network models improve the

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Generating and Using PACE Technology Files

modeling of distribution network topology and improve power analysis accuracy. The models apply to
a pure gate-level, mixed gate and RTL, or pure RTL power analysis.

18.9.1. Using Clock Distribution Network Models

The clock distribution network PACE models are designed to replace the 'SetClockBuffer' and
'SetClockGatingStyle' commands as much as possible. Since they are frequency dependent
(PowerArtist performs clock buffer selection based on frequency domains), you must specify the
'-frequency' option to the 'SetClockNet' command when you generate and use a PACE model.
You may also have to specify 'SetAttribute' commands to enable/disable the 'dont_use' attribute
in your Liberty library to control which clock buffers or ICGCs are chosen as a result of the electrical
parameters stored in the PACE model. The following run script is a good example:
SetClockNet -name clk1 -frequency 5e+08 -mode infer -clock_gate yes
SetClockNet -name clk2 -frequency 2e+08 -mode infer -clock_gate no
SetClockNet -name clk3 -frequency 1e+08 -mode infer -clock_gate yes

SetAttribute -cell CKENAIAX8 -library typical -name dont_use -value false

SetAttribute -cell BUFX16 -library typical -name dont_use -value true

CalculatePower -analysis_type average \

-scenario_file top.scn \
-synlib_files synlib.lib \
-verilog_startup_file verilog_files.vc \
-power_tech_file power.tech \
-top top \
-default_transition_time 64e-12 \
-domain_frequency_cell_selection true

Note the following points about this run script that uses a PACE model:

• The 'SetClockNet -frequency' option is specified for all clocks in the design.
• The 'SetAttribute' commands in this script ensure that cell 'CKENAIAX8' is considered as an ICGC
and buffer 'BUFX16' is not considered at all.
• The final line in this script is the 'CalculatePower' command that includes the PACE model through
the '-power_tech_file' option and other required parameters.
Note: You can also specify the '-power_tech_file' option with the 'ReducePower' command.

18.9.2. Using the SetClockGatingStyle Command

You can use the 'SetClockGatingStyle' command if you want explicit control over the following two
parameters:

• The '-min_bit_width' constraint

This overrides any value determined by the PACE model.
• The '-structure <branch | leaf>' option
This controls whether ICGCs directly fanout to registers ('leaf') or whether ICGCs can fanout
to buffers that then drive registers ('branch'). You can use this option to increase analysis
accuracy if you understand what happens during clock tree synthesis (CTS) and design
optimization. By default, the 'branch' or 'leaf' value is determined when the PACE model
is created and then that value is applied to your design.
You can see the impact of the '-structure' option in two different note messages that are
printed to your log file during power analysis:

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 Using a PACE Model

– ENG-189: Clock net <name> drives <int> enabled register bits.

These registers are being considered for clock gating.
<int> ICGCs (with fanout=<int>) will be used to clock
gate these.

– ENG-192: Clock net <name> drives <int> enabled register bits.

<int> <branch|leaf> ICGCs (with fanout=<float>) were used to
clock gate <int> registers. <int> registers were left ungated.

All other parameters specified with the 'SetClockGatingStyle' command are ignored when
using a PACE model.

18.9.3. Advanced Buffer Modeling

The PowerArtist tool can also generate advanced buffer and repeater PACE models, and insert them
during RTL power analysis. The advanced buffer models capture statistics related to high fanout net
buffer trees and repeater chains from a representative gate-level design. This statistical data is used
on RTL netlist to infer buffer trees and repeaters.

For more details, refer to the Advanced Buffer Modeling in PACE (p. 491) chapter.

18.9.4. Understanding Priorities and Precedence When Using PACE Models

When using a PACE model, you must recognize the following priorities:

• Manual back annotation methods take precedence over PACE models. This includes SPEF files, wire
capacitance files, output load files, and default output load capacitance.
• PACE models take priority over any wire load model-based capacitance estimation technique you
have applied. This includes SetWireLoadModel, default wire load library lookups in Liberty files,
and the 'seqcap.lib' default wire load model.

Also, it is your responsibility to determine that the PACE model is applicable to your design. At a
minimum, you should ensure that the technology node is the same as the one used to create the
PACE model.

18.9.5. Additional Guidelines for Using PACE Models

PACE models affect the way some PowerArtist commands are applied during power analysis. Remember
the following guidelines when writing scripts that use PACE models:

• Do not use the 'SetClockBuffer' command with a PACE model. This command is ignored completely.
Warning 'ENG-159' is issued if 'SetClockBuffer' is specified with a PACE model file when performing
a power analysis:
ENG-159: All SetClockBuffer command(s) in clock file foo.clk are
being ignored. Since clock power estimation is performed
using PACE file (aka power_tech_file).

• Do not specify the 'SetCellDefaultFanout' command as it has no effect when used with PACE
models.
• The following additional options are available to calibrate clock tree inferencing using the PACE
model:
– To infer inverter cells based clock tree, use:

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Generating and Using PACE Technology Files

pa_set pace_infer_inverter_clock_tree true

– To infer balanced buffers with same rise and fall slew, use:
pa_set pace_use_balanced_clock_buffers true

– To provide a list of clock buffers/inverters (same as a CTS tool), use:

pa_set pace_clock_buffer_list {clock_buffer_list}

Note: Wild cards are not supported in buffer names

– Specify minimum bit width of clock gating:
SetClockGatingStyle -min_bit_width 3

– To determine clock tree structure after clock gates, use:

SetClockGatingStyle -structure <branch | leaf>

– To eliminate undesired buffers, use the 'SetAttribute' command:

SetAttribute –cell {} –library {}
–name dont_use –value true
pa_set honor_dont_use_for_clock_tree true

– To honor user-specified 'root / branch / leaf' buffers (specified using 'SetClockBuffer'

commands) and PACE model to determine fanouts/ICGC, use:
pa_set pace_user_clock_buffers true

18.9.6. Understanding Output File Changes due to PACE Models

You can view PACE-related changes in the following files:

• Log File
PACE-related messages appear in the respective ('CalculatePower'/'ReducePower') log files.
• Report Files
Several additional sections are added to the report files while using a PACE model. For example,
if buffers are identified while using a PACE model, the report file has PACE explicitly identified,
as in the following sample output:
PACE Inferred Buffer Tree:
Net name : top.clk_2_0
Driver instance: top.U_2_0
Frequency : 100MHz
Number of Loads: 16
PACE Root Driver :
Cell : BUFX12
Library : typical
Count : 1
Cell maximum fanout : 8
Buffer power: static 1pW; dynamic 32.5uW
Fanout capacitance: wire 217fF; pins 17.4fF

PACE Branch Driver :

Cell : BUFX12
Library : typical
Count : 2
Cell maximum fanout : 8
Buffer power: static 2pW; dynamic 65uW
Fanout capacitance: wire 434fF; pins 34.9fF

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 PACE Technology Migration

PACE Leaf Driver :

Cell : BUFX12
Library : typical
Count : 4
Cell maximum fanout : 8
Buffer power: static 4pW; dynamic 130uW
Fanout capacitance: wire 868fF; pins 69.8fF

18.10. PACE Model Version

PowerArtist generates PACE technology files from gate-level netlists that can then be used during RTL
power analysis for better accuracy. These models are enhanced regularly to improve RTL power accuracy.

In some cases, when a PACE model generated with an older version of PowerArtist is incompatible with
a newer version of PowerArtist, it can report inaccurate results that can be difficult to identify. To resolve
this issue, the following warning will be issued to report a version mismatch:
Warning UTL-246 : There is a version mismatch between PACE version
'1.0' and the supported version '1.1'. Regenerate the PACE model
using current release version of 'PowerArtist/XP 18.1.1'

In addition to the warning, the message includes a recommendation to regenerate the PACE model for
improved results. The warnings appear on the standard output and the logs generated during power
analysis (CalculatePower) and power reduction (ReducePower).

The 'reportPaceInfo' utility is enhanced to print the version information from the PACE model file.
PACE models generated prior to the 18.1.1 release are regarded as version '1.0' and are backward
compatible. They are read and a warning is issued, which includes a recommendation to regenerate
the PACE model. The version of PACE model generated with 'PowerArtist 18.1.1' is '1.1'. This is updated
to '1.5' in 'PowerArtist 2021R2.1'.

The version information of a scaled PACE model (generated using the utility 'paceScaleCaps'), is the
same as the input PACE model.

18.11. PACE Technology Migration

PowerArtist features seamless migration of PACE models from older to newer technology. The tool
provides automated capacitance scaling and library cell migration, ensuring high accuracy and efficiency.

If you used older technology PACE models on a newer technology node, the power estimation during
RTL power analysis would be inaccurate compared to their respective gate-level power numbers.

To reuse the older technology files, such as 5nm cell models, on designs for a newer technology node,
such as 3nm, the PowerArtist tool now introduces the pa_set variable perform_tech_migration.

The following shows the usage flow for technology migration:

Inputs
First, you must re-generate library files based on newer technology.

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The following inputs are required to enable the technology migration in PACE-based power analysis
flow:

1. To enable technology migration, use the following command:

pa_set perform_tech_migration true

By default, the flow is disabled, which means the pa_set variable is false.
2. The following elements constitutes complete technology migration:
• Capacitance Scaling
• Cell Migration
To ensure cap scaling, you must provide old as well as new technology files, using the following
pa_set variables:
pa_set tech_file_for_older_process_node <old_tech_file name>

pa_set tech_files <new_tech_file name>

3. To improve the accuracy of technology migration, you can define attributes which help identify
unique cell patterns for cell mapping. Use the 'DefineTechMigrationPatterns' command with the
following attributes:
DefineTechMigrationPatterns
–source_cell_drive_strength <>
-target_cell_drive_strength <>
–source_cell_vt_group <>
-target_cell_vt_group <>
–source_cell_func <>
-target_cell_func <>

4. Use the DefineTechMigrationVTMapping command for more accurate cell mapping for different
cell function types during TechMigration:
DefineTechMigrationVTMapping -source_cell_vt_group <>
-target_cell_vt_group <> -pace_cell_function_type <>

The command is used to map the source VT group cells to the missing target VT group cells.
DefineTechMigrationVTMapping also supports the function type pattern matching to filter out
the potential mapping cells having same cell function type pattern as that of given source technology
cell.
For example, consider the source technology node as 5nm and target technology node as 3nm. You
can map the VT group cells which are available in source (5nm) PACE file but not in target (3nm)
PACE file to ones which are present in 3nm, but not in 5nm PACE files.

Outputs
When technology migration is enabled in SPEF flow, a migrated PACE file is generated with the name
migratedPace.tech in a sub-directory tech_migration_work.

By default, the tool uses this new PACE file instead of the older PACE file for power analysis.

18.12. Useful APSH Utilities for PACE

The following utilities are available to query PACE model data:

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• pacePlotCapTables
• pacePlotEstimatedCapTables
• paceScaleCaps
• reportPaceInfo

See the section titled 'PACE Query Commands' in the PowerArtist Reference Manual for complete details
of these utilities.

18.13. Performing Correlation Studies

After creating a PACE model, a CAD engineer may want to validate the quality of the PACE model when
used at the RT-level and compare it to a gate-level run with a back annotated SPEF file.

18.13.1. Setting Up Your RTL Analysis Environment

Remember to do the following at the RT-level:

• Use the 'SetClockNet -frequency' command for every clock net in the RTL design.
• When you specify the '-frequency' option, frequency-based cell selection is initiated, which is
orthogonal to mixed VT designs. In the PACE flow, frequency-based cell selection is disabled, by
default. To enable frequency-based cell selection, specify the following 'CalculatePower' option:
-domain_frequency_cell_selection true

• Pin-based analysis is the default for gate-level analysis. The same type of analysis must be done
for both gate and RTL. To disable arc-based estimation for your RTL design, specify the following
'CalculatePower' option:
-arc_based_estimation false

• Set the following to allow ICGCs to drive buffers rather than duplicating ICGCs that then drive
register clocks directly:
SetClockGatingStyle -structure branch

• Disable the 'dont_use' attribute for your clock buffers and ICGCs in your Liberty files by setting
the following environment variable:
setenv PT_PACE_CLK_DONT_USE false / -honor_dont_use_for_clock_tree false

By default, PACE models honor the 'dont_use' attribute on clock buffers and clock gating cells.
• Do not use the 'SetCellDefaultFanout' command. It changes the 'max_fanout' of all ICGC cells
in the library along with other cells and adversely impacts ICGC cell selection.
• Do not use the '-hierarchy' and '-instance' options of the 'SetClockNet' command with the
'-gate_clock yes' option while doing a correlation exercise. The options may change the
number of ICGCs inserted depending on how an enable signal is split in the hierarchy.

Note: While performing correlation exercises to understand and evaluate PACE models, do not use
a PACE model that includes only capacitance models.

18.13.2. Setting Up Your Netlist Analysis Environment

Remember to do the following when performing gate-level netlist power analysis:

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• Do not perform an arc-based power estimation.

• Specify the SPEF file to provide back-annotated capacitance values.
• Define your clocks using the following command:
SetClockNet -mode trace

This allows you to correlate the PACE clock network distribution model to an actual distribution
network.

18.13.3. Leading Correlation Indicators

The RTL and gate-level values for certain key statistics should closely match to ensure a high level of
correlation. Gather and evaluate the following key statistics while doing correlation studies:

• Gated Register Bits

The number of gated registers bits (both inferred and instantiated ICGCs) should match the
number of gate register bits at the gate-level.
• ICGC Count
The total number of inferred and instantiated ICGCs at RTL should match the gate-level
instantiated ICGC count.
• Register Selection
The default register chosen for RTL analysis should closely match the predominant flop at the
gate-level.

18.14. Multi-bit Flip-Flop (MBFF) Mapping in PACE Flow

PowerArtist supports two methods of mapping flops to multi-bit flip-flops (MBFF):

• In the first (default) method, PowerArtist attempts to map as many flip-flops to MBFFs as possible
and reports the percentages through the following message:
Note ENG-951 : MBF mapping performed for <x>% register bits based on RTL
even though the MBF mapping in PACE was <y>%. To apply the
MBF mapping threshold from PACE, use 'pa_set
pace_enable_multibitcell_mapping_threshold true'

• In the second method, the % of flops to be mapped to multi-bit flip-flops (MBFF) is derived from
the PACE cell model and applied during cell selection in RTL power analysis. This helps with
predictable RTL power accuracy compared to the reference gate design. Use the following variable
to enable this method:
pa_set pace_enable_multibitcell_mapping_threshold true

18.15. PACE Model per Hierarchy

In order to improve the accuracy of PACE-based RTL power analysis, a hierarchical PACE flow is available.
You can generate PACE models for different sub-blocks of the design and then apply them to the same
blocks when doing power analysis. This is especially useful for large chips where different blocks may
have significant differences in their physical implementation.

The hierarchical PACE flow is a two-step process as follows:

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 Using Incremental VT Settings for Cell Assignment/Selection

1. Use the 'WriteTechnologyFile' command to generate PACE models for different blocks in the
design.

2. Use the 'MapTechnologyFile' command during power analysis to apply PACE models to specific
blocks in the design. The syntax is as follows:
MapTechnologyFile -file <pace_model_path> \
-instance <hierarchical_instance_path>

Notes for using multiple PACE models:

• You can use multiple 'MapTechnologyFile' commands to map different PACE models to different
hierarchies in the design.
• The 'MapTechnologyFile' command specified for a lower-level design hierarchy overrides the
'MapTechnologyFile' command specified at higher-levels in the design hierarchy.
• If two or more 'MapTechnologyFile' commands are specified for the same instance hierarchy,
the one appearing later overrides the 'MapTechnologyFile' command specified earlier.
• The PACE model file specified using the 'CalculatePower -power_tech_file <filename>'
command is used as the default PACE model for the top- level design. This file is overridden if
a 'MapTechnologyFile' command is specified for the top-level design.

The hierarchical PACE models work for capacitance estimation and cell selection. The clock models are
derived only from the PACE model applied to the top module of the design. For cell selection, it can
be controlled by generating and applying individual PACE models at different hierarchical levels. This
enables better correlation for blocks with different design characteristics and constraints.

18.16. Merge Multiple PACE Models

Use this feature to pool data collected from several designs into a single PACE model file to improve
RTL power accuracy. You can use the 'MergeTechnologyFiles' command to merge multiple PACE model
files to generate a single PACE model file as output.

Note: The 'MergeTechnologyFiles' command does not support merging already merged PACE files.

18.17. Using Incremental VT Settings for Cell Assignment/Selection

With semiconductor foundries providing standard cell libraries with multiple VT offerings for design
flexibility in low power domains, designers often face a challenge in choosing the right mix of multi-VT
cells when providing optimization constraints to EDA tools. To meet this challenge, PowerArtist supports
what-if power analysis for various combinations of multi-VT cells with incremental VT settings to override
PACE cell models. On completing the what-if power analysis, designers can use the power analysis
results to specify the multi-VT constraints for logic and/or physical synthesis tools and reduce their time
to market.

This feature (to use incremental VT settings) is enabled through the following two enhancements:

• Enhanced 'WriteTechnologyFile' command to explicitly recognize and process VT groups when

generating the PACE technology file. The 'WriteTechnologyFile' command classifies cells into
multiple voltage threshold groups using information from:
– Library annotations for voltage threshold groups.

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Generating and Using PACE Technology Files

– Cell annotations for voltage threshold groups.

– User-specified cell patterns from the 'SetVoltageThreshold' command. The
'WriteTechnologyFile' command is enhanced to process the 'SetVoltageThreshold'
command.

• Enhanced 'CalculatePower' and 'ReducePower' commands to honor simultaneous use of PACE

cell models with multi-VT settings during power analysis and reduction.

The power analysis and reduction flows support multi-VT overrides to the PACE cell models at
various design hierarchies and/or functional categories with two different methodologies:

– 'SetVT' command methodology

Uses library cell information from the PACE cell model but overrides the multi-VT
distribution captured in the PACE model with user-specified 'SetVT' values.

Uses the 'SetVT' methodology when same libraries with the same voltage threshold
groups are used for RTL and representative gate designs.

– 'SetVoltageThreshold' command with 'SetVT' command methodology

Overrides library cell information and multi-VT distribution from the PACE cell models
with user-specified 'SetVoltageThreshold' and 'SetVT' values.

Use the 'SetVoltageThreshold' command with the 'SetVT' command when:

Migrating to a new technology node.
Using a different VT group for the same technology node.
Combining new or alternative VT groups with the voltage threshold groups
contained in the PACE technology file.

This updated flow is shown below:

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 Using Incremental VT Settings for Cell Assignment/Selection

PACE Generation for Incremental VT Setting Override

To enable this flow during PACE generation, do the following:

1. Specify annotated standard cell libraries used by the representative gate design. Annotate the
standard cells one of the following three methods:
• Annotate voltage threshold group information on the standard cells using Synopsys'
Library Compiler™ library level voltage threshold attribute:
default_threshold_voltage_group : "string";

• Annotate voltage threshold group information on the standard cells using Synopsys'
Library Compiler™ cell-level voltage threshold attribute:
threshold_voltage_group : "string";

• Annotate voltage threshold group information on the standard cells with user-specified
'SetVoltageThreshold' command:
SetVoltageThreshold -group LOW_VT -pattern {*L}
SetVoltageThreshold -group HIGH_VT -pattern {*H}

2. Specify the PACE models to generate:

pa_set generate_pace_model_category {[cap] [clock] cell}

3. Specify a name for output PACE technology file:

pa_set power_tech_file <filename>

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Generating and Using PACE Technology Files

4. Specify the required inputs to the 'WriteTechnologyFile' command to generate the PACE
model:
WriteTechnologyFile <options>

5. Run the 'reportPaceInfo' command to view a summary of the information captured in the
PACE technology file:
reportPaceInfo <options>

The 'WriteTechnologyFile' command uses the following precedence rules to determine the association
of a VT group with a standard cell when multi-VT attributes are provided using the different methods
shown in the table below:

Table 18.1: Precedence Rules for the WriteTechnologyFile command

Library Scope VT Cell Scope VT User-specified VT Result

Not Specified Not Specified Not Specified PowerArtist's default VT
Not Specified Not Specified Specified User-specified VT
Not Specified Specified Not Specified Cell Group VT
Not Specified Specified Specified User-specified VT
Specified Not Specified Not Specified Library Group VT
Specified Not Specified Specified User-specified VT
Specified Specified Not Specified Cell Group VT
Specified Specified Specified User-specified VT

Power Analysis/Reduction Incremental VT Setting Overrides with SetVT

To use alternate multi-VT distribution with PACE cell models, do the following:

1. Use the 'reportPaceInfo' command on the generated PACE technology file to obtain voltage
threshold groups and their distribution:
reportPaceInfo -in pace.tech
reportPaceInfo -in pace.tech -out pace.info.out

2. Ensure that the voltage threshold annotations of input libraries match the PACE technology
file design voltage threshold groups.

3. Specify mixed-VT distribution to use for RTL analysis with the SetVT command:
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {HVT:70 LVT:30}
SetVT -mode percentage -type {mux} -instance top -vt_group {HVT:50 LVT:50}

4. Provide the PACE technology file as input:

pa_set power_tech_file <filename>

5. Specify the PACE models to use for RTL analysis:

pa_set use_pace_model_category {cell [cap] [clock]}

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 Using Incremental VT Settings for Cell Assignment/Selection

6. Run RTL power analysis ('CalculatePower') or power reduction ('ReducePower'):

CalculatePower <options>
ReducePower <options>

Power Analysis/Reduction Incremental VT Setting Overrides with

SetVoltageThreshold + SetVT
To override library cell information and multi-VT distribution from the PACE cell models with user-specified
'SetVoltageThreshold' and 'SetVT' values, do the following:

1. Use the 'reportPaceInfo' command to obtain voltage threshold groups and their distribution:
reportPaceInfo -in pace.tech
reportPaceInfo -in pace.tech -out pace.info.out

2. Specify annotated standard cell libraries for RTL analysis with some/all voltage threshold groups
different from the PACE technology file voltage threshold groups. Annotate the standard cells
using one of the following three methods:
• Annotate voltage threshold group information on the standard cells using Synopsys'
Library Compiler™ library-level voltage threshold attribute:
default_threshold_voltage_group : "string";

• Annotate voltage threshold group information on the standard cells using Synopsys'
Library Compiler™ cell-level voltage threshold attribute:
threshold_voltage_group : "string";

• Annotate voltage threshold group information on the standard cells with user-specified
SetVoltageThreshold command:
SetVoltageThreshold -group SLVT -pattern {*SLVT}
SetVoltageThreshold -group RVT -pattern {*RVT}

3. Specify multi-VT distribution to use for RTL analysis with the SetVT command:
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {SLVT:40 RVT:60}
SetVT -mode percentage -type {mux} -instance top -vt_group {SLVT:30 RVT:70}

4. Provide the PACE technology file as input:

pa_set power_tech_file <filename>

5. Specify the PACE models to use during RTL analysis:

pa_set use_pace_model_category {cell [cap] [clock]}

6. Run RTL power analysis ('CalculatePower') or power reduction ('ReducePower'):

CalculatePower <options>
ReducePower <options>

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Generating and Using PACE Technology Files

RTL analysis and reduction flows use the precedence rules from Table 2 (p. 488) and Table 3 (p. 488) for
user-specified VT group overrides:

Table 18.2: User-specified VT Group Override Precedence Rules

SetVoltageThreshold SetVT Cell Selection Cell Distribution

Not Specified Not Specified PACE cell selection PACE distribution
Not Specified Specified PACE cell selection SetVT distribution
Specified Not Specified SetVoltageThreshold Refer Table 3 (p. 488).
based cell selection
Specified Specified SetVoltageThreshold SetVT distribution
based cell selection

Table 18.3: When SetVoltageThreshold command is specified

PACE- Gen SetVoltageThreshold RTL SetVT Result

Override
SetVoltageThreshold cell patterns and Not Specified PACE cell selection and PACE VT cell
VT groups are same as PACE-Gen distribution
SetVoltageThreshold cell patterns and Not Specified Error due to missing VT distribution
VT groups are different from PACE-Gen for new VT groups
SetVoltageThreshold cell patterns and Specified PACE cell selection and SetVT
VT groups are same as PACE-Gen distribution
SetVoltageThreshold cell patterns and Specified SetVoltageThreshold-based
VT groups are different from PACE-Gen cell-selection and SetVT distribution

Outputs
The following reports are updated to indicate user-override:

• PACE Report

The report generated by the 'reportPaceInfo' command provides summary information about
the PACE technology file and includes two new sections for VT-groups. A sample report is shown
below:
<snip>

User Specified Mixed-Vt Groups:

-------------------------------
VT GroupName: LOW_VT
Cell Pattern: *L

VT GroupName: HIGH_VT
Cell Pattern: *H
...
...
<snip>

Mixed-Vt Distribution:
----------------------

VT Source Usage VT Group Name

--------- ----- -------------
User Specified 86.3% HIGH_VT

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 Using Incremental VT Settings for Cell Assignment/Selection

User Specified 1.13% LOW_VT

Library Attribute 12.5% NORMALVT_70NM
PA Default 0% PA_defaultVT
...
...
<snip>

The sort order of the 'VT Group Name' column in the 'Mixed-Vt Distribution' section of the report
is as follows:
– User Specified VT in descending order
– Library Specified VT in descending order
– PA_defaultVT

• Average Power Report

The 'Mixed-VT Cells Distribution' section of the average power report prints the 'VT group'
information under the 'VT Group Name' column when available. A sample report is shown below:
8. Mixed-VT Cells Distribution
==============================

Hier-Instance Model VT Group Specified Number of Cells

Name Name Name Percentage Selected
------------- --------- -------- ---------- ---------------

top
Flop
SEQSDFFRQX1MTH HIGH_VT 41.1765 628
SEQSDFFQX1MTH HIGH_VT 41.1765 46
SEQSDFFQX1MTL LOW_VT 17.6471 19
---------------
Total 693
Inverter
SEQINVX12MTL LOW_VT 30.003 6
SEQCLKINVX1MTH HIGH_VT 23.3323 9
SEQCLKINVX16MTH HIGH_VT 23.3323 10
SEQCLKINVX12MTH HIGH_VT 23.3323 10
---------------
Total 35
Mux
SEQMX2X1MTH HIGH_VT 70 808
SEQMX2X2MTL LOW_VT 30 1
---------------
Total 809
Nand
SEQCLKNAND2X2MTH HIGH_VT 70 499
SEQCLKNAND2X2MTL LOW_VT 30 161
---------------
Total 660
Xor
SEQXOR2X1MTH HIGH_VT 70 318
SEQXOR2X1MTL LOW_VT 30 136
---------------
Total 454
Full Adder
SEQADDFX4MTH HIGH_VT 23.3323 8
SEQADDFX2MTH HIGH_VT 23.3323 7
SEQADDFX1MTH HIGH_VT 23.3323 7
SEQADDFX4MTL LOW_VT 15.0015 0
SEQADDFX2MTL LOW_VT 15.0015 0
---------------
Total 22
Rest of the Models
---------------
Total 0

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• Cell Selection Report

The cell selection report prints the 'VT group' information under 'VT Group' column when available.
A sample report is shown below:
Cell VT Group Function Class Occurrence

1. Cell summary of inferred netlist elements.

SEQCLKNAND2X2MTL LOW_VT Nand LowFast 161

SEQINVX12MTL LOW_VT Inverter LowFast 6
SEQMX2X2MTL LOW_VT Mux LowFast 1
SEQSDFFQX1MTH HIGH_VT Scan flop HighFast 46
SEQSDFFQX1MTL LOW_VT Scan flop HighFast 19
<snip>

2. Cell summary of inferred clock tree and net buffer tree.

SEQCLKBUFX4MTH HIGH_VT Branch clock buffer - 1

SEQCLKBUFX8MTH HIGH_VT Leaf clock buffer - 28
SEQCLKBUFX8MTH HIGH_VT Leaf net buffer - 11

3. Cell summary of inferred clock gates.

SEQTLATNTSCAX2MTH HIGH_VT Clock gate - 10

4. Cell summary of instantiated netlist elements.

DP256x32 - Memory - 8
DP512x32 - Memory - 12
SEQPIC - Buffer - 150
SEQPOC8A - Buffer - 137
<snip>

• Messages

Several new warnings (UTL-259, UTL-260, UTL-261, and ENG-956) and notes (UTL-262, FFR-127,
and ENG-955) are added to improve usability and enable easy debugging. A sample message
is shown below:
Warning UTL-259 : PACE model cells are missing from the libraries. For more accurate
analysis, specify the libraries containing these cells:
M8SDFRB1

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Chapter 19: Advanced Buffer Modeling in PACE
19.1. Introduction
The advanced PACE buffer models provide information related to design constraints, that must be
satisfied by the RTL design and buffer cells, to be used during buffer tree synthesis. Thus, the models
ensure that all RTL instances meet PACE captured design constraints by inserting enough buffers and/or
inverters.

You can configure additional options to differentiate power management cells such as isolation buffers,
level shifters, always-on buffers, power switches and physical cells such as filler, decap, well tap and
antenna cells from buffers used for high fanout net buffer tree synthesis, hold fixing and delay fixing.
Categorization of buffers with library attributes and pa_set variable configuration ensures data integrity
for PACE buffer and repeater models.

Chapter Organization
The following topics are covered in this chapter:

• Generating PACE Buffer and Repeater Models (p. 491)

• Using the PACE Buffer and Repeater Models (p. 492)
• Data Visualization and Debugging for PACE Buffer and Repeater Models (p. 493)
• Limitations (p. 493)
• Appendix I : Auxiliary Commands and Recommendations for PACE Buffer Categorization (p. 494)

19.1.1. Generating PACE Buffer and Repeater Models

To enable PACE buffer and repeater model generation, do the following:

1. Specify the power management cells and physical cells used in the gate netlist using
appropriate pa_set commands enumerated under Appendix I : Auxiliary Commands and
Recommendations for PACE Buffer Categorization (p. 494).

For example;
#sample pa_set commands for buffer categorization
pa_set pace_clock_cells { CK* }
pa_set pace_clock_isolation_cells { CKLI* }
pa_set pace_clock_level_shifter_cells { CKLV* }
pa_set pace_level_shifter_cells { LVL* }
pa_set pace_isolation_cells { IS* }
pa_set pace_antenna_cells { ANTENNA* }
pa_set pace_filler_cells { *FILL* }
pa_set pace_welltap_cells { TAPCELL* }
pa_set pace_always_on_cells { PT* }
pa_set pace_hold_buffer_cells { DEL* }
pa_set pace_switch_cells { HDR* }
pa_set pace_decap_cells { GDCAP* }

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Advanced Buffer Modeling in PACE

2. To generate PACE buffer and repeater model, use the following highlighted options:
pa_set generate_pace_model_category {cap clock cell buffertree repeater}

3. To generate the PACE technology file, use the following command:

WriteTechnologyFile

WriteTechnologyFile command uses the following information to categorize buffers:

a. Library attributes is_isolation_cell and is_level_shifter from Liberty.

b. Pre-configured instance name patterns using the pa_set commands mentioned in the
Instance Names of Appendix I : Auxiliary Commands and Recommendations for PACE
Buffer Categorization (p. 494). Instance names support wild card character *.

c. Pre-configured library cell name patterns using the pa_set commands mentioned in the
Library Cell Names of Appendix I : Auxiliary Commands and Recommendations for PACE
Buffer Categorization (p. 494). Library cell names support wild card character *.

4. To view the result summary for the PACE buffer and repeater models, use the following
command:
reportPaceInfo -in <pace-technology-file> -out <output-filename>

19.1.2. Using the PACE Buffer and Repeater Models

To use the PACE buffer and repeater models for high fanout net buffer tree synthesis and repeater
insertion during RTL analysis and/or reduction, use the following steps:

1. Specify input PACE technology file with the following command:

pa_set power_tech_file <filename>

2. Specify the PACE models to use for RTL analysis or reduction, using the following command:
pa_set use_pace_model_category {cap clock cell buffertree repeater}

3. Delete or comment out any existing SetHighFanoutNet commands, such as the following:
#SetHighFanoutNet -fanout 20

4. Delete or comment out any existing SetMaxFanoutNet commands, such as the following:
#SetMaxFanout -type logic -fanout 20 -instance *

The SetMaxFanout command overwrites the PACE buffer and repeater model design
constraints used during buffer tree synthesis.

5. Use the generated PACE technology file with the 'CalculatePower' or 'ReducePower' command
to perform power analysis or power reduction respectively:

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 Introduction

CalculatePower <option> -power_tech_file <pace.tech>

ReducePower <options> -power_tech_file <pace.tech>

19.1.3. Data Visualization and Debugging for PACE Buffer and Repeater
Models
The power analysis, reduction flows, and PACE generation reports are updated to provide buffertree
and repeater model.

19.1.3.1. PACE Report

The report generated by reportPaceInfo command summarizes information about the PACE
technology file and includes two new sections for buffer cell categorization. The two new sections
are as follows:

• Buffer cells
• Physical/Power management cells

Following is a sample snippet of the PACE report with buffer categorization:

Buffer cells:
_______________________________________________________________________
Function: always_on
Cell: BUFAONX1MTL lvt LOW_VT
Cell: BUFAONX2MTH hvt HIGH_VT
Function: buffertree
Cell: BUFX1MTH hvt HIGH_VT
Function: hold
Cell: DELX1MTH hvt HIGH_VT
Function: pad
Cell: INVPADSFX1MTH hvt HIGH_VT
Function: repeater
Cell: INVX2MTH hvt HIGH_VT
Cell: INVX4MTL lvt LOW_VT

Physical/Power management cells

_______________________________________________________________________
Function: antenna
Cell: ANTENNA1MTL lvt LOW_VT
Cell: ANTENNA2MTH hvt HIGH_VT
Function: decap
Cell: DCAP2MTH hvt HIGH_VT
Cell: DCAP4MTL lvt LOW_VT
Function: filler
Cell: FILL1MTH hvt HIGH_VT
Function: power_switch
Cell: HDRBUFX1MTH hvt HIGH_VT
Function: well_tap
Cell: TAPCELL1MTH hvt HIGH_VT

19.1.4. Limitations
The PACE buffer and repeater has following known limitations:

1. Power Management cells are handled through UPF directives.

2. No inference for HOLD buffers. Hold buffers are handled by Timing-Aware feature of PowerArtist.

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Advanced Buffer Modeling in PACE

19.1.5. Appendix I : Auxiliary Commands and Recommendations for PACE

Buffer Categorization
To model the impact of high fanout net buffer tree synthesis, repeater insertion, hold fixing, and
power management techniques or power intent specified with CPF or UPF files, the PACE generation
module can categorize buffers into different categories based on the library attributes, instance name
patterns, cell name patterns provided by the user as input to WriteTechnologyFile command.
Specification of reset, scan-enable buffer-cell patterns is optional, Advance Buffer Modeling can
auto-trace scan-enable paths and reset paths from corresponding sequential pins and identifies buffer
cells or instances.

Category Cell Type/ Instance Type Description

Physical pace_filler_cells (instances) Name patterns list for filler cells/instances
pace_decap_cells (instances) Name patterns list for decap cells/instances
pace_antenna_cells Name patterns list for antenna
(instances) cells/instances
pace_welltap_cells Name patterns list for well tap cells/instances
(instances)

Category Cell Type Description

Power pace_isolation_cells (instances) Name patterns list for power isolation
cells/instances
Management
pace_switch_cells (instances) Name patterns list for power switch
cells/instances
pace_level_shifter_cells (instances) Name patterns list for level shifter cells/instances
pace_enable_level_shifter_cells Name patterns list for level shifter cells/instances
(instances) with enable
pace_always_on_cells (instances) Name patterns list for always-on buffer
cells/instances
Power pace_clock_isolation_cells (instances) Name patterns list for clock isolation
Management cells/instances
(Clock) pace_clock_level_shifter_cells Name patterns list for clock level shifter
(instances) cells/instances
pace_clock_enable_level_shifter_cells Name patterns list for clock enable level shifter
(instances) cells/instances
pace_clock_always_on_cells Name patterns list for clock always-on buffer
(instances) cells/instances
Logical pace_buffertree_cells (instances) Name patterns list for high fanout net buffer
cells/instances
pace_hold_buffer_cells (instances) Name patterns list for hold fixing cells/instances
pace_pad_cells (instances) Name patterns list for pad cells/instances
pace_repeater_cells (instances) Name patterns list for repeater cells/instances
pace_reset_cells (instances) Name patterns list for reset tree buffer
cells/instances

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 Introduction

pace_scan_cells (instances) Name patterns list for scan buffer cells/instances

pace_spare_cells (instances) Name patterns list as spare buffer cells/instances
Logical pace_clock_cells (instances) Name patterns list for clock cells/instances
(Clock)

19.1.5.1. Recommended Settings

19.1.5.1.1. Power Management Category

Cell Type Liberty Attribute Can PA Must Reason

recognize/honor to
Liberty specify?
Attribute?
pace_switch_cells switch_cell_type No Yes PowerGate cells
{coarse_grain/fine_grain} usually contain
buffers embedded,
the tool recognizes
them as buffer,
hence pollutes with
repeaters/buffer-trees.
pace_(clock_) is_level_shifter Yes No* (If Level Shifters cells
level_shifter_cells {true/false} liberty usually contain
has buffers embedded,
level_shifter_type attribute, the tool recognizes
{LH/HL} Otherwise them as buffer,
Yes) hence pollutes with
repeaters/buffer-trees.
pace_(clock_) is_level_shifter Yes No Enable_level_shifer
enable_level_shifter_cells {true/false} cells are typically
not of
level_shifter_type buffer/inverter type.
{LH/HL} Usually they are of
AND/OR type. So
they doesn't pollute
the IBP.
pace_always_on_cells always_on {true/false} No Yes Always-on cells
usually contain
buffer/inverter logic,
the tool recognizes
them as buffer,
Hence pollutes with
repeaters/buffer-trees.
pace_isolation_cells is_isolation_cell Yes No ISOLATION cells are
{true/false} typically not of
buffer/inverter type.
Usually they are of
AND/OR type. So

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Advanced Buffer Modeling in PACE

doesn't pollute the

IBP.
pace_clock_isolation_cells is_clock_isolation_cell Not tested No CLOCK ISOLATION
{true/false} cells are typically
not of
buffer/inverter type.
Usually they are of
AND/OR type. So
doesn't pollute the
IBP.

19.1.5.1.2. Logical Category

Category Cell Type Liberty Can the tool Must Reason

Attribute recognize/honor to
Liberty specify?
Attribute
Logical pace_buffertree_instances
NA NA No Auto identification
pace_repeater_instances
NA NA No Auto identification
pace_reset_instances
NA NA No* Auto identification, based
on RESET pin tracing.
Specifying them helps
accuracy.
pace_scan_instances
NA NA No* Auto identification, based
on SCAN-ENABLE pin
tracing. Specifying them
helps accuracy.
pace_spare_instances
NA NA Yes* Auto identification, but
user can specify for
guiding the tool more
clearly, for better
accuracy.
pace_hold_buffer_instances
NA NA Yes* Not specifying the HOLD
buffer categories pollutes
repeaters/buffer-trees/logic
category buffers. Specify
them based on shortest
paths and/or PnR tool
specific patterns/strings.
Logical(Clock) pace_clock_cells NA NA No* This is to avoid cell
mapping of CTS
buffer cells
(exclusively meant
for CTS) in to data
path buffers.

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 Introduction

19.1.5.1.3. Physical Category

Category Cell Type Liberty Attribute Can the tool Must to Reason
recognize/honor specify?
Liberty
Attribute?
Physical pace_filler_cells is_filler_cell {true/false} No No *Pure
pace_decap_cells is_decap_cell {true/false} No No physical
cells do
pace_welltap_cells is_tap_cell {true/false} No No not
pace_antenna_cells antenna_diode_type No No contain
buffer or
{power/ground/power_and_ground} inverter
logic.
Hence,
they do
not
pollute
the IBP,
Buffer
modelling,
or
synthesis.

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Chapter 20: Design-specific PACE
20.1. Introduction
PACE models have traditionally contained a set of statistics calculated from a gate-level design that are
applied to cell assignment and wire capacitance estimation for similar RTL designs. Statistical cell
distribution provides accurate distribution for VT. However, cell sizes at top level, hierarchical cell
distribution, and instance-to-instance mapping between RTL and gate may differ, leading to a mismatch
between RTL and gate power.

Design-specific PACE is an enhancement that aims to maximize RTL power accuracy for register and
clock power using exact instance-to-instance cell mapping between RTL and gate. This is achieved by
analyzing a gate-level design and creating a model with data for each individual register. Then, the
registers in the corresponding RTL design are matched to the gate-level registers and the corresponding
data is assigned to them. Currently, this data includes the cell type, input slew, and output capacitance.

Chapter Organization
The following topics are covered in this chapter:

• Generating and Reading Models (p. 499)

• Name Mapping Gate-Level and RTL Instances (p. 500)
• Cell Mapping File (p. 501)
• Name Map File (p. 501)
• Debugging Name Mapping Issues (p. 502)

20.2. Generating and Reading Models

• To generate a new model when analyzing a gate-level design, use the following command:
pa_set generate_pace_model_category design

• To use the model for power analysis of the corresponding RTL design, use the following command:
pa_set use_pace_model_category design

You can generate and use other categories ('all', 'cap', 'cell', or 'clock') with 'design', though the
category 'cell', is automatically included when 'design' is specified.

See the PowerArtist Reference Manual for complete details of the above variables.

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Design-specific PACE

20.3. Name Mapping Gate-Level and RTL Instances

• Flip-flop instances in the gate-level and RTL designs are matched using their names. Since instance
names are commonly modified during synthesis, you have the ability to define the rules for name
modification. These take the form of Tcl functions that are applied individually to each gate-level
name and produce one or more RTL names. These functions must be listed in a file that can be
specified using the following command:
pa_set pace_name_transforms_file <filename>

Each function must also be registered using the 'RegisterGateTransform' command in the same file.
Review the following file for examples:
$POWERARTIST_ROOT/lib/tcl/NameTransformer/defaultTransforms.tcl

Note: The file 'defaultTransforms.tcl' is used if you do not specify any other file.
• Multi-bit instance names are automatically split before they are given to the Tcl functions if they look
like the following:
top.a[1:0]
MBIT_top_a_reg_1_MB_top_a_reg_0_

Use 'pace_multibit_prefix' and 'pace_multibit_delimiter' for multi-bit instance names

in the second format to specify strings other than 'MBIT' and 'MB', as shown in this example:
Example: If the RTL and gate registers are named as:
– Gate instance name:
top.MBIT_c_reg_2_AND__AND_c_reg_1_AND__AND_c_reg_0

– RTL name:
top.c[2:0]

Then, the variables to specify the strings are as shown in the example below:
pa_set pace_multibit_delimiter "AND__AND"
pa_set pace_multibit_prefix "MBIT_"

• In case the top-module of RTL and PACE model are different, the gate-level instance matching RTL
top module is specified using the 'pace_top_instance', as shown in the following example:
Example: If the RTL and gate instances are named as:
– Gate top module:
top_wrap

– RTL top module:

top

Then, the gate instance corresponding to the RTL top module 'top_wrap.u_top' is defined as:
pa_set pace_top_instance top_wrap.u_top

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 Name Map File

20.4. Cell Mapping File

You can assign cells to specific RTL register instances with a cell mapping file. The assignments in this
file override any assignments made using PACE models or built-in cell selection.

Format
The cell mapping file is a text file with two columns. In this file, the left column specifies the register
name(s) and the right column specifies the cell type. If multiple register bits are specified, then the
given single-bit cell are assigned to each bit. Specific bits and ranges of bits can be selected, as shown
in the example below:
top.a.R1[7:0] DFF1BIT
top.a.R2[1:0,3:5,7] DFF1BIT

You can combine separate register instances in a single line using Verilog-style concatenation with curly
braces, as shown in the example below:
{top.a.R1, top.a.R2} DFF1BIT

Multi-bit register cells can also be used in the file. The number of RTL register bits specified on lines
with multi-bit cells, though, must exactly match the width of the cell, as shown in the example below:
top.a.R1[1:0] DFF2BIT

Using the Mapping File

Once the cell mapping file is complete, use it for power analysis ('CalculatePower') or power reduction
('ReducePower') via the following variable:
pa_set cell_mapping_file <filename>

Limitation
If a cell is several bits wide, then the number of register bits must match the width of the cell.

20.5. Name Map File

A Tcl interface is available for configuring the design-specific PACE name mapping process (described
in the section Name Mapping Gate-Level and RTL Instances (p. 500)). However, writing and testing the
transformation functions is a tedious process.

So, using map files, such as those used by designers to map the RTL names to the gate-level names to
properly annotate activity data on the gate-level elements, is a more accurate and simple solution.

The mapping file is generated by using the 'SetNameMapFile' command, which specifies the path and
format of a file (that shows exactly which activity waveforms correspond to which gate-level elements).
The file is in 'pt' format, which is PowerArtist's proprietary format that consists of 'remap' commands.

This mapping solution is extended to support design-specific PACE as explained below:

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Design-specific PACE

1. Specify a name map file with 'SetNameMapFile' for power analysis:

SetNameMapFile -map_file <map_file_path> -format pt

The map file specified using the '-map_file <map_file_path>' option should contain
only basic 'remap' commands that specify RTL names (with the '-from' option) and gate-level
names (with the '-to' option), as shown below:
remap -from <rtl-name> -to <gate-level-name>

For gate-level names, specify nets, instances, or pins. For RTL names, specify only nets.
2. The map file is used during RTL power analysis if a design-specific PACE model is applied.
If the given file is valid and conforms to the 'pt' format, then it is the first source of mapping
information used during PACE application. Then, PowerArtist attempts to map any remaining
unmapped RTL instances using Tcl transformation functions, if they are given. If that fails for
any instances, then they are modeled using the generic PACE statistical model.

20.6. Debugging Name Mapping Issues

Use the following methods to debug name mapping issues:

1. Use File Lists Generated during Power Analysis

The following reports/files are generated during power analysis:

Report Name Description

mapped_state_points.rpt Contains a list of mapped flops.
unmapped_state_points.rpt Contains a list of unmapped flops.
rtl_data_for_mapping.rpt Contain RTL and gate flops names used for
mapping.
gate_data_for_mapping.rpt

By analyzing these files you can improve the naming rules in the transforms file to enable mapping
of unmapped flops.
The percentage of RTL registers that were successfully matched to gate-level registers are reported
in the log file as message 'ENG-907' and the percentage of unmatched registers are reported as
'ENG-906'. The higher the number of matched registers, the more accurate the power analysis results
are. Ansys recommends aiming for a match percentage of 90% or higher.
2. Generate Cell Mapping Information from PDB
You can create a cell mapping file using the 'mapRegisters' command. The command maps cells to
RTL registers for a gate-level design.

Limitations
• Data is currently collected and assigned only for flip-flops.
• Non-scan and scan flip-flops cannot be mixed.
• Unmatched flip-flops in the RTL design are not automatically assigned to multi-bit flip-flop cells.

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Chapter 21: Generating an RTL Power Model
21.1. Introduction
The design of the power delivery network (PDN) is critical for the successful and timely implementation
of SOCs. A badly designed PDN adversely affects functionality if timing errors occur due to excessive
voltage drop across supply rails. Longer term power grid failures occur due to electro-migration (EM).
Package selection must be done early on in development but if done badly leads to high voltage drop
due to inductive effects. As the chip moves into the sign-off phase, the designer needs to stress the
PDN with realistic worst-case vectors. However, the impracticality of running gate-level simulation means
that the availability of simulation vectors is almost non-existent.

Many of these problems can be mitigated by gaining early visibility into the expected power and current
profile of the design, and during sign-off being able to select (with confidence) realistic worst-case
stimulus with which to stress the PDN. The RTL Power Model (RPM) is a technology that allows you to
capture realistic worst-case vectors at the RT level of abstraction along with other key parameters that
affect the power grid.

Chapter Organization
The following topics are covered in this chapter:

• Benefits of the RPM Flow (p. 503)

• The RPM Flow (p. 504)
• Using the CreateRPM Command (p. 506)
• Generating a Total Power Plot (p. 506)
• RPM Performance Enhancement (p. 506)
• Fast Power Profiling (p. 507)

21.2. Benefits of the RPM Flow

The RPM-based flow between PowerArtist and RedHawk enables PDN analysis when parts of the chip
are in various stages of development. For example, when you create an RPM with PowerArtist, you can
use it to perform PDN analysis in RedHawk at any of the following stages:

• Early in the design flow when block-level layouts are not available
• Late in the design flow when blocks have been placed and routed
• Various combinations of the above stages, including blocks of third-party IP

Another benefit of this flow is that it becomes possible to create a Chip Package Model (CPM) early on
in the design flow to facilitate early package selection. Using data available during the RTL design stage,
PowerArtist generates an RPM. RedHawk consumes the RPM, even with early layout data, to generate

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Generating an RTL Power Model

a CPM, which is a spice-accurate chip PDN model. The CPM is then used with package models for early
chip-package co-design. The flow is shown in the following figure:

A key technology in RPM is the ability to do fast power based selection of worst-case PDN events from
many thousands of RTL simulation cycles. The current implementation supports two worst-case events:

• Largest peak power event

This event is selected when the average power is also high. When RedHawk analyzes this event, it
can determine the robustness of the power grid. This allows you to determine, for example, whether
there are enough decaps or whether the grid is wide enough.

• Largest di/dt event

This type of event causes chip and package inductance to ring, which causes the supply voltage to
collapse beyond the design tolerances.

The peak power and di/dt events are captured in a 'frame', where a 'frame' is a window of twenty
cycles of the dominant clock centered around the critical event clock cycle. The dominant clock is the
clock that encompasses 90% of the average power in the design and is automatically determined by
the tool.

RPM can be used both for early PDN analysis (when layout data is not available) and simulation
vector-based PDN analysis for the identified peak or di/dt frames (when layout data is available).

21.3. The RPM Flow

The following figure shows how PowerArtist generates an RPM and how the early analysis data is used
by RedHawk:

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 The RPM Flow

When PowerArtist generates an RPM, it performs the following three steps:

1. RTL inferencing

2. Power-critical frame selection

3. RPM generation

The resulting RPM contains the following types of information:

• Activity for selected power critical nets
• Estimated parasitics (R, C)
• Average and per-cycle power numbers

21.3.1. Inputs Required for RPM Generation

The setup to generate an RPM with PowerArtist is similar to the time-based power analysis setup.
The following data is required:

• RTL for the block or chip.

• RTL simulations results in the form of an FSDB file that covers an appropriate operating mode for
the design.
• Liberty libraries ('.lib') for the target process.
• Clock information, which can be in the form of an SDC file (or a PowerArtist clock file).
• Net capacitance information. This could be wire load models in a Liberty file or a PACE model.

21.3.2. Steps for RPM Generation

Use the following process to generate an RPM using PowerArtist:

1. Read the RTL using the 'Elaborate' command. This builds the scenario file that is required by all
subsequent steps.

2. Perform data validation steps to ensure a high probability of success for generating the RPM.

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Generating an RTL Power Model

Perform a single RTL interval time-based power analysis using 'CalculatePower -analysis_type
time_based' to generate quick power analysis results over a small simulation window. Examine
the power analysis results to see if they look reasonable. By performing this step, you can reveal
problems such as:
• missing technology libraries or cells for functions like memories
• poor or missing wireload models
• missing or incorrect clock definitions
• missing power-aware constraints that set parameters like your mixed VT percentages, define
your power domains or define your virtual supplies.

3. Generate the RPM using the 'CreateRPM' command with almost the same options as used for a
time-based power analysis run.

Note: You do not specify the '-reference_clock' option to the 'CreateRPM' command as it
automatically determines the correct analysis clock.

21.4. Using the CreateRPM Command

You use the 'CreateRPM' command to generate an RPM. The command analyzes the design along with
the supplied simulation vectors and generates an RPM containing the two worst-case events described
in the Benefits of the RPM Flow (p. 503) section. When 'CreateRPM' runs, it performs the following critical
steps:

1. Determines the parasitic capacitance associated with the nets in your design as well as counts of
all the cells that are used during the time-based power analysis of your design.

2. Performs a rapid power-based frame selection that identifies the di/dt and peak power frames.

3. Creates the RPM. The RPM is actually a directory with the 'rpm_model_name' you specified. You
can copy this directory anywhere you need to, but you must not alter the contents.

21.5. Generating a Total Power Plot

You can generate a plot of the total power profile for each frame in an RPM using the
'rpminfo'ncommand.

Syntax
rpminfo -r <rpm_filename>

This command generates an xgraph format file of the form 'frame.xg' for each frame in the RPM. You
can then view these files in the PowerArtist Waveform Viewer, xgraph, or gnuplot (version 4 or later).

21.6. RPM Performance Enhancement

The RPM flow is uses the updated fsdb parser, which exhibits better performance and memory usage.
You can apply existing FSDB processing options, such as 'fsdb_performance_factor' and
'fsdb_use_max_memory' to the RPM flow for enhanced performance and efficient memory usage.

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 Fast Power Profiling

21.7. Fast Power Profiling

A command called 'ProfilePower' is added to PowerArtist. 'ProfilePower' is a high performance power
profiling engine, which generates cycle-based peak and average power profile of a given simulation
vector. 'ProfilePower' trades off accuracy for performance and hence does not report absolute
power-per-cycle. Instead, it is architected to generate a power profile that allows reliable identification
of power and thermal critical time windows in long simulation vectors. You can run cycle-accurate
power analysis using the ''CalculatePower command for these critical time-windows to identify peak
and thermal critical cycles. 'ProfilePower' is 1000-3000 times faster than cycle-accurate power analysis
and can handle FSDB files hundreds of gigabytes in size.

The power profile is saved to an '.fsdb' file and can also be saved to a 'text' file for further processing
with custom scripts. A moving average profile is also calculated and saved to the same files. The moving
average is calculated over the most recent N-samples, where 'N' defaults to 10% of the analysis window.

Note: The 'ProfilePower' command can be run on gate-level and RTL designs.

See the PowerArtist Reference Manual for complete details of the 'ProfilePower' command.

21.7.1. Honoring 'reference_clock' during Power Profiling

In the power profiling flow, you can profile nets (critical and non-critical) by using the value specified
in the following variable:
pa_set reference_clock <clock_name>

Honoring the variable 'pa_set reference_clock <clock_name>' during power profiling can
change the power waveforms that are generated by the 'ProfilePower' command.

21.7.2. Profile Plotting per Supply

'ProfilePower' allows you to plot profiles per supply. To enable this enhancement, add the following
variable to your command file:
pa_set profile_plot_supplies true

This creates profile and average plots for each non-zero voltage supply to the fsdb file and the text
file (if the latter is requested). This feature is also used by ANSYS CMA (Chip Model Analyzer) for power
delivery network analysis of the chip, package, and system (CPS).

Note: The text file's header is easier to parse with a script and is of the following form:
# Version 1
# 0 Time 1e-09
# 1 Profile Total
# 2 Average Total
# 3 Profile {vdd_1} 1
# 4 Average {vdd_1} 1
# 5 Profile {vdd_1.1} 1.1
# 6 Average {vdd_1.1} 1.1
100 6.44061e-11 6.44061e-11 0 0 6.44061e-11 6.44061e-11
200 7.1208e-11 7.1208e-11 0 0 7.1208e-11 7.1208e-11
...

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Generating an RTL Power Model

The file has two parts:

1. The header consists of lines that begin with #.

The first line of the header defines the version id so that future changes to the format are handled
more efficiently. The remaining header lines describe the data of the body (on a per column basis).
For example, '# 0 Time 1e-09' indicates that 'column 0' reports time in units '1e-09' and '# 3
Profile {vdd_1} 1' indicates that 'column 3' is the profile of supply name 'vdd_1', which has a
voltage of '1v'.

Note: The tcl hard quote braces protect against supply names containing non-alphanumeric
characters.

2. The body of the file consists of data lines that begin with a non-# character.

21.7.3. ProfilePower Split FSDB Flow

'ProfilePower' allows distributed analysis on multiple processes. To invoke this flow, use the
'ConfigureParallelAnalysis' command to set the number of processes to use and to specify the script
to invoke (if you want distributed analysis to be handled by LSF/UGE).

The following two types of parallel flows are supported:

• If you specify the '-to_fsdb_index' option

'ProfilePower' performs power profiling across 'N' time-split '.fsdb' files. In this flow, the first
activity file is specified using the 'activity_file' option, and the index of the last '.fsdb' file
to process is specified using the '-to_fsdb_index' option. 'ProfilePower' then looks for FSDB
files of the form '<activity_file>_000N.fsdb', invokes an analysis on all of the files of this
type across the number of processes requested, and then combines the resulting profile FSDB's
into a single FSDB.

'ProfilePower' allows indexed FSDB file names to contain multiple dot separators, such as
'foo_001.hw.fsdb'. The index portion of the name must appear at the end of the string before
the first dot.

• If you do not specify the '-to_fsdb_index' option

'ProfilePower' splits the specified 'activity_file' into 'N' windows, where 'N' is the number of
CPU's requested, invokes an analysis on each window, and then combines the resulting profiles
into a single profile.

Notes:

• The script you specify for LSF/UGE operation is slightly different from the parallel time-based
flow. An example script for UGE is shown below:
#!/bin/sh
qsub -V -b y -cwd -j y -q sjo_all_hosts -sync y -S /bin/sh "$@"
exit $?

Note: The script should not return the UGE exit code directly but via the 'exit' command.
• Under some circumstances, the profile that is stitched together from the multiple analyses
might not be the same as a profile generated over the full simulation window, that is you

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 Fast Power Profiling

might see some glitches at the boundaries. This happens when clock cycles overlap the
sub-window boundaries. When this happens 'ProfilePower' does not know what toggle activity
is happening in the part of the clock cycle before the start time of the requested window so
cannot fully account for the power contribution in that cycle. Thus, the power for that cycle
is low. 'ProfilePower' issues a warning when it detects this situation.

21.7.4. ProfilePower Calibration Flow

In this flow, average power analysis is used to scale the profile generated by the 'ProfilePower'
command so that it better approximates a time-based profile. This allows the y-axis to be annotated
with units of power. In the past, a profile’s y-axis was unit-less to emphasize that while the profile
represents the real power profile, the values are not power.

This flow is called the calibration flow and is enabled by using the following variable:
pa_set profile_calibration_file <filename>

If the file specified with the variable does not exist, 'ProfilePower' writes calibration data to it and
calibrates the profile. If the file exists, it is used to calibrate the profile. If per supply profiles are
requested current profiles are also generated.

21.7.5. ProfilePower MonitorInstances Flow

'ProfilePower' allows profiling a hierarchical instance in a design without the need to re-elaborate
the design at that level. This flow uses the 'MonitorInstances' command to specify the hierarchical
instance of interest. You can enable this flow by using one of the following methods:
MonitorInstances -name <instance_path>

or
DefineGroup <group_name> <instance_path>
MonitorInstances -group <group_name>

Notes:

• If the instance you specify is small in size, the resulting profile is likely to be wrong.
'ProfilePower' issues a warning if it detects this situation.
• 'ProfilePower' attempts to use the clock you specify with 'reference_clock' but if that
clock does not connect to the monitored instance, it tries to select one that does.

21.7.6. Hierarchical Power Profiling

The power profiling flow enables power profiling of top module and multiple hierarchical instances
in the same run.

Inputs
1. Use the 'MonitorInstances' command to enable support for hierarchical power:

• Specify the instances you want to process, as shown below:

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Generating an RTL Power Model

MonitorInstances -name <inst1_name>

MonitorInstances -name <inst2_name>
MonitorInstances -name <inst3_name inst4_name>

For hierarchical power profiling to generate meaningful results, hierarchical instances with
small number of leaf-level instances are ignored. Use the following variable to change the
leaf-level instance count '%' threshold value:
% pa_set profile_leaf_instance_threshold <integer>

The default value of this variable is '5' and it represents the percentage of leaf-level instances
(of the total leaf-level instances in the design). If none of the hierarchies specified with the
'MonitorInstances' command meet the threshold value criteria, power profiling is performed
on the top module only.

• Or, create and specify a group of instances, as shown below:

DefineGroup <group1> <inst1_name>
DefineGroup <group2> <inst2_name>
MonitorInstances -group <group1, group2>

• Or, specify instances using the 'MonitorInstances -levels' option as shown below:
MonitorInstance -name <inst_name> -levels <integer>

All the instances below the specified hierarchy-level are processed.

Note: The option '-levels all' is not supported and the warnings 'TBE-240' or 'TBE-241' are
issued.

2. Use the 'ProfilePower' command.

ProfilePower <options>

Outputs
The following files are generated after successful power profiling:

• FSDB File

An FSDB file containing the waveforms for all hierarchical instances is generated. By default,
the file is saved as 'profile.fsdb'. Use the following variable to specify the name of the
file:
% pa_set profile_fsdb_file <filename>

You can view the waveform by loading 'profile.fsdb' in the 'Signal Viewer'. A sample
waveform is shown below:

Note: The instance name is prepended to the signal names in this waveform.

• Text File

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A text file containing the data for all hierarchical instances is generated when the following
variable is specified:
% pa_set profile_text_file <filename>

The data for each hierarchy is separated into sections where each section has the following
start and end markers:
$start <hierarchical_instance_name>
<profile data>
$end <hierarchical_instance_name>

A sample text file is shown below:

$start top
# Version 1
# 0 Time 1e-11
# 1 Profile Total
# 2 Average Total
379 0.0790024 0.0790024
1895 0.0790024 0.0790024
3411 0.0790024 0.0790024
<snip>
$end top
$start top.core1
# Version 1
# 0 Time 1e-11
# 1 Profile Total
# 2 Average Total
379 0.0790012 0.0790012
<snip>

• Additional Warnings

Warnings 'TBE-240' and 'TBE-241' are issued when an unsupported option is used. And warning
'FFR-126' is issued if PowerArtist detects one or more empty (with only constant and connect
nets) hierarchies.

Examples
• Example 1: In this example, a profile is generated for all instances that are '2' levels below
'top.core1':
MonitorInstance -name top.core1 -level 2

• Example 2: In this example, a profile and a text file are generated for instances 'top' and
'top.core':
MonitorInstances -name {top top.core1}
pa_set profile_fsdb_file test.fsdb
pa_set profile_text_file profile.txt

The following profile and text file are generated:

test.fsdb
profile.txt

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Generating an RTL Power Model

Limitations
• The memory usage may increase as the number of levels of hierarchies and number of instances
to process, increases.
• The waveforms generated for power profiles of hierarchical blocks with less than 10K nets may not
match the waveforms generated for the same peak points by time-based power analysis. Warning
'TBE-208' is reported for such blocks.

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Chapter 22: Analyzing Static Power Efficiency
22.1. Introduction
PowerArtist static power efficiency checks enable design analysis early in the RTL development cycle
before simulation vectors or technology specific Liberty models are available. These checks identify
power-inefficiencies in the RTL spanning sequential elements, datapath logic, and memories that can
potentially lead to wasted power in the design. Glitch power consumption is a growing concern in
smaller geometries and the static checks include identification of RTL code that is potentially glitch-prone
for early visibility and action. Static power efficiency metrics serve as an effective check to qualify RTL
check-ins as a part of a regression flow. A regression-based check of RTL check-ins ensures any hidden
power bugs are caught and addressed early in the design development flow.

Chapter Organization
The following topics are covered in this chapter:

• Types of Checks (p. 513)

• Use Model (p. 514)
• Data Requirements (p. 514)
• Syntax (p. 515)
• Reports (p. 515)
• Useful PDB Properties for Static Design Efficiency Analysis (p. 516)
• Support for 'regfiles' and Memory-related Checks (p. 518)
• Accessing Memory Output Pins (p. 519)

22.2. Types of Checks

The following three types of checks are available:

• Register Clock Gating Checks

– Detect registers with self-gating (XOR based gating)
– Detect registers with large enable depth
– Identify which register bits are: enabled, gated, both, none
– Identify redundant or inefficient clock gating:
Ungated registers
Constant clock enables
Floating clock enables
• Memory Analysis Checks
Analyze memory clock gating efficiency:

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Analyzing Static Power Efficiency

– Ungated memories
– Memories driving observability elements (Memory ODC conditions)
• Glitch Analysis Checks
– Analyze timing impact of clock gating:
Too many XOR based clock enables
Clock enables with large depth cone
– Identify glitch prone elements such as unregistered ALUs (adders & multipliers) with
unbalanced input logic paths

22.3. Use Model

Due to the structural nature of the analysis, this flow does not require any activity input, simulation, or
vectors. You can enable the flow by using the 'AnalyzeStaticEfficiency' command. The command is
run after design elaboration and saves the properties required for static design efficiency analysis in
the power database. Power analysis related steps such as simulation annotation, slew propagation,
activity propagation, and power calculation are not performed. Technology and file formats such as
PACE and UPF are also not required in this flow, hence they are not supported. You can use this flow
for early, vector-independent design efficiency checks to optimize design power consumption.

The figure below shows the inputs and commands to enable the flow:

22.4. Data Requirements

PowerArtist requires the following inputs to enable static power efficiency checks:

• RTL design files

• Liberty files (needed if RTL instantiates specific .lib cells)
• SDC file for clock definitions or equivalent PowerArtist 'SetClockNet' commands
• Minimum bit width ('-min_bit_width') to be used for clock gating, as consistent with synthesis
clock gating methodology
• The 'DefineMemory' command to identify memory ports during Memory ODC analysis

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 Reports

22.5. Syntax
The syntax to enable static power efficiency checks is given below:
AnalyzeStaticEfficiency
-power_db_name <filename>
-log <filename>
-static_efficiency_write_power_db <true | false>

Options
-power_db_name <filename>

User-specified power database (.pdb) file name that contains the static clock gating data.

-log <filename>

User-specified log file name. The default filename is 'AnalyzeStaticCG.log'.

-static_efficiency_write_power_db <true | false>

This is true by default and writes out the power database (pdb) after static analysis. PowerArtist
generates the OpenAccess database representation of all the static analysis results. The results can
be accessed using APSH container properties.

Refer to the PowerArtist Reference Manual for details of all the options supported by the command.

22.6. Reports
The command does not generate a formal text report. However, you can generate the following types
of reports:

• Custom Reports (p. 515)

• Logic Optimization Report (p. 516)
• Clock Gating Decision Report (p. 516)

22.6.1. Custom Reports

You can generate a custom report from power database using Tcl-based PDB properties. For example,
you can use the following commands to obtain information about clock gating on registers and
memories:
get_property -class cell <register> clock_gated
get_property -class pin <memory clock pin> is_clock_gated

You can define metrics such as '% gated_flops', '% always_on_gaters' (tied-1 clock enables),
or '% always_off_gaters' (tied-0 clock enables), '% glitchy_alu' to measure static design
efficiency by using PDB properties. Refer Useful PDB Properties for Static Design Efficiency
Analysis (p. 516) for details of the properties added to enable this.

Disclaimer: The clock gating results generated after 'CalculatePower' as compared with those
generated after 'AnalyzeStaticEfficiency' may not match under the following conditions:

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Analyzing Static Power Efficiency

• If '-mux_select_activity_based_clock_tracing true' is specified in your

'CalculatePower' tcl script.
• If '-frequency_independent_clock_tracing true' is not specified in your
'CalculatePower' tcl script.

22.6.2. Logic Optimization Report

You can generate the logic optimization report in the static power efficiency flow. To generate the
report, use the following variable:
pa_set logic_optimization_report <filename>

PowerArtist performs combinational logic optimization during 'Elaborate' and sequential logic
optimization during 'Elaborate' and 'AnalyzeStaticEfficiency'. The difference is that optimization
during 'Elaborate' is intra-module whereas optimization during 'AnalyzeStaticEfficiency' is
inter-module.

To generate a report of the optimizations performed by PowerArtist, set the following variables:

• Before 'Elaborate':
pa_set elaborate_report_options {optimization module detailed_module}
pa_set elaborate_report_file <elaborate_report>.txt

• Before 'AnalyzeStaticEfficiency':
pa_set logic_optimization_report <report_name>

22.6.3. Clock Gating Decision Report

You can generate the clock gating decision report in the static power efficiency flow. To generate
the report, use the following variable:
pa_set clock_gating_decision_report <filename>

22.7. Useful PDB Properties for Static Design Efficiency Analysis

You can query design clock gating and other design efficiency information from the PDB generated by
the 'AnalyzeStaticEfficiency' and 'CalculatePower' commands. The following table summarizes the
available properties:

Property Name Class Object Application

is_enabled Pin Inferred register output pins Register clock
cg_enable_depth Instance Inferred gaters (feedback gating efficiency
mux21) analysis

is_self_gated Pin Output pin of register

is_clock_gated Pin input clock-pin of memory
and output pin of register

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 Useful PDB Properties for Static Design Efficiency Analysis

clock_enable_expr Instance Inferred register Memory clock

gating analysis for
observability
alu_logic_depth Pin Input pins of unregistered Glitch analysis
ALU
unregistered_alu Instance Input pin of register

22.7.1. Register Clock Gating Efficiency Analysis

The following properties can be used to analyze the clock gating efficiency of the design:

• The 'is_enabled' property detects registers with a recirculating multiplexer. A register with
a recirculating multiplexer is clock gated by PowerArtist and synthesis if it meets the minimum
bit width criteria by itself or after combining with other registers.

Example:
set pin {core1/j1/#r0/dout[0]}
get_property -class pin $pin is_enabled

• The 'cg_enable_depth' property detects the clock enable depth of inferred gaters (this
property does not apply to instantiated clock gates).

Example:
set inferred_gater {core1/j1/#m0}
get_property -class cell $inferred_gater cg_enable_depth

You can also access the property through the column 'enable_depth' in the report generated
by the 'report_cg_efficiency' command.

Example:
report_cg_efficiency -cols {cg_inst enable_depth}

• The 'is_self_gated' property identifies if the register is clock gated using xor-based clock
gating where the input and output bits of a register are xor'd (may be followed by an or gate)
to detect any change in data, and the output of the xor is used as a clock enable.

Example:
set pin {core1/j1/#r0/dout[0]}
get_property -class pin $pin is_self_gated

• The 'is_clock_gated' property identifies if the specified register bit of an inferred register
instance is clock gated. This is different from the 'clock_gated' property, which returns clock
gating type for register instances.

Example:
set pin {core1/j1/#r0/dout[0]}
get_property -class pin $pin is_clock_gated

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Analyzing Static Power Efficiency

• The '-type' option of the 'get_cg_enables' command accepts these values - 'inferred',
'instantiated', and 'inferred_ecg'. When specified, 'inferred_ecg', returns clock-gate enables used
in enhanced clock gating.

22.7.2. Memory Clock Gating Analysis

The clock gating efficiency of memories can be improved by identifying ungated memory clocks and
detecting memories driving observability logic, which can be used to gate the memory.

The 'is_clock_gated' property described in the Register Clock Gating Efficiency Analysis (p. 517)
section can also be used to detect if memory clocks are gated. ODC-based power reduction
opportunities for memories can be accessed through the 'get_reductions' command. The clock enable
condition can be queried using the 'clock_enable_expr' property of the ODC reduction object
as shown in the example below:
foreach_in_container red [get_reductions -filter {reduction_type == ODC} {*}] {
set inst_name [get_property $red reduction_instance_name]
set cg_expr [get_property $red clock_enable_expr]
puts "Instance Name = $inst_name; ODC expr = $cg_expr"
}

The memory clock port and the net that the enable expression gates can be queried by the
'memory_clock_port' and 'memory_clock_net' attributes.

22.7.3. Glitch Analysis

Adders and multipliers with unbalanced and unregistered logic at input pins are more prone to
glitching. The following two properties identify such glitch-prone unregistered ALUs:

• The 'unregistered_alu' property returns '1' or '0' depending upon whether an ALU is
unregistered or not. An ALU is considered unregistered if one or more of its inputs are not
driven directly by a register.

• The 'alu_logic_depth' property returns the number of levels of logic between an upstream
register and the input pin of an ALU. The property is available only on the input pins of
unregistered ALU instances.

The following example shows how to use these properties:

set alu_list [get_instances -hier -filter \
{func_type == “full_adder” || func_type == “mult” && unregistered_alu == true} *]
set unregistered_pins [get_pins $alu_list -filter {direction == “in” }]
foreach_in_container pin $unregistered_pins {
set logic_depth [get_property $pin alu_logic_depth]
puts $logic_depth
}

22.8. Support for 'regfiles' and Memory-related Checks

To perform memory related checks and support register files in the static power efficiency flow, use
the following variable:
pa_set categorize_regfile_as_memory <true | false>

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 Accessing Memory Output Pins

22.9. Accessing Memory Output Pins

The power database generated by the 'AnalyzeStaticEfficiency' command, contains Observability Don’t
Care (ODC) conditions for memories, which can be accessed using the 'get_reductions' command.
Memories with multiple output ports have multiple reduction objects with different clock pins, nets,
and output ports. Reduction data with output pins and clock pins of memories is available. This helps
designers use the enable expression to insert a clock gate or strengthen the enable condition for the
memory instance. You can access the pins by using the 'get_pins' command as shown in the example
below:
foreach_in_container red [get_reductions -filter {reduction_type == ODC} {*}] {
puts “Enable expression: [get_property $red clock_enable_expr]”
foreach_in_container pin [get_pins $red -filter {direction == output}] {
puts “Output pin: [get_property $pin full_name]”
}
foreach_in_container pin [get_pins $red -filter {direction == input}] {
puts “Input pin: [get_property $pin full_name]”
}
}

If the above script is run on a design with the following memory instance:

Then, the output is:

Enable expression: top.selA
Clock pin: memBlk/mem/CLKA
Output pin: memBlk/mem/QA[31]
Output pin: memBlk/mem/QA[30]
Output pin: memBlk/mem/QA[29]
…

Enable expression: top.selB

Clock pin: memBlk/mem/CLKB
Output pin: memBlk/mem/QB[31]
Output pin: memBlk/mem/QB[30]
Output pin: memBlk/mem/QB[29]
…

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Chapter 23: Weighted Toggle Coverage (WTC)
23.1. Introduction
The power grid must be able to supply enough current for peak power scenarios. The quality of simulation
vectors for power and IR drop analysis is critical for power integrity sign-off. Vectors must trigger
worst-case but realistic scenarios for a robust and optimal power grid. Since power grid analysis is
compute-intensive, design companies use varied methodologies to assess multiple vector sets and then
choose a small subset of cycles.

The weighted toggle coverage metrics are used to analyze simulation vector coverage and quality.
These metrics are expected to aid the vector selection process. Using these metrics, vectors with low
toggle coverage on hierarchies and leaf instances can be identified and passed on to verification teams
who can then improve the input vectors.

Chapter Organization
The following topics are covered in this chapter:

• Usage Flow (p. 521)

• Use Model (p. 522)
• Outputs (p. 524)
• Multiple Time Slices (p. 529)
• Ignore Initial Transitions from 'X' / 'Z' States (p. 530)

23.2. Usage Flow

The following three types of toggle coverage flows are available:

• Max toggle coverage

Determines if an instance has been exercised in the vector and has toggled at least once
throughout the simulation duration. Use max toggle coverage to analyze large number of vectors
and identify instances with high or low coverage for a given vector.
• Dynamic toggle coverage
Computes instance coverage over time and generates waveforms that depict regions with high
and low toggle coverage for a given vector. Use the dynamic toggle coverage waveform to
identify peak power and di/dt cycles for IR drop analysis.
• Average toggle coverage
Determines the average toggle coverage of an instance. This is the average of dynamic toggle
coverage for an instance. Use average toggle coverage to calculate the average coverage
throughout the simulation duration.

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Weighted Toggle Coverage (WTC)

Each flow has two metrics to score the vector quality:

• %Instance toggle coverage (ITC)

Toggle coverage of the instance relative to max coverage of the instance.

• %Global toggle coverage (GTC)

Toggle coverage of the instance relative to max coverage of the top module.

Additionally, weighted toggle coverage draws attention to higher power consuming instances by
assigning a power weight to each instance. Power weight of an instance is the highest contribution an
instance can have to total design power.

23.3. Use Model

The weighted toggle coverage metrics are computed using the 'CalculateToggleCoverage' command.
The figure below shows the inputs and command flow to run 'CalculateToggleCoverage':

The 'CalculateToggleCoverage' command can be run right after the design is elaborated and clocks
processed. Either an SDC file or SetClockNet commands with '-frequency' option is required for
clock domain tracing. During clock tracing, all design instances are associated with the traced clock
domain. The clock domain frequency along with cell energy is used to calculate the cell weight for
weighted toggle coverage calculation. The weighted toggle coverage flow infers clock gating to analyze
the impact of clock gating on design activity, but it does not infer clock buffer trees.

The recommended usage for the 'ReadSDC' command flow is shown below:

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 Use Model

ReadSDC -sdc_files {}
-power_db_name <>
-sdc_clocks_mode ideal
-sdc_clocks_gated true
-sdc_clocks_ecg true
-sdc_trace_domain true
-sdc_out_file <>

The recommended usage for the 'SetClockNet' command flow is shown below:
SetClockNet -name <>
-mode <ideal | infer>
-frequency <>
-gate_clock true
-enhanced_cg true
-trace_domain true

To calculate Dynamic and Average toggle coverage, specify the time interval length at which the FSDB
data must be sampled. This is specified by using the following variable:
pa_set interval_size <>

Notes:

• The options '-reference_clock' and '-num_clock_cycles' that are supported in time-based

power analysis (CalculatePower -analysis_type time_based) are not supported in the
weighted toggle coverage flow.
• Instances that are not associated with any clock domain are not considered for coverage analysis.
• The 'MonitorInstances' command is used to specify the instances for toggle coverage calculation
and report generation.
Example:
MonitorInstances -name { top.m1 top.m4 } -levels 2

If the 'MonitorInstances' command is not specified, a waveform is generated only for the 'top'
module/instance.

Refer to the PowerArtist Reference Manual for complete syntax of the 'CalculateToggleCoverage' and
'MonitorInstances' commands.

Since the weighted toggle coverage flow supports computing the coverage numbers on a per-interval
basis, the following options related to time-based power analysis (CalculatePower -analysis_type
time_based) are also supported with the 'CalculateToggleCoverage' command:
-activity_file <filename>
-default_output_load <float>
-default_transition_time <string>
-frequency_independent_clock_tracing <true | false>
-gate_level_netlist <true | false>
-ignore_toggles_through_x <true | false>
-ignore_toggles_through_z <true | false>
-library_database_dirs <dir list>
-pace_driver_based_cap_model <true | false>
-pace_top_instance <string>
-power_tech_file <filename>
-scenario_file <filename>
-spef_file <filename>
-top_instance <string>
-use_pace_model_category <all | cap | clock | cell | design | cts>

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Weighted Toggle Coverage (WTC)

The following options that are not related to power/coverage analysis are not supported:
-cell_selection_report <filename>
-clock_gating_decision_report <filename>
-detailed_vertical_report <true | false>
-distribute_toggles_on_paths <true | false>
-enable_power_normalization <true | false>
-enable_power_per_supply_annotation <true | false>
-enhanced_glitch_analysis <true | false>
-vertical_report_instances <string list>

23.4. Outputs
The command generates text reports and dynamic coverage waveforms and these are explained in the
next sections.

23.4.1. Reports
The following reports are generated:

• Max and Average Toggle Coverage Report

This report is generated when the '-coverage_report_file <filename>' option is

specified. It reports the maximum and average weighted toggle coverage values of all
hierarchical and leaf- level instances, including inferred and instantiated instances. Use the
'-coverage_exclude_instances' option to exclude specific instances from coverage
analysis and report generation.

This report contains a 'Summary' and a 'Detailed' section:

– The 'Summary' section reports the cell weight and ITC/GTC per-category such as register,
latch, or clock. By default, the summary information is reported only for the top
module/instance.
– The 'Detailed' section reports the maximum and average weighted toggle coverage
values of all hierarchical and leaf-level instances, including inferred and instantiated
instances.

A sample report is shown below:

The following customization options are available for this report:

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 Outputs

– Cell Type Report

Use the following variable to limit the 'type' of instances to include in the 'Detailed'
section of the report:
pa_set coverage_report_detailed_cell_type <hier | leaf | seq | all>

Example:
pa_set coverage_report_detailed_cell_type seq
pa_set coverage_report_file test.rpt

A sample report ('test.rpt') is shown below:

– Instance-specific Summary Report

Use the following variable to include only the 'Summary' sections of the hierarchical
instances in the report. You need to provide a list of space-separated hierarchical
instances as input to the variable:
pa_set coverage_report_summary_instances {hierarchical_instance_names}

Example:
pa_set coverage_report_summary_instances {top.m1}
pa_set coverage_report_file test.rpt

A sample report ('test.rpt') is shown below:

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Weighted Toggle Coverage (WTC)

The last row is the instance name for which the 'Summary' section is printed. The values
in this row match the values reported for the instance in the 'Detailed' section.

– Instance-specific Detailed Report

Use the following variable to limit the 'Detailed' section of the report to specific instances
of interest. You need to specify a list of space-separated hierarchical or leaf-level
instances to include in the report:
pa_set coverage_report_detailed_instances {hierarchical_and/or_leaf-level_instances}

The ITC/GTC numbers are reported only for the specified hierarchical instances. By
default, 'all' the instances are reported.

Example:
pa_set coverage_report_detailed_instances {top.m1 top.m3.myInst top.#c1 top.m2}

A sample report is shown below:

– Summary Report

Use the following variable to skip printing the 'Detailed' section of the report:
pa_set coverage_report_skip_detail <true | false>

The default value of this variable is 'false'. This means that you need to set the variable
to 'true' to skip the 'detailed' section of the report.

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 Outputs

Note: To revert to the default report format within the same shell, you need to reset
the values of the above variables. Use the following variable to reset the variable values:
pa_reset <variable_name>

• Dynamic Report

This report is generated when the '-coverage_dynamic_report_file <filename>'

option is specified. It reports dynamic ITC and GTC values.

The output of this report depends on the 'MonitorInstances' command:

– If the 'MonitorInstances' command is not specified, this report contains information
only for the 'top' module/instance.
– If the 'MonitorInstances' command is specified, this report contains information for
the instances specified in the 'MonitorInstances' command.

A sample report is shown below:

This report can also be generated in .csv format, if 'csv' or 'both' is specified with the
'-coverage_report_format' option.

• Weight Report

This report is generated when the '-coverage_weight_report_file <filename>'

option is specified. It reports the cell weights for design instances in the format -
'<cell_weight> <Instance name>'.

A sample report is shown below:

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Weighted Toggle Coverage (WTC)

23.4.2. FSDB Waveforms

The FSDB file containing toggle coverage waveforms is generated when the
'-coverage_fsdb_output_file <filename>' option is specified. Two waveforms are generated
for every instance - one for dynamic ITC and other for dynamic GTC values. By default, waveforms
for all hierarchical instances are generated. Use the 'MonitorInstances -name <> -levels <>'
command to control the instances for which waveforms need to be generated.

A sample waveform is shown below:

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 Multiple Time Slices

23.5. Multiple Time Slices

In this flow, the 'CalculateToggleCoverage' command computes toggle coverage for multiple simulation
windows from a single long simulation vector file and generates a report for each simulation window
or time-slice. To enable this support, specify the following variable:
pa_set analysis_windows <string list>

Report Naming
The reports generated for each simulation window or time-slice specified by 'pa_set
analysis_windows <string_list>' follow these naming rules:

• User-specified Names
You can specify a suffix for the report names. For example, when the following commands are
specified, two reports are generated - one for each time-slice:
pa_set analysis_windows {4us:6us:file1 7us:9us:file2}
pa_set coverage_report_file_name coverage.rpt

The names of the two reports generated are:

– For time slice '4us:6us', the report is saved as 'coverage_file1.rpt'.
– For time slice '7us:9us', the report is saved as 'coverage_file2.rpt'
• Default Names

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Weighted Toggle Coverage (WTC)

By default, '_slice<window_number>' is appended to the report name. For example, when

the following commands are specified, two reports are generated - one for each time-slice:
pa_set analysis_windows {4us:6us 7us:9us}
pa_set coverage_report_file_name coverage.rpt

The names of the two reports generated are:

– For time slice '4us:6us', the report is saved as 'coverage_slice1.rpt'.
– For time slice '7us:9us', the report is saved as 'coverage_slice2.rpt'.

Notes:

• If you do not provide a suffix for even a single simulation window, the other suffixes are ignored
and the default suffix '_slice<window_number>' is appended to all report names.
• The multiple time slices flow is limited to FSDB simulation file format only.

Single FSDB File for Dynamic WTC

A single FSDB file is generated for multiple simulation windows. This support is added to the dynamic
weighted toggle coverage flow and the results are consistent with the time-based power analysis flow.
Consider the following example:

Note: In the waveform, a 'zero' is shown for any duration that is not a part of any window, as is the
case for the duration between '8300000' ps and '8400000' ps.

23.6. Ignore Initial Transitions from 'X' / 'Z' States

In this flow, the 'CalculateToggleCoverage' command ignores the initial transitions from 'X'/'Z' states.
To enable this support, specify the following variables:

• To ignore X -> 0/1, specify:

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 Ignore Initial Transitions from 'X' / 'Z' States

pa_set ignore_initial_toggle_x true

• To ignore Z -> 0/1, specify:

pa_set ignore_initial_toggle_z true

The default value of both these variables is 'false'.

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Chapter 24: The Streaming (PAVES) Flow
24.1. Introduction
This chapter describes the Siemens Veloce-Ansys PowerArtist Streaming flow, which enables power
analysis for live applications and results in a significant reduction in runtime.

The Veloce-PowerArtist streaming flow provides tighter integration between Siemens Veloce and Ansys
PowerArtist and enables power profiling for live applications from emulation runs and comprehensive
power analysis at RTL and gate-level, and provides high-performance interface by eliminating file-based
inefficiency and saves disk footprint of the tools.

Limitations in the Current Power Analysis Flow

The data acquired from a simulation testbench is consumed by PowerArtist for performing power
analysis. SAIF, VCD, and FSDB file formats are generally used to exchange switching data between
simulators/emulators and power tools but there are limitations of handling large simulation data in
these formats. Some of these limitations are explained below:

• SAIF may compromise accuracy especially for design with a large number of memories. Forward SAIF
provides a slightly improved accuracy in such cases.

• For most accurate results, full waveform activity provided by formats such as FSDB/VCD is required.
Full waveform also allows power tools to guide users to implement power. Unfortunately due to the
structure of FSDB/VCD, these formats are not an effective solution for emulation, which generally
produce a massive amount of data. VCD in particular, has a very large disk footprint, such that for
any significant size SoC design and for long trace depths, it becomes a non-viable option.

For FSDB, part of this performance slow down is due to the way it organizes the data (optimized for
signal access) and the way power tools analyze the data (time-based access).

So for optimum power analysis performance, an interface is needed that inherently handles data in a
time-based manner.

Chapter Organization
The following topics are covered in this chapter:

• Veloce-PowerArtist Streaming Flow (p. 534)

• Parallel Analysis in Activity Streaming Flow (p. 535)
• Environment and Flow Setup (p. 536)
• Veloce-PowerArtist Flow Known Limitations/Issues (p. 538)

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The Streaming (PAVES) Flow

24.2. Veloce-PowerArtist Streaming Flow

An emulator-based power analysis flow enables designers to run real-world test benches, execute long
verification cycles, and collect design activity over long operational cycles compared with regular
simulation. The key benefits of this flow are as follows:

• Early RTL power visibility for real-time live applications (such as 1080p video-frames, OS and firmware
boot-up, and GPS applications) by enabling RTL power flow for large vectors.
• High capacity to handle long durations and improved overall performance and efficiency with increased
coverage across test benches and scenarios.

Ansys and Siemens have collaborated to develope a tightly integrated solution using a data streaming
concept between Siemens' emulator Veloce and Ansys' PowerArtist that avoids the conversion of
switching data to and from the FSDB/VCD format. The PowerArtist VEctor Streaming (PAVES) interface
is the first integration of Siemens' Veloce Dynamic Read Waveform API into a power analysis tool and
the result is a significant reduction in runtime.

Figure 24.1: Veloce-PowerArtist Streaming Interface

24.2.1. Streaming Modes

This flow supports the following two modes that replace file-based activity transfer:

• Disk Mode

For situations where the Veloce emulator trace uploads are complete. In this mode, data is streamed
directly from the disk-based Veloce data set into PowerArtist without converting it to FSDB.

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 Parallel Analysis in Activity Streaming Flow

• Live Mode

In this mode, Veloce emulator trace uploads overlap with the Veloce wave generation and
PowerArtist GAF generation, which provides additional performance gain.

Figure 24.2: High Performance Veloce-PowerArtist Flow

ProfilePower support is available for the native activity format of the Siemens Veloce emulator.
ProfilePower support in the PAVES flow can be enabled in veloce_disk streaming mode and single
process only. ProfilePower PAVES Flow is available with Veloce 21.0.2 or higher.

Note: Parallel streaming for both the modes is enabled for average power analysis (CalculatePower
-analysis_type average) and vector analysis (GenerateActivityWaveforms).

The next section Parallel Analysis in Activity Streaming Flow (p. 535) explains this in detail.

24.2.2. Benefits
Current early access partners and customers have seen up to 10X runtime performance improvement
with the dynamic API flow in comparison to the file-based flow without compromising accuracy.

24.3. Parallel Analysis in Activity Streaming Flow

The activity streaming flow is currently supported for the following PowerArtist commands:

• GenerateGAF
• GenerateActivityWaveforms
• CalculatePower -analysis_type <average | time_based>

While this support provides improved runtime and memory performance vis-a-vis the conventional
FSDB/VCD format-based approaches, it has scope for further runtime improvement. Enhancing
PowerArtist's activity processing step (the GenerateGAF command) to generate multiple GAFs in parallel,
is a step in this direction. Multiple parallel processes can analyze activity from different time windows
in an FSDB file providing linear speed-up in the runtime for activity processing.

In this solution, PowerArtist launches multiple processes in parallel for the specified Veloce dataset
activity file, as shown by the following figure:

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The Streaming (PAVES) Flow

Figure 24.3: Veloce Power App + PowerArtist PAVES Flow

To enable this flow, use 'ConfigureParallelAnalysis -processes <>' and specify the number of
parallel processes to run, which is limited only by the number of parallel processes that your environment
can support.

24.4. Environment and Flow Setup

The environment setup is explained in the next sections.

24.4.1. Veloce Setup

Follow the Siemens/Veloce guidelines for setting up an emulation environment and ensure that you
add the path to the Veloce streaming shared library (libVelWave.so) to 'LD_LIBRARY_PATH'.

24.4.2. The PowerArtist-Veloce Setup

1. Specify the number of time slices into which simulation is divided using one of these options:
#For RTL designs
pa_set num_clock_cycles <integer>

#For gate-level designs

pa_set interval_size <float | time> <ps | ns>

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 Environment and Flow Setup

Note: You need to use these options only in the PAVES time-based flow.

2. Specify activity file

Use this variable to specify the veloce wave (.stw dir) instead of the FSDB/VCD file:
pa_set activity_file <veloce_dataset_path>

Note: Ansys recommends regenerating the '.STW' files to prevent errors due to backward
compatibility. Use 'Veloce_v21.0.2' or higher to regenerate the '.STW' files.

3. Specify the streaming mode:

pa_set activity_streaming_mode <veloce_live | veloce_disk>

Use this variable to set the timeout value (in minutes) for which PowerArtist should wait for activity
streaming data to be available from the Veloce side:
pa_set activity_streaming_timeout <>

The default timeout value is 60 minutes.

4. Verify that the Veloce dataset is successfully detected by PowerArtist

Depending on the mode, look for the following note in the gaf logfile:
Note VCD-258: Veloce 'veloce_disk' flow is used for dataset processing
or
Note VCD-258: Veloce 'veloce_live' flow is used for dataset processing

5. Specify the hierarchy separator

In the PowerArtist environment, the 'top_instance' name is passed with a dot ('.') separated
path for pure Verilog designs and slash ('/') separated path for mixed VHDL/Verilog designs.
PowerArtist identifies the design to be mixed if there are VHDL files present in the elaboration
input file list and converts the hierarchy separator in the 'top_instance' name from '.' to '/'
before invoking Veloce.

In the Veloce environment, if VHDL is not actually instantiated, it treats the design as a pure Verilog
design and expects the 'top_instance' name to be .' separated.

To ensure that this mismatch does not cause any issues, use the following variable to set the
hierarchical separator to '.' or '/':
pa_set activity_streaming_hier_separator <"." | "/">

24.4.3. Parallel Analysis Setup

The 'ConfigureParallelAnalysis' command defines the options for processing information in parallel.

Refer to the PowerArtist Reference Manual for complete details of the command.

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The Streaming (PAVES) Flow

24.4.3.1. Output Files

• There are two output files in the average power analysis/GAF flow:
– The final output GAF file
A single GAF file is generated after parallel analysis and the name of the file can be specified
by either of the following commands:
pa_set gaf_file <file_name>

or:
GenerateGAF -gaf_file <file_name>

– The log file

A single log file is generated after parallel analysis and the name of the file can be specified
by either of the following commands:
pa_set gaf_log <file_name>

or:
GenerateGAF -gaf_log <file_name>

• The output files in the time-based power analysis flow are described in section Distributed
Processing in Time-based Power Analysis (p. 272).

24.5. Veloce-PowerArtist Flow Known Limitations/Issues

There are some known limitations/issues in this flow on both Veloce and PowerArtist side. These
limitations are explained below:

• Veloce does not dump all memory signals (MDAs) by default. So you must obtain the missing
signal list from PowerArtist and then enable dumping during Veloce dataset generation. This
limitation can lead to multiple iterations.
• If GAF is killed while streaming data from Veloce, a subsequent PowerArtist run pointing to the
same Veloce dataset sometimes gives an error. The work-around is to delete the file
'.velwavegenInProgress' located in the directory 'dataset' before running PowerArtist
again.
• Multiple runs pointing to the same Veloce dataset cannot be executed at the same time, unlike
FSDB.
• Sequencing of clock versus control ports especially for macros is missing in Veloce simulation
data.
• The PowerArtist/Veloce streaming flow is not enabled for reduction (ReducePower), and rpm
(CreateRPM) flows.
• Multi-process ProfilePower is not supported. ProfilePower PAVES flow does not support
profile_calibration files, and the veloce_live streaming mode.

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Chapter 25: Supporting DesignWare ® Components
25.1. Introduction
PowerArtist supports a flow that automates the synthesis and use of DesignWare® (DW) components.
Any DW component, which is instantiated in the RTL and is not defined either by you or PowerArtist
using the '-macromap' option, can be automatically synthesized under-the-hood using your synthesis
environment. This is a single-pass flow and the synthesized DW netlist is automatically plugged-in and
used for power analysis.

Chapter Organization
The following topics are covered in this chapter:

• Enabling Synthesis of DesignWare Components (p. 539)

• Re-using a Synthesized DW Netlist (p. 540)
• Creating AW Wrappers for Unsupported DW Components (p. 540)
• Passing Options to External Synthesis Tools (p. 543)
• The DWCompDefinition.txt File (p. 543)

25.2. Enabling Synthesis of DesignWare Components

You can enable the generation and use of synthesized DesignWare (DW) components by using the
following variable:
pa_set enable_dw_synthesis <true | false>

By default, the generated DW netlists are stored at: '${PWD}/aw_worklib'. You can change the
default location by using the following variable:
pa_set dw_write_directory <dir_name>

If the directory specified by '<dir_name>' is non-writable, PowerArtist generates an error and exits.

During external synthesis of DW components, the technology libraries should be in the '.db' format.
However, they are usually provided in '.lib' format to PowerArtist (using the '-synlib' option). So,
while synthesizing the DW components, '.lib' libraries are converted to the '.db' format.

If there are pre-existing libraries in the '.db' format, use the following variable:
pa_set dblib {<dblib__name_1> <dblib__name_2> <dblib_name_3> ...}

For better performance, use the above option to specify the '.db' files (only for the standard cells).

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Supporting DesignWare ® Components

25.3. Re-using a Synthesized DW Netlist

You can re-use a pre-generated synthesized DW netlist in subsequent runs by using the following
variable:
pa_set dw_synthesized_dir_path <dw_worklib>

where, 'dw_worklib' is the directory containing the pre-generated synthesized netlist per DW
component.

If a pre-generated synthesized DW netlist is missing from the specified directory, then those DW
components are black-boxed by PowerArtist and a warning message is issued.

Note: This option does not call the external synthesis tool and therefore saves runtime by preventing
repeated synthesis of DW components.

To re-write or re-generate an existing generated DW netlist, you have to delete the netlist and re-run
with only the '-enable_dw_synthesis' option.

You can also use the following two options together:

• To enable the generation and use of synthesized DW components, use

'-enable_dw_synthesis'.
• To re-use a pre-generated synthesized DW netlist in subsequent runs, use
'-dw_synthesized_dir_path'.

When you use these options together, PowerArtist looks for the presence of a generated netlist in the
path specified using the '-dw_synthesized_dir_path' option.

If the generated netlist is present, it is used for final power analysis. If the generated netlist is not
present, then the DW component is marked for external synthesis and added to an intermediate file.
This way, only the non-existing DW components are synthesized by calling the external synthesis tool,
leading to overall improved runtime.

25.3.1. DesignWare Cache Directory Location

The location of the Synopsys cache is changed from the 'home' directory to the 'work' directory. This
helps in cases where the 'home' directory has limited disk space.

25.4. Creating AW Wrappers for Unsupported DW Components

The DW component to be synthesized must have an AW (AnsysWare) wrapper. An AW wrapper is a
module, defined in a '.v' file, that instantiates the DW component. The AW wrapper is synthesized and
its gate-level netlist is stitched back to PowerArtist's netlist.

Several AW wrappers are pre-installed in the release tarkit, which improve accuracy of the flow. The
installation path for AW wrappers and corresponding DW components is:
$POWERARTIST_ROOT/pthdl_src/macros

The default location of the input file containing the list of AW wrappers is:

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 Creating AW Wrappers for Unsupported DW Components

$POWERARTIST_ROOT/pthdl_src/macros/DWCompDefinition.txt

You can change the default location of 'DWCompDefinition.txt' and specify the directories containing
the user-defined AW wrappers by using the following variable:
pa_set aw_directories {<dir1> <dir2> <...> }

PowerArtist reads all the user-defined directories first and then the default location. If the same DW
wrappers are present in multiple directories, they are read from the first directory specified.

The AW wrappers are named like their DW counterparts. For example, the wrapper module for
'DW01_add' is named 'AW01_add' and the wrapper file name is 'AW01_add.v'.

25.4.1. Steps to Create an AW Wrapper

This section describes the steps you need to follow to create an AW Wrapper.

1. Create the RTL description of the AW wrapper in a file by using the following template:
module <AW_name> (<port_list>)
<parameter declaration>
<input/output port declarations>
<corresponding DW instantiation with the parameter and port mapping>
endmodule

The components of the template are described below:

• The name of the wrapper module '<AW_name>' is created by replacing the first character
'D' of the DW component by 'A'. For example, if the DW component is named 'DW01_add',
the wrapper name is 'AW01_add' and the corresponding file name is 'AW01_add.v'.

• The interface of the wrapper module '<port_list>' is identical to the corresponding DW

component. You can copy the DW component's port list.

• The '<parameter declaration>' and '<input/output port declarations>' should also be similar
to the parameter and port declarations of the DW component.

• Instantiate the DW component specifying the parameter mapping and named port-mapping.
For example, the wrapper module for 'DW01_add' can be defined as:
module AW01_add ( A, B, CI, SUM, CO );

parameter width = 4 ;
input [width-1 : 0] A;
input [width-1 : 0] B;
input CI;
output [width-1 : 0] SUM;
output CO;

// Instance of DW01_add
DW01_add #(width) U1 (.A(A), .B(B), .CI(CI), .SUM(SUM), .CO(CO) );

endmodule

2. Save the wrapper module in a file named '<AW_name>.v' and specify the location of the file (s)
by using the following variable:

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Supporting DesignWare ® Components

pa_set aw_directories {<dir1> <dir2> <...> }

3. Add the entry for the DW component's parameter description at the bottom of the user-defined
'DWCompDefinition.txt' file.

The format of this file is very important for the flow to work properly, so the new entry must be
in exactly the following format:
<DW_comp_name> <single_or_multiple_spaces> <param_name_1>
<single_or_multiple_spaces> <param_name_2>.....

For example, the entry for the component 'DW02_tree' (with two parameters) is as below:
DW02_tree num_inputs input_width

4. Send details of the newly added wrapper(s) to PowerArtist R&D so that support for these
components is added to the next release and you do not need to recreate them.

Note:This is the most important step towards improving DW support in PowerArtist.

25.4.2. Sample AW Wrappers

Sample AW wrappers are described below:

module AW01_absval
module AW01_absval ( A, ABSVAL );

parameter width = 4;

input [width-1 : 0] A;
output [width-1 : 0] ABSVAL;

// Instance of DW01_absval
DW01_absval #(width) U1 (.A(A), .ABSVAL(ABSVAL);

endmodule

module AW01_addsub
module AW01_addsub ( A, B, CI, ADD_SUB, SUM, CO );

parameter width = 4;

input [width-1 : 0] A;
input [width-1 : 0] B;
input CI;
input ADD_SUB;
output [width-1 : 0] SUM;
output CO;

// Instance of DW01_add
DW01_addsub #(width) U1 (.A(A), .B(B), .CI(CI),
.ADD_SUB(ADD_SUB), .SUM(SUM), .CO(CO) );

endmodule

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 The DWCompDefinition.txt File

25.5. Passing Options to External Synthesis Tools

For better power-correlation, you can specify various options used by DC commands, such as 'analyze',
'elaborate', or 'compile_ultra' in a '.tcl' file. Use the command 'set_app_var' to set the options in the
input '.tcl' file. For example, you can add the following command to the '.tcl' file to enable
clock-gating in DW components:
set_app_var compile_ultra_gate_clock true

You can specify this '.tcl' file during elaboration by using the following variable:
pa_set dw_synthesis_options_file <tcl_filename>

A sample 'dc_options.tcl' file is shown below:

set_app_var compile_ultra_ungroup_dw false
set_app_var compile_seqmap_propagate_constants false

Sample Tcl File

You can use a '.tcl' file during elaboration with the DW flow enabled. A sample file is shown below:
pa_set verilog_startup_file <filename>
pa_set system_verilog true
pa_set top <topName>
pa_set scenario_file <scn_file>

pa_set enable_dw_synthesis true

pa_set dw_synthesized_dir_path <dw_pool_dir_name>
pa_set dblib {std_cell1.db std_cell2.db}
pa_set dw_write_directory <dw_netlist_write_dir>
pa_set aw_directories {aw_dir1 aw_dir2}

Elaborate <options>

<snip>

25.6. The DWCompDefinition.txt File

Refer to Appendix A: DWCompDefinition Text File (p. 545) for the contents of the default
'DWCompDefinition.txt' file.

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Appendix A. DWCompDefinition Text File

A.1. The DWCompDefinition.txt File

The contents of the default DWCompDefinition.txt file:

DW01_add width
DW01_absval width
DW01_addsub width
DW01_dec width
DW01_inc width
DW01_sub width
DW_lzd a_width
DW01_decode width
DW01_cmp2 width
DW01_cmp6 width
DW01_csa width
DW_minmax width num_inputs
DW02_mult A_width B_width
DW02_tree num_inputs input_width
DW02_mult_2_stage A_width B_width
DW02_mult_3_stage A_width B_width
DW02_mult_4_stage A_width B_width
DW02_mult_5_stage A_width B_width
DW02_mult_6_stage A_width B_width
DW01_bsh A_width SH_width
DW02_mac A_width B_width
DW02_sum num_inputs input_width
DW01_binenc A_width ADDR_width
DW01_prienc A_width INDEX_width
DW02_multp a_width b_width out_width
DW_div_pipe a_width b_width tc_mode
DW01_mux_any A_width SEL_width MUX_width
DW_pl_reg width in_reg stages out_reg rst_mode

Release 2025R1.2 - © ANSYS, Inc. All rights reserved. - Contains proprietary and confidential information
of ANSYS, Inc. and its subsidiaries and affiliates. 545
 Release 2025R1.2 - © ANSYS, Inc. All rights reserved. - Contains proprietary and confidential information
546 of ANSYS, Inc. and its subsidiaries and affiliates.