PICMG 2.0 R2.

CompactPCI Specification
TM

Short Form
September 2, 1997

NOTE: This short form specification is a subset of Revision 2.1 of the CompactPCI
specification. For complete guidelines on the design of CompactPCI compliant boards and
systems, the full specification is required.
For a full copy of the CompactPCI specification please contact the PCI Industrial Computers Manufacturers group
c/o:
Rogers Communications, 301 Edgewater Place, Suite 220, Wakefield MA 01880.
Phone: +1.617.224.1100.
FAX: +1.617.224.1239.
http://www.picmg.org

Copyright 1995, 1996, 1997 PCI Industrial Computers Manufacturers Group (PICMG).

PICMG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors or omissions
that may appear in this document, nor is PICMG responsible for any incidental or consequential damages resulting from the use of any data contained in this document,
nor does PICMG assume any responsibility to update or correct any information in this publication

CompactPCI Short Form Specification, Revision 2.1 1

Overview Systems
This short form specification is a subset of the full A CompactPCI system is composed of one or more
CompactPCI Specification, Revision 2.1 as approved by the CompactPCI bus segments. Each segment is composed of up
PICMG. This document is meant as a guide for those to eight CompactPCI board locations (at 33 MHz) with
considering CompactPCI, but is not a design document. 20.32 mm (0.8 inch) board center-to-center spacing. Each
Anyone wishing to design a system board, adapter board, or CompactPCI segment consists of one System Slot, and up to
backplane for CompactPCI should obtain the full seven Peripheral Slots.
specification from PICMG. You can also download a PDF The System Slot board provides arbitration, clock
or HTML version of this short form specification from the distribution, and reset functions for all boards on the
PICMG Web Site at www.picmg.org. segment. The System Slot is responsible for performing
CompactPCI is an adaptation of the Peripheral Component system initialization by managing each local board’s IDSEL
Interconnect (PCI) Specification for industrial and/or signal. Physically, the System Slot may be located at any
embedded applications requiring a more robust mechanical position in the backplane. For simplicity, this specification
form factor than desktop PCI. CompactPCI uses industry assumes one CompactPCI bus segment in which the System
standard mechanical components and high performance Slot is located on the left when the backplane is viewed
connector technologies to provide an optimized system from the front side.
intended for rugged applications. CompactPCI provides a The Peripheral Slots may contain simple boards, intelligent
system that is electrically compatible with the PCI slaves, or PCI bus masters.
Specification, allowing low cost PCI components to be
utilized in a mechanical form factor suited for rugged Figure 1. CompactPCI form factors
environments.
CompactPCI is an open specification supported by the
PICMG (PCI Industrial Computer Manufacturers Group),
which is a consortium of companies involved in utilizing
PCI for embedded applications. PICMG controls this
specification.
Form Factor
The form factor defined for CompactPCI boards is based
upon the Eurocard industry standard. Both 3U (100 mm by
160 mm) and 6U (233.35 mm by 160 mm) board sizes are
defined. See Figure 1 opposite. The 3U form factor is the
minimum for CompactPCI as is accommodates the full
64Bit CompactPCI bus. The 6U extensions are defined for
boards where the extra board area or connection space is
needed. Rear connectors are numbered J1-J5 starting at the
bottom connector. The Specification defines the locations
for all these connectors but only the signal-pin assignments
for the CompactPCI bus portion J1 and J2. Use of the
remaining connectors (J3, J4, and J5) are the subject of
additional specification efforts, or can be user defined for
specific applications. Several PICMG sub-committees have
been formed to create specifications for standard application
use of J3-J5. Consult PICMG for more details.
Front Panels Backplanes
CompactPCI boards provide a front plate interface that is The default CompactPCI backplane is illustrated in Figure
consistent with Eurocard packaging and are compliant with 2. As viewed from the front of the system chassis. Other
IEEE 1101.1 or IEEE 1101.10 (EMC panels). Ejec- topologies besides the linear arrangement illustrated are
tor/injector handles that are compliant with IEEE 1101.10 allowed by CompactPCI. However, this specification and all
are also be used. One ejector handle is used for 3U boards. backplane simulations have assumed a linear topology using
6U boards use two handles. Filler panels do not require 20.32 mm (0.8 inch) board center-to-center spacing. Any
handles. other topology must be simulated or otherwise verified to
ensure compliance to the PCI specification.

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CompactPCI Short Form Specification, Revision 2.1
Slot Spacing Connector
Slot spacing SHALL be 20.32 mm (.8 inch). Bus segments
SHALL not have more than eight slots without one or more The CompactPCI connector is a shielded, 2 mm-pitch, 5-
PCI bridges. row connector as defined by IEC 917 and IEC 1076-4-101.
Features of this connector include:
Slot Designation • Pin and socket interconnect mechanism
Physical backplane slots SHALL be designated 1, 2, 3, • Multi-vendor support
through N, where N is the number of slots. For example, an • Coding Mechanism providing positive keying
eight slot backplane would designate the backplane slots as • Staggered make-break pin populations for optional
1 through 8 with the compatibility glyphs. Slot numbering hot-swap capability
SHALL start at the top left corner as viewed from the front. • Rear pin option for through-the-backplane I/O
Logical slot numbers are used in the nomenclature to define applications
the physical outline of a connector on a bus segment. Please • High density PCI capability
see Chapter 3 of the Full Specification for signal routing
• Shield for EMI/RFI protection
requirements.
• Expandability for end user applications
Each slot MAY be implemented with one or more
CompactPCI is defined as a 5 row by 47 position array of
connectors. Backplane connectors SHALL be designated as
pins divided logically into two groups corresponding to the
P1 through P5 corresponding in location to the board’s
physical connector implementation. 32-bit PCI and
connectors.
connector keying is implemented on one connector (J1). An
Any given connector SHALL be referenced by first
additional connector (J2) is defined for 64-bit transfers or
specifying the logical slot number (1...8) followed by a
for rear panel I/O in the 3U form factor. 6U form factor
hyphen and then the individual connector (P1...P5). For
boards also provide J3-J5 capability.
example, in a 32-bit 3U system the rear-panel I/O connector
The CompactPCI connector utilizes guide lugs located on
in logical slot 5 would be designated by 5-P2. In a 64-bit 6U
the board connector to ensure correct polarized mating.
system the rear-panel I/O connector in logical slot 1 would
Proper mating is further enhanced by the use of coding keys
be designated by 1-P3.
for 3.3 V or 5V operation, with or without Hot-Swap
Bus Segments capability, to prevent incorrect installation of boards.
Bus segments MAY accommodate 64-bit operation or
J1 (3U and 6U Boards)(32-Bit PCI Signals)
SHALL provide individual pull-up resistors at each board
CompactPCI board connector J1 is used for the 32-bit PCI
slot for the REQ64# and ACK64# signals. Refer to the PCI
signals. 32-bit boards SHALL always use this connector.
specification for details. The System Slot SHALL use both
Use of the J2 connector is optional.
J1 and J2 to allow the arbitration and clock signals to be
connected to the backplane from a System Slot board. J2 Connector (3U and 6U Boards)
Connectors require pin staging to accommodate hot-swap J2 MAY be used for 64-bit PCI transfers or for rear-panel
operation. I/O. J2 SHALL be used on System Slot boards to provide
CompactPCI bus segments SHALL bus all signals in all arbitration and clock signals for peripheral boards.
slots within the segment except the slot specific signals:
J3 through J5 Connectors (6U Boards)
CLK, REQ# and GNT#. Each logical slot also has a unique
J3 through J5 are available in 6U systems for application
IDSEL signal connected to one of the upper ADxx signals
use. Applications include rear-panel I/O, bused signals (e.g.
for configuration (plug and play) decoding.
H.110), or custom use. Consult PICMG for standardized
.
pin assignments of J3 through J5.
Figure 2. CompactPCI Backplane.
Bussed Reserved Pins
= SYSTEM SLOT = PERIPHERAL SLOT
The BRSVPxxx signals SHALL be bussed between
22
2-P2 7-P2
22 connectors and are reserved for future definition.
Non-Bussed Reserved Pins
The RSV signals are non-bused signals that SHALL be
reserved for future definition.
1 1
25 25

Power Pins
All CompactPCI connectors provide pins for +5V, +3.3V,
+12V and -12V operating power. Additional power pins
labeled +V(I/O) provide power for Universal boards
utilizing I/O buffers driving backplane signals that MAY
1 1
z a b c d e f

1
2-P1

2 3 4 5 6
7-P1

7
z a b c d e f

8
operate from +5V or +3.3V. On these boards, the PCI
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CompactPCI Short Form Specification, Revision 2.1
components I/O buffers SHALL be powered from V(I/O), boards (real panel I/O) into the subrack is defined by IEEE
not from +5V or +3.3V power pins. P1101.11.
Backplane pins labeled V(I/O) are connected to +5V on 5V Physical board locations within the subrack SHOULD be
keyed systems and +3.3V on 3.3 V keyed systems. indicated by a numbering scheme visible from the front (and
Alternatively, a separate V(I/O) power plane may be pro- rear if back panel I/O is utilized) of the subrack.
vided to supply 5V or 3.3 V power.
CompactPCI Signal Additions
5V/3.3V PCI Keying CompactPCI defines some additional signals beyond the
CompactPCI implements a keying mechanism to PCI specification that may be applicable to board designs.
differentiate 5V or 3.3 V signaling operation. The keying These signals are: Push Button Reset (PRST#), Power
mechanism is designed to prevent a board built with one Supply Status (DEG#, FAL#), System Slot Identification
buffer technology (5V or 3.3 V) from being inserted into a (SYSEN#), System Enumeration (ENUM#), Geographical
system designed for the other buffer technology (3.3 V or Addressing and legacy IDE interrupt support. Consult the
5V, respectively). Universal boards MAY operate in either Full Specification for more details.
+5V or +3.3V systems and are not keyed. Positions 12-14 of
Signal Termination
the CompactPCI J1 connector are used for the keying
All bussed PCI signals SHALL include a 10 Ω stub
mechanism. Backplanes SHALL be configured as either 5V
termination resistor located on the board at the CompactPCI
or 3.3V and SHALL provide the appropriate key. It is not
connector interface. The signals that SHALL be terminated
possible to have a “universal” backplane. Refer to the
are: AD0-AD31, C/BE0#-C/BE3#, PAR, FRAME#,
CompactPCI Keying Specification for additional details on
IRDY#, TRDY#, STOP#, LOCK#, IDSEL, DEVSEL#,
keying.
PERR#, SERR#, and RST#.
If used by a board, the following signals SHALL also be
Hot Swap Capability terminated: INTA#, INTB#, INTC#, INTD#, SB0# ,
The CompactPCI Connector accommodates the mechanical SDONE, AD32-AD63, C/BE4#-C/BE7#, REQ64#,
prerequisites for hot swap by staging the pin sequence ACK64#, and PAR64.
within the backplane connector. A PICMG sub-committee The following signals do not require a stub termination
has specified thoroughly a hot swap implementation for resistor: CLK, REQ#, GNT#, TDI, TDO, TCK, TMS, and
CompactPCI. Contact PICMG for details. TRST#.
The stub termination minimizes the effect of the stub on
each board to the PCI backplane. The resistor SHALL be
Adapter Boards placed within 15.2 mm (0.6 inches) of the signal’s
CompactPCI board design SHALL adhere to the design connector pin. This length SHALL be included in the
requirements for standard desktop PCI boards as outlined in overall length of trace that is allowed for the signal.
the PCI Specification. This section documents additional Peripheral boards that drive REQ# SHOULD provide a
requirements and/or restrictions as needed. The design series terminating resistor at the driver pin (not a stub
rules apply to PCI bus operation up to 33 MHz. termination resistor at the connector). On System Slot
Physical Outline boards, a series resistor (sized according to the output
CompactPCI defines two board sizes, 3U and 6U. characteristics of the clock buffer) SHALL be located at the
3U Boards driver for the CLK signal provided to each slot. Each
3U boards are 100 mm by 160 mm. The PCB is 1.6 mm System Slot board’s GNT# signal SHALL also be series
thick. A 2 mm (IEC-1076-4-101) connector is used for terminated at the driver with a resistor as required by the
interfacing to the CompactPCI bus segment.. 32-bit PCI is driving buffer output characteristics.
implemented on J1. J2 MAY be used for 64-bit PCI Peripheral Board Signal Stub Length
signaling, or rear-panel I/O, or System Slot functions. Signal length for 32-bit and 64-bit signals SHALL be less
6U Boards than or equal to 38.1 mm (1.5 inches). These lengths are
6U boards are 233.35 mm by 160 mm. 32-bit PCI is imple- measured from the connector pin through the stub or series
mented on J1. J2 is used for 64-bit PCI signaling, or rear- termination resistor to the PCI device pin. These lengths
panel I/O, or System Slot functions. J3, J4 and J5 MAY be are consistent with the PCI Specification requirements but
used for rear-panel I/O. also include the resistor in the total trace length.
Rear-panel I/O MAY be defined by the user and/or utilize A maximum of one PCI load SHALL be allowed on any PCI
PICMG specifications. Contact PICMG for copies of these signal from the connector on any given board. Peripheral
specifications. boards with more than one load are not compliant with the
Front entry of CompactPCI boards into the subrack is CompactPCI Specification and SHALL not be declared
defined by IEEE 1101.1 and IEEE 1101.10. Rear entry of CompactPCI compatible.

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CompactPCI Short Form Specification, Revision 2.1
System Board Loading The I/O plate is assumed to be connected to earth ground
The System Slot MAY have two PCI loads on each signal and isolated from logic ground. CompactPCI boards SHALL
on a PCI backplane segment to accommodate practical not connect earth ground (on front panel) through a low
implementations of PCI based CPU designs. The impedance path to logic ground used on-board.
CompactPCI system modeling was performed with this For applications requiring coupling between earth and logic
requirement. The second load SHALL not add more than ground, boards MAY implement a coupling method.
25.4 mm (1 inch) to the signal length for any PCI signal in Because coupling methods are application dependent,
addition to the 38.1 mm (1.5 inches) allowed for 32-bit PCI specification for coupling circuits are beyond the scope of
signals. In absence of a second load, System Slot Boards the specification.
MAY have up to 63.5 mm (2.5 inches) of signal length for
any PCI signal. Only one stub termination resistor is Backplane Design Rules
required per PCI signal on System Slot designs and this
SHALL be placed within 15.2 mm (0.6 inches) of the CompactPCI defines a backplane environment that MAY
connector pin as outlined in the Speification. System Slot have up to eight boards. One slot, the System Slot, provides
Boards that have more than two loads or that violate the the clocking, arbitration, configuration, and interrupt
total trace length allowed SHALL NOT claim CompactPCI processing for the other 7 slots. Fewer slots may be
compliants nor be considered such. provided in a CompactPCI backplane, but the following
sections assume that a maximum configuration is employed.
Peripheral Board PCI Clock Signal Length Backplanes SHALL provide separate power planes for 3.3
On Peripheral boards, the PCI clock signal length SHALL V, 5V, and ground. If V(I/O) is configurable as 3.3 V or 5V,
be 63.5 mm ± 2.54 mm (2.5 inches ±0.1 inches), and is then a separate power plane SHALL be dedicated for
allowed to drive one load only on the board. V(I/O).
Pull-up Location Clock Routing Requirements
Pull-up resistors required by the PCI specification SHALL A 2 ns maximum skew SHALL be maintained between any
be located on the System Slot board. The pull-up resistor, two PCI components (not connector to connector) per PCI
for those signals requiring a pull-up, SHALL be placed on specification requirements. Adherence to backplane and
the in-board side of the stub termination resistor. board rules contained in this specification help meet this
The System Slot board SHALL provide a pull-up resistor for requirement.
the REQ64# and ACK64# signals even if the System Slot Revision 2.1 compliant CPU boards SHALL drive 7
board does not use these signals, as in the case of a 32-bit independent clock signals to the backplane. Revision 2.1
System Slot board. This requirement accommodates 64-bit Backplanes are only required to route 5 independent clocks
boards. They SHALL see the signal REQ64# as false during (CLK0-CLK4). Hot Swap systems require independent
reset to properly connect to the 32-bit PCI bus. The pull-up clock routing on the backplane. In future Revisions of the
resistor also prevents floating REQ64# or ACK64# signals CompactPCI Specification, individual clock routing will be
on 64-bit boards. required on the backplane. Board slots receive their specific
Connector Shield Requirements clock using the CLK pin (J1:D6).
The CompactPCI connector SHALL load a shield at row F Signaling Environment
on the board. This shield covers the top of the IEC-1076-4- Each CompactPCI backplane provides for either a 5V or
101 connector and helps to provide a low impedance return 3.3V signaling environment. PCI allows for two types of
path for ground between the board and the CompactPCI buffer interfaces for inter-board connection. 5V signaling
backplane. This is required for CompactPCI compliance will generally be used for early systems. A gradual shift to
and was used in the simulation modeling of the 3.3V will occur as the semiconductor industry shifts to the
CompactPCI environment. Boards that do not use this lower power interface for speed and power dissipation
shield are not compliant and are not guaranteed to work in reasons. The V(I/O) power pins on the connector are used
all CompactPCI system topologies. to power the buffers on the peripheral boards, allowing a
The lower shield option that is provided for in the IEC- card to be designed to work in either interface.
1076-4-101 connector is not required for CompactPCI CompactPCI allows for this dual interface scheme by
boards and SHALL not be loaded if it protrudes into the providing a unique backplane connector-coding plug for
inter-board separation plane. either system. The CompactPCI backplane may be either a
Front Panel I/O Connector Recommendations fixed signaling environment backplane (e.g., 5V only) or
CompactPCI boards SHOULD utilize metalized shell may be configurable. In any case, when configured for 5V
connectors for EMI/RFI protection. The shell SHOULD be operation, the 5V coding plug (Brilliant Blue) SHALL be
electrically connected to the I/O plate through a low imped- used, and when configured for 3.3V operation, the 3.3V
ance path in accordance with IEEE 1101.10. coding plug (Cadmium Yellow) SHALL be installed in the
backplane connector.
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CompactPCI Short Form Specification, Revision 2.1
IDSEL Assignment • Geograhical Addressing
The PCI signal IDSEL is used to provide unique access to • System Enumeration (ENUM#)
each logical slot for configuration purposes. By connecting Consult the Full Specification for Details.
one of the address lines AD31 through AD25 to each
board’s IDSEL pin (J1:B9), a unique address for each board Power Distribution
is provided during configuration cycles. Power is distributed in a CompactPCI system by utilizing a
backplane. Each backplane SHALL make provisions for the
REQ#/GNT# Assignment
The System Slot interfaces to seven pairs of REQx#/GNTx# standard regulated direct current (DC) supply voltages in
pins called REQ0#-REQ6# and GNT0#-GNT6#. Each Table1 below.
board slot interfaces to one pair of REQx#/GNTx# signals Table 1. Power Specifications.
using pins called REQ# and GNT#.
The System Slot on any given CompactPCI backplane Mnemonic Description Nominal Tolerance Max.
segment SHALL support the full complement of Value Ripple
REQ#/GNT# signals. 5V +5VDC 5.0V ±5% 50 mV
If a System Slot board can not support the full complement
of REQ#/GNT# signals, provision SHALL be made to 3.3 V +3.3 VDC 3.3 V ±5% 50 mV
configure which slots in the CompactPCI backplane are +12V +12VDC 12.0V ±5% 50 mV
supported for arbitration. In this manner, boards using -12V -12VDC -12.0V ±5% 50 mV
REQ#/GNT# signals may be located in any given slot as
required by the application. GND Ground

PCI Interrupt Binding

The backplane SHALL provide power connectors for all of
Interrupt binding of the BIOS setup program SHALL
the supply voltages in Table 1. One of two methods MAY be
require backplane assignments from the System Slot
chosen:
interrupt pins INTA#-INTD# to the logical board slot inter-
rupts. • Power terminals MAY be located on the front or rear
Backplane assignments rotate through logical board slots to side of the backplane for external power sources.
provide a unique PCI interrupt to each board for the first
• An IEC 603-2 (DIN 41612) style connector and rear
four PCI connectors (assuming that each board drives just
side power terminals SHOULD be used for in-rack
its INTA# signal). Rotating interrupt assignments allows
modular power supplies.
multiple PCI peripherals that drive only INTA# in order to
utilize a different interrupt on the System Slot board without Power Decoupling
the need to share an interrupt with another PCI interface. CompactPCI boards may utilize any of the voltages in Table
Since multi-function PCI devices are allowed to drive more 1. Without adequate power decoupling on the backplane for
than one interrupt, shared interrupts may be required even the 5 and 3.3 Volt power, intermittent operation may result.
within the first four board slots. In addition, the rotating The backplane has dedicated 5V and 3.3V power pins along
pattern repeats itself after logical slot four, which also with V(I/O) power pins. The V(I/O) power pins are
requires the sharing of an interrupt for slots that are four connected to either 5V or 3.3V depending on if 5V or 3.3V
connectors apart (logical slots 2 and 6 for example). backplane signals are being used.
The Interrupt assignments are consistent with the PCI-PCI All power voltages SHALL be decoupled to ground in such
Bridge Specification as defined by the PCI SIG. This is to a manner as to provide for reasonable management of
allow PCI-PCI bridge technology on CPU boards between switching currents (di/dt). Low impedance power planes
Bus 0 and CompactPCI. and connections to low equivalent series resistance (ESR)
capacitors should be used. Even if a system does not use 3.3
CompactPCI Signal Additions
or 5V, the unused power pins SHALL be connected and
CompactPCI utilizes PCI signals as defined by the PCI
decoupled to provide an additional AC return path.
Local Bus Specification with some additional signals. These
additional signals do not affect the PCI signals but MAY PCI Clock Distribution
enhance system operation by providing push button reset, The System Slot board SHALL provide clock signals for all
power supply status, System Slot identification, and legacy PCI peripherals in the system, including devices on the
IDE interrupt support features. The additional signals System Slot board. Peripheral boards are provided clock
defined are: signals via the CompactPCI backplane. A maximum skew
• Push Button Reset (PRST#) of 2 ns SHALL be maintained across the system operating at
• Power Supply Status (DEG#, FAL#) 33 MHz between any two PCI devices at the clock input of
• System Slot Identification (SYSEN#) the integrated circuits. Consult the Full Specification for
• Legacy IDE Interrupt Support (INTP and INTS) Design Details.
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CompactPCI Short Form Specification, Revision 2.1
Table 2. CompactPCI Pinouts
22 GND GA4 GA3 GA2 GA1 GA0 GND
21 GND CLK6 GND RSV RSV RSV GND
20 GND CLK5 GND RSV GND RSV GND
19 GND GND GND RSV RSV RSV GND P2
18 GND BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 GND /
17 GND BRSVP2A17 GND PRST# REQ6# GNT6# GND J2
16 GND BRSVP2A16 BRSVP2B16 DEG# GND BRSVP2E16 GND
15 GND BRSVP2A15 GND FAL# REQ5# GNT5# GND
14 GND AD[35] AD[34] AD[33] GND AD[32] GND
13 GND AD[38] GND V(I/O) AD[37] AD[36] GND C
12 GND AD[42] AD[41] AD[40] GND AD[39] GND O
11 GND AD[45] GND V(I/O) AD[44] AD[43] GND N
10 GND AD[49] AD[48] AD[47] GND AD[46] GND N
9 GND AD[52] GND V(I/O) AD[51] AD[50] GND E
8 GND AD[56] AD[55] AD[54] GND AD[53] GND C
7 GND AD[59] GND V(I/O) AD[58] AD[57] GND T
6 GND AD[63] AD[62] AD[61] GND AD[60] GND O
5 GND C/BE[5]# GND V(I/O) C/BE[4]# PAR64 GND R
4 GND V(I/O) BRSVP2B4 C/BE[7]# GND C/BE[6]# GND
3 GND CLK4 GND GNT3# REQ4# GNT4# GND
2 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND
1 GND CLK1 GND REQ1# GNT1# REQ2# GND
25 GND 5V REQ64# ENUM# 3.3V 5V GND
24 GND AD[1] 5V V(I/O) AD[0] ACK64# GND
23 GND 3.3V AD[4] AD[3] 5V AD[2] GND
22 GND AD[7] GND 3.3V AD[6] AD[5] GND P1
21 GND 3.3V AD[9] AD[8] M66EN C/BE[0]# GND /
20 GND AD[12] GND V(I/O) AD[11] AD[10] GND J1
19 GND 3.3V AD[15] AD[14] GND AD[13] GND
18 GND SERR# GND 3.3V PAR C/BE[1]# GND
17 GND 3.3V SDONE SBO# GND PERR# GND
16 GND DEVSEL# GND V(I/O) STOP# LOCK# GND C
15 GND 3.3V FRAME# IRDY# GND TRDY# GND O
12-14 KEY AREA N
11 GND AD[18] AD[17] AD[16] GND C/BE[2]# GND N
10 GND AD[21] GND 3.3V AD[20] AD[19] GND E
9 GND C/BE[3]# IDSEL AD[23] GND AD[22] GND C
8 GND AD[26] GND V(I/O) AD[25] AD[24] GND T
7 GND AD[30] AD[29] AD[28] GND AD[27] GND O
6 GND REQ# GND 3.3V CLK AD[31] GND R
5 GND BRSVP1A5 BRSVP1B5 RST# GND GNT# GND
4 GND BRSVP1A4 GND V(I/O) INTP INTS GND
3 GND INTA# INTB# INTC# 5V INTD# GND
2 GND TCK 5V TMS TDO TDI GND
1 GND 5V -12V TRST# +12V 5V GND
Pin Z A B C D E F

Consult the Full Specification for complete design Details

END OF DOCUMENT

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CompactPCI Short Form Specification, Revision 2.1