PLL Layout

Outline
1. Introduction

2. Charge Pump PLL Linear Analysis

3. Phase Noise Analysis

4. Circuit Design and Simulation

5. Layout and Post-Layout Simulation

6. Chip Measurements

7. Conclusion
1. Introduction
Phase-locked loops are building blocks used extensively in
many analog and digital system.
Applications:
(1) Clock/data recovery
(2) Frequency synthesis/generation
(3) Frequency modulation/demodulation
The PLL does two jobs:
(1) if Vref(t) differs from VCO in frequency, the PLL adjust its
frequency to equal the input frequency. (called latching).
(2) Once the PLL adjusted in frequency, locked, it must hold
that frequency by developing a voltage, which is related to a
phase difference, to enable it to stay locked in frequency to
the input frequency.

Generally, the phase comparator can be

(1) An exclusive-or gate for digital signals
(2) A mixer for analog signals
The phase comparator generates a output voltage Ve(t)
according to the phase/frequency difference of its inputs.
The loop filter removes the high frequency components and
outputs a voltage Vc(t).
Here we focus on the nonlinear mixer (phase comparator) and
its generation of new frequencies at the output of the filter.
Let Vref ( t ) = Vref sin (ω ref t + θ ref ) → the input frequency
And Vfb ( t ) = Vfb sin (ω fbt + θ fb ) → the feedback frequency
The mixer output is (KPD is mixer gain):
Ve ( t ) = K PD [ Vref sin (ω ref t + θ ref ) ] ⋅ [ V fb sin (ω fbt + θ fb ) ]
1
 sin α sin β = [ cos(α − β ) − cos(α + β )]
2
The mixer output can written as
K PD Vref V fb
Ve ( t ) = {cos[(ω ref −ω fb )t + (θ ref −θ fb )] − cos[(ω ref +ω fb )t + (θ ref +θ fb )]}
2
If ω ref fb are closely match, thus ω ref − ω fb < < ω ref + ω fb
and ω
Low pass filter response removes the higher component.

ω ref − ωfb ω ref + ωfb

The Loop filter output is
Vc ( t ) =
K PD Vref V fb
2
[
cos (ω ref − ω fb )t + (θ ref −θ fb )]
When ω ref = ω fb

K PD Vref V fb
Vc ( t ) = cos(θ ref − θ fb )
2
When the frequency is equalized, the loop filter output only
depends on the phase error.
K PD Vref V fb
Vc ( t ) = cosθ e
2
Where cosθ e is phase error, and equal to cos(θ ref − θ fb )
Then, the frequency of a voltage controlled oscillator (VCO) is
varied with the voltage Vc(t), the phase error.
The modified output frequency Vout(t) is divided by N times by
frequency divider.
With the feedback loop, the phase error between reference and
feedback frequency will be smaller and smaller. And, the PLL
circuit locks the reference frequency.
2. Charge Pump PLL Linear Analysis
The linear model is based on some specific conditions:
(1) Reference and feedback signals have same frequency.
(2) The phase error is within the detectable range of the PFD.

K PD KVCO F ( s )
The forward gain is G fwd ( s ) =
s
K PD KVCO F ( s )
The open loop gain is Gol ( s ) =
sN
The close loop transfer function is
θ ( s) G fwd ( s ) K PD KVCO F ( s )
H ( s ) = out = =
θ in ( s ) 1 + Gol ( s ) s + K PD KVCO F ( s )
N
If Gol ( s ) = 0dB and ∠ Gol ( s ) = − 180 , this equals to Gol ( s ) = − 1 .


In these conditions, the close loop transfer function equals zero

making the loop unstable.
Phase margin tells how far the design is from the instability,
usually goal being 45°.
The PLL transfer function is
  sCR2 + 1 
K PD KVCO  
θ out ( s )  C ( R + R )
2 
H ( s) = = 1

θ ref ( s ) s 2 + s PD
K + K VCO CR 2 + N
+
K PD KVCO
NC ( R1 + R2 ) NC ( R1 + R2 )
 Nω n2 

s 2ξ ω n −  + ω n2
K PD KVCO 
= 
s + 2ξ ω n s + ω n2
2

1 K PD KVC "O  N 
Where damping factor is ξ =  CR2 + 
2 NC ( R1 + R2 )  K PD KVCO 
K PD KVCO
And nature frequency is ωn =
NC ( R1 + R2 )

The Plot shows the second order system transfer response with
different damping factors.
Damping factor is a measure of stability and corresponds to the
phase margin of the high order system.
3dB peaking equals to 45 degrees of phase margin.
Due to the sample nature of the phase detector and the
frequency divider, the loop cannot be treated as a continuous
time system in it’s strictest sense.
In addition to that, all the loop components e.g. phase detector
and VCO are not exactly linear.
Still if the loop bandwidth is less than tenth of the phase detector
sampling frequency and all the components can be
approximated by linear functions, the continuous time Laplace
domain representation can be used.
If the loop BW gets closer to the phase detector sampling
frequency, the discrete time effects should be taken into account
in order to get accurate simulation results.
The discrete time z-domain analyses should be used.
The sampling introduces inherent sampling delay which tends to
decrease phase margins compared to continuous time analyzes.
Sampling also causes aliasing of the noise at the offset of
sampling frequency to the base-band frequencies.
3. Phase Noise Analysis
Ideal periodic signal has only an impulse at the fundamental
frequency.
In circuit implementation, the frequency spectrum consists of
impulse with skirts of energy.
Skirts = phase noise.
Psideband ( ω 0 + ∆ ω , 1Hz Bandwidth )
Definition of phase noise: L{ ∆ ω } = Pcarrier .
The input noise is shaped by low
pass characteristic of PLL.
Make the PLL bandwidth as narrow
as possible to reduce the input
contributed phase noise.
 Nω n2 
s 2ξ ω n −  + ω n2
θ out ( s ) K K
= N  PD VCO 

θ ref ( s ) s + 2ξ ω n s + ω n2
2

The VCO noise is shaped by

high pass characteristic of PLL.
Make the PLL bandwidth as
wide as possible to reduce the
VCO contributed phase noise.
sω n2 N
s2 +
θ out ( s ) K PD KVCO
= 2
θ vcon ( s ) s + 2ξ ω n s + ω n2
The dead zone is a region over which the PFD gain becomes
very small.
A peak-to-peak jitter approximately equal to the width of the
dead zone arises in the output signal.

4. Circuit Design and Simulation

The conventional PLL contains：
(1) Phase-Frequency Detector (PFD)
(2) Charge Pump (CP)
(3) Loop Filter (LF)
(4) Voltage-controlled Oscillator (VCO)
(5) Frequency Divider (FD)

（1）Phase-Frequency Detector (PED)

The phase frequency detector (PFD) circuit is used to detect the
phase/frequency difference between the reference and feedback
signals.
Generally, the dead zone effect of three-state PFD circuit may
cause the jitter problem.
However, the current mismatch between charge and discharge
paths of the four-state PFD circuit causes the jitter problem, too.
For this case, three-state PFD circuit is adopted.

Half circuit of the PFD is composed of a three-stage N-Rich

dynamic logic circuit which is a pre-charge type circuit.
The half circuit truth table is shown below.
Transistor Q1 is controlled by another half circuit and it’s used
to discharge the internal voltage between two dynamic logic
stages.
Without transistors Q1 and
Q2, two output signals will
go high at the same time,
when the frequency
difference between two input
signals is too large.
It cause the PFD circuit to
have the unwanted fourth
state.
Without decreased buffers,
the internal race problem
between two dynamic logics
make two output signals
generate a unneeded pulse
signal, when the frequency
difference between two input
signals is too small.

（2）Charge Pump (CP)

Charge pump circuit is used to control the input voltage of the
voltage-controlled oscillator.
It can be separated into two types:
(1) Current output charge pump circuit
(2) Voltage output charge pump circuit
Current output gives the better linearity than voltage output.
Charge pump circuit is composed of two current sources and
two switches.
When the reference frequency leads before the feedback one, the
pulse signal of the Up turns off the upper switch and charges the
output node Ve.
By the same way, when reference frequency lags after the
feedback one, the pulse signal of the Dn turns off the lower
switch and discharges the output node Ve.

Traditional MOS switch :

The clock feed-through effect makes the input control
voltage transition couple to capacitors of the loop filter
through its gate-drain or gate-source overlap capacitance.
Improved MOS switch:
(1) NMOS M0 and PMOS M1 are used to replace the traditional
switch formed by single MOS.
(2) The inverter I2 is used to generate an opposite signal and
PMOS M2 and NMOS M3 are used to balance the timing
delay of the inverter I2.
(3) Furthermore, inverters I0, I1, I3 and are used to stretch the
 pulse width of the input signal.

（3）Loop Filter (LP)

PLL circuit use the low pass filter to filter out the high
frequency component of phase error signal Ve and noise.
For different applications, low pass filter can be
(1) Active-lag filter
(2) Passive-loop filter
(3) Active PI filter
(4) Switch capacitor
For power and noise consideration, passive loop filter is used as
the loop filter.

If only a capacitor is used as the loop filter, the following loop

transfer function is obtained.
The PLL has become an unstable system, because there are two
poles on the imaginary axes.
The damping factor is set to zero.
Any excitation input to the system will result in a steady “phase
oscillation” with a frequency equal to the natural frequency of
the system.
θ ( s) K PD KVCO C1
H ( s ) = out = Fig. (a)
θ ref ( s ) s 2 + K PD KVCO
NC1
In order to stabilize the PLL system, a zero is inserted into the
loop filter by a series-wound resistor.
With the inserted resistor, the loop’s pole is moved from the
imaginary axis to the left plane.
The PLL system has become a stable
system.

 1 
K PD KVCO R s + 
θ out ( s )  RC1 
H ( s) = = Fig. (b)
θ ref ( s ) s 2 + s K PD KVCO R + K PD KVCO
N NC1

However, in circuit implementation, the voltage ripple caused by

continued charge and discharge of the CP circuit might induce a
lot of noise to PLL system.
In order to suppress the voltage ripple, another capacitor is
inserted to form a two-order loop filter.
With the two-order loop filter, the PLL system can be more
stable and have less noise.
In generally, capacitor C1 is 10 times the capacitor C2 .
sC1R1 + 1
H ( s) = Fig. (c)
s( sC1C2 R1 + C1C2 )

（4）Voltage Controlled Oscillater (VCO)

The circuit is composed of three basic subblocks:
(1) symmetric load.
(2) self-biased replica-feedback current source biased circuit.
(3) Differential_to_single circuit.

This architecture is a fully

differential source coupling Vdd
circuit, and the two inputs
are the gates of source
coupling nmos .
In order not to affect the Vbp
Vo- Vo+
bias current of the nmos
current source from the Vi+ Vi-
power and the substrate’s
voltage, the bias of the gate
always keep on redressing Vbn
and let the time delay of the
delay cell be fixed.

Symmetric loading structure forms by parallel two same size

pmos, one is a diode connected pmos and another pmos which
has a fixed bias.
In theory, symmetric loading structure need a linear I-V
characteristic curve. Although this structure is not linear, but the
voltage swing of the two loading nodes haves a middle
symmetry characteristic . It also has a great noise against ability
when in the small signal common-mode voltage noise condition
.

The goals which the Vd

d
bias circuit need to Vctrl
get are two: one is
provide a correct
working swing
limit; the other one
can tune nmos
+
Vbn
_

Diff. Amplifier Half-Buffer Replica

current source’s bias at random, and let the current value fix and
not easy to be affected when current source varying.
This architecture includes a differential amplifier and a half-
buffer replica circuit, and what the half-buffer replica circuit’s
goal is to get the signal which varies with the delay cells at the
same time.

In order to avoid the condition all transistors have no current ,we

need a Start-up circuit to control it.
Control voltage buffer can not only let the loop filter’s capacitor
to be easy to control, but also can decrease the interference
which external noise make to Vctrl when routing

Because vco’s output waves are not full swing , the circuit can
not drive the divider circuit. For this reason, we need
differential_to_single circuit. This circuit can make the output
waves to become the full swing waves.
（5）Frequency Divider (FD)
Frequency divider can be used to change the input frequency
range, increase the signal integrity, or multiply the input
frequency.
For different applications, frequency divider may use the
(1) Integer-N structure
(2) Fractional-N structure
Fractional-N structure is harder to be implemented than integer-
N structure in PLL, because it needs the additional
compensation circuit to attenuate the fractional sideband effect.

In this application, the integer-N structure is used and the divisor

N is equal to 16.
It is implemented by 4 D-type flip-flop (DFF) circuits.
For the consideration of high operating speed and simple circuit
structure, nine-transistor TSPC DFF of Yuan and Svensson is
used in the frequency divider.

（6）Circuit Simulation
When PLL circuit is locked, feedback signal Fb_F is equal to the
input reference signal Ref_F.
Reference frequency is 25MHz.

When input frequency is equal to 25MHz, PLL lock time is

about 8us.
Output frequency Out_F is 16 times the input reference
frequency Ref_f.

5. Layout and Post-Layout Simulation

Layout skills:
PFD: Symmetry
CP: Symmetry, Guard ring
VCO: Guard ring
System: Power noise, Power regulated capacitance
（1）PED and CP layout
PFD circuit has a symmetric circuit structure.
Symmetric layout can be easily implemented by copying and
mirroring the half circuit.

Asymmetry layout may increases the dead-zone effect of the

PFD circuit.
Charge pump circuit is composed of
(1) Current mirrors and switches
(2) Bias circuit

Symmetric layout can be easily implemented by copying and

mirroring the half circuit.

Bias circuit needs a guard ring to isolate the external digital

noisy signal.

Symmetric layout and guard ring protection make charge pump

circuit have a better performance.

Asymmetry and none guard ring layout structures increase the

PLL clock jitter.
A fixed height of layout cells make a better floor plan.

Asymmetric layout increase the wire length and the parasitical

capacitance (wire loading).

（2）VCO layout
VCO circuit is composed of
(1) Symmetric load
(2) Self-biased replica-feedback current source biased circuit.
(DC bias signal)
Bias circuit needs a analog guard ring to isolate the external
digital noisy signal.

Symmetric load is a high frequency circuit component.

Bias circuit needs a digital guard ring to isolate the internal
digital noisy signal.
The bias and high frequency circuit must be placed as far as
possible.
Analog and digital guard ring must be connect to different
power signal.

（3）System layout
Power noise:
(1) Separate analong power and digital powr.
(2) Separate device power and gurading ring power.
(3) Use of multiple bond pads and bond wires on each supply
net to reduce inductance.
Power regulated capacitor:
(1) Place the power regulated capacitor to separate the analog
and digital circuit.
(2) Place the power regulated capacitor to separate the adjacent
circuit.
(3) MOS capacitor has the highest area efficiency.
（4）Post-layout simulation
When PLL circuit is locked, feedback signal Fb_F is equal to the
input reference signal Ref_F.
Reference frequency is 25MHz.

When input frequency is equal to 25MHz, PLL lock time is

about 2.5us.

Output frequency Out_F is 16 times the input reference

frequency Ref_f.
6. Chip Measurements
7. Conclusion
Careful layout and correct layout skills increase the chip yield.
Different circuit structure needs the different layout skills.
Effective communication and management speed up the chip
layout time.
Professional electrical consideration increase the circuit
performance.

（1）PED netlist
PED
.SUBCKT pfd Ext Int dn up
*.PININFO Ext:I Int:I dn:O up:O
MM28 dn net7 vssd! vssd! nch W=1u L=250n M=1
MM25 net7 net38 vssd! vssd! nch W=1u L=300n M=1
MM22 up net16 vssd! vssd! nch W=1u L=250n M=1
MM21 net16 net35 vssd! vssd! nch W=1u L=300n M=1
MM16 net19 Ext net22 vssd! nch W=1u L=250n M=1
MM15 net22 Int vssd! vssd! nch W=1u L=250n M=1
MM14 net25 Int net28 vssd! nch W=2u L=250n M=1
MM13 net28 net19 vssd! vssd! nch W=2u L=250n M=1
MM12 net38 Int net34 vssd! nch W=2u L=250n M=1
MM11 net34 net25 vssd! vssd! nch W=2u L=250n M=1
MM10 net19 net35 vssd! vssd! nch W=1u L=250n M=1
MM9 net58 net38 vssd! vssd! nch W=1u L=250n M=1
MM8 net43 net52 vssd! vssd! nch W=2u L=250n M=1
MM7 net35 Ext net43 vssd! nch W=2u L=250n M=1
MM6 net49 net58 vssd! vssd! nch W=2u L=250n M=1
MM5 net52 Ext net49 vssd! nch W=2u L=250n M=1
MM4 net55 Ext vssd! vssd! nch W=1u L=250n M=1
MM3 net58 Int net55 vssd! nch W=1u L=250n M=1
MM27 net7 net38 vddd! vddd! pch W=3u L=250n M=1
MM26 dn net7 vddd! vddd! pch W=2.9u L=250n M=1
MM23 up net16 vddd! vddd! pch W=2.9u L=250n M=1
MM20 net16 net35 vddd! vddd! pch W=3u L=250n M=1
MM19 net19 Int vddd! vddd! pch W=3u L=250n M=1
MM18 net25 net19 vddd! vddd! pch W=3u L=250n M=1
MM17 net38 net25 vddd! vddd! pch W=6u L=250n M=1
MM2 net35 net52 vddd! vddd! pch W=6u L=250n M=1
MM1 net52 net58 vddd! vddd! pch W=3u L=250n M=1
MM0 net58 Ext vddd! vddd! pch W=3u L=250n M=1
.ENDS

（2）CP netlist
CP---switches
SUBCKT inv A Y
*.PININFO A:I Y:O
MM1 Y A vssd! vssd! nch W=1u L=250n M=1
MM0 Y A vddd! vddd! pch W=3u L=250n M=1
.ENDS
.SUBCKT p_switch in sw0 sw1
*.PININFO in:I sw0:I sw1:O
XI1 net19 net17 / inv
XI0 in net19 / inv
MM3 sw0 net17 sw1 vssd! nch W=8u L=250n M=1
MM2 net19 vddd! net8 vssd! nch W=1.2u L=250n M=1
MM1 net8 vssd! net19 vddd! pch W=1.2u L=250n M=1
MM0 sw1 net8 sw0 vddd! pch W=8u L=250n M=1
.ENDS

CP
.SUBCKT charge_pump down out up
*.PININFO down:I up:I out:O
XI1 down out net24 / p_switch
XI0 up net7 out / p_switch
MM0 vdda! vdda! net13 vssa! nch W=5u L=500n M=2
MM1 net13 net13 net18 vssa! nch W=5u L=500n M=2
MM2 net18 net18 vssa! vssa! nch W=3.6u L=500n M=1
MM3 net21 net18 vssa! vssa! nch W=3.6u L=500n M=1
MM6 net24 net18 vssd! vssd! nch W=4.5u L=500n M=1
MM4 net7 net21 vddd! vddd! pch W=4.8u L=500n M=1
MM5 net21 net21 vdda! vdda! pch W=3.6u L=500n M=2
.ENDS

（3）LF netlist
LF
.SUBCKT loop_filter Vc
*.PININFO Vc:B
CC1 Vc vss! 5p $[CP]
CC2 net17 vss! 53p $[CP]
RR0 Vc net17 4K $[RP]
.ENDS

（4）VCO netlist
VCO---bias circuit
.SUBCKT bias4 vbn vbp vc
MM18 net9 vbn vss! vss! nch W=8u L=800.0n M=1
MM17 net12 vbn vss! vss! nch W=8u L=800.0n M=1
MM16 vbp vdd! net9 vss! nch W=4u L=800.0n M=1
MM15 net46 vdd! net12 vss! nch W=4u L=800.0n M=1
MM14 net19 net19 vss! vss! nch W=8u L=800.0n M=1
MM13 vbn net19 vss! vss! nch W=8u L=800.0n M=1
MM12 net30 vbn vss! vss! nch W=8u L=800.0n M=1
MM11 net30 net6 vss! vss! nch W=8u L=800.0n M=1
MM10 net6 vbn vss! vss! nch W=600.0n L=800.0n M=1
MM9 net33 vdd! net30 vss! nch W=8u L=800.0n M=1
MM8 vbp vbp vdd! vdd! pch W=3u L=800.0n M=1
MM7 vbp vbp vdd! vdd! pch W=3u L=800.0n M=1
MM6 net46 net46 vdd! vdd! pch W=3u L=800.0n M=1
MM5 net46 vc vdd! vdd! pch W=3u L=800.0n M=1
MM4 net19 net46 net50 vdd! pch W=3u L=800.0n M=3
MM3 vbn vc net50 vdd! pch W=3u L=800.0n M=1
MM2 net50 net33 vdd! vdd! pch W=3u L=800.0n M=1
MM1 net33 net33 vdd! vdd! pch W=3u L=800.0n M=1
MM0 net6 vss! vdd! vdd! pch W=1.8u L=8u M=1
.ENDS

VCO---symmetric load
.SUBCKT vcocell vbn vbp vim vip vom vop
*.PININFO vbn:I vbp:I vim:I vip:I vom:O vop:O
MM6 net5 vbn vss! vss! nch W=8u L=800.0n M=1
MM5 vop vim net5 vss! nch W=4u L=800.0n M=1
MM4 vom vip net5 vss! nch W=4u L=800.0n M=1
MM3 vop vop vdd! vdd! pch W=3u L=800.0n M=1
MM2 vom vbp vdd! vdd! pch W=3u L=800.0n M=1
MM1 vop vbp vdd! vdd! pch W=3u L=800.0n M=1
MM0 vom vom vdd! vdd! pch W=3u L=800.0n M=1
.ENDS

VCO---differential to single circuit

.SUBCKT difftosingle out vbn vom vop
*.PININFO vbn:I vom:I vop:I out:O
MM13 net27 vbn vss! vss! nch W=580.00n L=500.00n M=1
MM12 net21 vbn vss! vss! nch W=580.00n L=500.00n M=1
MM11 net13 vop net21 vss! nch W=580.00n L=500.00n M=1
MM10 out net19 vss! vss! nch W=580.00n L=500.00n M=1
MM9 net19 net19 vss! vss! nch W=580.00n L=500.00n M=1
MM8 net22 vom net21 vss! nch W=580.00n L=500.00n M=1
MM7 net25 vom net27 vss! nch W=580.00n L=500.00n M=1
MM6 net28 vop net27 vss! nch W=580.00n L=500.00n M=1
MM5 out net13 vdd! vdd! pch W=750.00n L=500.00n M=1
MM4 net19 net25 vdd! vdd! pch W=750.00n L=500.00n M=1
MM3 net13 net22 vdd! vdd! pch W=750.00n L=500.00n M=1
MM2 net28 net28 vdd! vdd! pch W=750.00n L=500.00n M=1
MM1 net25 net28 vdd! vdd! pch W=750.00n L=500.00n M=1
MM0 net22 net22 vdd! vdd! pch W=750.00n L=500.00n M=1
.ENDS

VCO---buffer
.SUBCKT buffer input output
*.PININFO input:I output:O
MM3 output net8 vss! vss! nch W=580.00n L=250.00n M=3
MM2 net8 input vss! vss! nch W=580.00n L=250.00n M=1
MM1 output net8 vdd! vdd! pch W=900.00n L=250.00n M=3
MM0 net8 input vdd! vdd! pch W=900.00n L=250.00n M=1
.ENDS

VCO
.SUBCKT diffvco_final vin vout
*.PININFO vin:I vout:O
XI2 net8 net35 net28 net27 / difftosingle
XI1 net35 net34 vin / bias4
XI0 net35 net34 net19 net20 net28 net27 / vcocell
XI6 net35 net34 net25 net26 net20 net19 / vcocell
XI5 net35 net34 net31 net32 net26 net25 / vcocell
XI4 net35 net34 net28 net27 net32 net31 / vcocell
XI3 net8 vout / buffer
.ENDS

（5）FD netlist
FD
.SUBCKT DFF CLK D Q Qbar
MM10 Q Qbar vddd! vddd! pch W=1.5u L=250.00n
MM0 net9 D vddd! vddd! pch W=3u L=250.00n
MM1 net25 CLK net9 vddd! pch W=3u L=250.00n
MM8 Qbar net31 vddd! vddd! pch W=1.5u L=250.00n
MM5 net31 CLK vddd! vddd! pch W=1.5u L=250.00n
MM9 Q Qbar vssd! vssd! nch W=600.0n L=250.00n
MM2 net25 D vssd! vssd! nch W=600.0n L=250.00n
MM3 net28 CLK vssd! vssd! nch W=1.2u L=250.00n
MM4 net31 net25 net28 vssd! nch W=1.2u L=250.00n
MM6 Qbar CLK net37 vssd! nch W=1.2u L=250.00n
MM7 net37 net31 vssd! vssd! nch W=1.2u L=250.00n
.ic v(Qbar)=0
.ENDS
.SUBCKT frequency divider Fb_F Out_F
*.PININFO Out_F:I Fb_F:O
XDFF3 net028 net3 net020 net3 / DFF
XDFF4 net020 net025 Fb_F net025 / DFF
XDFF2 net032 net9 net028 net9 / DFF
XDFF1 Out_F net12 net032 net12 / DFF
.ENDS
（6）PLL netlist
PLL
SUBCKT PLL Out_F Ref_F
*.PININFO Ref_F:I Out_F:O
XI3 Vc Out_F / diffvco_final
XI4 Fb_F Out_F / frequency_divider
XI2 Vc / loop_filter
XI1 Dn Vc Up / charge_pump
XI0 Ref_F Fb_F Up Dn / pfd
.ENDS

（7）command file
Command fild
.lib 'mix025_1.l' tt
x1 Out_F Ref_F PLL
v1 Ref_F 0 pulse(0 2.5 0 0.1n 0.1n 19.9n 40n)
vdda vdda! 0 2.5
vssd vssd! 0 0
vddd vddd! 0 2.5
vssa vssa! 0 0
.option post
.ic v(x1.xi3.net28)=0 v(x1.xi3.net27)=2.5
.op
.tran 1n 20u
.end
Reference
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J. A. Grawford, Frequency Synthesizer Design Handbook. New
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