Printed Page: 1 of 2
Subject Code: KCA105
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0
MCA
(SEM I) THEORY EXAMINATION 2024-25
COMPUTER ORGANIZATION & ARCHITECTURE
TIME: 3 HRS M.MARKS: 100
Note: Attempt all Sections. In case of any missing data; choose suitably.
SECTION A
1. Attempt all questions in brief. 2 x 10 = 20
Q no. Question CO Level
a. Compare the various addressing modes used in processor organization. 1 K2, K3
b. How does bus width affect data transfer rates? 1 K2, K3
c. Analyze the process of floating-point division and describe the 2 K2, K4
challenges involved in implementing floating-point arithmetic in
hardware.
d. Explain the architecture of an ALU. 2 K2, K4
e. Apply the principles of instruction pipelining and identify hazards that 3 K3
can occur in a pipeline.
f. Apply the concept of micro-operations in program control. Explain how 3 K3
4
control signals govern their execution.
13
g. 90
Explain the trade-offs between speed, cost, and capacity. 4 K2, K3
2.
h. Analyze the impact of cache memory on processor performance. 4
_2
K2, K3
24
i. Explain Direct Memory Access. 5 K1, K2
P2
j. Explain synchronous and asynchronous serial communication. 5
5.
K1, K2
5D
.5
SECTION B
17
P2
2. Attempt any three of the following: 10 x 3 = 30
Q no. Question |1 CO Level
Q
a. Explain the role of functional units. How do these units interact using 1 K2,
AM
system buses, and what are the different types of bus architectures used K3
in modern computers?
2
b. Explain how floating-point numbers are represented, normalized, and 2 K2,
:0
rounded, and discuss the implications of precision errors in scientific K4
07
computations.
c. Apply the concept of Reduced Instruction Set Computer and Complex 3 K3
9:
Instruction Set Computer. Compare their architectural differences and
5
analyze their impact on performance and power consumption.
02
d. Explain the design and performance considerations of cache memory. 4 K2,
How do replacement policies affect cache performance? K3
-2
e. Analyze standard communication interfaces. How do these interfaces 5 K1,
ar
impact data transfer speed and system performance? K2
M
3-
SECTION C
|0
3. Attempt any one part of the following: 10 x 1 = 10
Q no. Question CO Level
a. Understand the concept of bus arbitration and compare different bus 1 K2, K3
arbitration techniques. How do these techniques impact system
performance in multiprocessor environments?
1|Page
QP25DP2_290 | 03-Mar-2025 9:07:02 AM | 117.55.242.134
Printed Page: 2 of 2
Subject Code: KCA105
0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0
MCA
(SEM I) THEORY EXAMINATION 2024-25
COMPUTER ORGANIZATION & ARCHITECTURE
TIME: 3 HRS M.MARKS: 100
b. Remember the different types of registers in a processor and explain 1 K2, K3
their specific functions. How does the use of general-purpose and
special-purpose registers improve computational efficiency?
4. Attempt any one part of the following: 10 x 1 = 10
Q no. Question CO Level
a. Explain the concept of look-ahead carry adders and analyze how they 2 K2, K4
improve addition speed compared to ripple carry adders. Explain their
working principle with an example.
b. Analyze Booth’s algorithm for signed operand multiplication. Provide a 2 K2, K4
step-by-step example of multiplying two signed binary numbers using
Booth’s algorithm and explain how it optimizes the multiplication
process.
4
5. Attempt any one part of the following: 10 x 1 = 10
13
Q no. Question 90 CO Level
2.
a. Apply the concept of instruction cycles and sub-cycles to explain the 3 K3
_2
24
complete execution of an instruction in a processor. How does
P2
instruction pipelining improve the efficiency of execution? Provide a
5.
detailed example.
5D
.5
b. Apply the differences between hardwired and microprogrammed 3 K3
17
control units. Design a simple microprogrammed control unit and
P2
explain how microinstructions are sequenced and executed.
|1
Q
6. Attempt any one part of the following: 10 x 1 = 10
AM
Q no. Question CO Level
a. Make use of the concept of virtual memory and explain how it is 4 K2, K3
2
implemented using paging and segmentation. Discuss the role of the
:0
Memory Management Unit in address translation.
07
b. Compare and contrast the differences between various types of 4 K2, K3
9:
secondary and auxiliary storage devices. How do advancements in
storage technology impact computing performance?
5
02
7. Attempt any one part of the following: 10 x 1 = 10
-2
Q no. Question CO Level
ar
a. Explain the different types of I/O interfaces and their role in computer 5 K1, K2
M
architecture. Explain how memory-mapped I/O differs from isolated I/O
3-
and discuss their advantages and disadvantages.
b. Analyze the different types of interrupts and their role in handling 5
|0
K1, K2
external and internal events in a computer system. How does interrupt
priority affect system performance?
2|Page
QP25DP2_290 | 03-Mar-2025 9:07:02 AM | 117.55.242.134
