GATE QUESTIONS

1. J-K Flip-Flop Analysis

In a J–K flip-flop, J=Q' and K=1. Starting from Q=0, determine the output sequence for 6 clock pulses.

2. Synchronous Counter Logic

Given a state table for a 2-bit synchronous up-counter using D flip-flops:

• Derive expressions for D1D_1D1 and D2D_2D2.

3. Free-Running Flip-Flops

A D flip-flop output feeds J and K of a J–K flip-flop, whose output returns to the D. Starting from QD=1, QJK=0 what is the output bit pattern?

4. Minimum Flip-Flop Count

For synchronous counter with sequence 0–1–0–2–0–3–0…, find minimum JK flip-flops required.

5. Counter Pulses Difference

8-bit up-counter from 172 (10101100₂) to 39 (00100111₂). How many pulses?

6. Master-Slave Input X

Design a two-flip-flop circuit toggling state. Given three clock cycles, what is the state of outputs P, Q?

7. RS Flip-Flop Oscillation

Which input sequence (00,11 / 01,10 / …) leads to oscillations using cross-coupled NAND latch?

8. Mod-12 Ring Counter

How many flip-flops in a ring counter with modulus 12?

9. RS Flip-Flop State

In RS flip-flop using NAND gates: what is output when S=0, R=0?

10. Throughput & Latency

Sequential circuit running at 1 GHz. What is throughput in Mbit/s and latency in ns?

11. Traffic Lights FSM

Cycle GREEN YELLOW RED durations: 70s, 5s, 75s. Clock with 5s period—how many flip-flops needed?

12. Latch Duty Cycle

Two-level latch: one latch clock delayed by 1/5 period. What’s duty cycle at output?

13. Power Dissipation in Flip-Flop Chain

Five D-FFs, 30% duty cycle. Gates ideal, resistor R=10 kΩ, supply 5 V. Calculate average power in resistor.

14. Mod-n Counter via Synchronous Clear

Given synchronous counter with clear input, find its modulus.

15. JK Flip-Flop Counter Identification

Circuit uses J-K flip-flops with active low reset. Which counter sequence is formed?

16. Cascade JK Counter Frequency Division

Five JK flip-flops in cascade, clock 1 MHz. What is frequency at the third flip-flop output?

17. Multiplexer Realized FF Function

Given a multiplexer circuit with unknown Boolean output, find which function is implemented

18. Race-around Condition Case

Given a flip-flop circuit, identify the race-around condition occurrence and explain.

19. Shift Register State Transitions

Given 4-bit register ABCD = 1101, in a right shift operation with serial input = 1, how many cycles to reach 1111?
 PROBLEMATIC QUESTIONS
Flip-Flop Conversion Problems (Very Common in Interviews)

1. Convert the following flip-flops (design with logic diagram and equations):

o D flip-flop to T flip-flop

o JK flip-flop to D flip-flop

o T flip-flop to JK flip-flop

o SR flip-flop to D flip-flop

2. Design a T flip-flop using only a D flip-flop and logic gates. Derive the expression.

3. Convert a JK flip-flop into a SR flip-flop. Explain the invalid condition handling.

Design-Based Sequential Circuit Questions

4. Design a 3-bit synchronous counter using T flip-flops. Show the state transitions.

5. Design a modulo-6 counter using JK flip-flops.

6. You are given a 4-bit binary up-counter. Modify it to count:

o Even numbers only

o Gray code sequence

7. Design a sequence detector that detects the pattern “1011” using a Mealy machine.

o Explain state transitions with overlapping allowed.

8. Design a lock system that unlocks only when the binary sequence 1101 is entered.

Tricky and Logical Thinking Questions

9. Why is race-around condition a problem in JK flip-flop and how is it resolved in master-slave JK flip-flop? Give a practical timing example.

10. You have a D flip-flop with setup time = 5ns and hold time = 2ns. The clock has skew of 1ns. Will data arriving 3ns before the clock be latched correctly?

11. A shift register contains the value 1011. After 4 right shifts with serial input 1, what will be the output?

12. Design a finite state machine to detect 1001 in a stream of bits and reset after detection. Draw state diagram and explain.

13. A circuit has a D flip-flop with input D = Q' (complement of output). What kind of circuit does this form?

• What’s the output pattern?

Timing, Glitch, and Edge-Case Questions

14. Explain what happens when setup and hold times are violated. Give an example with clock waveform and input.

15. If you connect the output of one flip-flop to the clock of another (asynchronous), what problems could arise?

16. A counter is not counting properly. After 8 cycles it resets. Identify the issue and suggest modifications.

17. You are designing a vending machine FSM. It should accept coins of 1, 2, and 5 rupees and dispense item at ₹7.

• Design FSM with minimum states.

State Minimization and FSM Conversion

18. Given a state table with 6 states, reduce it to minimum number of states using partitioning method.

19. Convert a Mealy machine to a Moore machine for a given function. Draw both diagrams.

20. Given a truth table of a sequential circuit with next state and output, determine the flip-flop type used.
 BASIC QUESTIONS
Basic Conceptual Questions

1. What is a sequential circuit? How is it different from a combinational circuit?

2. What are the types of sequential circuits?

o Synchronous vs Asynchronous

3. What is a flip-flop? How is it different from a latch?

4. Explain setup time and hold time. Why are they important?

5. What is propagation delay and clock skew in sequential circuits?

Flip-Flop Specific Questions

6. Explain the working of SR, JK, D, and T flip-flops.

7. What is the race-around condition in JK flip-flops? How is it avoided?

8. How can a D flip-flop be used as a frequency divider?

9. Design a T flip-flop using a D flip-flop.

10. What is edge triggering? How does it differ from level triggering?

State Machine and Analysis Questions

11. What is a finite state machine (FSM)?

12. Differentiate between Mealy and Moore machines.

13. How do you minimize states in a state machine?

14. Given a state diagram, write the corresponding state table and implement the logic.

15. What is the significance of the reset and preset inputs in flip-flops?

Practical and Design-Oriented Questions

16. Design a sequence detector for a binary sequence (e.g., 1011).

17. Implement a 4-bit synchronous counter using T flip-flops.

18. Design a modulo-5 counter using JK flip-flops.

19. Explain how shift registers work.

20. What are the types of shift registers? Where are they used?

TIPS

Always draw timing diagrams when explaining flip-flop behaviour.

Know how to convert between flip-flops (e.g., JK to D, D to T).

Practice K-map simplification for logic design questions.