CO Assignment

1. Write the key features of Von Neumann architecture of a computer.

Ans: The key features of Von Neumann architecture is

data and instructions are both stored as binary digits.

data and instructions are both stored in primary storage.

instructions are fetched from memory one at a time and in order (serially).

the processor decodes and executes an instruction, before cycling around to

fetch the next instruction.

the cycle continues until no more instructions are available.

2. What is Von Neumann Bottleneck?

Ans: The von Neumann bottleneck is the idea that computer system throughput is
limited due to the relative ability of processors compared to top rates of data transfer.
According to this description of computer architecture, a processor is idle for a
certain amount of time while memory is accessed which causes suboptimal
performance.

The von Neumann bottleneck is named after John von Neumann, a 20th century
mathematician, scientist and computer science pioneer who was also involved in the
Manhattan Project.

3. Write down the equation in terms of i-th carry-in/carry-out to detect

overflow of signed

2’s complement addition

Ans : Overflow occurs when:

1. Two negative numbers are added and an answer comes positive or

2. Two positive numbers are added and an answer comes as negative.

Overflow can be detected using 2 Bit Comparator just by checking Carry-in(C-in) and
Carry-Out(C-out) from MSB’s or n-1th bit. Consider N-Bit Addition of 2’s Complement

CO Assignment 1
 number.

Overflow will occur when the C-in and C-out are equals to each other. With the help
of below analysis, we can explain the above expression for an overflow.

In the first image, 0 shows the MSB of two numbers that indicate that they are
positive. If we get 1 as Carry-in, the result of MSB will also be 1, which means that
result is negative (Overflow). In this case, Carry-out will also be 0. It is proved that
the Carry-in and Carry-out are not equal to each other, hence overflow.
In the second image, 1 shows the MSB of two numbers that indicate that they are
negative. If we get 0 as Carry-in, the result of MSB will also be 0, which means that
result is positive (Overflow). In this case, Carry-out will also be 1. It is proved that the
Carry-in is not equal to Carry-out hence overflow.

CO Assignment 2
 With the help of above explanation, we can say that the overflow can be detected by
the C-in and C-out at MSB (Most Significant Bit), which is described as follows:

With the help of above XOR gate, we can easily detect the overflow.

So effectively the equation for overflow detection can be written as

Y = C-in(MSB) ⊕ C-out(MSB)

4. What is Biased Exponent? Give an example.

Ans : In floating-point arithmetic, a biased exponent is the result of adding some

constant (called the bias) to the exponent chosen to make the range of the exponent
nonnegative.

Following IEEE 754 single precision method, 2nd digit to 9th digit signifies the
exponent of the number. While storing the value of the floating point number, a
constant 127 (27 − 1) is added. Thus the stored exponent value of the floating point
number is a biased exponent.

5. What is a denormalized number and how it is represented in IEEE format?

Ans : In floating point number representation, normalized numbers are those where
the implicit leading binary digit is a 1. To reduce the loss of precision when an
underflow occurs, IEEE 754 includes the ability to represent fractions smaller than
are possible in the normalized representation, by making the implicit leading digit a
0. Such numbers are called denormalized numbers.

A denormal number is represented with a biased exponent of all 0 bits, which

represent an exponent of -126 in IEEE 754 single precision, or -1022 in IEEE 754 in
double precision

CO Assignment 3
 6. Write (15.625)10 into IEEE 64 bit format

Ans :

1. Converting the integer part of the number into binary

15 = (1111)2
2. Converting the fractional part to binary -

0.625 = (0.101)2
3. Positive number before normalization -

15.625 = (1111.101)2
4. Normalising the binary representation of the Number -

15.625 =
(1111.101)2 =
(1111.101)2 × 20 =
(1.111101)2 × 23
5. Up to this moment, there are the following elements that would feed into the 32
bit single precision IEEE 754 binary floating point representation:

Sign : 0 ( it is a positive number)

Exponent(unadjusted) : 3
Mantissa(notnormalized) : 1.111101
6. Adjusting the exponent -

Exponent(adjusted) =
Exponent(unadjusted) + (210 − 1)
3 + 1023 =
1026
7. Converting the adjusted exponent from decimal(base 10 ) to 11 bit binary-

1026 = (10000000010)2

CO Assignment 4
 8. Normalizing the mantissa by removing the leading( left most) bit, Adjusting the
length to 52 bits by adding necessary zeroes to the right

Manitssa(normalized) =
1111 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
The three elements that make up the number's 32 bit single precision IEEE 754
binary floating point representation:
Sign = 0
Exponent = 10000000010
Mantissa = 1111 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000

So the number 15.625 in IEEE 64 bit format would be 0 - 10000000010 - 1111

0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

7. Convert IEEE 32 bit format number (8C700000)16 into equivalent decimal

number.

Ans: (8C700000)16 = (10001100011100000000000000000000)2

Sign : 1 ( it is a negative number )

Exponent (biased): 0001 1000

Mantissa : 111 0000 0000 0000 0000 0000

So the significand of the number will be = (1.111)2 = (1.875)10

exponent will be = (00011000)2 − 127 = 24 − 127 = −103
The number = −1.875 × 2−103

9. Apply Booth’s to multiply two numbers (-12) and (-13). Assume the
multiplier and multiplicand to be of 5 bits

Ans :

Multiplicand(B) = (−12)10 = (10100)2 (2’s complement method )

CO Assignment 5
 Multiplier(Q) = (−13)10 = (10011)2 (2’s complement method)
In the below diagram the procedure of booth’s algorithm is shown

Here A refers to the accumulator whose initial value is (00000)2

Q0 refers to the least significant bit of the multiplier

Q−1 initial value is 0
As the multiplication are of 5 bits n(count ) initial value is 5
Initial values of

A = 00000
Q = 10011
Q−1 = 0

CO Assignment 6
 First Cycle : As Q0 is 1 and Q−1 is 0, we first do A = A − B and then do the
arithmetic shift of . A, Q, Q−1

After the end of the first cycle -

A = 00100
Q = 01001
Q−1 = 1
n(count) = 4
Second Cycle : As Q0 is 1 and Q−1 is 1, we do the arithmetic shift of . A, Q, Q−1

After the end of the second cycle -

A = 00011
Q = 00100
Q−1 = 1
n(count) = 3
Third Cycle : As Q0 is 0 and Q−1 is 1, we first do A = A + B and then do the
arithmetic shift of . A, Q, Q−1
After the end of the third cycle -

A = 11011
Q = 10010
Q−1 = 0
n(count) = 2
Fourth Cycle: As Q0 is 0 and Q−1 is 0, we do the arithmetic shift of . A, Q, Q−1

After the end of the fourth cycle

A = 11101
Q = 11001
Q−1 = 0
n(count) = 1
Fifth Cycle : As Q0 is 1 and Q−1 is 0, we first do A = A − B and then do the
arithmetic shift of . A, Q, Q−1

A = 00100
Q = 11100

CO Assignment 7
 Q−1 = 1
n(count) = 0
As the count becomes 0 the algorithm finishes. The answer stands =
(0010011100)2 = (156)10 which was our desired result.

11. Apply non restoring division to divide 11 by 3

Ans : Here is the flow chart of non restoring division

CO Assignment 8
CO Assignment 9
 let’s pick the step involved:

First the registers are initialized with corresponding values (Q = Dividend, M =

Divisor, A = 0, n = number of bits in dividend

Implementation of the above Algorithm is shown in tabular form

N M A Q Action

4 0011 0 1011 Start

00001 011_ Left shift AQ

11110 011_ A=A-M

3 11110 0110 Q[0]=0

11100 110_ Left shift AQ

11111 110_ A=A+M

2 11111 1100 Q[0]=0

11111 100_ Left Shift AQ

00010 100_ A=A+M

1 00010 1001 Q[0]=1

00101 001_ Left Shift AQ

00010 001_ A=A-M

0 00010 0011 Q[0] =1

So at last Quotient = 3 (Q)

Remainder = 2(A)

10. The need for restoring step in the above algorithm was avoided to get the
non restoring
division algorithm.What is the logic behind that?

Ans: In restoring division, you generally do a test subtraction for each digit step; if
the result is positive or zero, you note down a 1 as next digit of your quotient. non-
restoring method: you don’t do that – you keep negative remainder and a digit 1, and
basically correct things by a supplementary addition afterwards. By doing so you
reduce the time required and you correct if needed at last.

CO Assignment 10
 12. Explain the role of various registers, buses, accumulator etc. for
instruction fetch, decode and execute stages.
Ans: Roles of different registers, accumulators, and buses are explained in each
stage of fetch, decode, and execute cycle -

Program Counter(PC): It holds the address of the next instruction to be fetched and
executed. Program counter value is increased automatically in fetch phase.

Current Instruction Register(CIR) : It holds the current instruction being executed.

Memory Address Register(MAR) : This holds the address of the instruction to be

fetched or when if any instruction requires writing to the memory then it holds the
address of the memory to be written.
Memory Address Register(MDR) : This data holds the data which has been read in
fetch phase, or the data to be written if required in the execution phase.

Accumulator: It holds the data currently being worked on or the results of arithmetic
and logical operations .

System bus : It is used to read data from the memory or write data in the memory,
the data goes through system bus from processor to memory.

Internal Processor bus : It is used for transferring data within the processor
between different registers, accumulator, mdr, pc, etc.

13. Design a 4 bit carry look ahead Adder. Calculate the number of gate delays
to get outer most carry

Ans : Let’s consider two numbers A = A3 A2 A1 A0 and B = B3 B2 B1 B0

Let’s consider S0 as the sum of A0 , B0 , C0 ( the first carry-in)

S1 be the sum of A1 , B1 , C1 (the second carry in)

S2 be the sum of A2 , B2 , C2 (the third carry in)
S3 be the sum of A3 , B3 , C3 (the fourth carry in)
Let’s define two terms Carry Propagate and Carry generate:
Pi = Ai ⊕ Bi ith Carry propagate
Gi = Ai Bi ith Carry generate
Notice that both propagate and generate signals depend only on the input bits and
thus
will be valid after one gate delay.

CO Assignment 11
 The new expressions for the output sum and the carryout are given by:
Si = Pi ⊕ Ci−1
Ci+1 = Gi + Pi Ci
These equations show that a carry signal will be generated in two cases:

if both bits Ai and Bi are 1

if either Ai or Bi is 1 and the carry-in Ci is 1.

Let's apply these equations for a 4-bit adder:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 (G0 + P0 C0 ) = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 +
P3 P2 P1 P0 C0
These expressions show that C2 , C3 and C4 do not depend on its previous carry-in.
Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is
computed, C4
can reach steady state.

The logic gate of the following designed 4 bit carry look ahead adder will be -

CO Assignment 12
 Calculation of gate delay in 4 bit carry look ahead adder : As we know that once
C0 is available all the digits of Sum output will be found simultaneously. From the
above picture we can easily that at top sits Propagate generator, after that a carry
generator, and at last sum generator. So calculating maximum gate delay in each
level and adding them up will give us the desired delay for generting the sum .
At PG generator following two logics are executed
Pi = Ai ⊕ Bi
Gi = Ai Bi
The XOR gates takes 3 gate delay, AND gates take 2 gate delay

Therefore, Maximum delay in PG generator level = 3

At Carry generator level following logic is executed
Ci+1 = Gi + Pi Ci
delay for this operation = 2 gate level
Therefore, Maximum delay in Carry Generator level = 2
At last Sum generator executes the following logic -

Si = Pi ⊕ Ci−1
Therefore, Maximum delay in Sum generator level = 3
So total delay in 4 bit carry look ahead adder = (3 + 2 + 2) = 8 level

15. Discuss various addressing modes with examples.

Ans : Addressing modes are mechanism of specifying the location of the operands.
Various addressing modes are discussed below

Immediate Addressing : In this type of addressing, the operand data are the part of
instruction itself. No memory access is required.

Example - ADD #25 // ACC =ACC + 25

Direct Addressing : In this type of addressing, the instruction contains the field that
holds the memory address of the operand

Example - ADD R1, 20A6H // R1 = R1 + Mem[20A6]

Indirect Addressing : In this type of addressing, the instruction contains a field that
holds a memory location, which in turn holds the memory address of the operand.
Example - ADD R1, (20A6H ) // R1 = R1 + (Mem[20A6H])

CO Assignment 13
 Register Addressing : In this type of addressing, the operand is held in the register,
and instruction specifies the registration number
Example - ADD R1, R2, R3 // R1 = R2 + R3

Register Indirect Addressing : In this type of addressing, the instruction specifies

the register, which in turn holds the memory address where the operand is stored.

Example - ADD R1, (R5) // PC = R1 + Mem[R5]

Relative Addressing( PC Relative) : the instruction specifies an offset of
displacement, which is added to the Program Counter(PC) to get the effective
address of the operand.
Indexed Addressing : A special purpose register, or a general purpose register
which is used as index register in this addressing mode, the instruction specifies the
offset of displacement which is added to the index register to get the effective
address of the operand.
Example - LOAD R1, 1050(R3) // R1 =Mem[1050 + R3]

There are also other type of addressing modes, like stack addressing, base
addressing, auto-increment addressing, auto-decrement addressing.

16. Evaluate the arithmetic statement Y= (A+B) x C in zero, one, two and three
address
machines.

Ans : Evaluating this arithmetic statement in various addressing machines.

Zero Address Instruction : zero address instruction is used in stack-organized
computers. The following Program shows how Y = (A+B) * C will be written for stack
organized computer . (TOS stands for top of stack)
PUSH A TOS←A

PUSH B TOS ← B
ADD TOS ← A + B
PUSH C TOS ←C

MUL TOS ← (A+B) * C

POP Y M[Y] ← TOS
One Address Instruction : One-address instructions use an implied accumulator
(AC) register for all data manipulation. For multiplication and division there is a need

CO Assignment 14
 for a second register. However, here we will neglect the second and assume that the
AC contains the result of tall operations. The program to evaluate Y = (A+B) * C
LOAD A ACC← M[A]

LOAD B ACC← M[A] + M[B]

STORE T M[T] ←ACC

LOAD C ACC ←M[C]

MUL T ACC ← ACC* M[C]
STORE Y M[Y] ← ACC

Two Address Instruction : This is the most common type of Instruction. The
program to evaluate as follows :
MOV R1, A R1← M[A]

ADD R1, B. R1←R1+M[B]

MOV R2, C R2← M[C]

MUL R1, R2. R1← R1 * R2

MOV Y, R1 M[Y] ← R1
Three Address Instruction : Computers with three-address instruction formats can
use each address field to specify either a processor register or a memory operand.
The program to evaluate the expression Y = (A+B) * C -

ADD R1, A, B R1←M[A] + M[B]

MUL Y, R1, C M[Y] ← R1 * C

17. How many 256 X 4 RAM chips are needed to provide a memory capacity of
2048 bytes?
Show the corresponding interconnection diagram.

Ans : Required memory Capacity = 2048 bytes = 211 × 23 bits

number of 256 × 4 memory required will be 211 × 23 /28 × 22 = 16 × 2 = 32
16 (256 × 4) memory in 2 different columns will be required to provide the required
memory

The corresponding interconnection diagram will look like -

CO Assignment 15
 Here A11 .....A0 is the address of particular memory location
(I couldn’t find exact question, just replace 128 × 8 with 256 × 4, ignore the residual
above sentence and pretty obvious time stamp of youtube.)

18. Consider a 32 bit microprocessor that has an on-chip 32 KByte four-way

set associative
cache. Assume that the cache has a line size of four words( here a word
means 32 bit
).Show the various fields(tag,set,word offset) of this cache organization.

Ans : 32 Kb cache size

4 way set associative/
As the word addressing is used, so offset bits =2 for 4 words.

Line size = 4 * 32 bit = 16 bytes.

Number of sets = no of lines / p(ways)

Number of lines = cache size/line size = 215 /24 = 211

Number of sets = 211 /4 = 29

CO Assignment 16
 sets requires = 9 bits
tag requires = (32 -2 -9) = 21 bits
so the various fields of this cache organization will be -

tag(21 bits) sets(9 bits) block size(2 bits)

19. Where in the cache is the word from memory location AB5CDE7F mapped
in the above
cache organization.

Ans : Memory address = AB5CDE7F

its binary form 1010 1011 0101 1100 1101 1110 0111 1111
so it can be divided as 1010 1011 0101 1100 1101 1(tag) 110 0111 11(set), 11(word)

The set = 110 0111 11

so the given memory address will be mapped to 110111112 or to set number 415.

20. Given the following, determine size of the sub fields( in bits) in address for
direct mapping, associative and set associative cache mapping scheme.
We have 1 GB main memory and 16MB cache memory. The address space
of this processor is 1GB. The block size is 256Bytes. There are 8 blocks in
a cache set.

Ans : Size of the memory = 1GB = 230 bytes.

So the required number of bits to address this memory = 30

Line Size or Block Size = 256 Bytes = 28 bytes
word offset = 8 bits

Size of the cache = 16 MB = 16 * 220 bytes = 224 bytes

Direct Mapping :

Number of blocks = size of the cache / line size = 224 / 28 =216

number of bits required to for blocks = 16 bits
number of bits in tag = (30-16-8) = 8 bits

various fields in direct mapping will be -

CO Assignment 17
 tag(6 bits) Line Number(16 bits) block offset (8 bits)

Associative Mapping :
bits to represent tag = 30 -8 = 22

various fields of Associative mapping will be -

tag(22 bits) block offset(8 bits)

Set Associative Mapping :

number of ways in a set = 8

number of sets = 216 / 23 = 213

bits required to represent the sets = 13
bits required to represent the tag = (30 - 13 -8) = 9

various fields of set associative mapping will be

tag( 9 bits) sets( 13 bits) block offset ( 8 bits)

21. Explain ‘write through’ and ‘write back’ technique?

Ans:
Write Through : Write-through cache is a caching technique in which data is
simultaneously copied to higher level caches, backing storage or memory. It is
common in processor architectures that perform a write operation on cache and
backing stores at the same time.
Write-through cache helps increase read performance in memory access methods
because the requested data is already present in the cache and memory. In each
write-through operation, data that is brought into the cache is also written into the
backing store, which is the primary memory (RAM, in most cases).
Write-through cache also helps with data recovery, as the data in operation is written
to both cache and memory. It is nearly impossible to restore data from cache.
However, to an extent, modern operating systems (OS) have the ability to save an
instance of running memory.
Write Back : A caching method in which modifications to data in the cache aren’t
copied to the cache source until absolutely necessary. Write-back caching is

CO Assignment 18
 available on many microprocessors, including all Intel processors since the 80486.
With these microprocessors, data modifications (e.g., write operations) to data
stored in the L1 cache aren’t copied to main memory until absolutely necessary.
Write-back cache is designed to improve or reduce write operations from and to a
cache and its data source (RAM, in most cases). It enables control of the time and
the frequency at which data is written or copied into the source backing store.

22. Why do we need memory hierarchy, show the memory hierarchy diagram
indicating the speed and cost

Ans : Here is diagram that shows the speed and cost diagram of typical memory
hierarchy -

As shows from the above that faster memory have high cost and not feasible for
packing densely.
The tradeoff between speed and cost is found in memory hierarchy due to two
special features of computer programs - 1) Temporal Locality and 2) Spatial Locality
Temporal Locality : Recently executed instructions are likely to be executed again
very soon .

For example - computing factorial of a number n -

ADDI $t1,$zero,1
ADDI $t2,$zero,N
ADDI $t3,$zero,1

CO Assignment 19
 LOOP: MUL $t1,$t1,$t3
ADDI $t3,$t3,1
SGT $t4,$t3,$t2
BNEZ $t4,Loop

You can see that 4 lines of the loop are being repeatedly executed.
Spatial Locality : Instruction residing residing close to a recently executed
instruction are likely to be executed soon. For example to access the elements of
array sequentially

SUB $t1,$t1,$t1
ADDI $t2,$zero,N
ADDI $t3,$zero,1
ADDI $t5,$zero, 8

Loop: LW $t8,0,($t5)
ADD $t1,$t1,$t8
ADDI $t3,$t3,1
SGT $t4,$t3,$t2
BNEZ $t4,Loop

Looking at the assembly code, you can easily see that performance can be improved
by copying the array into cache memory.

24. Construct an 8-line common bus using suitable multiplexer

Ans : let’s say that there are 4 8 bit registers that need to be connected using a 8 line
common bus .

Number of multiplexers required = no of bits in each register = 8

Number of inputs in each multiplexer = no of registers = 4
The diagram for such a system is shown below -

CO Assignment 20
 The below table shows how different register can be selected for putting their data
into the common bus

Select Lines combination S1S0 Register Selected

00 Register A

01 Register B

10 Register C

11 Register D

25. Why SRAM is faster than DRAM

Ans : Dynamic RAM is the most common type of memory in use today. Inside a
DRAM chip, each memory cell holds one bit of information and is made up of two
parts: a transistor and a capacitor. A capacitor is like a small bucket that is able to
store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To
store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak.
In a matter of a few milliseconds, a full bucket becomes empty. Therefore, for
dynamic memory to work, either the CPU or the memory controller
has to come along and recharge all of the capacitors holding a 1 before they
discharge. To do this, the memory controller reads the memory and then writes it
right back. This is called dynamic refreshing of the memory. While this refreshing
occurs, no memory access can be done which causes delay.

Static RAM uses a completely different technology. In SRAM, a form of flip-flop holds
each bit of memory. A flip-flop for a memory cell takes four or six transistors along

CO Assignment 21
 with some wiring, but never has to be refreshed. Therefore there is no delay while
accessing memory. This makes SRAM significantly faster than DRAM.

26. What is instruction pipelining?

Ans : Instruction pipelining is a technique of organising the instructions for execution

in such a way that the execution of the current instruction is overlapped by the
execution of its subsequent instruction. Instruction pipelining improves the
performance of the processor by increasing its throughput i.e. number of instructions
per unit time.

27. Compare RISC and CISC.

Ans : The comparison between RISC and CISC is shown in the following table -

- RISC CISC

RISC stands for Reduced Instruction CISC stands for Complex Instruction Set
1
Set Computer Computer

RISC processors have simple

CISC processors have complex instructions
instructions taking about one clock
that take up multiple clock cycles for execution.
2 cycle. The average Clock cycles Per
The average Clock cycles Per Instruction of a
Instruction(CPI) of a RISC processor is
CISC processor is between 2 and 15
1.5

There are hardly any instructions that

3 Most of the instructions refer memory
refer memory.

RISC processors have a fixed CISC processors have variable instruction

4
instruction format format.

The instruction set is reduced i.e. it has

The instruction set has a variety of different
only few instructions in the instruction
5 instructions that can be used for complex
set. Many of these instructions are
operations.
very primitive.

RISC has fewer addressing modes CISC has many different addressing modes
and most of the instructions in the and can thus be used to represent higher level
6
instruction set have register to register programming language statements more
addressing mode. efficiently.

CO Assignment 22
 - RISC CISC

Complex addressing modes are CISC already supports complex addressing

7
synthesized using software. modes

8 Multiple register sets are present Only has a single register set

They are normally not pipelined or less

9 RISC processors are highly pipelined
pipelined

The complexity of RISC lies in the

10 The complexity lies in the micro program
compiler that executes the program.
The most common RISC
Examples of CISC processors are the
microprocessors are Alpha, ARC,
11 System/360, VAX, PDP-11, Motorola 68000
ARM, AVR, MIPS, PA-RISC, PIC,
family, AMD and Intel x86 CPUs.
Power Architecture, and SPARC.

28. What is interrupt? What are the differences between vectored and non-
vectored interrupt

Ans : An interrupt in computer architecture is a signal that requests the processor to

suspend its current execution and service the occurred interrupt.

A vectored interrupt is where the CPU actually knows the address of the interrupt
service routine in advance. All it needs is that the interrupting device sends its
unique vector through a data bus and through its I/O interface to the CPU. The CPU
takes this vector, checks an interrupt table in memory and then carries out the
correct ISR for that device. Therefore, the vectored interrupt allows the CPU to be
able to know that ISR to carry out in software (memory) .
A non–vectored interrupt is where the interrupting device never sends an interrupt
vector. An interrupt is received by the CPU and it jumps the program counter to a
fixed address in hardware. This is typically a hard coded ISR which is device
agnostic. The CPU crucially does not know which device caused the interrupt
without polling each O/I interface in a loop and checking the status register of each
I/O interface to find the one with status “interrupt created”.

29. Explain the basic DMA operation for transfer of data bytes between
memory and peripherals.

CO Assignment 23
 Ans : DMA stands for Direct Memory Access. All the memory access operations to
the peripherals or I/O devices happens through DMA controller. Below we have the
diagram of DMA controller which will help to explain DMA operation for data transfer
between memory and peripherals.

1. Whenever an I/O device wants to transfer the data to or from memory, it sends
the DMA request (DRQ) to the DMA controller. DMA controller accepts this DRQ
and asks the CPU to hold for a few clock cycles by sending it the Hold request
(HLD).

2. CPU receives the Hold request (HLD) from DMA controller and relinquishes the
bus and sends the Hold acknowledgement (HLDA) to DMA controller.

3. After receiving the Hold acknowledgement (HLDA), DMA controller

acknowledges I/O device (DACK) that the data transfer can be performed and
DMA controller takes the charge of the system bus and transfers the data to or
from memory.

4. When the data transfer is accomplished, the DMA raise an interrupt to let know
the processor that the task of data transfer is finished and the processor can

CO Assignment 24
 take control over the bus again and start processing where it has left.

30. How does interrupt initiated I/O work?

Ans : Interrupt I/O is a way of controlling input/output activity whereby a peripheral or

terminal that needs to make or receive a data transfer sends a signal. It is a complex
process where both softwares and hardwares play major role. In the below simplified
flow chart, this process is shown

Figure 2: Simple Interrupt Processing

1. A device driver initiates an I/O request on behalf of a process.

2. The device driver signals the I/O controller for the proper device, which initiates
the requested I/O.

3. The device signals the I/O controller that is ready to retrieve input, the output is
complete or that an error has been generated.

4. The CPU receives the interrupt signal on the interrupt-request line and transfer
control over the interrupt handler routine.

CO Assignment 25
 5. The interrupt handler determines the cause of the interrupt, performs the
necessary processing and executes a “return from” interrupt instruction.

6. The CPU returns to the execution state prior to the interrupt being signaled.

7. The CPU continues processing until the cycle begins again.

CO Assignment 26