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Numerical study on thermal impacts of different void patterns on

performance of chip-scale packaged power device

Article in Microelectronics Reliability · March 2012

DOI: 10.1016/j.microrel.2012.01.015

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Microelectronics Reliability 52 (2012) 1409–1419

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Numerical study on thermal impacts of different void patterns on performance

of chip-scale packaged power device
Kenny C. Otiaba ⇑, R.S. Bhatti, N.N. Ekere, S. Mallik, M.O. Alam, E.H. Amalu, M. Ekpu
Electronics Manufacturing Engineering Research Group, School of Engineering at Medway, University of Greenwich, Chatham Maritime, Kent ME4 4TB, UK

a r t i c l e i n f o a b s t r a c t

Article history: Chip scale package (CSP) technology offers promising solutions to package power device due to its rela-
Received 25 August 2011 tively good thermal performance among other factors. Solder thermal interface materials (STIMs) are
Received in revised form 30 January 2012 often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from
Accepted 30 January 2012
the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes
Available online 28 February 2012
heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily
in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by
out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids
have been extensively studied, but not much information exist on precise effects of different patterns
of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study,
three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical stud-
ies were carried out to characterise the thermal impacts of various voids configurations, voids depth and
voids location on package thermal resistance and chip junction temperature. The results show that for
equivalent voiding percentage, thermal resistance increases more for large coalesced void type in com-
parison to the small distributed voids configuration. In addition, the study suggests that void extending
through the entire thickness of solder layer and voids formed very close to the heat generating area of the
chip can significantly increase package thermal resistance and chip junction temperature. The findings of
this study indicate that void configurations, void depth and void location are vital parameters in evalu-
ating the thermal effects of voids.
Ó 2012 Elsevier Ltd. All rights reserved.

1. Introduction interconnections, heat removal from the device is primarily

through the backside of the silicon die (chip). Heat dissipating
The continuing trends on miniaturization of microelectronic units such as the heat spreader and/or heat sink are usually at-
packages coupled with the need to maximise their thermal perfor- tached to the backside of heat generating silicon die in an effort
mance require innovative package designs for power devices and to improve the surface area available for heat dissipation. The
modules. State-of-the-art integrated circuit (IC) packaging tech- bonding of the heat spreader/sink to the heat generating silicon
niques such as chip scale packaging (CSP) technology [1–5] offer die is often done using thermal interface materials (TIMs) in order
promising solution for packaging power electronics. This is as a re- to improve contact between the mating surfaces and thermal
sult of the technology’s inherent size advantage and relatively im- transfer across the interface by suppressing interstitial air-filled
proved thermal and electrical performance [1]. Indeed, there has gaps [9]. Therefore, the efficiency of heat transfer through TIMs is
been continuous progress in applying CSP to power electronics in critical in flip-chip CSP technology. Solder thermal interface mate-
recent years; among them are the MOSFET (metal oxide rials (STIMs) are preferred to their polymer-based counterparts
semiconductor field effect transistor) BGA packages from Fairchild because they offer higher thermal conductivities [10–13].
Semiconductor [6,7], FlipFET package from International Rectifier Nevertheless, voiding remains one of the major reliability con-
[8] and flip chip packages for power chips used in the IPEMs from cerns in the use of solder as TIMs [14]. The use of lead(Pb)-free sol-
centre for power electronics systems (CPES) [1]. ders has even escalated concerns emanating from solder voids due
In flip-chip CSP technology (Fig. 1), whilst the active side of the to its comparatively poor solderability [15] as studies have re-
silicon device is mounted onto a substrate, which can be attached ported the occurrence of voids in excess of 50% of solder joint vol-
to a printed circuit board (PCB) via ball grid array (BGA) solder ume in some Pb-free solders [16,17]. Voids reduce the effective
solder cross-section area available for heat transfer [18] and subse-
quently result in an increase in thermal resistance and chip peak
⇑ Corresponding author. Tel.: +44 (0) 1634 883873. temperature which can lead to temperature activated failure
E-mail address: [email protected] (K.C. Otiaba).

0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2012.01.015
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1410 K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419

lead-free solder voids to package thermal behaviour. The purpose

of the present study is to apply FEA to a systematic investigation
of the effects of different numerically controlled Pb-free solder void
patterns on the thermal performance of chip-level packaged power
device. The solder void patterns under investigation include dis-
tributed small voids and large single coalesced voids; shallow
voids and deep voids; corner/edge voids and centre voids. Thermal
characterisation of the impacts of these voids is crucial in assessing
Fig. 1. Schematic of flip-chip CSP configuration. the role of different void patterns in package thermal performance
and improving the overall reliability of semiconductor power
devices.
mechanisms. Unfortunately, voids formation are almost inevitable
in solder joints during manufacturing mainly due to the following
2. Thermal implications of voids
circumstances which are too complicated to control [19,20]:
The heat generated by the power dissipated above the void has
 The entrapment of gas bubbles formed by reactions among
to flow laterally around the void and hence obstruct thermal flow
materials and fluxes during the reflow soldering process.
as shown in Fig. 2. This impediment in heat flow could result in
 Poor wetting of solder due to defective or contaminated back-
overheating or other temperature activated failure mechanisms.
side metallisation of the silicon die or heat spreader/sink.
A practical example of voids induced failure case is shown in
Fig. 3; the occurrence of voids in the STIM have resulted in high
Voids can also occur or degrade during device operation as a re-
thermal resistance and subsequent melting of gold (Au) bonding
sult of solder-alloy fatigue due to cyclic thermo-mechanical stres-
wires found in another piece of our experimental works.
ses [15,16]. Owing to the different aspects of solder voids, they can
The rate of conductive heat transfer through a solder joint based
be classified into groups or types. For example [21],
on Fourier’s law is given as:

 From the solder wetting point of view, there could be shallow dT T1  T2

Q ¼ kA ¼ kA ð1Þ
voids (partially wetted) and deep voids (completely non-wetted dx L
voids). where Q is the heat transferred; k is the thermal conductivity; A is
 Based on void configuration, the formation of distributed small the cross sectional area of the solder joint; dT/dx is the temperature
voids and large single coalesced voids is feasible. gradient; L is the thickness of the solder; and T1  T2 is the temper-
 As regards void location, voids can form at the corner/edge or ature difference. It can be inferred from Eq. (1) that the heat trans-
centre of the STIM layer. ferred is directly proportional to the cross sectional area of the
solder layer. Defining resistance as the ratio of a driving potential
These various void types could have different level of impact on to the corresponding transfer rate, it follows from Eq. (1) that the
the thermal performance of an electronic package and thus, the heat spreading resistance for conduction in the solder joint can be
evaluation of the precise thermal effects of these different void pat- expressed as:
terns is essential. It should be noted that numerous studies on the
impacts of voids on thermal performance of various electronic T1  T2 L
h¼ ¼ ð2Þ
packages have been carried out by other researchers. For instance, Q kA
Chang et al. [15] investigated the effect of solder void size and loca- As a result of voids detrimental impact on heat conduction, pro-
tion on thermal resistance of power devices using three dimen- cess conditions are usually controlled carefully during manufactur-
sional (3-D) finite element modeling. Their result suggested an ing stage in order to keep void percentage at an acceptable level.
increase in chip temperature and thermal resistance with the in- This acceptable level is defined by the impact of voids on critical
crease in void percentages. Thermal resistance increased to 6.53% thermal parameters of an electronic package. A convenient param-
and 27.18% when the void percentages were 20% and 79%, respec- eter used in characterising and comparing the thermal effects of
tively. Fleischer et al. [22] used experimental and numerical meth- different cases of solder voids investigated in this paper is referred
ods to predict the relationship between void geometry and package to as h – JC (thermal resistance), defined as the ratio of the device
thermal resistance. Package thermal resistance was observed to in- temperature increase over ambient to the average power dissi-
crease as void percentage rises. Thermal resistance increased to pated in the device [24] (which is a measure of the ability of a
30% with 73% voiding for random voids. This was in contrast with package to dissipate heat via conduction from the surface of the
contiguous voids, with package thermal resistance increase of up die to the heat spreader surface) [25,26]. This is expressed as:
to 200% for 73% voiding. Biswal et al. [23] employed finite element
analysis (FEA) to assess the impact of solder voids on the overall
heat conduction of a high power module. It was found that solder
voids of relatively large radii impede heat conduction process to a
great extent than distributed voids. Zhu [21] used FEA to study
thermal impact of voids on a power device. The results showed
that large, coalesced and/or edge voids have greater impact on
the thermal resistance of the device than small, distributed voids.
It was also suggested that the temperature in the chip is much
more sensitive to a void extending across the chip width than a
void along the chip length.
Although the aforementioned studies provide vital information
on the relationship between package thermal performances and
voids in the STIM layer, more studies are needed for an in-depth
understanding of the precise contribution of different patterns of Fig. 2. Schematic of heat flow with void present in the die attach.
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K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419 1411

Fig. 3. Images of melted Au bonding wires due to overheating caused by voids in the STIM layer (A) X-ray image (B) SEM image.

T max  T min Fig. 5A and B, respectively. The maximum temperature was at-
h  JC ¼ ð3Þ
P tained at the centre of the chip where the heat source is located.
The thermal resistance and chip junction temperature were found
where Tmax is the maximum temperature at the chip junction;
to be about three times higher in the package without a heat sprea-
Tmin is the minimum temperature at the top surface of the heat
der compared to the package with heat spreader. It is apparent that
spreader; P is the power dissipation of the silicon chip. h – JC is an
improved thermal performance could be achieved through cou-
important thermal design parameter which can be used to deter-
pling a heat spreader to the backside of the die using a TIM [28].
mine the maximum allowable power or the chip peak temperature
This is because of the relatively lower thermal conductivity
under a given power for infinite heat sink [27].
through the front-side intermediate layers of the package particu-
larly the organic substrate and also limited number of solder
3. Finite element modeling of the thermal effects of voids bumps that make only a small fraction of contact area. A more de-
tailed work on the contribution of the solder balls under the chip
3.1. Thermal model (chip front-side) to heat dissipation has been reported in Ref. [3].
Hence, the present work considers only the backside of the package
The thermal models (shown in Fig. 4A and B for packages with with heat spreader (shown in Fig. 6) as the representative im-
and without heat spreader respectively) were created in ANSYS proved heat removal path under investigation. The focus is on ef-
13.0. Table 1 specifies the properties and dimensions of the differ- fects of die attach voids on thermal performance of the package.
ent components of the models. The heat (1 W) generating area (ac-
tive area) is applied as a heat flux on the top surface of the silicon
chip. The mesh consists of 1287,365 nodes and 438,204 elements. 3.1.1. Local modeling of voided solder die attach
Temperature distributions around the package with and without The local (simplified) model consists of a silicon die of the
heat spreader in natural convection (stagnant air) are shown in packaged semiconductor power device mounted upon a stack of

Fig. 4. Model structure for package (A) with heat spreader (B) without heat spreader.
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Table 1
Dimensions and properties of models in Fig. 4.

Parameter Chip Solder (Sn3.0Ag0.5Cu) Copper heat spreader Bumps Substrate Solder balls PCB
Length (mm) 5 5 9.59 – 9.59 – 9.59
Width (mm) 5 5 9.59 – 9.59 – 9.59
Thickness (mm) 0.3 0.04 1 – 0.4 – 1.6
Radius (mm) – – – 0.05 – 0.33 –
Pitch (mm) – – – 0.5 – 1.27 –
Standoff (mm) – – – 0.1 – –
Conductivity (W/mK) 120 50a 386 50a 0.3 50a 0.3
a
Ref. [15].

Fig. 5. Temperature distribution for package (A) with heat spreader (B) without heat spreader.

Fig. 6. Schematic of (a) full flip-chip CSP configuration (b) representative heat dissipation path (considered in the simulation).

Fig. 7. Simplified model structure.

supporting layers of STIM and copper heat spreader (IHS) as de- A geometric model without solder void, serving as control, was
picted in Fig. 7. The properties and dimensions of the different first developed and then modified by introducing large coalesced
components of the simplified model are listed in Table 2. void and small distributed voids accordingly. Large coalesced void
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K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419 1413

Table 2
Properties and dimensions of package assembly constituents.

Parameter Silicon die Solder (Sn3.0Ag0.5Cu) Copper heat spreader Void

Length (mm) 5 5 10 –
Width (mm) 5 5 10 –
Thickness (mm) 0.3 0.04 1 –
Radius (mm) – – – Varies as in Table 2.
Conductivity (W/mK) 120 50a 386 0.0261
a
Ref. [15].

Fig. 8. Examples of void configuration for 10% void area concentration with (A) showing evenly distributed small voids and (B) showing large single void.

takes the form of a single, large centrally located, circular void in the results obtained from the two different approaches. Thus,
while small distributed voids are modeled as evenly spaced circu- in order to reduce computational time, all cases of void models
lar voids with equivalent total void area as the large coalesced void. considered in this study are modeled as vacuum unless otherwise
The voiding area was calculated in such a way that one single coa- stated. It is important to know that even though the values ob-
lesced circular void would be equivalent to 25 small evenly distrib- tained through the approach employed in this study can be used
uted circular voids as delineated in Fig. 8 for 10% void area to predict and compare thermal response of a package due to the
concentration. The complete void configurations are shown in Ta- effects of different solder die-attach void patterns; they may not
ble 3. represent real quantitative values of thermal resistances due to
Considering that the MIL-STD-883D, method 2030 [29], for the the limitations of the approach. Factors, such as defects of materi-
ultrasonic inspection of die attach requires that the overall solder als, thermal contact/interfacial resistances and non-linearity in the
void area should not exceed 50% of the total joint area, the void materials including solder voids are not considered in the model-
area percentages (total area of voids/foot print of solder) 5%, 10%, ing. These factors are traded off for an in-depth comprehension
20%, 30%, 40%, 50% are chosen as levels of interests, and a 75% void of the impacts of different numerically controlled solder die-attach
selected as a worst case reference for this study. void patterns on package thermal performance. In line with the
method the simulations were carried out, this section will be pre-
3.1.2. Boundary conditions sented in four parts:
Overall boundary conditions for the simplified model like the
global model include a uniform heat flux Q (W/mm2) at the top
centre surface of the die. The heat (1 W) generating area (active 4.1. Effect of heat generating source area on thermal resistance values
area) is applied as a heat flux on the top surface of the silicon chip.
A fixed temperature (25 °C) is applied at the backside of the copper Considering that the active (heat source) area in a chip is often
heat spreader, representing an infinite heat sink. The other surfaces smaller than the total chip area, the influence of the heat (1 W)
are assumed to be adiabatic, i.e. no heat transfer by convection or generating area on thermal resistance is examined by varying the
radiation is considered. The heat is dissipated from the chip pri- active area in the chip from 10% to 100% for the two different void
marily by conduction through the supporting layers. Thus, only configurations (10% large and distributed voids area). The results
conduction mode of heat transfer is considered for all the void are shown in Fig. 10. It is clear from the results that h – JC decrease
cases (models) investigated in this paper. as the heat generating area increases. At each heat generating area,
The FEA program (ANSYS) subdivides the assembly into finite h – JC is higher for large coalesced void configuration than distrib-
elements (mesh) as shown in Fig. 9. The mesh consists of uted voids. As the heat generating area increases from 10% to 100%,
606,219 nodes and 120,564 elements, the results are checked for h – JC variation for the distributed voids configuration is 338%
mesh independence by comparison to models with 355,971 nodes which is higher than the 284% observed for large coalesced void
and 2909,666 nodes. Only ½ geometric symmetry of the assembly configuration. Thus, this study suggests that h – JC values may
is used in the analysis to reduce computational time and storage strongly depend on the heat (power) generating area of the chip.
space. It is of immense consequence to thermal engineers creating accu-
rate thermal models to understand that the effect of the chip
4. Results and discussions power on thermal resistance depends on the area of the chip gen-
erating the power. Considering that the heat generating area of the
The voids are firstly modeled as vacuum with no material prop- chip is much smaller than the total chip area in reality, a fixed heat
erty and then with the material property of air (0.0261 W/mK generating area of 2 mm  2 mm (40%) at the top centre surface of
thermal conductivity). There was no significant variation noticed the chip as shown in Fig. 7 is employed as a level of interest for
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Table 3
Large and distributed void configurations.

Model Configuration type Void radiusa (mm) Number of voids Void areab (mm2) Percentage of void area (V%)
No void 0 0 0 0

Large 0.631 1 1.25 5

Distributed 0.126 25 1.25 5

Large 0.892 1 2.49 10

Distributed 0.178 25 2.49 10

Large 1.261 1 4.99 20

Distributed 0.252 25 4.99 20

Large 1.544 1 7.49 30

Distributed 0.309 25 7.49 30

Large 1.784 1 10.00 40

Distributed 0.357 25 10.00 40

Large 1.995 1 12.50 50

Distributed 0.399 25 12.50 50

Large 2.442 1 18.74 75

Distributed 0.488 25 18.74 75

a

2
Approximated to three decimal places, the voids radii were calculated using formula: r 2 ¼ R5 , where r is the radius of each of the small distributed
voids; R is the radius of large single coalesced void.
b
Approximated to two decimal places, voids areas were calculated using formula: 25(pr2) = pR2.

Fig. 9. An example of a meshed model.

Fig. 10. Effect of heat generating area on h – JC.
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K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419 1415

maximum of 2.105 °C/W with 75% voids, and is well correlated with
a polynomial fit: h – JCD = 0.0001V2 + 0.0039 V + 1.1736. As regards
large void pattern, equivalent void percentage to that of distributed
voids results in a much higher increase in thermal resistance (h – JCL)
of 6.367 °C/W for 75% voiding. This is well correlated with a power
fit: h – JCL = 1.0042V0.4348. The results suggest that:

 h – JC increases as void percentage increases.

 Void configuration has a significant impact on the thermal per-
formance of a package.
 Large single void can greatly increase the thermal resistance of a
package compared to distributed voids of equivalent void
percentage.

Fig. 11. Variation of h – JC with different void configurations. More attention should therefore be given to large coalesced
voids when setting criteria for solder die-attach inspection. The
difference in the thermal spreading resistance behaviour of large
subsequent studies on effect of different void patterns on package coalesced and small distributed void configurations can be qualita-
thermal resistance. tively explained through the effects of heat flow. Three-
dimensional heat spreading comprises of both vertical flow and
4.2. Effect of void configurations – large vs. distributed lateral flow [30]. Therefore, there could be vertical heat flow resis-
tance from the heat generating source above the void, and a lateral
The voids are 0.04 mm deep in a 0.04 mm thick solder layer. The heat flow resistance from the region above the void to the sur-
results as presented in Fig. 11 show that for both void configura- rounding non-voided areas [22]. Void in solder die attach area re-
tions, h – JC rises as void percentage increases. Furthermore, as sults in a thermal spreading resistance as heat is forced to flow
illustrated in Figs. 12 and 13, the chip junction temperature also laterally around the void region. Additionally, heat flow in the ver-
rises as h – JC increase. The increase in chip junction temperature tical direction is restricted by the high thermal resistance through
due to 75% large coalesced void configuration is 451.7%, which is the void itself. For the same void percentage, lateral heat flow
more than the 74.6% observed for equivalent percentage (75%) of resistance is higher for large coalesced void configurations since
small distributed voids. heat flows laterally for a much shorter distance for the small dis-
There is a distinct difference in the thermal impact of large and tributed voids. Thus, large coalesced voids result in a much more
distributed voids as void percentage increases. The thermal resis- increase in the overall thermal resistance.
tance due to distributed void configurations (h – JCD) increases to a

Fig. 12. Thermal performance due to large voids.

Fig. 13. Thermal behaviour due to distributed voids.

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1416 K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419

4.2.1. Comparison with available experimental data

Experimental work on void configuration is scarcely available in
literature; this could be as a result of the complexities and interac-
tions associated with the many factors that affect void formation
during manufacturing and operating stages [31]. Hence, practically
controlling exact void configurations in a solder layer of about
0.04 mm thickness would be too complicated. No wonder, finite
element thermal analysis is often employed to isolate and charac-
terise the precise effects of the different void configurations as Fig. 15. Schematic showing (A–C) shallow void cases and (D) through void (not
even a mixture of these voids can form in one given solder joint drawn to scale).
in reality. To the authors’ knowledge, the only previous experimen-
tal work which allows the exact control of void configuration is Shallow voids can be formed at different vertical positions in
that of Fleischer et al. [22]. They studied the effect of large void the solder layer. This is because voids can be encapsulated in the
and distributed void experimentally by precisely etching square middle of solder layer due to entrapment of gas bubbles formed
void patterns directly onto the backside of the chip. They also car- by flux and other reactants during reflow soldering process. Fur-
ried out a numerical study to show that the thermal effect of voids thermore, there is a potential for voids to occur at the surface be-
located in the chip backside is equivalent to voids located in the die tween the solder layer and metallised silicon die or heat spreader
bond layer. Their results as depicted in Fig. 14 showed that large as a result of poor solder wetting due to defective backside metal-
contiguous void results in a much higher thermal resistance com- lisation or backside contamination during manufacturing. Hence,
pared to small distributed voids of equivalent voiding percentage. representative shallow voids are situated at different vertical posi-
This validates the finding of this study which suggests that small tions in the solder layer as shown in Fig. 15A–C. Through void
distributed voids account for less thermal resistance compared to (Fig. 15D) can occur as a result of degradation of shallow voids dur-
large coalesced void of the same voiding percentage. Nonetheless, ing device service and also due to completely non-wetting of solder
considering that in reality, solder voids do not follow a regular during manufacturing.
square-like shape but appear to progress roundly/chaotically, this Four cases of voids depth were simulated; the cases are referred
study employ a circular void approach precisely embedded in the to as top voids (case 1), middle voids (case 2), bottom voids (case 3)
solder die-attach layer. This approach is different from the square and through voids (case 4). Top voids are 0.02 mm deep located
void patterns precisely etched onto the backside of the chip in Ref. centrally in the upper part of the solder layer (0.04 mm thick) next
[22]. The strong qualitative agreement in the results from the two to the silicon die as illustrated in Fig. 15A. Middle voids are
different approaches suggests that void geometry may not have an 0.02 mm deep located centrally in the middle of 0.04 mm thick sol-
effect on thermal resistance. The quantitative discrepancies be- der layer as shown in Fig. 15B, leaving 0.01 mm thick of solder
tween the simulation results reported in this paper and the exper- layer on top and below the voids. Bottom voids are 0.02 mm deep
imental results in Ref. [22] are expected because the experimental located centrally in the lower part of the solder layer (0.04 mm
parameters including the material properties of lead-based solder thick) next to the copper heat spreader as delineated in Fig 15C.
attach layer studied by Fleischer et al. were different from the Through voids are 0.04 mm deep in a solder layer of 0.04 mm
parameters used in the present numerical study. thickness, creating a through solder void as shown in Fig. 15D.
The solder void models used for this study are modeled by filling
4.3. Effect of voids depth (shallow vs. deep voids) the void depths with material that has the thermal conductivity
of air (0.0261 W/mK). Other dimensions including the void area
Previous analysis suggests that large coalesced voids have more percentages are as earlier listed in the thermal model section for
adverse impact on the thermal resistance of package than distrib- large coalesced voids.
uted voids for equivalent voiding percentage. Hence, large coa- Fig. 16 shows h – JC rises as the void percentage increases for
lesced void was chosen for this study. the different void cases. The thermal performance predictions for

Fig. 14. Variation of thermal resistance with contiguous and distributed void percentage [22].
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K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419 1417

θ
θ

Fig. 16. h – JC performance for the different void cases.

Fig. 18. (A) shows solder layer without void (B) shows void location A (C) shows
void location B (D) shows void location C. (E) shows void location D (not drawn to
scale).

voids were used for this investigation because they account for
more profound effect on h – JC compared to shallow voids as evi-
dent from the previous finding.
While the heat source is kept constant as shown in Fig. 7, 10%
void was arbitrary located at different proximities (void location
A–C) to the heat generating source as depicted in Fig. 18B–D repre-
senting corner voids. Additionally, 10% void area was positioned
near the centre of the heat generating chip (Fig. 18E) representing
centre void (void location D). A depiction of solder layer without
Fig. 17. Variations of h – JC due to the different void cases.
void is presented in Fig. 18A to serve as a reference. The solder
voids are 0.04 mm deep in a solder layer of 0.04 mm thickness.
the different void cases are observed to be similar as the result data Other dimensions and properties remained as previously listed in
for each case is correlated with a power fit. Fig. 17 depicts the com- the thermal model section. While the heat distribution effects of
parison of thermal resistance due to the different void cases. the four different void locations are as shown in Fig. 19B–E,
Among the shallow void cases, top voids (closest to the heat Fig. 19A delineates the temperature contour at the back surface
source) relatively lead to the highest increase in h – JC. Further- of the chip when there is no void in the solder layer as a reference.
more, bottom voids (next to the heat spreader) which occur in sol- Visual inspection of the temperature contour at the back surface
der layer surface further from the heat generating chip result in of the silicon die reveals that voids significantly impede thermal
less values of h – JC compared to the middle voids. The variations path as delineated in Fig. 19B–E with reference to Fig. 19A. A strong
in h – JC due to the different shallow void cases with the same upshot of void location on die back surface temperature is evident.
thickness result from the vertical proximity of the voids to the heat One can easily differentiate the void location as it is qualitatively
generating source. With regards to the four void cases, as expected, reproduced on the back surface temperature contour of the chip.
thermal resistance is highest for through voids. A through void in
the solder layer replaces a relatively much higher thermal conduc-
tivity solder region with an extremely low thermal conductivity
void. Overall, there is no significant variation in h – JC as a result
of the four different void cases as h – JC only varies between 1%
and 5% as the voids percentages increase from 5% to 75%. Similar
result trend as regards the void cases was reported by Chen et al.
[27]. However, the work of Chen was limited to 10% void area. In
this study, the influence of void depth/position on thermal resis-
tance can be observed in detail from 5% to 75% void area, greatly
extending the current state of knowledge. This detailed informa-
tion particularly may be of assistance to thermal engineers espe-
cially with works [16,17] reporting the occurrence of voids in
excess of 50% of solder joint volume in some Pb-free solders.

4.4. Effect of void location (corner voids vs. centre void)

MIL-STD-883D, method 2030 [28], for the ultrasonic inspection

Fig. 19. Heat distribution effects on the back surface of the silicon chip (A) when
of die attach requires that a corner void should not be bigger than there is no void (B) as a result of void location A (C) shows hot spot as a result of
10% of the total void area. Hence, 10% large coalesced void area was void location B (D) shows hot spot as a result of void location C (E) shows hot spot
chosen for this study as a level of interest. Furthermore, through as a result of void location D (not drawn to scale).
 Author's personal copy

1418 K.C. Otiaba et al. / Microelectronics Reliability 52 (2012) 1409–1419

 Shallow voids formed in the solder die attach layer next to the
surface of the heat generating chip result in a relatively higher
h – JC than equivalent shallow voids present at other vertical
positions further from the heat generating chip. Nonetheless,
through-thickness void (voids extending through the whole sol-
der layer) in the same lateral position as the shallow voids is
accountable for the highest h – JC values.
 h – JC is highest for voids present near the center of the heat
source. A void at the edge (very far from the heat source) of
the solder die attach layer may not result in hot spot (represent-
ing the hottest spot at the chip back surface).
Fig. 20. Thermal effects of the four different void locations.

Acknowledgments

The authors acknowledge the support of EMERG and the School

of Engineering staff of University of Greenwich. Also, we would like
to thank Dr. Shefiu S. Zakariyah for his input in the research work
reported in parts in this paper.

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