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Module 2 CMOS Inverter Revision Notes

The CMOS inverter consists of an nMOS and pMOS transistor, providing efficient power consumption during switching. Key characteristics include voltage transfer curves, noise margins, and delay calculations, which are essential for reliable operation. Design considerations emphasize achieving symmetry in transistor parameters and managing power dissipation while accounting for the effects of voltage scaling on performance.

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18 views2 pages

Module 2 CMOS Inverter Revision Notes

The CMOS inverter consists of an nMOS and pMOS transistor, providing efficient power consumption during switching. Key characteristics include voltage transfer curves, noise margins, and delay calculations, which are essential for reliable operation. Design considerations emphasize achieving symmetry in transistor parameters and managing power dissipation while accounting for the effects of voltage scaling on performance.

Uploaded by

chethana8182
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CMOS Inverter Module 2 (Simplified Notes for Quick Revision)

1. CMOS Inverter Basics

- CMOS inverter uses one nMOS and one pMOS transistor in a complementary arrangement.

- For Vin = 0V pMOS ON, nMOS OFF Vout = VDD (Logic HIGH).

- For Vin = VDD nMOS ON, pMOS OFF Vout = 0V (Logic LOW).

- Power is consumed only during switching, making CMOS highly power efficient.

2. Voltage Transfer Characteristics (VTC)

- VTC plots Vout vs. Vin. It shows five distinct regions (A-E).

- Regions: A nMOS OFF, pMOS ON; E nMOS ON, pMOS OFF.

- Middle region: both transistors are ON defines the switching point.

- Sharp transition region ensures high noise immunity.

3. Noise Margins

- NMH = VOH - VIH, NML = VIL - VOL.

- These margins define tolerance against noise in logic HIGH and LOW.

- Higher noise margins mean more reliable operation.

4. Calculating VIL and VIH

- At VIL nMOS in saturation, pMOS in linear region.

- At VIH nMOS in linear, pMOS in saturation.

- Use KCL equations equating IDn and IDp, then solve with slope condition dVout/dVin = -1.

5. Switching Threshold (Vth)

- Defined where Vin = Vout.

- Both transistors operate in saturation.

- Vth = (VTn + VDD + |VTp|) / (1 + kR), where kR = kn/kp.

6. Delay in CMOS Inverters

- Delay arises due to charging/discharging of load capacitance.

- Propagation delay (tp) = (tpHL + tpLH) / 2.

- Use current equations for nMOS/pMOS and Cload to estimate delays.

7. Delay Calculation Example (Simplified)

- Given: Cload = 300fF, kn = 200A/V2, VDD = 3.3V, VTn = 0.6V.


- Use saturation/linear current equations to find tpHL and tpLH.

- Saturation: IDn = (1/2)kn(Vin - VTn)2.

- Linear: IDn = kn[(Vin - VTn)Vout - 0.5Vout2].

8. Design Considerations

- For symmetric inverter: VTn = |VTp| and kn = kp.

- Ensure switching threshold Vth = VDD/2 for ideal behavior.

- To achieve unity kR: (W/L)p = 2 (W/L)n, due to n 2p.

9. Power and Area Consideration

- CMOS has almost zero static power dissipation.

- Dynamic power: P = Cload VDD2 f (switching).

- Area increases due to pMOS and nMOS side-by-side layout and wells.

10. Effects of VDD Scaling

- Reducing VDD reduces power but affects noise margins and delay.

- Minimum VDD = VTn + |VTp| to ensure both transistors can operate.

- Below this limit, inverter enters hysteresis behavior due to incomplete switching.

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