PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
COURSE STRUCTURE & SYLLABUS M.Tech ECE
VLSI & Embedded System
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
L P C
I Year II Semester 3 0 3
Analog and Digital CMOS VLSI Design
Course objectives:
To teach fundamentals of CMOS Digital integrated circuit design such as
importance of Combinational MOS logic circuits, and Sequential MOS logic
circuits.
To teach the fundamentals of Dynamic logic circuits and basic semiconductor
memories which are the basics for the design of high performance digital
integrated circuits.
Basic design concepts, issues and trade offs involved in analog IC design are explored.
To learn about Design of CMOS Op Amps, Compensation of Op Amps, Design of
Two-Stage Op Amps, Power Supply Rejection Ratio of Two-Stage Op Amps,
Cascade Op Amps, Measurement Techniques of OP Amp.
Syllabus Contents:
Technology Scaling and Road map, Scaling issues, Standard 4 mask NMOS Fabrication process
Digital CMOS Design:
Unit 1: Review: Basic MOS structure and its static behavior, Quality metrics of a
digital design: Cost, Functionality, Robustness, Power, and Delay, Stick diagram
and Layout, Wire delay models. Inverter: Static CMOS inverter, Switching
threshold and noise margin concepts and their Evaluation, Dynamic behavior,
Power consumption.
Unit 2: Physical design flow: Floor planning, Placement, Routing, CTS, Power
analysis and IR drop estimation-static and dynamic, ESD protection-human body
model, Machine model.
Combinational logic: Static CMOS design, Logic effort, Rationed logic, Pass
transistor logic, Dynamic logic, Speed and power dissipation in dynamic logic,
Cascading dynamic gates, CMOS transmission gate logic.
Unit 3:Sequential logic: Static latches and registers, Bi-stability principle, MUX based latches,
Static SR flip-flops, Master-slave edge-triggered register, Dynamic latches and registers,
Concept of pipelining, Pulse registers, Non-bistable sequential circuit. Advanced
technologies: Giga-scale dilemma, Short channel effects, High–k, Metal Gate Technology,
FinFET, TFET etc.
Analog CMOS Design:
Unit 4: Single Stage Amplifier: CS stage with resistance load, Divide
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
connected load, Current source load, Triode load, CS stage with source
degeneration, Source follower, Common gate
stage, Cascade stage, Choice of device models. Differential Amplifiers: Basic difference
pair, Common mode response, Differential pair with MOS loads, Gilbert cell.
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
Unit 5: Passive and active current mirrors: Basic current mirrors, Cascade mirrors, Active
current mirrors. Frequency response of CS stage: Source follower, Common gate stage,
Cascade stage and difference pair, Noise. Operational amplifiers: One stage OPAMP,
Two stage OPAMP, Gain boosting, Common mode feedback, Slew rate, PSRR,
Compensation of 2 stage OPAMP
Text Books:
1. J P Rabaey, A P Chandrakasan, B Nikolic, “Digital Integrated circuits: A
design perspective”, Prentice Hall electronics and VLSI series, 2nd Edition.
2. Baker, Li, Boyce, “CMOS Circuit Design, Layout, and Simulation”, Wiley, 2nd Edition.
3. BehzadRazavi , “Design of Analog CMOS Integrated Circuits”, TMH, 2007.
Reference Books:
1. Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford, 3rd
Edition.
2. R J Baker, “CMOS circuit Design, Layout and Simulation”, IEEE Inc., 2008.
3. Kang, S. and Leblebici, Y., “CMOS Digital Integrated Circuits, Analysis and
Design”,TMH, 3rdEdition.
4. Pucknell, D.A. and Eshraghian, K., “Basic VLSI Design”, PHI, 3rd Edition.
Course Outcomes:
At the end of this course, students will be able to
Appreciate the trade-offs involved in analog integrated circuit design.
Understand and appreciate the importance of noise and distortion in analog circuits.
Analyze complex engineering problems critically in the domain of analog
IC design for conducting research.
Demonstrate advanced knowledge in Static and dynamic characteristics of
CMOS, Alternative CMOS Logics, Estimation of Delay and Power, Adders
Design.
Solve engineering problems for feasible and optimal solutions in the core area of digital
ICs.
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
L P C
I Year II Semester 3 0 3
REAL TIME OPERATING SYSTEMS
Course Objectives:
To Know the Basic Designs using an RTOS.
To Know the Functions and Types of RTOS for Embedded Systems.
To Analyze the issues in real time operating systems
To Study the Programming Concepts of RT Linux.
To Understand Applications Control by RT Linux System.
To Analyze the Operating System Software
UNIT I
Introduction to Real-Time Operating Systems - Defining an RTOS, The scheduler,
Kernel Objects and services, Key characteristics of an RTOS
Task- Defining a Task, Task States and Scheduling, Typical Task Operations, Typical Task
Structure, Synchronization, Communication and Concurrency
UNIT II
Semaphores - Defining Semaphores, Typical Semaphore Operations, Typical Semaphore Use
Message Queues - Defining Message Queues, Message Queue States, Message Queue
Content, Message Queue Storage, Typical Message Queue Operations, Typical Message
Queue Use, Pipes, Event Registers, Signals and condition Variables
UNIT III
Exceptions and Interrupts - Exceptions and Interrupts, Applications of Exceptions and
Interrupts, Closer look at exceptions and interrupts, processing general Exceptions, Nature
of Spurious Interrupts Timer and Timer Services - Real-Time clocks and System
Clocks, Programmable Interval Timers, Timer Interrupt Service Routines.
I/O Subsystems - I/O concepts, I/O subsystems
UNIT IV
Memory Management - Dynamic Memory Allocation in Embedded Systems, Fixed-Size
Memory management in Embedded Systems, Blocking VS. Non-Blocking Memory
Functions, Hardware Memory Management Units
Modularizing an application for concurrency- An outside-in approach to decompose
Applications, Guidelines and Recommendations for Identifying Concurrency, Schedulability
Analysis
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
UNIT V
Synchronization and Communication - Synchronization, Communication, Resource
Synchronization Methods, Critical section, Common practical design patterns, Specific
Solution Design Patterns, Common Design Problems - Resource Classification,
Deadlocks, Priority Inversion.
Text Books
1. Qing Li, Caroline Yao (2003), “Real-Time Concepts for Embedded Systems”, CMP
Books.
Reference Books
1. Albert Cheng, (2002), “Real-Time Systems: Scheduling, Analysis and
Verification”,Wile Interscience.
2. Hermann Kopetz, (1997), “Real-Time Systems: Design Principles for
Distributed Embedded Applications”, Kluwer.
3. Insup Lee, Joseph Leung, and Sang Son, (2008) “Handbook of Real-Time
Systems”Chapman an Hall.Krishna and Kang G Shin, (2001), “Real-Time Systems”,
McGraw Hill.
Course Outcomes
Upon the completion of the course student will be able to
Illustrate real time programming concepts.
Apply RTOS functions to implement embedded applications
Understand fundamentals of design consideration for embedded applications
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
SOC DESIGN
Unit 1:
ASIC: Overview of ASIC types, design strategies, CISC, RISC and NISC
approaches for SOC architectural issues and its impact on SoC design
methodologies, Application Specific Instruction Processor (ASIP) concepts.
Unit 2:
NISC: NISC Control Words methodology, NISC Applications and Advantages,
Architecture Description Languages (ADL) for design and verification of
Application Specific Instruction set Processors (ASIP), No-Instruction-Set-
computer (NISC)- design flow, modeling NISC architectures and systems, use of
Generic Netlist Representation - A formal language for specification, compilation
and synthesis of embedded processors.
Unit 3:
Simulation: Different simulation modes, behavioral, functional, static timing, gate level,
switch level, transistor/circuit simulation, design of verification vectors, Low power
FPGA, Reconfigurable systems, SoC related modeling of data path design and control
logic, Minimization of interconnects impact, clock tree design issues.
Unit 4:Low power SoC design / Digital system:
Design synergy, Low power system perspective- power gating, clock gating,
adaptive voltage scaling (AVS), Static voltage scaling, Dynamic clock
frequency and voltage scaling (DCFS), building block optimization, building
block memory, power down techniques, power consumption verification.
Unit 5 :Synthesis
Role and Concept of graph theory and its relevance to synthesizable constructs,
Walks, trails paths, connectivity, components, mapping/visualization, nodal
and admittance graph.
Technology independent and technology dependent approaches for synthesis,
optimization constraints, Synthesis report analysis Single core and Multi core
systems, dark silicon issues, HDL coding techniques for minimization of power
consumption, Fault tolerant designs
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
Text Books:
1. Hubert Kaeslin, “Digital Integrated Circuit Design: From VLSI
Architectures to CMOS Fabrication”, Cambridge University Press,
2008.
2. B. Al Hashimi, “System on chip-Next generation electronics”, The IET, 2006
Reference Books:
1. Rochit Rajsuman, “System-on- a-chip: Design and test”, Advantest America R & D
Center,2000
2. P Mishra and N Dutt, “Processor Description Languages”, Morgan Kaufmann, 2008
3. Michael J. Flynn and Wayne Luk, “Computer System Design: System-on-Chip”. Wiley
Course Outcomes:
At the end of the course, students will be able to:
Identify and formulate a given problem in the framework of SoC based design
approaches Design SoC based system for engineering applications
Realize impact of SoC on electronic design philosophy and Macro-electronics thereby
incline towards entrepreneurship & skill development.
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
L P C
I Year II Semester 3 0 3
Communication Busses and Interfaces
(Elective IV)
UNIT I
Serial Busses- Cables, Serial busses, serial versus parallel, Data and Control Signal- data frame, data
rate, features Limitations and applications of RS232, RS485, I2C , SPI
UNIT-II
CAN
ARCHITECTURE- ISO 11898-2, ISO 11898-3, Data Transmission- ID allocation, Bit timing,
Layers- Application layers, Object layer, Transfer layer, Physical layer, Frame formats-
Data frame, Remote frame, Error frame, Over load frame, Ack slot, Inter frame spacing,
Bit spacing, Applications.
UNIT-II
PCIe
Revision, Configuration space- configuration mechanism, Standardized registers, Bus
enumeration, Hardware and Software implementation, Hardware protocols,
Applications.
UNIT-IV
USB Transfer Types- Control transfers, Bulk transfer, Interrupt transfer, Isochronous transfer.
Enumeration- Device detection, Default state, Addressed state, Configured state,
enumeration sequencing. Descriptor types and contents- Device descriptor, configuration
descriptor, Interface descriptor, Endpoint descriptor, String descriptor. Device driver.
UNIT V
Data streaming Serial Communication Protocal- Serial Front Panel Data Port(SFPDP)
configurations, Flow control, serial FPDP transmission frames, fiber frames and copper
cable.
TEXTBOOKS
1. A Comprehensive Guide to controller Area Network – Wilfried Voss,
Copperhill Media Corporation, 2nd Ed., 2005.
2. Serial Port Complete-COM Ports, USB Virtual Com Portsand Ports for
Embedded Systems- Jan Axelson, Lakeview Research, 2nd Ed.,
PYDAH COLLEGE OF ENGINEERING (A)
Approved by AICTE & Affiliated to JNTU Kakinada
REFERENCES
1. USB Complete – Jan Axelson, Penram Publications.
2. PCI Express Technology – Mike Jackson, Ravi Budruk, Mindshare Press.
Course Outcomes:
At the end of the course, students will be able to:
Select a particular serial bus suitable for a particular application.
Develop APIs for configuration, reading and writing data onto serial bus.
Design and develop peripherals that can be interfaced to desired serial bus.
