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The document discusses the design and testing of state-of-the-art Systems on Chip (SoCs), focusing on core-based systems and the challenges associated with testing them. It highlights the importance of design reuse, standardization initiatives like IEEE P1500, and the implementation of Network-on-Chip (NoC) for efficient communication and testing access. Additionally, it addresses the need for increased test parallelism and the potential of using microprocessors as test sources to minimize test time and area overhead.

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0% found this document useful (0 votes)

6 views86 pages

Clase 8

Uploaded by

benderbundy

We take content rights seriously. If you suspect this is your content, claim it here.

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Download as PDF, TXT or read online on Scribd

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Testing State-of-the-art

Systems on Chip

Marcelo Lubaszewski

Universidade Federal do Rio Grande do Sul

Departamento de Engenharia Elétrica
Porto Alegre - RS - Brasil
e-mail: [email protected]
Electronic Systems Design

• High level specification

• Mixed-technologies
– HW and SW
– optical, analogue, digital, micro-mechanical

• Design reuse and automation

• Design for test
Design Reuse
hard
Soft
ENTITY MUX _2
(
in_1 : IN bit_vector(m downto 0);
in_2 : IN bit_vector(m downto 0);
selector : IN bit;
out : out bit_vector(m downto 0)
);
...

Firm
Core-Based Systems

System
A/D
Analogue sensor Converters
(hard) (hard)

DMA μprocessor
(firm) (soft)
Core-Based Systems

System
A/D CONTROL
Analogue sensor Converters
(hard) (hard) Arithmetic
unit
DMA μprocessor ROM
(firm) (soft)
Core-Based Systems

System
A/D CONTROL
Analogue sensor Converters
(hard) (hard) Arithmetic
unit
DMA μprocessor ROM
(firm) (soft)

Core-based system-on-chip
(SoC)
Core-based Systems

• Less design effort

Core-based Systems

• Less design effort

• Several description styles

• IP protection
• Harder to validate and test
Outline

• Test requirements of core-based systems

• Standardization initiatives
• Test planning of state-of-the-art SoCs
– NoC-based TAM
– Multiprocessors on-chip
– Mixed-signal cores testing
Test Steps - System-on-Board
RTL description Logic Validation

Synthesis

Hardware description Synthesis Verification

Manufacturing

Production Test

Interconnections
verification
Test Steps - System-on-Chip
Core description Core description Core description
#1 #2 #n

Logic Verification Logic Verification Logic Verification

SOC description
core #n
core #1 Logic Verification
core #2

Synthesis

Production Test

System Test
SoC Test Challenges

Core #1 Core #2

Core #3 Core #n

- core test
- test information
SoC Test Challenges

SOC
User Defined
Logic

Core #1 Core #2

Core #3 Core #n

- core designer
Test Schemes

SOC
User Defined
Logic

Core #1 Core #2

Core #3 Core #n

- BIST
- Scan chains
- ad-hoc
SoC Test Challenges

- interconnection test
- test access
TestCore
vectors
#1 Core #2

Core #3 Test Core #n

responses
SoC Test Challenges
- system designer
SOC
User Defined
Logic

TestCore
vectors
#1 Core #2

Core #3 Test Core #n

responses
Test Schemes

- multiplexing modes
SOC - test busses insertion
User Defined
- use of transparency
Logic

Core #1 Core #2

Core #3 Core #n
SoC Test Challenges
- test integration
- UDL test
SOC - test scheduling
User Defined
Logic - test controller

Core #1 Core #2
- system restrictions
• test time
• area overhead
• power
Core #3 Core #n • time-to-market
SoC Test Challenges
- system designer
SOC
User Defined
Logic

TestCore
vectors
#1 Core #2

Core #3 Test Core #n

responses
Test Schemes

SOC
User Defined - test controller
Logic
- boundary scan compatibility
Core #1 - microprocessors reuse
Core #2

Core #3 Core #n
Outline

• Test requirements of core-based systems

• Standardization initiatives
• Test planning of state-of-the-art SoCs
– NoC-based TAM
– Multiprocessors on-chip
– Mixed-signal cores testing
Standardization Initiatives
IEEE P1500
– interface between core providers and users

SRAM PCI
ROM

CUT
CPU DRAM

MPEG
SOC
Conceptual Architecture

SRAM PCI
ROM

test data test access CUT test access test data

source mechanism mechanism sink
CPU DRAM

MPEG
SOC
Conceptual Architecture

SRAM PCI
ROM

test data test access CUT test access test data

source mechanism mechanism sink
CPU DRAM

MPEG
SOC

external, built-in or both

Conceptual Architecture

SRAM PCI
ROM

test data test access CUT test access test data

source mechanism mechanism sink
CPU DRAM

MPEG
SOC

test busses, scan chains, bus sharing, control functions

Conceptual Architecture

SRAM PCI
ROM

test data test access CUT test access test data

source mechanism mechanism sink
CPU DRAM

MPEG
SOC

normal, internal test, external test, transparency

Wrapper P1500 Básico
WRAPPER

WBR
WBR

n
m
CORE

WBY
WSO
WSI Wrapper Instruction Register

n
wc WPI
Parallel Bypass
WRAPPER

WBR

WBR
n
m
CORE

WBY
WSO
WSI Wrapper Instruction Register

wc n
Serial Bypass
WRAPPER

WBR
WBR

l
m
CORE

WBY
WSO
WSI Wrapper Instruction Register

wc n
Wrapper Instruction Register
WRAPPER

WBR
WBR

n
m
CORE

WBY
WSO
WSI Wrapper Instruction Register

n
wc
Outline

• Test requirements of core-based systems

• Standardization initiatives
• Test planning of state-of-the-art SoCs
– NoC-based TAM
– Multiprocessors on-chip
– Mixed-signal cores testing
State-of-the-art in SoC design
SoC design
• communication among
cores
• Network-on-chip
State-of-the-art in SoC design
Bus NoC
• long wires • shorter wires
• synchronous system • modular architecture
– clock skew • GALS system:
– power consumption – globally asynchronous and locally
• much simpler synchronous
• no parallelism – lower power consumption in
channels
• limited bandwidth – support for multiple clocks
– uses handshake for
communication
• higher silicion area
• parallelism/pipeline
State-of-the-art in SoC testing
SoC design SoC testing
• communication among • access to cores
cores • test bus, reuse
• Network-on-chip • extra hardware
Putting design and test to pace
SoC design SoC testing
• communication among • access to cores
cores • test bus, reuse
• Network-on-chip • extra hardware

NoC-based SoC

• available access to each embedded core

• efficient communication mechanism
• reuse the NoC as Test Access Mechanism (TAM)
Outline

• Test requirements of core-based systems

• Standardization initiatives
• Test planning of state-of-the-art SoCs
– NoC-based TAM
– Multiprocessors on-chip
– Mixed-signal cores testing
NoC Basics

Core 1 Core 2 Core 3

Core 4 Core 5 Core 6

NoC Basics

Core 1 Core 2 Core 3

Router Router Router

Core 4 Core 5 Core 6

Router Router Router

NoC Basics

Router Router Router

N bits
NoC Basics

• Read header
– store message
– compute destination

core
NoC Basics
payload

payload
payload

header
tail

Router Router Router

NoC Basics

payload
payload
payload

header
tail

Router Router Router

NoC Basics

payload
payload
payload

header
tail

Router Router Router

NoC Basics

payload
payload

payload

header
tail

Router Router Router

NoC Basics

payload
payload
payload

header
tail

Router Router Router

NoC Basics

payload

payload
payload

header
tail
Router Router Router

Router Router Router

NoC Basics

payload

payload
payload

header
tail
Router Router Router

Router Router Router

NoC Basics

Core 1 Core 2 Core 3

Router Router Router

Core 4 Core 5 Core 6

Router Router Router

NoC Basics

Core 1 Core 2 Core 3

r er
r p e p p
p e a p r a
a p w r w
w r
Router Router Router

Core 4 Core 5 Core 6

er r
er p p p e
p a p
ap w r r a
wr w
Router Router Router
Reuse Model

SoC
core core core

core core core

Reuse Model

tester

SoC
core core core

core core core

Reuse Model

tester

SoC
core core core

core core core

Reuse Model

tester

SoC
core core core

core core core

Reuse Model
Wrapper:
- test mode
- basic P1500 modes

SoC
core core core