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Cec334 - Syllabus

The document outlines a course on Analog IC Design, covering topics such as MOS circuits, amplifier noise characteristics, feedback systems, and logic circuit testing. It includes detailed units on single-stage amplifiers, high-frequency noise analysis, operational amplifiers, stability, and testing techniques. Practical exercises and course outcomes are also provided, along with recommended textbooks and references.

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ECE 2024
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0% found this document useful (0 votes)
31 views3 pages

Cec334 - Syllabus

The document outlines a course on Analog IC Design, covering topics such as MOS circuits, amplifier noise characteristics, feedback systems, and logic circuit testing. It includes detailed units on single-stage amplifiers, high-frequency noise analysis, operational amplifiers, stability, and testing techniques. Practical exercises and course outcomes are also provided, along with recommended textbooks and references.

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ECE 2024
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© © All Rights Reserved
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CEC334 ANALOG IC DESIGN LTPC

2 023

 To study the basics of MOS Circuits.


 To analyse the noise characteristics of amplifiers.
 To study the performance parameters of amplifiers.
 To comprehend the compensation techniques
 To understand the detection and testing of faults.
UNIT I SINGLE STAGE AMPLIFIERS
6

Basic MOS physics and equivalent circuits and models, CS, CG and Source Follower, differential amplifier with active
load, Cascode and Folded Cascode configurations with active load, design of Differential and Cascode Amplifiers – to
meet specified SR, noise, gain, BW, ICMR and power dissipation, voltage swing, high gain amplifier structures.
UNIT II HIGH FREQUENCY AND NOISE CHARACTERISTICS OF AMPLIFIERS
6

Miller effect, association of poles with nodes, frequency response of CS, CG and Source Follower, Cascode and
Differential Amplifier stages, statistical characteristics of noise, noise in Single Stage amplifiers, noise in Differential
Amplifiers.
UNIT III FEEDBACK AND SINGLE STAGE OPERATIONAL AMPLIFIERS
6

Properties and types of negative feedback circuits, effect of loading in feedback networks, operational amplifier
performance parameters, single stage Op Amps, two-stage Op Amps, input range limitations, gain boosting, slew rate,
power supply rejection, noise in Op Amps.
UNIT IV STABILITY , FREQUENCY COMPENSATION
6

Multipole Systems, Phase Margin, Frequency Compensation, Compensation Of Two Stage Op Amps, Slewing in
Two Stage Op Amps, Other Compensation Techniques.
UNIT V LOGIC CIRCUIT TESTING
6

Faults in Logic Circuits- Basic Concepts of Fault Detection- Design for Testability- Ad Hoc Techniques,
Level-Sensitive Scan Design, Partial Scan, Built-in Self-Test.
30 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Design a CMOS inverter and analyze its characteristics.
2. Design a Common source amplifier and analyze its performance.
3. Design a Common drain amplifier and analyze its performance.
4. Design a Common gate amplifier and analyze its performance.
5. Design a differential amplifier with resistive load using transistors.
6. Design three stage and five stage ring oscillator circuit and compare its frequencies.
List of equipment needed for a batch of 30 students (3 in a bench):
 Cadence/Tanner/equivalent EDA Tools -10 User License

COURSE OUTCOMES:
Upon successful completion of the course the student will be able t
CO1: Design amplifiers to meet user specifications.
CO2: Analyse the frequency and noise performance of amplifiers.
CO3: Design and analyse feedback amplifiers and one stage op amps .
CO4: Analyse stability of op amp.
C O5: Testing experience of logic circuits. TOTAL:60
PERIODS
TEXTBOOKS:
1. Behzad Razavi, “Design Of Analog Cmos Integrated Circuits”, Tata Mcgraw Hill, 2001.(Unit –
I,II,III,IV)
2. Parag K.Lala, “An Introduction to Logic Circuit Testing”, Morgan & Claypool
Publishers,2009.(Unit V)
REFERENCES:
1. Willey M.C. Sansen, “Analog Design Essentials”, Springer, 2006.
2. Grebene, “Bipolar And Mos Analog Integrated Circuit Design”, John Wiley & Sons,Inc.,2003.
Phillip E.Allen, Douglas R .Holberg, “Cmos Analog Circuit Design”, Oxford University Press, 2nd
Edition, 2002.
3. Recorded Lecture Available at http://www.ee.iitm.ac.in/vlsi/courses/ee5320_2021/start
4. Jacob Baker “CMOS: Circuit Design, Layout, And Simulation, Wiley IEEE Press, 3rd Edition,2010.
CO’s-PO’s & PSO’s MAPPING

CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO
1 3 3 3 3 2 2 - - - - - 2 3 3 3
2 3 3 2 2 1 2 - - - - - 2 3 2 3
3 3 3 2 2 2 2 - - - - - 2 3 2 3
4 3 3 3 2 2 1 - - - - - 2 1 2 2
5 3 3 3 2 2 2 - - - - - 3 2 1 2
CO 3 3 2.6 2.2 1.8 1.8 - - - - - 2.2 2.4 2 2

1 - low, 2 - medium, 3 - high, ‘-' - no correlation

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