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A High-Resolution Time-To-Digital Converter Using a Three-Level Resolution

Article in International Journal of Electronics · September 2015

DOI: 10.1080/00207217.2015.1092599

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 International Journal of Electronics / International Journal of Electronics Letters

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A High-Resolution Time-To-Digital Converter Using a Three-
Level Resolution
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Journal: International Journal of Electronics

Manuscript ID: TETN-2014-0173

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Manuscript Type: International Journal of Electronics (2501-4500 word limit)

Date Submitted by the Author: 28-Feb-2014

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Complete List of Authors: Dehghani, Asma; Shahid Bahonar University,

Saneei, Mohsen; Shahid Bahonar University,
Mahani, Ali; Shahid Bahonar University,
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Digital Electronics, Integrated circuits, Logic, Frequency analysis, Analog-

Keywords:
digital conversion
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URL: http:/mc.manuscriptcentral.com/intjelectron Email: [email protected]

Page 1 of 16 International Journal of Electronics / International Journal of Electronics Letters

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A High-Resolution Time-To-Digital Converter
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7 Using a Three-Level Resolution
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9 A. Dehghani, M. Saneei, and A. Mahani
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Department of Electrical Engineering, ShahidBahonar University, Kerman, Iran
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16 Abstract—In this paper a Three-Level resolution Vernier delay line time-to-digital converter (TDC) is proposed.
17 The proposed TDC core is based on the pseudo-differential digital architecture that makes it insensitive to nMOS
18
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19 and pMOS transistor mismatches. It also takes advantages of a Vernier delay line (VDL) used in conjunction with an
20 asynchronous read-out circuitry. The time interval resolution is equal to a difference of delay between buffer of
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22 upper and lower chain. Then via extra chain which included in lower delay line, the resolution is controlled and the
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23 area and power consumption is reduced. This method leads to high resolution, low area and low power consumption.
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25 The measurement results of the TDC show a resolution of 4.5-ps, 12-bit output dynamic range and integral
26 nonlinearity is 1.5 least significant bits. This TDC achieve the consumption of 68.43µW from 1.1-V supply.
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27
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29 Keywords—Tree-level resolutions VDL, Vernier delay line, Time-to-Digital Converter, TDC.
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34 I. INTRODUCTION
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36 A phase-locked loop (PLL) with the loop filter implemented by a digital filter is generally defined as the digital PLL
37 (DPLL) [1]. PLLs are widely used in many communication systems for clock and data recovery or frequency
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39 synthesis [2,3], such as Cellular phones, computers, televisions, radios, and motor speed controllers [4].
40 The conventional analog PLL must overcome the digital switch noise coupling with power through power supply
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42 as well as substrate induced noise. In addition, the analog PLLs are sensitive to process parameters and must
43 therefore, be redesigned for each new technology [4]. Moreover, capacitors and resistors, which are required in the
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loop filter, usually cause area penalty [5].
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46 In the evolution of phase-locked-loops (PLLs) towards a more flexible digital architecture, the time to digital
47
converter represents a bottleneck in a spurs-free and low noise designs. Indeed, the quantization noise limits the PLL
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49 integral in-band phase noise while the Time-to-Digital converter (TDC) distortions generate unwanted tones near the
50
output carrier [6,7].
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52 In the previous All Digital Phase-Locked Loops (ADPLLs) architecture the conventional phase frequency detector is
53 replaced in part by a Time-to-Digital converter (TDC) [8, 9], which is an important component to measure timing
54
55 difference [10].
56 The conventional TDC architecture is based on a series connected delay line (DL), including samplers. So TDC
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58 resolution is limited by the delay of single buffer [11]. The DL-TDC which is shown in figure (1-a), detects the
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 International Journal of Electronics / International Journal of Electronics Letters Page 2 of 16

1
2
3 phase error between the reference clock (FREF) and the oscillator clock (CKV). The rising edge of the CKV
4
5 propagates through the chain of buffers, when the rising edge of the FREF signal is appeared. Then flip-flops sample
6 the output of the buffers and produce a thermometer code that determines the relative time interval [12]. But the
7
8 time resolution is limited to the buffer delay.
9 Another TDC architecture is based on a Vernier Delay line (VDL) shown in figure (1-b). The resolution was
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11 improved due to the delay difference between unequal delay cells [11], but its area and power consumption is
12 increased [13].
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24 (a)
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35 (b)
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37 Fig.1. (a) Delay line TDC. (b) Vernier Delay line TDC.
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40 The dynamic range of the TDC, i.e. the maximum time that can be measured, is limited to
    ,
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41 where n is number of delay elements of the delay line [14].

42
43 The main drawbacks of traditional Vernier delay line TDCs, are high area overhead and power consumption,
44 especially in high resolution applications. Also, mismatching of the delay elements in manufacture process is
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46 another issue when the number of delay units is increased. To overcome that drawbacks time amplification is
47 proposed to build a two-stage Vernier delay line TDC [15]. The idea is analogous to a pipeline TDC, which
48
49 amplifies the residual voltage of the first stage, then digitized by the next stage with the same resolution. In [16, 17],
50 another type of TDC architecture with multiphase reference clock as a fine TDC and a binary counter as a coarse
51
52 TDC was reported. But, if two TDC input signals (i.e., FREF and CKV) are not synchronous with the counter clock
53 (the reference clock), the counter value is erroneously sampled.
54
55 A multipath gated ring oscillator (GRO) structure was proposed to improve the TDC resolution to 6ps in a
56 0.13µm technology [18]. This GRO-based TDC also achieves first order quantization noise shaping by holding the
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58 phase of the oscillator output between measurements. This GRO based TDC achieves a detectable range of 11 bits
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Page 3 of 16 International Journal of Electronics / International Journal of Electronics Letters

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3 with up to 21mW power consumption and an area of 0.04 mm2 [19].
4
5 The resolution of GRO is still constraint by inverter delay. So a new TDC combining Vernier and GRO structures
6 is proposed in [20]. It uses two GROs in a classic Vernier TDC to achieve both process-independent high time
7
8 resolution and first-order shaped noise characteristic. The first-order noise shaping pushes much noise to the high-
9 frequency region which could be filtered by a low-pass noise transfer function in an ADPLL [20].
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11 In this paper, a novel Vernier Delay TDC (VDTDC) is proposed that leverages the time difference between two
12 chains of delay cells to achieve a time resolution of 4ps. Unlike the conventional Vernier delay TDC, the propose
13
14 TDC set the delay cells to control format such that the delay chains can be reused for measuring large, medium and
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15 small time intervals. The reuse of Vernier delay cells in a novel structure achieves fine resolution and large
16
17 detectable range simultaneously with small area and low power consumption.
18 This paper is organized as follows: The architecture of the proposed TDC is introduced in section II. Section III
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19
shows the simulation results and comparisons. Finally, section IV covers concluding remarks to this brief.
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23 II. PROCEDURE TIME TO DIGITAL CONVERTER
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The block diagram of proposed TDC block diagram which is includes two comparator blocks (comparator1 and
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27 comparator2), Arbiter circuit and TDC core is shown in figure 2. The TDC employs the coarse-middle-fine
28 architecture with the 12-bit period output code.
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51 Fig. 2.Architecture of the proposed TDC.
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54 This structure is operating as follows:
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56 Comprator1 clarify the delay between input signals, which is positive or negative (identifying which signal
57 corresponds with the first positive edge).
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 International Journal of Electronics / International Journal of Electronics Letters Page 4 of 16

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3 The Comprator2 detects the phase difference between the Data and the CLK, and then coarse, middle or fine chain is
4
5 activated and the CLK is transferred.
6 Finally, the pseudo thermometer code the output 0: 11 which contains information about the timing interval
7
8 between the rising edge of the Data and the rising/falling edges of the CLK of Arbiter circuit. According to en1, the
9 correct output (out) code is generated and send to the next block. The component architecture is explained in the
10
11 next discussion.
12
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14 A. Comparator1
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16 The functional and block diagram of comparator1 is shown in figure 3(a). Comparator1 clarify that the delay
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between input signals is positive or negative and then decided which signals appear at the upper delay line and
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19 which signals appear at the lower delay line.
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39 (a)
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46 (b)
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53 (c)
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56 Fig. 3. (a) Architecture of the Comparator1. (b) Rising edge of FREF sooner than rising edge of TDCO. (c). Rising
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edge of TDCO sooner than rising edge of FREF.
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Page 5 of 16 International Journal of Electronics / International Journal of Electronics Letters

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3 Comprator1 is operating as follow:
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5 FREF is passed through a delay element to make the setup time of the flip-flop zero. The TDCO and the FREF
6 delayed are applied to the flip-flop and generates en1, and then both of the input signals (TDCO, FREF) arrived in
7
8 multiplexers.
9 The multiplexer is controlled with flip-flop’s output (en1) so that if en1 = ‘0’ the result is Data = FREF and CLK =
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11 TDCO, and if en1 = ‘1’ the result is Data = TDCO and CLK = FREF, see figure 3(b, c) [21].
12
13 B. Comparator2
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26 Fig. 4.Architecture of the Comparator 2.
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29 Similar to the functionality of a Vernier delay line TDC, a comparator2 is needed at every stage to compare the time
30
interval between arriving signals. Then the CLK propagates through one of the lower delay line (slow line (fine),
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32 medium line (middle) or fast line (coarse)). So the comparator2 is responsible to enable the lower delay line (Figure
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4).
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35 Usually a D-flip-flop (DFF) is used to build above comparator. However, the DFF’s used in the sampler will suffer
36
from the setup time violation. If the input signal and the sampling clock are very close, the resolving time of DFF’s
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38 will become wrong. The solution of this problem is to introduce an extra buffer DFF’s as shown in figure 5 [22].
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55 (a)
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 International Journal of Electronics / International Journal of Electronics Letters Page 6 of 16

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36 (c)
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38 Fig. 5. (a) When T larger than Delay T1 and T2. (b) When T lesser than Delay T1 and larger than Delay T2. (c)
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When T lesser than Delay T1 and T2.
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Time intervals between output of comparator1 (Data, CLK) are achieved with comparator2. Data and CLK have
43
44 been considered as C and D. C passed through two delay elements (Equal coarse and middle delay) and produced
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CLK1 and CLK2, respectively. However, due to the absence of zero setup time, delay elements have been
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47 considered as follows:
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49 T1 = T −T (1)
Coarse Setup−time
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51 T =T −T (2)
52 2 middle Setup − time
53 In this comparator, when timing interval between Data and CLK are larger than the coarse delay (T1), en1 = en2 =
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55 ‘0’ and en(c) = ‘1’ then coarse delay line is active.
56 When timing separation between the surfaces of Data and CLK are smaller than the middle delay (T2), en2 = en1 =
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58 ‘1’ and en(f) = ‘1’, then fine delay line is active.
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Page 7 of 16 International Journal of Electronics / International Journal of Electronics Letters

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3 Finally when timing interval between Data and CLK are between T1 and T2, en1 = ‘1’ and en2 = ‘0’ then en(m) =
4
5 ‘1’ and middle delay line is active. In this structure, delay of comparator1 and comparator2 are not equal and outputs
6 of comparator1 are used as inputs of comparator2, which leads to sampling errors and jitter in TDC core.
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8 For eliminated sampling errors a tri-state-buffer in beginning of the upper delay line is used. Delay of tri-state-
9 buffer is equal with the setup-time of flip-flop and would be active or deactivate with en (en = en(c) OR en(m) OR
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11 en(f)).
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14 A. TDC Core
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42 Fig. 6.Structure of core TDC.
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Four different delay elements are needed to create the coarse, middle and fine structure. The TDC core (Three-
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46 level Resolution) is shown in figure 6.

47 It is made up by the delay elements, which could be implemented with either an inverter or a buffer that consists of
48
49 two cascade inverter switch.
50 The presence of two cascade inverter offers isolation between the capacitor, leads to sharper edges in front of the
51
52 each stage [6].
53 An inverter has small input and output load capacitance and so reduces the propagation delay. But the inverter line
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55 produces uneven delay due to the rise and fall time mismatch of the inverter and asymmetric flip-flop characteristics
56 [12].
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 International Journal of Electronics / International Journal of Electronics Letters Page 8 of 16

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3 To improve linearity in TDC configurations, buffers are used in the delay line in which the uneven systematic
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5 delay error does not produce.
6 Increasing the size of the inverter culminates in bigger input and output capacitance of each stage, and so sharp
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8 transitions in the cascaded structure of the chain could not obtain. But two inverters in a buffer isolate the input and
9 output capacitance in the chain and so achieving fast transition with buffers is easier.
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11 In order to control the resolution and also to activate the lower delay line, a turned on/off structure is needed. As
12 such, non-inverter buffers are composed of two cascade inverters, then tri-state inverters are connected to the flip-
13
14 flops. This structure is illustrated in figure 6. Using this method partially improves the distortion and PVT variation,
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15 especially for coarse time intervals.
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17 TDC Core is operating as follows:
18 Two input signals from the reference time base are applied to the inputs of the VDL. In this structure buffer’s
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delay in upper delay line is larger than lower delay line. So the rising edge of the input signals which arrived earlier
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21 is passed through an upper delay line (comparator1) and is considered as Data, the other input signal is considered as
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CLK. Data signal before entering the upper delay line is passed through the tri-state buffer, which his equal by

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24 (equal to setup time of flip-flop) and activated with en (en = en(c) OR en(m) OR en(f))(comprator2). This buffer
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eliminates distortion, PVT buffer delay variations, sampling errors and setup time of the flip-flop.
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27 Then Data and CLK, to determine any phase difference in the input signals, passed through a complementary
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string of N=12 non-inverter buffers and flip-flops. The difference delay between them is equal to
 ,
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30    . Data and CLKpropagate through upper and lower delay line, respectively. For example, an
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active coarse delay line with ! buffers long, has !.
"# delay at the end of the upper delay lines, and !.
$%& ' (
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33 ∆
*+ delay at the end of lower delay line.
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35 In this structure N (number of delay element)and the time resolutions are:

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37 T
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38 (Tup − Tlow ) = ( DR ) (3)

N
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40 Tres = Tup − Tlow (4)
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43 The number of required delay element for delay line during dynamic range of coarse delay line activation is one
44 period of FREF. That delay element is used to cover a dynamic range. Each line has N stages of non-inverter delay
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46 elements with fixed delays and flip-flops.

47 As depicted in figure 6, in this configuration
"#  4
- (
- is delay of one buffer), but
$%& and T are obtained as
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49 follows:
50
For active coarse delay line:
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52
53 Tlow = Tcoarse = Tbc
54  T
DR
T
FREF (5)
 →N
c
=
T
=
(4T − T )
55  T =T res(coarse) b bc
56  DR FREF
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Page 9 of 16 International Journal of Electronics / International Journal of Electronics Letters

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3 For active middle delay line:
4
5
6  T =T = 2T
T
7  low middle bm res ( coarse)
 →N
m
=
T
8 T = T = 4T − T res ( middle)
9  DR res(coarse) b bc
10
(6)
11
12 ( 4T − T )
b bc
13 →N =
m ( 4T − 2T )
14 b bm
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16 For active fine delay line:
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 T =T = 3T
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19 low fine bf T
20  res( middle)
 →N
f
=
T
21 T =T = 4T − 2T res( fine)
22  DR res(middle) b bm
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24 (7)
25 ( 4T − T )
26 b bm
→N =
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27 f ( 4T − 3T )
b bf
28
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30 Where TDR denotes the dynamic range and
.. ,
/%0123 ,
4*55$3 and
6*+3 are period of the reference, delays of
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32 coarse, middle and fine buffers, respectively. Also,
132 is structure’s resolution and
-/ ,
-4 
-6 denotes delay
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34 of buffer used in Coarse, Middle and Fine chain, respectively.
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35 Power line connections and fabrication variations are major sources of error which affecting the linearity for more
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than 40 stages in DLL and VDLL [12]. Therefore, 12 stages are selected in our proposed architecture.
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38 The total power consumption of the TDC is the sum of the power consumption of the inverter chain and
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comparators, which mathematically described as follows [23]:
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42 PTDC = (k × Pinv ) + PComp (8)
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Where K (the number of output bits) is equal to number of delay element. In our structure K is reduced as
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46 considerable ratio (N2/2), since In our structure 4N buffers are used which leads to small number of delay element
47
(comparison of 2! 8 ), low area and power consumption.
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49 Finally the delayed clock vector 90: 11 is sampled by an array of flip-flops on the rising edge of the delayed
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reference clock :;0: 11 .
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52 The pseudo thermometer-coded output 0: 11 contains information about the timing interval between the rising
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edge of the Data and the rising/falling edges of the CLK. The pseudo thermometer-coded arrived to the Arbiter
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55 circuit and, the Arbiter circuit produces the correct output code based on en1 and finally the code is converted to
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binary string by a simple digital priority decoder.
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 International Journal of Electronics / International Journal of Electronics Letters Page 10 of 16

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5 A. Arbiter circuit
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7 Arbiter circuit is shown in figure 8, which corrects time interval between the input signals and send it to the decoder.
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18 Fig. 8.Arbiter circuit.
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21 As mentioned in Section II, when the rising edge of the input signals arriving earlier, it passes through an upper
22 delay line and considered as Data.
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24 So, the circuit performance is dependent on the reference signal, which may pass to upper delay line. In other
25 words, when Data= FREF, the output code 0: 11 should be passed without change, <  0: 11 .
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27 Otherwise, as shown in figure 7, inverted output would be transmitted, <  ===========

0: 11 . The Arbiter works at
28 enable state (en1=1) and when the Arbiter was disabled, data was transmitted as is [21].
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III. SIMULATION RESULTS
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33 We designed and simulate three-level resolution Veriner delay line TDC in a0.65nm CMOS technology by PTM.
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35 Prototypes of the TDC were made with delay lines having 0.77ns, 0.1ns, 0.71ns and 0.765ns for upper, coarse,
36 middle and fine delay line, respectively. Four delay cells were placed in series to obtain 0.8ns steps. The data are
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38 available at the output of decoder with 9.25ns delay.

39 We have represented, only one period of the system response to facilitate the analysis.
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41 Using simulation method it is possible to evaluate precisely and accurately the propagation time of TDCO an
42 FREF, through both chains (upper and lower).
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44 For operating TDC at clock frequency of 125MHz, the coarse line is locked in 670ps and middle line is locked in
45 60ps duration. So, the third line corresponds to fine resolution measurement, that is locked in5ps duration and its
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final resolution value depends on the fine time interval measurement. In order to operated TDC at a 1.1Vsupply and
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48 125MHz reference clock, the three-level Vernier delay line have to be composed of 12 stage, that number of cells
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corresponds to 670ps (670ps × 12=8ns) equal to the coarse resolution.
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51 The phase difference between the TDCO and FREF signals are carefully tuned to achieve the full-range integral
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nonlinearity (INL) and differential nonlinearity (DNL).
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54 Differential nonlinearity is defined as the deviation of each bin or step size from its nominal actual value (TLSB) or
55 from the average bin width [24].
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3 INL is defined as the total deviation from the ideal characteristics of each bin for all measurements data.
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5 Nonlinearities basically originate from variation of elements inside the TDC.
6 In most of the circuits, there are delay chains to generate delayed version of input signals. Variations of these
7
8 elements from each other lead to nonlinearities in performance of TDC.
9 These variations occur due to process, voltage and temperature variations, as well as inappropriate design of the
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11 TDC which leads to having different loads at different nodes of the design.
12 DNL expresses the variation of each element compared to others and INL expresses the accumulated error in
13
14 cascade elements. For an ideal TDC, the DNL is 0LSB and when DNL is greater than 1LSB leads to missing codes
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15 in the transfer characteristics.
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17 Figure 9 plots the DNL with maximum value of 0.1LSB are shown. In this plot output codes considered as
18 Decimals forms. When omitting the data coming from the middle and fine measurement system, we achieve a 670ps
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resolution, and then measured INL and the DNL were obtained 0.9LSB and 0.1LSB, respectively.
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21 The corresponding DNL and INL in the performance of the system the middle and fine are shown in figure 10 and
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11, presents a maximum values of INL are 0.7LSB and 0.65LSB. This clearly shows that, the designed TDC offers
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24 good linearity compared to recent similar works.
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27 DNL of coarse delay line INL of coarse delay line

0.1 1
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29 0.5
0.05
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INL (LSB)
DNL (LSB)

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0
32 -0.5
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-0.05
34 -1
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-0.1 -1.5
36 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Code Code
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39 (a) (b)
40 Fig. 9.Measured Coarse TDC linearity. (a) DNL. (b) INL.
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42 DNL of middle delay line INL of middle delay line
0.1 1
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44 0.5
0.05
IN L (LSB)

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D N L (L SB )

46 0
0
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48 -0.5
-0.05
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50 -1
0 500 1000 1500 2000 2500 3000 3500 4000
51 -0.1
0 500 1000 1500 2000 2500 3000 3500 4000 Code
52 Code
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54 (a) (b)
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Fig. 10.Measured Middle TDC linearity. (a) DNL. (b) INL.
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 International Journal of Electronics / International Journal of Electronics Letters Page 12 of 16

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3 DNL of fine delay line INL of fine delay line
0.1 1
4
5
0.05 0.5
6

INL (LSB )
DN L (LSB)

7
0
8 0

9
10 -0.05 -0.5

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12 -1
-0.1 0 500 1000 1500 2000 2500 3000 3500 4000
0 500 1000 1500 2000 2500 3000 3500 4000
13 Code Code
14
Fo
15 (a) (b)
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17 Fig. 11.Measured Fine TDC linearity. (a) DNL. (b) INL.
18
rP
19
20 Figure 12 shows that at 200MHz frequency of TDCO, the power consumption is around 160µW and reduced to
21 70µW at 100MHz frequency (when T=500ps and T=25̊c). So as we expect increasing the frequency of the TDCO
22
signal, increases the power consumption.
ee
23
24
25
26
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150
27
28 130
Power (µW)

29
110
30
ev

31 90
32
70
33
34 50
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35 90 110 130 150 170 190 210

36
Frequency of TDCO (MHz)
37
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38
39
40 Fig. 12.The TDC power consumption at different TDCO frequencies.
On

41
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43 12
44
45 10
ly
Fine resolution(ps)

46 8
47
48 6
49 4
50
51 2
52 0
53 0 25 50 75 100 125 150
54
55 Temerature
56 (a)
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Page 13 of 16 International Journal of Electronics / International Journal of Electronics Letters

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2
3
4 120
5
100
6

Middle resolution(ps)
7 80
8
9 60
10
11 40
12
20
13
14 0
Fo
15
0 25 50 75 100 125 150
16
17 Temerature
18
(b)
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19
20 1050
21 1000
22 950
Coarse resolution(ps)

ee
23 900
24
850
25
800
26
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750
27
700
28
29 650
30 600
ev

31 550
32 0 25 50 75 100 125 150
33 Temperature
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35 (c)
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37
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Fig. 13.Dependence of the time resolution on the temperature. (a) Fine. (b) Middle. (c) Coarse.
38
39
40 6
On

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5.5
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43
Resolution (ps)

5
44
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ly

4.5
46
47 4
48
3.5
49
50 3
51
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
52
53 Vdd (V)
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55 Fig. 14.Measured TDC resolution versus supply voltage.
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 International Journal of Electronics / International Journal of Electronics Letters Page 14 of 16

1
2
3
4
5 TABLE I
6 COMPARISON TO PREVIOUS WORK
7 Measuring rang (bit) Tec. Supply Power Resol. Input Freq.
8
9 work [NM] [V] [MW] [PS] [MHz]
10 [11] 13 90 1.2 18 13.6 40
11
12 [13] 9 180 NA NA 39 200
13
14 [14] 500 120 NA NA 10 200
Fo
15
16
[15] NA 90 1.2 NA <10 250
17
18
[21] 12 130 1.5 7.5 8 NA
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19
20
This work 12 65 1.1 0.098 4.5 200
21
22
ee
23
24
25 It is clear that in our proposed structure maximum power consumption is about 450µW and the conversion time is
26 around 4ns which is at the beginning time of the sampling.
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27
28 Figure 13 shows the dependence of the time resolution on the temperature and figure 14 shows the delay line
29 resolution of TDC versus power supply level.
30
The depicted results are obtained by Monte Carlo simulation in Hspice. Within the temperature range from 0°C to
ev

31
32 125°C, The propagation delays of the delay element in the fine, middle and coarse line exhibit temperature
33
34 coefficients of 0.06ps/ C
̊ , 0.37ps/ C
̊ and 3.1ps/ C
̊ , respectively.
ie

35 The temperature coefficient of the delay difference between three delay lines is 2.31ps/ C
̊ , so the temperature
36
37 coefficient in coarse line is higher than the fine and middle line.
w

38 In Table I the measured results are compared with those of other solutions presented in literature. The number of
39
40 delay stages required for a given number of quantization interval time is significantly lower than all the others, and
On

41 is comparable only to the solution reported in [15] which adopts two-stepsarchitecture. The proposed prototype
42
43 shows the lowest power consumption.
44
45 During analysis of these comparison results we should point that different implementations use different
ly

46
technologies, which is difficult to evaluate their impacts.
47
48
49 IV. CONCLUSION
50
51
This paper has presented a new type of simple TDC having principal core (VDL), two comparators and Arbiter.
52
53 The TDC is specific but it could be easily adapted for wide range of applications, such as equipment and space
54 science. The proposed TDC contains a deferent type of VDL that improves power, resolution and results in area
55
56 reduction. The architecture is based on a novel VDL-TDC that makes it less noise sensitive. A TDC circuit is
57 successfully demonstrated and implemented in 65nm CMOS technology.
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Page 15 of 16 International Journal of Electronics / International Journal of Electronics Letters

1
2
3 The measurement results of the Three-Level VDL showed the resolution of 4.5ps, 12bit output dynamic range,
4
5 68.43µW power consumption from 1.1V supply with reference frequency of 125MHZ. INL and DNL in Fine TDC
6 are 1.5LSB and 0.1LSB are the best reported so far in CMOS technology, respectively. In addition, the area is the
7
8 lowest.
9
10
11
REFERENCES
12
13 [1] Young-Hun Seo, Seon-Kyoo Lee, and Jae-Yoon Sim, “A 1-GHz Digital PLL With a 3-ps Resolution Floating-
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18 [2] KhurramWaheed, Mahbuba Sheba, Robert BogdanStaszewski, FikretDulger and Socrates D. Vamvakos
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32 [18] M. Z. Straayer and M. H. Perrott, “An efficient high-resolution 11-bit noise-shaping multipath gated ring
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