Computer Organization & Architecture (COA)

GTU # 3140707

Unit-8
Input-Output
Organization
 Outline
Looping
• Asynchronous Data Transfer
• Modes Of Transfer
• Priority Interrupt
• DMA
• Input-Output Processor (IOP)
• Questions asked in GTU exam
Section - 1
Asynchronous Data Transfer
 Asynchronous data transfer between two independent units requires that control signals be
transmitted between the communicating units to indicate the time at which data is being
transmitted.
 Two ways of achieving
1. Strobe
2. Handshaking

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Strobe Method
 1.1 Source initiated Strobe  1.2 Destination initiated Strobe

Data Bus Data Bus

Destination Destination
Source unit Strobe Source unit Strobe
unit unit

Data Valid Data Data Valid Data

Strobe Strobe

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2.1 Source initiated Handshake

Source unit Destination unit

Data bus
Data valid Destination Place data on bus.
Source unit
Data accepted unit Enable data valid.
Accept data from
bus.
Enable data accepted.
Valid
Data bus Data
Disable data valid.
Invalidate data on
bus.
Data valid Disable data
accepted.
Ready to accept data
(initial state).
Data accepted

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2.2 Destination initiated Handshake
Data bus
Data valid Destination Source unit Destination unit
Source unit
Ready for data unit
Ready to accept
data.
Enable Ready for
Place data on data.
bus.
Ready for data
Enable data valid.
Accept data from
bus.
Data valid Disable Ready for
Disable data valid.
Invalid data on data.

Valid bus
Data (initial state).
Data bus

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Asynchronous Serial Transfer
 Rules for transmission
1. When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit, which is always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected when the line returns to the 1-state for
at least one bit time.

1 1 0 0 0 1 0 1

Start Stop
Character bit
bit bits

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Section - 2
Modes of Transfer
 Data transfer between the central computer and I/O devices may be handled in a variety of
modes.
 Some modes use the CPU as an intermediate path; others transfer the data directly to and from
the memory unit.
 Data transfer to and from peripherals may be handled in one of three possible modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)

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Programmed I/O
Read data register

Check flag bit

=0
Flag
Data bus Interface I/O bus
=1
Address bus Data register
Data valid I/O Read status register
CPU
I/O read device
Status
I/O write F Data accepted
register Transfer data to memory

Operation no
complete?
yes

Continue with program

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Interrupt-initiated I/O
 An alternative to the CPU constantly monitoring the flag is to let the interface inform the
computer when it is ready to transfer data.
 While the CPU is running a program, it does not check the flag.
 However, when the flag is set, the computer is momentarily interrupted from proceeding with
current program and is informed of the fact that the flag has been set.
 The CPU deviates from what it is doing to take care of the input or output transfer.
 After the transfer is completed, the computer returns to the previous program to continue what
it was doing before the interrupt.

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Section - 3
Priority Interrupt (Daisy-Chaining Technique)
 Determines which interrupt is to be served first when two or more requests are made simultaneously
 Also determines which interrupts are permitted to interrupt the computer while another is being
serviced.
 Higher priority interrupts can make requests while servicing a lower priority interrupt.

Processor data bus

VAD 1 VAD 2 VAD 3
Device 1 Device 2 Device 3
PI PO PI PO PI PO
To next
device

Interrupt request
INT
CPU
Interrupt acknowledge
INTAC
K
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Section - 4
DMA (Direct Memory Access)
 The transfer of data between a fast storage device such as magnetic disk and memory is often
limited by the speed of the CPU.
 Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer.
 This transfer technique is called direct memory access (DMA).
 During DMA, CPU is idle and has no control of the memory buses.
 A DMA controller takes over the buses to manage the transfer directly between the I/O device
and memory.

ABUS Address bus High-

Bus request BR impedance
DBUS Data bus
CPU (disabled)
RD Read when BG is
Bus granted BG WR Write enabled

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DMA Controller
DMA Controller Address bus
 DMA controller -
Interface which Data bus Data bus buffers Address bus buffers
allows I/O transfer
directly between

Internal Bus
Memory and Device, Address register
freeing CPU for DMA Select DS
other tasks Register select RS Word count register
Read RD Control
 CPU initializes DMA Control register
Write WR logic
Controller by BR
Bus request
sending memory Bus grant BG
address and the Interrupt Interrupt
DMA Request
block size (number DMA Acknowledge to I/O device
of words).

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Section - 5
Input-Output Processor (IOP)

Central
Processing Unit
(CPU)
Peripheral Device

Memory Bus
Memory Unit PD PD PD PD

Input-Output
Processor
I/O Bus

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 CPU operations IOP operations

CPU – IOP Send instruction to test

IOP path Transfer status word to
Communication memory location

If status OK, send start

I/O instruction to IOP Access memory for IOP
program

CPU continues with Conduct I/O transfers

another program using DMA; prepare
status report

I/O transfer completed;

interrupt CPU
Request IOP status

Transfer status word to

Check status word for memory location
correct transfer

Continue
Section - 6
Questions asked in GTU exam
1. Explain daisy chain priority interrupt.
2. Explain the DMA operation.
3. What is the use of IOP? Explain its communication with CPU.
4. Explain asynchronous data transfer using timing diagrams.
5. Differentiate isolated I/O and memory mapped I/O.
6. Differentiate Programmed I/O and Interrupt initiated I/O.
7. What are the advantages of Serial Data Transmission of data?
8. Briefly explain source initiated transfer using handshaking.
9. Enlist possible modes of data transfer to and from peripherals.

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