COMPUTER ORGANIZATION AND

ARCHITECTURE
Unit 1
An Overview of Computing Systems: History of Computers, The Computing Device,
The ARM7TDMI Programmers’ Model: Introduction, Data types, Processor Modes,
Registers, Program Status Registers, The vector Table.
Assembler Rules and Directives: Structure of Assembly Language Modules, Registers,
Directives, and Macros.
Loads, Stores, and Addressing: LODS and STORES instructions, Operand Addressing,
ENDIANNES
Text Book-1: 1.1 to 1.3; 2.1 to 2.6; 4; 5.3, 5.4, 5.5

An Overview of Computing Systems

• A printed circuit board is a rigid structure that contains electrical circuitry made up
of embedded metal surfaces called traces and larger areas of metal called planes.
• A System On a Chip (SOC) is an integrated circuit that integrates all components of a
computer or other electronic system.
• A SoC is nothing more than a combination of processors, memory, and graphics chips
that have been fabricated in the same package to save space, time and power.
• System-on-chip designs are becoming increasingly sophisticated, and engineers are
looking to save both money and time in their designs.
• This idea of building a complete system around a microprocessor has even spilled into
the microcontroller industry.
• A microprocessor can be seen as a computing engine with no peripherals.
• Very simple processors can be combined with useful extras such as timers, universal
asynchronous receiver/transmitters (UARTs), or analog-to-digital (A/D) converters to
produce a microcontroller, which tends to be a very low-cost device for use in
industrial controllers, displays, automotive applications, toys, and hundreds of other
places one normally doesn’t expect to find a com putting engine.

What is the difference between microprocessor and micro controller?

• Microprocessor: A microprocessor is a processing unit used for only processing
purposes.
• The microprocessor consists of only a Central Processing Unit, The microprocessor is
useful in Personal Computers
• Microcontroller: The microcontroller is a complete computer system that is embedded
on a single chip.
• Micro Controller contains a CPU, Memory, I/O all integrated into one chip. •
 Micro Controller is useful in an embedded system

History of RISC

• The history of Reduced Instruction Set Computers (RISC) actually goes back quite a
few years in the annals of computing research. Arguably, some early work in the field
was done in the late 1960s and early 1970s by IBM, Control Data Corporation and
Data General.
• In 1981 and 1982, David Patterson and Carlo Séquin, both at the University of
California, Berkeley, investigated the possibility of building a proces sor with fewer
instructions
• Their goal was to create a very simple architecture, one that broke with traditional
design techniques used in Complex Instruction Set Computers (CISCs), e.g., using
microcode (defined below) in the processor; using instructions that had different
lengths; supporting complex, multi-cycle instructions, etc.

What is RISC?
RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that
utilizes a small, highly-optimized set of instructions, rather than a more specialized set of
instructions often found in other types of architectures.

History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early
80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a
similar philosophy which has become known as RISC. Certain design features have been
characteristic of most RISC processors:
o one cycle execution time: RISC processors have a CPI (clock per instruction) of one
cycle. This is due to the optimization of each instruction on the CPU and a technique
called PIPELINING
o pipelining: a technique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
o large number of registers: the RISC design philosophy generally incorporates a larger
number of registers to prevent in large amounts of interactions with memory
1. Single-cycle execution: Unlike processors of its time, which often required multiple
cycles for instructions, this system executed all instructions in a single cycle,
streamlining programming.
2. Fixed instruction format: All instructions were of the same size and had a fixed format,
simplifying decoding and reducing the complexity of hardware design.
3. Absence of microcode: Unlike many processors, this system didn't utilize microcode,
which simplified validation and debugging processes.
4. Explicit data access: Data retrieval from external memory required explicit Load and
Store instructions, contrasting with the single-instruction memory operations in other
architectures.
5. Simplified instruction set: The processor featured a small number of instructions,
making decoding easier and requiring fewer bits for encoding operations. 6. Increased
program size: Due to the simplicity of operations, program size was expected to increase
compared to older architectures, but this was offset by boosting processor frequency.
7. Trade-off with complexity: While easier for programmers, the design complexity
increased, especially with respect to hardware design and validation.
WHY ARM?
1. The processor still had no caches (on-chip, localized memory) or memory management unit
(MMU),
2. multiply and multiply-accumulate instructions were added to increase performance,
3. More registers for handling interrupts were added to the architecture,
4. This microprocessor achieved a typical clock speed of 12 MHz in a 2-micron process
Origins with Acorn Computers: ARM Holdings PLC traces its roots back to Acorn
Computers, a UK-based company known for producing desktop PCs, notably the BBC
Micro, popular in educational markets.
Development of ARM1: In 1983, Acorn decided to design its own microprocessor instead of
using existing architectures like the Motorola 68000. Steve Furber and Sophie Wilson joined
the design team, with VLSI Technology producing the first samples.
Introduction of ARM1: The ARM1, utilizing less than 25,000 transistors, was fabricated in
1985. Remarkably, it functioned correctly upon arrival, a rarity at that time.
Processor Speed: Unlike today's processors running at gigahertz speeds, the ARM1 operated
at a modest 4 MHz due to technological limitations of the era.
Evolution to ARM2: Subsequent revisions led to the ARM2, featuring enhancements such
as multiply instructions and increased clock speed, making it suitable for use in the
Archimedes desktop PC.
Application in Archimedes Desktop PC: Acorn incorporated the ARM2 into its
Archimedes desktop PC, while VLSI Technology marketed it as the VL86C010 processor
chip set, bundled with various controllers.
The Creation of ARM LTd
1. Introduction of ARM3: In response to evolving desktop architectures in 1989, ARM
developed the ARM3, featuring a 4K unified cache, to compete with the Motorola
68000 and x86 families.
2. Shift towards Embedded Processors: While Acorn faced challenges with the
dominance of IBM PC, VLSI Technology found success in marketing ARM
processors for embedded systems, attracting companies like Apple for their personal
digital assistants (PDAs).
 3. Formation of Advanced RISC Machines Ltd. (ARM Ltd.): Apple's interest in a
processor for their PDAs led to the creation of ARM Ltd., with Apple and Acorn
Group as stakeholders, adopting a unique business model of licensing processor
designs to other companies.
4. Evolution to ARM6: The ARM6, introduced after architectural extensions, included
32-bit addressing and supported both big- and little-endian memory formats, paving
the way for further innovations in processor design.
5. Introduction of ARM7: Introduced in 1993, the ARM7 lacked some features but set
the stage for its successor, the ARM7TDMI, which incorporated new hardware for
external debugging and introduced the Thumb instruction set for enhanced
performance in embedded systems.
6. Expansion and Adoption: ARM7TDMI's compact design, low power consumption,
and rich instruction set made it popular in embedded systems, especially in the
burgeoning cell phone industry, laying the groundwork for subsequent processor
designs.
7. Continued Advancements: Throughout the 1990s, ARM made continual
improvements to its architecture with the introduction of ARM8, ARM9, and ARM10
processor cores, along with derivatives, marking significant milestones in the
evolution of ARM processors.
8. Expansion into Other Markets: Agreements with companies like Digital Equipment
Corporation led to the creation of StrongARM and subsequent versions produced by Intel
under the brand XScale, showcasing ARM's expansion beyond its original scope.

ARM Today
ARM's Growth and Expansion:
1. Proliferation of ARM-Based Devices: By 2002, ARM processors were powering
around 1.3 billion devices, particularly in cell phones dominated by Nokia, with TI as
a major silicon supplier alongside other partners like Philips and Qualcomm.
2. Diversification Beyond Processor Cores: ARM expanded its focus beyond
processor cores, acquiring companies like Adelante Technologies, Axys Design
Automation, Artisan Components, Keil Software, Falanx, and SOISIC to offer
comprehensive solutions including DSP processors, hardware tools, standard cell
libraries, and 3D graphics accelerators.
3. Rapid Growth and Adoption: Over six years, ARM experienced rapid growth,
aiming to facilitate the design of complete system-on-chip architectures using ARM
technology, resulting in billions of ARM processors being shipped across various
applications.
4. Underappreciated Presence in Finished Products: Despite ARM's widespread
adoption, its presence in finished products often goes unnoticed by average
consumers, with silicon vendors receiving more attention. For instance, Nokia cell
phone users might not realize that ARM provided part of the design alongside TI's
silicon.

THE COMPUTING DEVICE

 1. Instruction Mechanisms: Machines receive instructions through various means such
as paper tape, switches, or punch cards, as demonstrated by Joseph Marie Jacquard's
invention in 1804.
2. Stored-Program Computer: Instructions are stored in memory for retrieval by the
processor, along with data for computation, forming the fundamental components of a
computer: processor, memory, and data transfer buses.
3. Assembly Language Programming: Focuses on writing instructions for the
processor in a human-readable format, facilitating interaction with the processor's
fundamental operations.
4. Input/Output Interfaces: Traditional computer models include interfaces for I/O
devices like keyboards, disk drives, and printers, although embedded systems may
lack these components, relying solely on sensor inputs.
5. Hierarchy of Computing: At the lowest level, transistors manipulate electrons to
create switches, leading to the construction of gates and blocks like adders and
multipliers, which form the basis of a processor's architecture.
6. Processor's Language: Specifies how data is processed, memory controlled, and
external events handled, with instructions directing operations such as arithmetic
calculations and data storage.
7. Assembly Code and Beyond: This text focuses on assembly code for ARM
architecture, but higher-level languages like C or C++ can be used to generate
assembly code, and further levels involve working with operating systems like
Android for task execution.

The ARM7TDMI Programmers’ Model

The way the processor is controlled, such as

• where data can be stored,
• what happens when you give the machine an invalid instruction,
• where your registers are stacked during an exception, and so forth. This description is
called the programmer’s model.
Data Types

• Representation of Data: Data in machines is represented as binary digits, known as

bits, where each bit can be either on (1) or off (0).

• Grouping of Bits: Bits are often grouped into units of eight, called bytes, or larger
units depending on the device manufacturer.

• Data Sizes: Different processors have different definitions for data sizes. For
example:

•A 16-bit data value is called a "word" in processors like Intel 8086 or

MC68040.

• In ARM cores, a 32-bit data value is considered a "word."

• Supported Data Types: The ARM7TDMI and Cortex-M4 processors support the
following data types:

• Byte: 8 bits

• Halfword: 16 bits

• Word: 32 bits

• Instruction Length: While the length of instructions doesn't matter initially, later
we'll learn that instructions can be either 16 or 32 bits long. This means:

• Two bytes are needed to create a Thumb instruction.

• Four bytes are required for an ARM instruction or a Thumb-2 instruction.

• Data Alignment: In ARM7TDMI, halfwords must be aligned to two-byte boundaries,

and words to four-byte boundaries in memory addresses.

• Data Operations: Most data operations like ADD are performed on word quantities,
but we'll also work with smaller, 16-bit values later on.

Processor Modes
Version 4T cores support seven processor modes: User, FIQ, IRQ, Supervisor, Abort,
Undefined, and System, as shown in Figure 2.1. It is possible to make mode changes under
software control, but most are normally caused by external conditions or exceptions. Most
application programs will execute in User mode. The other modes are known as privileged
modes, and they provide a way to service exceptions or to access protected resources, such as
bits that disable sections of the core, e.g., a branch predictor or the caches, should the
processor have either of these.
Modes of Operation:

• Modes indicate what the processor is currently doing.

• Common modes include User mode and Supervisor mode.

Interrupt Handling:

• External events, like signals or user inputs, are treated as interrupts.

• ARM7TDMI supports two types: Fast Interrupt (FIQ) mode and Interrupt Request
(IRQ) mode.

• FIQ mode handles urgent interrupts, while IRQ mode handles lower priority
interrupts.
Abort Mode:

• Used for recovering from exceptional conditions, such as invalid memory access. •

Also supports virtual memory systems, often used by operating systems like Linux.
Undefined Mode:

• Entered when the processor encounters an unrecognized instruction.

• Programmers or the operating system must determine how to recover from such
errors.

• Historicallyused for supporting floating-point instructions on machines without

dedicated hardware.
Focus of Study:

• Main focus on working in User mode or Supervisor mode.

Registers

• Registers are essential storage areas on the chip.

• They can hold various types of data or addresses.

• The ARM7TDMI processor has 37 registers:

• 30 general-purpose registers

•6 status registers

•1 Program Counter register

• General-purpose registers are 32 bits wide, named r0 to r15.

• Registers are organized in partially overlapping banks, depending on the processor

mode.

• Different modes show different sets of registers to the programmer.

• Bankedregisters are swapped during mode changes to save machine state quickly
during interrupts.

• Some registers have special purposes:

• r13: Stack Pointer (SP)

• r14: Link Register (LR)

• r15: Program Counter (PC)

• The Program Counter holds the address of the instruction being fetched. •

The Current Program Status Register (CPSR) stores machine state.

• Eachprivileged mode (except System mode) has a Saved Program Status Register
(SPSR).

• CPSR contains condition code flags and control bits.

• Condition code flags can be altered by certain instructions.

• Control bits include interrupt disable bits and a state indicator bit (Thumb/ARM). •

Processor mode is determined by specific bit configurations in PSRs. • Invalid bit

configurations result in unpredictable behavior.

Vector Table

• The vector table is a common component in processors.

• It consists of designated addresses in external memory.

• These addresses hold information for handling exceptions, interrupts, or resets.

• For example, when an interrupt (IRQ) occurs, the processor changes the Program
Counter to a designated address and begins fetching instructions from there.

• Instructions located at these addresses are actual ARM instructions.

• Many processors, including the Cortex-M4, have addresses at these vector locations
in memory, while the ARM7TDMI processor places instructions here.

• The Reset exception vector, located at address 0x0 in memory, is essential as the
machine fetches from this address immediately after reset.
• Development tools often provide startup files for microcontrollers, including startup
code, initialization routines, and exception vector assignments.

• However, for simplicity, exceptional conditions may be ignored temporarily to focus

 on simpler instructions.

Assembler Rules and Directives

• The routine's main purpose is to add the numbers 10 and 3 together.

• Thecode includes directives for the assembler and an instruction to put the processor
in an infinite loop.

• Source lines in assembly files generally follow a specific structure: •

{label} {instruction|directive|pseudo-instruction} {;comment}

• Labels represent memory addresses and are optional but must be unique.

• Instructions,
directives, and pseudo-instructions must be preceded by
whitespace.

• One common mistake is starting an instruction in column one.

• Blank lines can be used to improve code readability.

• ARM7TDMI instructions come from the ARM version 4T instruction set, while
Cortex-M4 uses Thumb-2 instructions from the v7-M instruction set.
• Directives and pseudo-instructions offer additional functionality and flexibility.

• TheUnified Assembler Language (UAL) supersedes earlier versions of ARM and

Thumb assembler languages.

• UAL introduces subtle changes, such as differences in shift operation syntax.

• Disassembly
of code may show UAL notations, particularly with RealView tools or
Code Composer Studio.

• Detaileddocumentation of code is essential for clarity and understanding, especially

in collaborative projects.
Guidelines for effective commenting include:

• Avoid commenting the obvious, such as simple arithmetic operations. •

Use concise language to describe register contents or function behavior.

• Comment sections of code where understanding may be challenging for other

programmers.

• Provide short descriptions of functions, subroutines, or long code segments. •

Avoid unnecessary abbreviations, as they may obscure meaning.

• Explain acronyms or shortened peripheral register names to enhance

understanding.

• In Keil tools, the first semicolon on a line marks the beginning of a comment,
unless within a string constant.

• Comments can span entire lines, ending at the line's conclusion.

• TI assembler allows comments marked by either an asterisk (*) or semicolon

anywhere in the line.
• Constants in assembly can be in decimal (e.g., 123) or hexadecimal (e.g.,
0x3F).

• Keil supports constants in the format n_xxx, where n is a base between 2 and
9, and xxx is a number in that base.

• Character constants are enclosed in single quotes, while string constants are
enclosed in double quotes.
 • Standard C escape sequences can be used within string constants, interpreted
differently by various assemblers.

• Keil tools allow single character constants and string constants with escape
sequences.

• Code Composer Studio tools use .string directive for string constants but do
not interpret escape characters.

• To include escape characters and add a NUL character, use the .cstring
directive.

• Keil tools have case rules for commands, allowing either uppercase or
lowercase but not a mix.

• TI assembler is case-insensitive regarding mnemonics.

Keil tools
Predefined Registers
Most assemblers provide predefined register names for readability in code. • The

ARM assembler includes a set of case-sensitive predefined register names.

• Predefinednames cover basic registers, status registers, floating-point registers, and

coprocessors.

• Notable predefined register names for immediate use include:

• r0-r15 or R0-R15: General-purpose registers

• s0-s31 or S0-S31: Floating-point registers

• a1-a4: Argument, result, or scratch registers (synonyms for r0 to r3) •

sp or SP: Stack pointer (r13)

• lr or LR: Link Register (r14)

• pc or PC: Program Counter (r15)

• cpsr or CPSR: Current Program Status Register

• spsr or SPSR: Saved Program Status Register

• apsr or APSR: Application Program Status Register

Difference between Directives and Instructions

• Assembler directives are the commands to the assembler that direct the assembly
process. Example: AREA, END
• An instruction is a statement that becomes executable when a program is assembled.
• Instructions are translated by the assembler into machine language bytes, which are
loaded. and executed by the CPU at runtime.
 • Examples: MOV R1, R2 ADD R0,R1,R2

FREQUENTLY USED DIRECTIVES

1) Defining a Block of Data or Code
Keil Tools
1) Register Name Definition
2) Equating a Symbol to a Numeric Constant
3) Declaring an Entry Point
4) Allocating Memory and Specifying Contents
5) Aligning Data or Code to Appropriate Boundaries
6) Reserving a Block of Memory
7) Assigning Literal Pool Origins
8) Ending a Source File
• Register Name Definition (Keil
Tools):

• TheARM assembler in Keil tools offers a directive called RN for defining

custom register names.
• Syntax:name RN expr, where name is the custom register name and expr is
a value from 0 to 15.

• Register Name Definition (Code Composer

Studio):

• In CCS, register names can be assigned using the directive.

.a
s
g

• Syntax: .
.asg "character string", substitution
symbol

• Example usage: .
.asg R13,
STACKPTR
 • Equating a Symbol to a Numeric Constant (Keil
Tools):

• TheEQU directive associates a symbolic name with a numeric constant. •

Syntax: .
name EQU
expr{,type}

• Equating a Symbol to a Numeric Constant (Code Composer

Studio):

• CCS provides directives for the same purpose.

. an .e
s d q
e u
t

• Syntax: or .

symbol .set symbol .equ

value value

• Declaring an Entry Point (Keil

Tools):

• The ENTRY directive specifies the entry point for a program.

• Syntax: .
ENT
RY

• Allocating Memory and Specifying Contents (Keil

Tools):

• Memory allocation directives like DCB, DCW, and DCD are used to define
data contents.
• Allocating Memory and Specifying Contents (Code Composer
Studio):

• CCS provides directives like .byte, .half, .int, etc., for initializing memory with
different data types.

• Aligning Data or Code to Appropriate Boundaries (Keil

Tools):

• TheALIGN directive ensures alignment to specified boundaries. •

Syntax: .
ALIGN
{expr{,offset}}

• Aligning Data or Code to Appropriate Boundaries (Code Composer

Studio):

• CCS uses the .align directive for the same purpose.

• Syntax: .
.align {size in
bytes}

• Reserving a Block of Memory (Keil

Tools):

• SPACE and .space directives reserve zeroed memory blocks.

• Syntax: .
{label} SPACE
expr

• Reserving a Block of Memory (Code Composer

Studio):

• CCS provides .space and .bes directives for memory reservation. •

Syntax: {label} .space size (in bytes) or {label} .bes size (in bytes).

• Assigning Literal Pool

Origins:
 • Literalpools are managed using LTORG directive to ensure correct placement
in code sections.

• Ending a Source
File:

• The END directive marks the end of a source file.

• Syntax: (Keil Tools) or (Code Composer Studio).

E .e
N n
D d

KEIL tools
1. Register Name Definition
The RN directive defines a register name for a specified register.
Syntax name RN expr
where:
name name to be assigned to the register. name cannot be the
same as any of the predefined names.
expr evaluates to a register number from 0 to
Usage
• Use RN to allocate convenient names to registers, to help you to remember what you
use each register for. Be careful to avoid conflicting uses of the same register under
different names.
Example
regname RN 11 ; defines regname for
register 11
sqr4 RN r6 ; defines sqr4 for
register 6
2. Equating symbol to a numeric constant

• The syntax for the EQU directive is

 name EQU expr{,type}
where name is the symbolic name to assign to the value, expr is a register-relative
address, a program-relative address, an absolute address, or a 32-bit integer constant. •
The parameter type is optional and can be any one of
• ARM
• THUMB
• CODE16
• CODE32
• DATA
3. Declaring an entry point
• ENTRY directive declares an entry point to a program.

• syntax is ENTRY
• Your program must have at least one ENTRY point for a program
• Example

• AREA ARMex, CODE, READONLY

ENTRY ; Entry point for the application

5. Allocating memory and specifying contents

• Strings, floating-point constants, and even addresses can be stored in memory as data
using various directives.
• Keil Tools
• DCB, actually defines the initial runtime contents of memory. The syntax is •
{label} DCB expr{,expr}…
• where expr is either a numeric expression that evaluates to an
integer in the range −128 to 255, or a quoted string, where the
characters of the string are stored consecutively in memory.
• Since the DCB directive affects memory at the byte level, you should use an ALIGN
directive afterward if any instructions follow to ensure that the instruction is aligned
correctly in memory.
6. Aligning Data or Code to Appropriate Boundaries
The ALIGN directive aligns the current location to a specified boundary by padding with
zeros. The syntax is
ALIGN {expr{,offset}}
where expr is a numeric expression evaluating any power of two from 20 to 231, and
offset can be any numeric expression. The current location is aligned to the next
address of the form
offset + n * expr
If expr is not specified, ALIGN sets the current location to the next word (four byte)
boundary.
AREA Example, CODE, READONLY
start LDR r6, = label1
; code
MOV pc,lr
label1 DCB 1 ; pc now misaligned
ALIGN ; ensures that subroutine1 addresses
subroutine1 MOV r5, #0x5 ; the following instruction

7. Reserving a block of memory

To reserve a block of memory for variables, tables, or storing data during routines.
 The SPACE and .space directives reserve a zeroed block of memory.
The syntax is
{label} SPACE expr
where expr evaluates to the number of zeroed bytes to reserve.
AREA MyData, DATA, READWRITE
data1 SPACE 255 ; defines 255 bytes of zeroed storage

8. . Assigning Literal Pool Origins

Literal pools are areas of data that the ARM assembler creates for you at the end of every
code section, specifically for constants that cannot be created with rotation schemes or
that do not fit into an instruction’s supported formats.
The LTORG directive instructs the assembler to assemble the current literal pool
immediately.
Syntax LTORG
Usage
• The assembler assembles the current literal pool at the end of every code section. The
end of a code section is determined by the AREA directive at the beginning of the
following section, or the end of the assembly.
• These default literal pools can sometimes be out of range of some LDR, VLDR, and
WLDR pseudo-instructions. Use LTORG to ensure that a literal pool is assembled
within range.
• Large programs can require several literal pools. Place LTORG directives after
unconditional branches or subroutine return instructions so that the processor does not
attempt to execute the constants as instructions.
• The assembler word-aligns data in literal pools.

Macros:
Macros in assembly language serve a similar purpose to functions in higher-level languages.
They allow developers to define a set of instructions or operations once and then invoke them
multiple times by name throughout the code. This abstraction saves time and effort by
eliminating the need to rewrite the same sequence of instructions repeatedly.
Advantages and Disadvantages:

• Advantages:

• Code Reusability: Macros facilitate the reuse of code segments, leading to

shorter and more concise source code.

• Maintenance: Since macro definitions are centralized, modifying the

behavior of a particular operation only requires editing the macro definition,
thereby simplifying code maintenance.

• Readability: Well-named macros enhance code readability by providing

descriptive names for common operations.

• Disadvantages:

• Increased Memory Usage: Each macro invocation results in the expansion of

its code at the point of invocation, potentially increasing memory usage,
especially if macros are used extensively.
• Complexity: Macros can introduce complexity, particularly if they are large or
 involve intricate logic. Understanding and debugging complex macros may
be challenging.
Macro Definition Syntax:

• MACRO Directive: Begins the macro definition.

• MEND Directive: Ends the macro definition.

• Parameters: Can be defined within the macro definition to accept arguments passed
during invocation.
Example:
Suppose you have a sequence of instructions that performs a specific computation and is
repeated at multiple places in your code. Instead of copying and pasting this sequence each
time, you can define a macro to encapsulate these instructions. Then, whenever you need to
execute this sequence, you simply invoke the macro by its name, providing any necessary
arguments.
The MACRO directive marks the start of the definition of a macro. Macro expansion
terminates at the MEND directive.
Syntax Two directives are used to define a macro. The syntax is: MACRO
{$label} macroname{$cond} {$parameter{,$parameter}...}
; code
MEND
where:
$label is a parameter that is substituted with a symbol given when the macro is
invoked.
The symbol is usually a label.
macroname is the name of the macro. It must not begin with an instruction or
directive name.
$cond is a special parameter designed to contain a condition code. Values other
than valid condition codes are permitted.
$parameter is a parameter that is substituted when the macro is invoked. A default
value for a parameter can be set using this format:
$parameter="default value"
Double quotes must be used if there are any spaces within, or at either end of,
the
default value.
• where $label is a parameter that is substituted with a symbol given when the macro is
invoked.
• The symbol is usually a label.
• The macro name must not begin with an instruction or directive name.
• The parameter $cond is a special parameter designed to contain a condition code;
 however, values other than valid condition codes are permitted.
• The term $parameter is substituted when the macro is invoked.
• Within the macro body, parameters such as $label, $parameter, or $cond can be used
in the same way as other variables. They are given new values each time the macro is
invoked.
Parameters must begin with $ to distinguish them from ordinary symbols. Any number of
parameters can be used. The $label field is optional, and the macro itself defines the locations
of any labels
Assembler Operators:
Assembler operators are primitive operations applied to data before its use in an instruction.
These operators are not part of the instruction set but are used to manipulate data efficiently.
Types of Operators:

• Unary Operators: Operate on a single value.

• Binary Operators: Operate on two values and are more commonly used.

Example:
Binary operators, such as shifting, rotating, and bitwise logical operations, are particularly
useful for bit manipulation tasks. For instance, to set a specific bit in a register, you can use
the bitwise OR operator to combine the register value with a bitmask representing the desired
bit.

Loads, Stores, and Addressing

1. Load/Store Architecture: In RISC architectures like ARM, data movement between

memory and registers is explicitly handled by load and store instructions. Unlike
some older architectures, there are no complex load-store instructions that combine
multiple operations into one.
2. Instruction Format: Load and store instructions have a uniform format:
LDR|STR{<size>}{<cond>} <Rd>, <addressing_mode>
1.

• <size>: Optional size specifier (byte, halfword, word).

• <cond>: Optional condition code.

• <Rd>: Destination (for loads) or source (for stores) register.

• <addressing_mode>: Specifies the memory address to load from or store to.

2. Base Register and Offset: The addressing mode typically involves a base register
and an optional offset. For example:
LDR r9, [r12, r8, LSL #2]

• Base register: r12

 • Offset: r8 << 2 (shifted left by 2 bits)

2. Effective Address: The effective address is the final memory address calculated
based on the base register, offset, and any additional shifts or operations. It's denoted
as ea<operands>.
3. Addressing Modes:

• Pre-indexed addressing: Offset is applied before accessing memory. •

Post-indexed addressing: Offset is applied after accessing memory. 4. Special

Cases:

• Simple loads/stores are special cases of pre-indexed addressing with zero

offsets.

• Halfword and byte loads/stores handle data in specific parts of the register
(LSB for loads, and LSB for stores).

OPERAND ADDRESSING
1. Format of Pre-indexed :
Addressing

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code

LDR|STR{<size>}{<cond>} <Rd>, [<Rn>, <offset>]

{!}

•: Optional size specifier (byte, halfword, word).

<siz
e>

<con
d>

<R
d>
 •: Optional condition code.
•: Destination (for stores) or source (for loads) register.
•: Base register.
<R
n>

<offse
t>

•:Offset added to the base register to calculate the effective address. • :

Optional specifier to update the base register with the effective address.
2. Operati :
on

• The offset is added to the value in the base register () to calculate the
effective address. n>
<R

• If the specifier is used, the effective address is written back to the base

register.
• Without , the base register retains its original value after the instruction.

3. Offset :
Options

• Offset can be a shifted register or an immediate value.

• For ARM7TDMI, offset options include shifted register with any 5-bit
constant, unshifted 12-bit constant, or immediate value.
• Barrel shifter can be used for logical and arithmetic shifts of constants.

4. Exampl :
es

• Examples include storing and loading data with various offset calculations:
 • STR r3, [r0, r5, LSL
#3]
•
LDR r6, [r0, r1, ROR
• #6]!
• LDR r0, [r1, #-
• 8]

• LDR r0, [r1, -r2, LSL

#2]
•
LDRSH r5,
[r9]

LDRSB r3, [r8,

#3]

LDRSB r4, [r10,

#0xc1]

Pre-indexed addressing offers flexibility in accessing memory by allowing

dynamic calculations for the effective address based on the base register and
offset

1. Format of Post-indexed :
Addressing

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code

LDR|STR{<size>}{<cond>} <Rd>, [<Rn>],

<offset>

: Optional size specifier (byte, halfword, word).

• <siz
e>
•
<con
• d>
• <R
• d>

<R
n>

<offse
t>
 : Optional condition code.
: Destination (for stores) or source (for loads) register.
: Base register.
: Offset added to the base register after the data transfer.
2. Operati :
on

• Theeffective address is calculated from the unmodified value in the base

register <Rn>.
• The offset is added to the base register, and the sum is written back to <Rn>.
• Post-indexed addressing automatically updates the base register.

3. Incrementing :
Usefulness

• Useful
for stepping through tables or lists, as the base address is automatically
updated.

4. Exampl :
es

• Examples include storing and loading data with automatic base register
updates:

•: Store to effective address , then

LDRH r3, [r9], 7
STR r7, [r0], #2
#24 r0 = r0
+
2 .
4 r <r
0>

•: Load halfword to from effective address ,

then .
r9 = r9 r <r
+2 3 9>

•: Store halfword from to effective address ,

r5 = r5
STRH r2, [r5], +8
#8

<r
r 5>
then . 2
 5. Flexibili :
ty

• Similarrules to pre-indexed addressing apply, including limitations and

options for offset calculations.
• ARM7TDMI offers more flexibility, allowing operations like rotations on the
offset value.

Post-indexed addressing simplifies memory access by automatically updating the base

register after each access, making it particularly useful for iterating over data structures
like arrays or linked lists.

ENDIANNESS

• Origin of the Term "Endianness":

• Coined by Danny Cohen in 1981, likening the debate over bit and byte
ordering to conflicts in literary works like Gulliver's Travels and Alice's
Adventures in Wonderland.

• Endianness in ARM:

• ARM supports both little-endian and big-endian formats through software

and/or hardware mechanisms.

• Little-Endian vs. Big-Endian:

• Little-endian stores the least significant byte at the lowest address, while big
endian stores the most significant byte there.

• Example Scenario:

• Given the value 0x0A0

B0C0D stored to memory addresses 0x400 to 0x403:

• Little-endian: 0x0D, 0x0C, 0x0B, 0x0A.

• Big-endian (word-invariant): 0x0A, 0x0B, 0x0C, 0x0D.

• Practical Implications:
 • Impact felt when transferring halfwords or bytes, affecting data returned.

• Example: loading 0xBABEFACE at address 0x400, loading a halfword at

address 0x402:

• Little-endian: 0x0000BABE.

• Big-endian: 0x0000FACE.

• Configurations and Preferences:

• No ARM preference; determined by hardware designers.

• ARM7TDMI can switch using BIGEND pin.

• Cortex-M4 mostly little-endian.

• Some applications favor big-endian for simplicity in reading network traffic. •

Programming Considerations:

• Book examples assume little-endian.

• Memory display might seem backward in big-endian systems.

• Tools like Keil and Code Composer Studio may reorder data for clarity.