Processor Logic Design & Control Logic Design

Part 1: Processor Logic Design

Processor Logic Design deals with the fundamental building blocks and their
interconnections that make up the Central Processing Unit (CPU) of a computer. It
focuses on how data is processed, manipulated, and stored within the processor.
1. Processor Organization
The processor (CPU) is the "brain" of the computer. It's broadly organized into three
main components:

● Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition,

subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR).
● Control Unit (CU): Directs and coordinates all operations within the CPU and the
computer system. It fetches instructions, decodes them, and generates control
signals.
● Registers: Small, high-speed storage locations within the CPU used to hold data,
instructions, and addresses during processing.

Conceptual Diagram: Basic CPU Organization

+---------------------+
| Control Unit |
| (CU) |
+---------------------+
| Control Signals
V
+-------------------+ +-------------------+
| Registers |<----->| Arithmetic Logic |
| (General Purpose, | | Unit (ALU) |
| Status, etc.) | +-------------------+
+-------------------+ ^
| Data
V
+-------------------+
| Memory |
| (RAM, Cache) |
+-------------------+

2. Arithmetic Logic Unit (ALU)

The ALU is the core computational component of the CPU. It performs all arithmetic and
logical operations.

● Arithmetic Operations: Addition, subtraction, multiplication, division. These are

usually implemented using dedicated circuits (e.g., adders).
● Logic Operations: AND, OR, NOT, XOR. These are implemented using logic gates.

Key Components of an ALU:

● Operation Select Lines: Control signals that determine which operation the ALU
will perform.
● Operands (A and B inputs): The data values on which the operation will be
performed.
● Result Output: The output of the operation.
 ● Status Outputs (Flags): Indicate characteristics of the result (e.g., zero, carry,
negative, overflow).

3. Design of Arithmetic and Logic Circuits

a) Design of Arithmetic Circuits:

● Half Adder: Adds two single binary digits and produces a sum and a carry-out.
o Logic Diagram: (Typically drawn with an XOR gate for sum and an AND gate
for carry)
o A ----+
o |--- XOR --- Sum
o B ----+
o |--- AND --- Carry Out
● Full Adder: Adds three single binary digits (two input bits and a carry-in) and
produces a sum and a carry-out. Full adders are cascaded to build multi-bit adders.
o Logic Diagram: (Typically drawn using two Half Adders and an OR gate)
o A -----+
o | Half
o B -----+ Adder --> Sum1
o |
o Carry In -+ Carry Out1
o | OR ---- Carry Out
o |
o Half
o Adder --> Sum
o |
o Carry Out2
● Ripple-Carry Adder: A multi-bit adder formed by cascading full adders. The carry-
out of one stage becomes the carry-in of the next. Simple but can be slow due to
carry propagation delay.
● Carry-Lookahead Adder: A faster multi-bit adder that generates carries in parallel,
reducing propagation delay. More complex to design.

b) Design of Logic Circuits:

Logic circuits are built using basic logic gates (AND, OR, NOT, NAND, NOR, XOR,
XNOR).

● AND Gate: Output is 1 only if all inputs are 1.

● OR Gate: Output is 1 if at least one input is 1.
● NOT Gate (Inverter): Output is the opposite of the input.
● XOR Gate: Output is 1 if inputs are different.

These gates are combined to perform logical operations. For example, a 4-bit AND
operation would involve four 2-input AND gates.
4. Design of Arithmetic Logic Unit (ALU)
An ALU is designed by combining various arithmetic and logic circuits and using
multiplexers (MUX) to select the desired operation.
Conceptual Diagram: Simple ALU Design (e.g., 2-bit ALU)
Operation Select (S1, S0)
|
V
+-------------------------------------------------+
| |
| Input A (e.g., 2 bits) |
| Input B (e.g., 2 bits) |
| |
| +-------------------+ +-------------------+ |
| | Arithmetic | | Logic | |
| | Circuits (Add, | | Circuits (AND, | |
| | Sub, etc.) | | OR, etc.) | |
| +-------------------+ +-------------------+ |
| | | |
| V V |
| +---------------------------------------+ |
| | Multiplexer (MUX) | |
| +---------------------------------------+ |
| | |
| V |
| Output Result |
| Status Flags (Zero, Carry, etc.) |
+-------------------------------------------------+

● The Operation Select lines (e.g., S1, S0 for 4 operations) control the MUX, routing
the output of the selected arithmetic or logic circuit to the ALU's main output.

5. Status Registers (Flags)

Status registers, often called flags, are a special type of register that stores information
about the result of the most recent arithmetic or logical operation. They are crucial for
conditional branching and error handling. Common flags include:

● Zero Flag (Z): Set (1) if the result of the operation is zero; otherwise, reset (0).
● Carry Flag (C): Set if an unsigned arithmetic operation results in a carry-out (for
addition) or a borrow (for subtraction).
● Sign Flag (N or S): Set if the most significant bit (MSB) of the result is 1 (indicating a
negative number in two's complement).
● Overflow Flag (V or O): Set if a signed arithmetic operation results in an overflow
(the result is too large or too small to be represented in the available bits).
● Parity Flag (P): Set if the result has an even number of 1s.

6. Design of Shifter
A shifter is a combinatorial circuit that shifts the bits of a binary word to the left or right.
They are used for various operations like multiplication/division by powers of 2, bit
manipulation, and data alignment.
Types of Shifts:

● Logical Shift Left (LSL): Shifts bits to the left, inserting zeros on the right.
● Logical Shift Right (LSR): Shifts bits to the right, inserting zeros on the left.
● Arithmetic Shift Left (ASL): Identical to LSL for signed numbers.
● Arithmetic Shift Right (ASR): Shifts bits to the right, replicating the MSB (sign bit)
on the left to preserve the sign of the number.
● Rotate Left (ROL): Shifts bits to the left, wrapping the MSB around to the LSB
position.
● Rotate Right (ROR): Shifts bits to the right, wrapping the LSB around to the MSB
position.

Conceptual Diagram: Barrel Shifter (Commonly used in ALUs)

A barrel shifter can perform a shift of any number of positions in a single clock cycle. It's
typically implemented using multiple stages of multiplexers.
Shift Amount (S0, S1, ...)
|
V
Input Bits (B0, B1, B2, B3)
|
V
+---------------------------------+
| Stage 1 (e.g., shift by 1) |
| (using 2x1 MUXes) |
+---------------------------------+
|
V
+---------------------------------+
| Stage 2 (e.g., shift by 2) |
| (using 2x1 MUXes) |
+---------------------------------+
|
V
Output Bits (shifted)

● Each stage in a barrel shifter performs a specific power-of-two shift (1, 2, 4, etc.). By
activating combinations of these stages, any arbitrary shift can be achieved.

7. Processor Unit (Datapath)

The processor unit, also known as the datapath, comprises the registers, ALU, and the
internal buses that connect them. It's the part of the CPU that actually performs data
operations and transfers.
Key Elements of a Datapath:

● Registers: Hold operands and results.

● ALU: Performs computations.
● Internal Buses: Pathways for data transfer between registers and ALU.
● Multiplexers: Select data sources for the ALU inputs or register writes.
● Decoders: Used for selecting specific registers for read/write operations.

Conceptual Diagram: Simple Processor Unit (Datapath)

+-------------------------------------------------------------+
| |
| +-----------+ +-----------+ +-----------+ |
| | Register R1 | | Register R2 | | Register R3 | ... |
| +-----------+ +-----------+ +-----------+ |
| ^ ^ ^ |
| | | | |
| +-----|---------------|---------------|-----------------+ |
| | Internal Bus (Data Bus) | |
| +-----|---------------|---------------|-----------------+ |
| | | | |
| V V V |
| +-----------------------------------------------------+ |
| | Input MUXes for ALU | |
| +-----------------------------------------------------+ |
| | |
| V |
| +-------------------+ |
| | Arithmetic Logic | |
| | Unit (ALU) | |
| +-------------------+ |
| | (Result) |
| V |
| +-------------------+ |
| | Output MUX for | |
| | Register Write | |
| +-------------------+ |
| | |
| V |
| +-----------------------------------------------------+ |
| | Write Enable & Decoder for Registers | |
| +-----------------------------------------------------+ |
| |
+-------------------------------------------------------------+

● The Control Unit (not shown here, but generates signals) would control the MUXes,
ALU operations, and register enable signals.

8. Design of Accumulator
An accumulator is a special-purpose register that is implicitly used in many arithmetic
and logic operations. It often serves as one of the operands for the ALU and receives the
result of the operation.
Characteristics of an Accumulator-based Architecture:

● One operand is typically the value already in the accumulator.

● The result of the operation is stored back into the accumulator.
● This simplifies instruction formats as one operand is implied.

Conceptual Diagram: Accumulator with ALU Interaction

Data Input (from Memory/Registers)
|
V
+-------------------------------------------------+
| Multiplexer |
| (Selects Accumulator value or Data Input) |
+-------------------------------------------------+
|
V
+---------------------------------+
| Input to ALU (e.g., A Input) |
+---------------------------------+
|
V
+---------------------+
| Arithmetic Logic |
| Unit (ALU) |
+---------------------+
| (Result)
V
+-------------------------------------------------+
| Accumulator Register |
| (Holds previous result, acts as an input) |
+-------------------------------------------------+
 |
V
Output to Memory/Registers

● The accumulator acts as both a source and destination for ALU operations.

Part 2: Control Logic Design

Control Logic Design focuses on how the operations within the processor unit are
orchestrated and sequenced. It's about designing the Control Unit (CU) that directs the
flow of data and execution of instructions.
1. Processor Organization (Revisited for Control)
From a control perspective, the CPU organization highlights the interaction between the
Control Unit and the Datapath:

● Control Unit (CU): Generates timing and control signals.

● Datapath: Executes operations based on these signals.

The CU essentially translates machine instructions into a sequence of micro-operations

(primitive actions like register transfers, ALU operations) and generates the necessary
control signals to activate the datapath components.
Conceptual Diagram: Control Unit and Datapath Interaction
+---------------------+
| Instruction |
| Register |
+---------------------+
| (Opcode)
V
+---------------------+
| Control Unit |
| (Sequencer, Control |
| Logic, Decoders) |
+---------------------+
|
| Control Signals (to MUXes, ALU, Registers)
V
+---------------------+
| Datapath |
| (Registers, ALU, |
| Buses, Shifters) |
+---------------------+
^
| Status Signals (Flags from ALU)
| (from Datapath to Control Unit for conditional branching)
|
| Data (to/from Memory/I/O)
V
+---------------------+
| Memory and I/O |
+---------------------+
2. Hardware Control (Hardwired Control)
In hardwired control, the control signals are generated by a dedicated combinational
circuit. The design involves using logic gates (AND, OR, NOT) and flip-flops to produce
the required control signals based on the current instruction, status flags, and timing
signals.
Characteristics:

● Speed: Very fast as control signals are generated directly by logic circuits.
● Flexibility: Not flexible. Any change in the instruction set or control logic requires
redesigning the entire hardware circuit.
● Complexity: Becomes very complex for large instruction sets.
● Implementation: State decoders, sequence counters, and a large number of logic
gates.

Conceptual Diagram: Hardwired Control Unit

+---------------------+
| Instruction |
| Decoder |
+---------------------+
| (Decoded Instruction)
V
+---------------------+ +---------------------+
+---------------------+
| Timing Signal | | Status Flags | | External Inputs
|
| Generator |<--| (from ALU) |<--|
|
+---------------------+ +---------------------+
+---------------------+
| | |
V V V
+-----------------------------------------------------+
| Combinational Logic Circuit |
| (AND, OR, NOT gates implementing control logic) |
+-----------------------------------------------------+
|
V
+---------------------+
| Control Signals | (to Datapath components: ALU, Registers, MUXes)
+---------------------+

3. Microprogrammed Control
In microprogrammed control, the control signals are not generated by hardwired logic but
are stored as "microinstructions" in a special memory called Control Memory (CM).
Each machine instruction's execution is broken down into a sequence of
microinstructions.
Characteristics:

● Flexibility: Highly flexible. Changes to the instruction set or control logic can be
made by simply updating the microprogram in Control Memory. This is called
"firmware."
● Speed: Generally slower than hardwired control due to memory access time.
● Complexity: Easier to design and debug for complex instruction sets.
 ● Implementation: Requires a Control Memory, a Microprogram Sequencer, and
microinstruction decoders.

Conceptual Diagram: Microprogrammed Control Unit

+---------------------+
| Instruction |
| Register (Opcode) |
+---------------------+
|
V
+---------------------+
| Mapping Logic | (Maps instruction opcode to starting address in
CM)
+---------------------+
| (Starting Address)
V
+---------------------+
| Microprogram |<---------------------+
| Sequencer | |
| (Next Address Logic)| |
+---------------------+ |
| (Next Microinstruction Address) |
V |
+---------------------+ |
| Control Memory (CM) | |
| (Stores Microprogram)| |
+---------------------+ |
| (Current Microinstruction) |
V |
+---------------------+ |
| Microinstruction | |
| Register (MIR) | |
+---------------------+ |
| |
V |
+---------------------+ |
| Control Field | |
| Decoder | |
+---------------------+ |
| |
V |
+---------------------+ |
| Control Signals | (to Datapath) |
+---------------------+ |
| (Conditional Branch
Address based on Flags)
+---------------------+ |
| Condition (Flags) |-----------------------+
| Logic |
+---------------------+

4. Control of Processor Unit

Regardless of whether it's hardwired or microprogrammed, the Control Unit's role is to
generate the specific control signals that govern the operations within the Processor Unit
(Datapath).
Examples of Control Signals:
 ● ALU Operation Select: Specifies which operation the ALU should perform (e.g.,
Add, Subtract, AND).
● Register Load/Enable: Enables writing data into a specific register.
● Multiplexer Select: Determines which input is passed through a multiplexer (e.g.,
selecting an operand for the ALU).
● Memory Read/Write: Controls data transfer to/from memory.
● Bus Enable: Activates a specific bus for data transfer.

These signals are generated in a precise sequence for each instruction fetch, decode, and
execute cycle.
5. PLA Control (Programmable Logic Array Control)
A Programmable Logic Array (PLA) is a type of programmable logic device that can
implement combinational logic. It consists of a programmable AND array followed by a
programmable OR array.

● PLA in Hardwired Control: PLAs can be used to implement parts of a hardwired

control unit, especially for generating specific control signals from a set of inputs
(e.g., instruction opcode, timing signals, flags). They offer more flexibility than fixed
logic gates but less than microprogramming.
● Advantages of PLA: Reduces the number of gates required compared to discrete
logic, simpler design for complex logic functions.
● Disadvantages of PLA: Can be slower than fully optimized discrete logic, limited
size.

Conceptual Diagram: PLA Structure

Inputs
(e.g., Opcode bits, Clock, Flags)
|
V
+-------------------------------------+
| Programmable AND Array |
| (Generates product terms/minterms) |
+-------------------------------------+
|
V
+-------------------------------------+
| Programmable OR Array |
| (Combines product terms to generate |
| outputs) |
+-------------------------------------+
|
V
Outputs (Control Signals)

6. Microprogram Sequencer
The microprogram sequencer is a crucial component of a microprogrammed control unit.
Its primary function is to determine the address of the next microinstruction to be fetched
from the Control Memory.
Functions of a Microprogram Sequencer:

● Incrementer: Generates the next sequential address (e.g., for normal instruction
flow).
 ● Branching Logic: Allows for conditional or unconditional jumps to a non-sequential
microinstruction address based on:
o Conditional Flags: Status flags from the ALU.
o Branch Address Field: A field within the current microinstruction itself.
o Mapping Logic: For branching to the start of a new machine instruction's
microprogram routine.
● Stack (Optional): For handling micro-subroutines (e.g., common routines like
effective address calculation).

Conceptual Diagram: Microprogram Sequencer

+-------------------------------------------------+
| |
| Current Microinstruction Address (from CM) |
| |
| +---------------------+ +---------------------+
| | Incrementer | | Branch/Jump Logic |
| +---------------------+ +---------------------+
| | ^ |
| | | |
| V | |
| +---------------------+ +---------------------+
| | Multiplexer |<--| Conditional Flags |
| | (Selects Next Addr) | | (from Datapath) |
| +---------------------+ +---------------------+
| | |
| V |
| Next Microinstruction Address (to CM) |
+-------------------------------------------------+

7. Computer Design (System Level Perspective)

Computer design, in this context, refers to the overall process of integrating the processor
logic (CPU's internal structure) with the control logic (how the CPU operates) and other
system components (memory, I/O) to create a functional computer system.
Key Aspects of Computer Design at a High Level:

● Instruction Set Architecture (ISA) Design: Defining the set of instructions the
processor will understand (e.g., data types, addressing modes, instruction formats).
This strongly influences both processor and control logic design.
● Datapath Design: Designing the internal components of the CPU (ALU, registers,
buses) to efficiently execute the ISA.
● Control Unit Design: Choosing between hardwired or microprogrammed control
and designing the logic to sequence operations.
● Memory Hierarchy Design: Integrating caches and main memory to optimize
performance.
● I/O System Design: Designing interfaces for communication with peripheral
devices.
● Performance Optimization: Techniques like pipelining, parallelism, and caching to
improve execution speed.

Essentially, computer design involves making trade-offs between performance, cost,

complexity, and power consumption based on the target application and requirements.