Lab Report 02

Characterization of CMOS DC Analysis

Date: 26-Feb-2024
Objectives
In the following exercise the aim of this lab will be to be able to draw a basic circuit,
be comfortable with various cadence tools and to observe I/V characteristics of an
NMOS transistor using TSMC PDK. In doing so, the following in the Cadence Virtuoso
design suite will be explored.

• Schematic drawing and editing tool

• ADE (analog design environment) simulation tool

o DC and transient analysis

o Parametric analysis

o Calculator tool

Tasks
1. IV Characteristics of NMOS
1.1. Introduction
The I-V characteristic analysis of an NMOS transistor is fundamental to
understanding its electrical behavior. This task involves simulating the drain
current (ID) as a function of gate-to-source voltage (VGS) and drain-to-source
voltage (VDS ) using Cadence Virtuoso. The results help determine important
transistor parameters such as threshold voltage (Vth ) and transconductance
(gm).

1.2. Components Used

The following components were used in the schematic:
• NMOS transistor (from the TSMC PDK, e.g., nch or nmos3v)
• Two DC voltage sources (vdc from analogLib)
• Ground (gnd) (gnd from analogLib)

1.3. Working Principle

The NMOS transistor operates in different regions depending on the applied
voltages:

• Cutoff Region: VGS<Vth, where the transistor is OFF and ID≈0

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 • Linear (Triode) Region: VGS>Vth and VDS is small, where ID increases linearly
with VDS.
• Saturation (Active) Region: VGS>Vth and VDS is large, where ID is nearly
constant and controlled by VGS.

By sweeping VGS and VDS , the transistor’s behaviour is characterized, providing

insights into its operating regions and electrical properties.

1.4. Schematic Diagram

1.5. Analyses
1.5.1. DC Analysis
In the DC analysis of the NMOS transistor, we swept VGS while keeping VDS
constant to observe the drain current (ID) behavior. Using the Calculator tool,
we also derived transconductance (gm) to evaluate the transistor's gain
efficiency.
1.5.2. Parametric Analysis
In the parametric analysis of the NMOS transistor, we varied VGS across
multiple values while sweeping VDS to observe its impact on drain current (ID).
This generated a family of ID -VDS curves, revealing different transistor
operating regions (cutoff, linear, and saturation).

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 1.6. Results
1.6.1. ID VGS Characteristic curve and gm curve

1.6.2. Observations
The DC analysis results showed that the NMOS transistor starts conducting at
the threshold voltage (Vth), with ID increasing exponentially as VGS rises beyond
Vth. In the cutoff region, ID remains nearly zero, while in the saturation region, ID
becomes relatively stable, controlled mainly by VGS. The transconductance
(gm) curve highlighted the optimal biasing range, where the transistor
achieves maximum gain.
1.6.3. ID VDS Characteristic curve with varying VGS and gm curve

1.6.4. Observations

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 The parametric analysis results showed that as VGS increased, the drain
current (ID) also increased for a given VDS, confirming enhanced channel
formation. The family of ID-VDS curves demonstrated distinct transistor regions:
linear (ohmic) at low VDS and saturation at higher VDS . The transconductance
(gm) varied with biasing, helping identify the optimal operating range for
maximum gain.

2. IV Characteristics of PMOS
2.1. Introduction
The I-V characteristics of a PMOS transistor help analyze its electrical behavior,
particularly how the drain current (IDI_DID) responds to variations in the gate-to-
source voltage (VSG) and drain-to-source voltage (VSD). This task involves
simulating a PMOS transistor in Cadence Virtuoso to observe its operation in
different regions (cutoff, linear, and saturation).

2.2. Components used

• PMOS transistor (from the TSMC PDK, e.g., pch or pmos3v)
• Two DC voltage sources (vdc from analogLib)
• Ground (gnd) (gnd from analogLib)

2.3. Working Principle

The PMOS transistor operates inversely compared to an NMOS transistor. The key
regions are:
• Cutoff Region: When VSG < ∣Vth∣, the transistor is OFF, and ID≈0.
• Linear (Triode) Region: When VSG>∣Vth∣ and VSD is small, ID increases linearly
with VSD.
• Saturation (Active) Region: When VSG>∣Vth∣ and VSD is large, ID becomes
nearly constant and controlled by VSG.
• By sweeping VSG and VSD, we characterize the PMOS behavior, helping
determine key parameters such as threshold voltage (Vth) and
transconductance (gm).

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 2.4. Schematic Diagram

2.5. Analyses

2.5.1. DC Analysis
In the DC analysis of the PMOS transistor, we swept VSG while keeping VSD
constant to observe the drain current (ID) behavior. Using the Calculator tool,
we derived transconductance (gm).
2.5.2. Parametric Analysis
In the parametric analysis of the PMOS transistor, we varied VSG across
multiple values while sweeping VSD to analyze its impact on drain current (ID).

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 2.6. Results

2.6.1. ID VSG Characteristic curve and gm curve

2.6.2. Observations
The DC analysis of the PMOS transistor showed that ID starts increasing in
opposite direction when VSG exceeds the threshold voltage (Vth), confirming
the transistor's turn-on behaviour. In the cutoff region, ID remains near zero,
while in the saturation region, it stabilizes and is mainly controlled by VSG. The
transconductance (gm) curve highlighted the most efficient operating range
for gain.

2.6.3. ID VSD Characteristic curve with varying VSG

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 2.6.4. Observations
The parametric analysis of the PMOS transistor showed that as VSG increased,
the drain current (ID) also increased in opposite direction for a given VSD,
confirming stronger conduction. The family of ID-VSD curves highlighted the
transition from the linear region (low VSD) to the saturation region (higher VSD,
where ID stabilizes).

3. Acquiring double derivatives of gm curves

3.1. Curve for PMOS

3.2. Observation
Taking the double derivative of the ID vs. VSG curve helps identify the region
where the transistor exhibits linear behavior, meaning that the rate of change of
transconductance (gm) is stable. The result will show a range of VSG (or VGS for
NMOS) where the second derivative is nearly constant. This indicates a
predictable and well-behaved gain region, which is essential for analog circuit
design, such as low-noise amplifiers and precision biasing circuits.

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4. Linearity range behavior of NMOS/PMOS transistors against
varying temperature
4.1. Behavior for PMOS

4.2. Observation
As temperature increases from 20°C to 60°C, the drain current (ID) generally
decreases due to reduced carrier mobility (μ) caused by increased lattice
scattering. Although threshold voltage (Vth) decreases, leading to an earlier turn-
on, the dominant effect of lower mobility results in overall lower ID in strong
inversion. However, in the subthreshold region, leakage current may increase
slightly due to higher intrinsic carrier concentration. These variations impact gain,
power efficiency, and circuit stability, making temperature compensation
essential in precision analog design.

Conclusion
• Began with setting up file system for the circuit block
• Schematic editing tool was then explored and drew a circuit for
characterization
• Explored the ADE for DC analysis of the circuit and schematic node
annotations
• Used Calculator tool for post-simulation analysis
• Learned to use parametric sweep tool to vary more than one variable

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