1.1 GATES Getes are the means by which logic signals are switched in or out of digital Circuits. The gate is either closed or open according to the voltage level applied at its input and since the gate performs a binary operation ie open or closed there are two Sane sonding voltage levels namely § volts and 0 volts. The two states closed or ‘Open can also refer to OFF or ON and the two voltage levels are usually referred to as HIGH or LOW which are signified by the binary digits 1 end O. When 1 is taken as HIGH and 0 as LOW the Circuit is said to operate on POSITIVE LOGIC and the reverse Ease gives NEGATIVE LOGIC ie OV = HIGH, 5V = LOW. Positive logic is the more usual and popular operational mode and is considered in these notes. Gates perform the following logic functions namely, NOT (INVERT), AND, OR, NAND,NOR, EXCLUSIVE OR (EX-OR) and EXCLUSIVE NOR (EX-NOR) and these are explained as follows. 1.11 NOT GATE Function Y =A” ~ An event A not occurring produces the other event Y resulting, A ts Yea ‘Symbol Fig 1.11 Truth table inven |v) 0 ft 1 ° Operation: The output is the ‘invert’ of the input logic circuit, Uses: Mainly to invert logic signals.1.12 AND GATE Function: Y = AB The event Y occurs only if A and B both occur. 4 Symbol: s—)— Fig 1.12 (i) Truth table: B oY 0 Oo 4——>— 1 0 ae 2 oO ° 1 1 +-400> Operation: (1) If an input is lett at logic O then irrespective of the other input the output gemains at Logic 0 but when the input changes to 1 the Output simply takes the value of the other input ie the other input is enabled to pass to the output. (2) Only when both inputs are 1 does it give a 1 output otherwise it remains a O at the output. Uses: Based on operation (1) if data is applied to one input the other input can be used to control its flow ie one of the inputs is used to switch on or off to the output, data from the other input. A sot of AND gates can therefore be combined to switch a given code * ofdata as shown. ye Fig 1.12 {ii) Oo @ inhibited state) Oa! ats as the : output, ForB =0 output For8 = 1 output << ou =osue Operation (2) allows it to be used as switch to another | Output is @ switch O or 1 to another circuit A 8 * * _Y switches C toZ or inhibits it depe 00. This can be shown to have the si gate. A B ‘On2 © 0 0 0 This givesz = ABC 09 © -1 0 ieevent Z occurs only w oO 1 Oo A A and C all 0 1 1 QO 1 Oo oO 0 1 ° 1 0 1 1 0 0 it 1 1 1 1 ° Y= AtB ee Function: (OY ay aceite enene ‘symbol:Truth table: ==00> B oO 1 ° 1 Serio Operation: (1) Ifone inputis at logic 1 then irrespective of the other input the GutPut remains at logic 1, but if the input reverts to logic O then the output simply takes the value of the other input. (2) As long as any of the inputs is 1 the output remains 3 1 but when both inputs are 0 the output becomes a 0. Uses; This is used similar to the AND gate to inhibit or enable a signal tO Pass to the output. Oniy in this case the input state 1 resulting in Gn OUIpU state 1 is the inhibited state while the input state 0 is the enabligg stete that enables the other input to pasy to the Output, This as we can see is based on operation (1). Thus the OR Gate can similarly be arranged to switch ON or OFF a given code of data as shown, As A2 Al Ao — Fig 1.13 B=-1 cee UTNE. <(inhibfead state) Beto = AL Az At Ao (Enabled state << < Similar to the AND gate, operation (2) allows it to be used as s, stago oF circult ie Its output Is a switch 1 oF 0 to enother cin inhibiting or enabling data sent to that circuit, +h {0 another cuit therebySato) or 0 fespactively which in wun {can bé shown to have o simitar truth table to a 3 - input OF Buon SUeeS =-00--000 Function: Symbol: or : dopending AB = (01. n inhibits oF anables C 1 z © This gives the function as. 1 "2; mein tere 1 {othe event Z occurs it any 1 Of A or 8 or © occurs. 1 1 1 1 =o-0-0-00Truth table; A ep y 0 9 1 oi le Omura st meno Operation: (1) When an input is at fo the output stays at to, the output is the inve; gic O then irrespective of the other input Gie 1, but when the input becomes 1 then Ht of the other input. (2) When both inputs are 0 the Output is 1 and when both inputs = 361 the outputis 0. Uses: ne io ee Fig 1.14 (iy (0) Inverter B permanently at 1 gives Rat the output. Also based on operation (2) it can be used as an inputs A and B together to form a inverted at the output. inverter by tying both common input X which comes out A ape! Fig 1.14 (ii)ge As in the AND gate and OR gate we can combine a set of NAND gat ‘switch or invert a set of data inputs representing a code of information. B=0 Bet Function: Y = g@ AFB The event Y occurs if neither A nor B occurs ie if A occur. A Symbo: 8 Truth table:Speration: (1 Asiong 43 Gre of the Inputeie at logic 1 thon irrespective of | the other input, the Output remains at 0, but when it becomes a O then the ‘Output is the invert of the other input. (2) When, Doth inputs are © the output is a 1 and when both 'MPULS are 1 the output is a 0, Uses: Based on operation (1) it-can be used purely as an inverter or as an inverting switch. (9) Inverting Switch (0) loverter A. =p i Ber vio vam BS Oia x Fig 1.15 (iy Also based o both inputs A and fomman input X which comes ‘Out Inverted at the output, De\ Symbol: Truth table: Operation: (1) When one of the inputs is at logi the value of the other input ie it enab! a pass. Whon the given input becomes a 1 the output wert’ of the other input, Uses: (1) Based on operation (1) it can be usad.to a circuit or to invart the data as shown, 2 o uy = 61, “aU8l the output is 2.0 but when they are unequal the output From the wuth table we (PServe that the EX - OR function can be written as: Vas Function, oy 7_ AO __B = Aog The event Y occurs it neither of a and B oceurs oF both A and B occur. In other words it doze NOt occur if A oF B alone Ie occurs, hai) Ng Symbol: 8: Fig 1.17 (iy Truth table; a ++00> 8 ° 1 ° 1 soo4K< This is seen 10 be the ‘invert’ of the EX - OR gate function, Operation: (1) When one inputis at logic 1 the outpui takes the value of imesother input but when itis 2t logic 0 tne conven is the * invert’ of the other input. (2) When both inputs are oqual the output is 1 but when, they are unequal the output is 0. leoe W a 3 e ‘We can use tha EX-NOR in the seme way as we did the E: OR ie based on operation (1) it can be used to enable ¢ OF invert the data es shwon* In this case the enabl inverting signals are the opp {ean also be used as a comparator based on operation (2), Case the output ingicates a 1 when the inputs are equal and a 0 they are not equal. ‘We also note from the truth table that the function can be v 38 Y= AE ap hos Many more uses abound for all the gates mentioned they are all dependent on the basic principles stated abcompanarons = \~ JOR functor shown From the truth tables of the EX-OR function and the EX-NOR function shown bel w it can be observed that in the case of the EX-OR s00> -o-08 ons0< +-cop so-0a ~oo-N the output is a1 only when the wo puts are unequal whereas in the case of Ihe Earn toe) eutontl la: donly, wien the iwo gipucs’ ere equal hi property can therefore be wed in constructing @ comparator for the two variables A and B. The function of the EX-OR is given as Y = AB + AB while that of the Ex-OR it 25 AB+ABOrY= By AB From the wruth table of the EX-OR it ean io noted thar the entry RB which has A = © and B = | indicates that 8 > Aio.A <8 Steirly Mo entry AB which has A m Lond B = 0 indicates that A> 0, Tru ners in these entries separately: will give tno two inequalities, white combining them by @ NOA gate to obtain the EX NOR function obtains The simplest circuit is as shown below the equality 4 = 9 A partial NAND gate implementation of the above is as shown below Hate The NAND gate implementation of ho EX. OR by ise guts « comparator The above case descrived » bi comparator, Suppase exch of the compara vortables iad two bits 1.0. AsAA, e+ 8,6, art(2) gmnarly Presting key 2 only eng 'y enables gate 1, pressing key 3 enab) enables gates Dy nd 50 09. 8 Do? N AZ Fig 2-34 Lacocker Citcuit A AB A>é (iF AB=I) ipicot logic | La see die he int=() Y eee FB Acalig 8-1) 8 _AxBGERE<0) COn ge +6 AB inplemtrdation » (if 8: 78=0) £5 (if 20) 8 fig 2:35 Comparator Cirdai és =nen if the magnitude of the highest bits is (eSted and one of them is greater, the corresponding variable is greater, ie. if A, > 6 test Ao, 8p. Similarly if the most signiticant dit of one variable is loss, = Bile (A, < By) > u @ 0 (AL= Bile (Ay = By ‘TRUS representing the previously obtained one bit comparator by @ block ihe Gisgrem below shows how two one-bit comparators can be combined 10 forma two- bit comparator. “Similarly any number of bits can be compared by combining @ number of n- bit comparators. As A> A>B Ai=By 8 ] Ae8 Ao boi. ne ug ADDERS 1, HallAdson: The halt adder produces a sum § and a two inputs A and B. This is shown by the functional block below: 'y C lrom the addition of The circuit to achieve this tunction is obtained by considering the truth table for an adder shown pee A "4, @ 2 full adder is as shown: A (8 ols EG vehwre Cl = Carry input 0. (0 = 0g oN So Co '= Cany ouput 0 Dae eo 01 oe Oi ae oe cues 1 2 Oe 1 oO 1 ° 1 Mere feb 1 1 #7 aS The sum output has the function: S= CAB + CAG + C[AB + CiAB 2nd the carry output has the function Co = CLAB + CiAB + CAB + CAB ‘Thus the carry output is simplified 10.Co = Ci(AB + AB) 4 ABICL + Gy CIIA®B) + ap lows: Eeralel Adder; Consider the addition of A ana B which are (wo 4-bit variables, Each of the variables is held in a storage register to he gated in to the 4 uladdel are iy tequired to add each peir of bits. Also the carry from a fowor stage is directly fed to the cary input of me next Stage. Consider the variables to be A= ALA,A, A= 1011 B= 88,88 =0110 Then their sum is observed to be 10001 The adder obtains this as follows: 2%Clock, A (9 2-38 Parallel Baldo Dely pr bat Fig 237 Serial Relctes eafle. Kader ih , to At time (0 When the bits are presented to the full adders the addition of Ay, By gives 103 the Sum Sp and no carry/i.e. Ci = 0 while addition of Ay, 8, gives the sum §, as and carry C, as 1. Also Ay, 6; give S, = 1 and C, = 0, and A,, 8, give S, = 1 and G, = 0. However aftor an interval corresponding to the Propagation delay of the adder, thacarty C; = 1 {tom adder (1) wil pass 10 adder (2) changing the sum of that adder from S; = 1 10S; = 0 and also generating a carry so thot C3 = is changed 0 C, = 1, Again after another propagation delay the carry Ceaser (2) will pass to adder | £8) changing the sum of that adder from S, = 1 10 $5 = Oano also generating a carry CG =1 Thus the final state of the output of the adder is GQ 8, earEEUINES Ji) a which is seen to agroo with the value observed earlier on. ‘This tyPe of adder is also reletted 10 as 2 tipple through adder since the carry ripples through the stages. | Serial Adder; Consider the addition of the same 4 bit variables A= ASALA, Ay = 1011 8 =8,8,8,8,-0110 Those wil be stored in shift registers so that each pair of bits starting from the {east slonificant pair is shifted into the full addor to be added. The sum output trom the adder is also taken to shift register so that each successive sum is chitted right towards Its proper place tually. Also a D-type latch (tip flop is used). This holds “Dota bit at ks D Input until it receives a clock mput wihere upon this is passed to ns 30a ouput. Hence it finds application here as 2 delay element which dolays the carry output from the adder and delivers it to the Carry imput of the adder at the audition of aig oust Pall OF BIS When © clock pulse feceived, The ciel for eaTEIe am 5 perefore as shown below, av given moments in time the clock pulse enables the acuvity involved in the agdition. Let these moments in time be denoted PYRG = 0, 1, 2,3, 4) so that ingiestas the tlme before the first clock pulse while t, indicates tha time during the {ust clock pulse-and so on. During tg the input to the adder is the pair of bits 4,. 8, while Ciis 0 initially because there is no previous. carry initially. The sum output of the adder during ty S.vrhile the carry outputs that which wil be adéed to the next pair of bits and hence appropriately denoted Ci + 1, which since i = 0 is C1, When the first clock pulse arrives i.e. during time ty, Sp which akeady appeared as the 1st bit left in the § registers from the last addition is now shifted right to the next cell, the Contents of A and B registers are shifted right with O taking the place of the left most bits veeated and Ay, 8, becoming the newiinputs to the adder. Also the clock passes C, at the © input of the batch to the Q cutput so that C, now becomes the carty-in Input to the adder. During this time interval the sum output is S, while the coiry ovr 's C;, The same procedures describe the activi tabulated as shown below, Consid the added variables to be A=1011 and B=0110 /hen the above table becomes(EEE) ol -EE oyoyiy-[- of olor y— !{ofoTe TT] Those bree = thetof thaG easier e110 O10 Tac Note that the eam as AoPk pRBA reared ISTE weoon nia upper TRA be added ang also note thet the final earry bit becomes the most significant bit sa1 J i gt Dieductey Cmncopee i lopie Chex Denn he egos KMS halt 1h Xe comparing ced’ b Inferno! loo,¢ A fi ; 204 Ens , and i honk tehion of Pome fogre CHO oO fea i osteo bf Ho Las Com Pp Ong he wag ~ % 8ECH05 We Cong, oles rules and J? 2Ceel.2.05 tal erable he sign of base Cogie a, a @ Phase by Cone rcltting to fillers hagie rules and Weoreing « pasicesed /n + jx ie eae X#tx = x Xf] = | te fe) xR =o Kt One XtK = f Xe9Z = & F(x +z) Proof (K+ 1)(x+Z) = Kx\ i) RASA aat 6 Se ee Ve Proof KAY = KC A) = x DRO — CSA = XE KAN =X (14 Ay) = % fi) a xT A+y Proof: on X+yz =K&tWx+z) het @- xX hen Nees = &+Y)(X+5) = xLY fv) XY4XI = K” Provf: AY 4txF= XCY+F) =x () Kt(x+9) =x Proof. fef Z=4 19 X#422 KEYW(x4 2) Tan &ENCx ED = Xt4F =x WW xtxe =x fe KEK ix Gey Wi) X€x4+4) =X &@ An+xY= X+Ky-y Wii) GEDDY = XY ve xY+YY = xy 1) See TR as S Known as Do Mow Gan > HCV in Another form of the Heovod’ is W XYZ = K+*V4Z Bt‘i CorS0rBe8 Zecrem @ Qy 3 Ri tat AZ & XY ake poof XY +b+4X)yZ 4 RS Dey ee wr 2)#®zCiey) Kk YZ is refundant ky) Con8ensus Fecrem @ CDC Tre « Capea Proofs OC+2XR +2) =O +x2)R +2) Wz xz XX EYE AND age K(x tye 2X4 4) = &HY)(Rtz) Tug & PINCH) +2) c CAYC wo on tat specifies ha yy fact have A gales than the Via. feewh 4 4 botean A. ofr, DO 8 Welt Sati. of ho Puncher. We Ghes be tho \vt \ \ | pooh us & mingncde [logic &kPrestren, ) ty pata in ple, ey f feo Cxanplos i Pont. Fxanple hEED + 4aCS Aalkas ln £4 Cage a fom eae 2b eee =x ay. fo Hap Cay 4 ee reolucea te ABD & PEP(C +2) = gaz Prample 2 46+ ABC 4 IED can 66 reduced! 7, [enplorey the rile XAKY = XK sfuccow/ vel, jwolow 2B= x v |%2, we have Aglire) +482 | = 48+ 46D = £8(/+d) = #6 Rample eS fo untnewsn Aigrtal CesCust voit, 3 raputs land oe batpet tas bested! and produced Ae pOsults Shown in the tru Fable. Of 42;, he ig, pest conpigusation Of KA cistuit 36t Soluhon o Y= hic + ABC + ABC 4 Aa ! = @ - 0 = 8C(A+A) + aglere) | = AB+ Bc Q { A 0 I lo thi S example we pote har he exiginal ex pression +@ Pr08 0.47, Enc hen of the fiuth table hag 9 the} of epht gates, re [bree Oe Pork AND ates And one Ok- Wa; wWurle Ke FCMLOM aise. 2h ebteans pod IO Ae2. “Tha example alte chews that tke cesjgn of a Combinahonal logic cist 6 dono 6 fist: 8bfarn eae, 4ab6le of te per Cmdihiong ald thoes Cor, re2POnd a SutPu® then In An An @x[reIKon rOl(AADYS pe Putpadt (whanih is rede) & Ke input pr Obs eu 9 EP» RATA RA MiSs Prllosed by rectuc, he eOxpressScon & obtain @ ie J Citik af mploments ae Exampl : 0 may use he PPh that xux =x Mlude aur extra Loin an OXPr esseon, Yo foci Late chs reclucho. ag Shes ds The ilo 1 ARC FABC ACH one nec See nical) owe pyc sane ‘ Sr xb) 70° I neCar®,wple 4 Conte, Lb fe | ac + PBCH ABC + ARE 2 nc (BtB) + 8ce(ara) f Acre a9 i ie ample 5 E Cedanclant On en, bp Clinina eof kL apy ap A Coss ee ae he _ plloring: 4BG +Bcp y+ hen Na Cons enous Reorem js Given as XYAV eRe a XY+Rz AUN SOMO ETT ry “> HQ CX PreSL0~ to Lot, Porne ve C0 lene ted anal uncomplene~ ted and (de, “ny Chace & M3 Case € & par vasakle hue ep @ = x hen BDay sees AR-= Zz We horefore have BCD= xy ye ABC = eZ AbD = JB. BD = yz ; hus KBD is te redundant perp Pelt eSnkig YZ th KQ Con8ensus theorem Tercfore BBE 4B6D+ ABD = Poche MOINISa he, ABE + EcDd Boolean | (an ales be PTEA (And possrte, Pk) | Dic tori ally by milange ef Ko Karaugé DapA 4 a7 Winteem Max 109m’ anal Karnaugh, 41a s - ni AE a tec vanabl boolean fuanC tide, oe X2)- Each of ke variables Aas logre Skakes a ano Ome Ky 21, 120 : =1,%2> 2 flus he Aoo parviateias be tonhined! 07 of & possi iL AND Chons — XrXe , Xa X) XoX), Xarks- he tar alsoMbenCo:. Leeman of # possible ‘De fant hors, (ex) Con (x2 4%) and (tg 4X7) - Similarly a 2-vavagle Loolar func hoo Y= fExK2X1, x0) Can be combed a any of 23= 3 Ppess: ble AND farChions aS well as Pye Tira aos 12 Whe possitle AND farthOnS atl - Kaki ke, Kakixe Ras Ko ars Ke Yak Re Kaki Ke, KaXi Ko, Xa x) ho while HL Peed oR [Ce aAze:— Oe, + Ko), 2.414 Xe), (Ra +X1 + Ko), K24X + Xe), Katt Ke) Katkit te), Katxt+Ko), X2+A/+ x0 Dus? Gr 1 YaAHaAble function hag 2? Stales 98 conclifions - fonclifions oCcuf AS Product Lams (and funchons) a are refed t as minreems and whan ogcut AF Sums (OR f., chara) hey are Hey 2 fe 23 MaKXTEeMS | ee and maxfleims are (ark koa by OSS ble blhen those ule or Oeeimet gk ni Valent! A9 Bown and we het each Uifesal oy he martkeim 79 aneeal in a pyyhesm, : He Genres peiding th AatZtex. Mo XatX+Ao My Hat ¢Xe wr X2tHit%e Ms X24+Xi+Xp My Kot %o Ms 22+X+AXe Me X2t Kit Xe My 3° 0 0 0 ! t 1 t It iS ob8erved hay Mm, = Aa Xe = No 4+ Re = M7 Smilasly Me = Me Mss c/a CO ae has a MAxreem CSG ice of a MNTERM tod 10? versa 2 Bellean furcher say Y= HX Xe + Xa Xe t 22 Xe S00. TOC cae Mie Me yi sey cane Kined a ghandasel Gem uf Pre cte, torre, 2S GE En, “ Mst+ Mem, of ZUL5, 6) Sori dealy FE MCL Ye ENE Picdaee S naxkesme agua &S hesmod x Shan clas A Prodlac é Of Sums R Oren. as Z= Wim) = HU, 5?) ve mM, me 1¢ a \fe fa fru Kainaugh maps le Min LO§mS Or A represen reel We cay hore & 48 $ Sho. 4 bor af Shown and te napping of aa Of boxes Produas a a~ple a Avo vasiakl be re prese. 40d oo BE Lown Kainangs ep ae ey | fruth Leb og, 1A q th ree ef a ta 4 wht, La ble Can 60 Onleped i 4 Lab te @ soz We cantepresent ke ud Ad re map * ‘Tetfowss 0 varraAb@ Kase augh S02 Oy [ome Te Tra [oe] Nola in Ais cae thar adjacent boxes differ by ee teral (J bk) Only and ths 13 he trdamental rule ConStruchn wle Wis coe yas, a bQ ty uth table Gos Pee 27 x LLImS and store fore — Qe) boxe 4 map. e elaine yavate eee vatable Lasnacgh maps AS GLO. f- ee fe oo or ic 0! oo or it a u 10)WS pr v A a 4 Variable map 4a the 3- vasiable “ap PEON 3- vasia kip S Covre, Durs fe Cxam ry Age Bt fact Mm in te FESC LAKE. oD. say pnilarty PLED Ig im The PEM OW8 K- Vas all; y Which «$ ABCD = sror = 13 frre vasiakle ps SIK- VASia b@ MAPS Cor be Mini /aaly POpreseted BF may have Wcsal tomes prcles ma ps Com posivng Foe » OXAmple a F- viarsiatle map can have hoo Wk - vavatle maps “hile « 6-vasiabl fia Ca have pe y-vasiahl naps MP Bln tog if Ke use of Re Karma. Minimise a beoseai, (lepre) Mo consrclesed. Wwe ey es hak to Minkein? fala om he val0 7 whe, we Winch oe, by 2a fd ‘CAS 15 & & TRUE (haga, Oe Put 7) and Ke M ho 4 vasfable Map is ‘ Er eSOnhak 42i) % HW 1SE (KAS An Ontp, . re ae, Pot O)+ Ra gum of produc pre LEPTESES 7CRDOL oe nile ate wd Re prectice © io )¢ Stem g represen. rshan maxt2ime AiO 1 or mnleins ay O- We yyreneet the fomes Case soit 1 bn he ininagh map ard the lates with O jer ho MAaKkhe§mo) - iy go exam ple Ye APBC+ ABC + HEC + FBC represe~# fo Sum Of min heims 211160) oe t shown be WL FeHras Sf map as 6 ooo “ J ies 7 (ae Cc 10 Sinslasly Y= Grover rare nnrereareed) artons 77 (0,5, 1.6) pope cen i2 Ae prodact of ; oO ‘eB Ye we congicles Y= ABCD+ ABCD ed cs 10 C56» fact by minteins fy ad Ing and | p0mezented On Hho KAIn Sue We Puce FL oan eee cos ¢ VvSwowoY 12 \ | pining The two OnOS sols @ P we noe Or ai bles thah 700» bf ABs FOup th be Pec bil Po reduadant Lecause tha rep toss in 40 Dard dD. plo nolo Aowoves ie Boolan algebra that PACD +ARID = PBC(D+D) = 28C Gus #2 COrbirahs., Of %0 fe ink a grap Pra bles tha eminahe, Of redan das ‘yaaa bles, Aence facylite Les min aise of a farChon : fe following set ef nites Apply 2b0n Gro. pi. a wal Le Fae a fonchien ~ 0 Gr "G4 Atl nade suck Bak to unt, fo gnc enh @3 oe Can onby £2 owes fae WA #8, 16 ee bk aos 3,6, 10,12 eve D bul adjack./ Press o ent le3 Can be prnpe Zopehes BAR Cant enAvep feng Hoge wotith have gno ditesal Change bebo 001, Horny and Beitfone be hex} bh eget phar in Ht FAME FOX oY Column whe. thy map is wrapped youn iH3ebf ‘ D Face, elegy m3 belong b the farpest o> Ping Posse - 4) Py ProP S enbr ies chrch has al iG Ctries also bbls & obey growed cs & red. dat romp % & Cwespo-le T. a ~ f1% 1 pprStn Sus HRoro.,, 7 s fon fos in bovka,, kagnaugh Maps fran ple / MinrmiSt W2 give, Boolean favction a“siog a heea te Mme L9Chon minimisahon wrth oy Matin SQ bron wrth, fli, cP)= Abed + FazdLAaED H-AGED ¢ ABED.+ AGED | Sola bon 7a Lap represen pation of to fon choo = 28 Ghoion anol U2 min looms s AN ae qe eee ag Phowon > ed Ss | | —s | Group X gives Bed A 8 redundant | Group Y pees AC 6,2 aw redundays | Grenp z ges BED A 18 retundany here fove Ke min ton ter Pirctios é& bbLen ef a fe Nor B2d7 BER x aa- at yo an ple 2 (a Q ninmun, eK Pression. por to plloorg firchion fe loon 1 6a Aen eee in hen Mn tlio’ are re presemven pea ke nep BP Shoo, . ol, we Sods | o ele (> | oa iy ; vor, P vee | sense | iL | Group 9 belongs te both P and 2 anaf & j + & 1 0tlin Aan!, 25 efore Gaving ry aes Pee se Sic) yee Zo wee Him © far CAE rs, hiner at Pier Gropp P gives B24, shen Gop R gives As 4x fanser eh Group & pe Az Az a the TA Rie 4 Basle Ch AT AL Ay a — pints Ri cugghte’ Rate"! fa fat 2 ts He |Rec. :. = » Sy 155 / gore pnnise #2 Crbla. f..ohs., GHen 2 fe TMCS, 4557,9,00,13, Hi5) on Ee K- map & chhained AY Shor, mbing ta fre - thak mexteims aw nite quot Hers entries repr egeAy Ko pre? hams 2% indicated! y on 4 = 5 tho “ a 02 Ol yt 10 PAR < ate © ' o0| pl aggro <4 Kena ® @)| ecco lo oO lt shoul! be rofedl tar ite Iilesals of a may lerm Bil TKO ComplemOnt of hose of @ fin Loam. ees fer 4m frlo Vine P. world . [have “minkeins ABA Ro but for a Marlesm Wis & Bz fh, Po = AZ +4, +A. Bins faaly Grenp 0 es Bat Ne ee R “gues As + A, + bo 201 (Pomp Z fe AS ee oe Titra lantern, footer &s = Oavartacy(Ayt it Bel As +3 + A.) (Fat Bo) | he2b 76 . S a frchor 8 uncettar, 5, oe ie . ae S oxipn. hase Don 7 Cage e tn 0 keoap ps cher minfernre ef Tho jun as i HO XG 220 onl, aac He 19 b Complale 4 Riso are not n0D bint igs a4 Thon. ves. ta "ed pas fee b. a Zo peep Reed ue 2d Pe he res lh Chon ae eet hap & shore -fove obtained 29 EDPAD 2 cH»Ir co a > : aX 1.2 FUIPFLOPS ‘These are logic circuit olements whi quence thus creating a delay in propag membering the logic signal for onward pr Fe externally stimulated or occur naturall frat the signals change in a time sequon pmployed to act sequentially and are thus Ich produce signals that change in a time jating logic signals. This delay amounts to ‘Opagation at an approp 'Y a5 @ feature of the component. Tho fact ee sakes the circuits in which flipflops are setae tera tsa teen nee ogu Man synchronous Pircuit, whilst it is referred to as an asynchronous circuit when the time Geay occurs Naturally as an inherent feature of th fe is opegating through the circuit). e Components (ie the delay is self Flipflons themselves ere built from gates and the various types are described. 1.21,S RELIPFLOP Of LATCH Fig 1.21 i) o Fig 1.21 (i) Shows a NOR gate implementation of the S R flipflop where 1wo NOR gates are connected in a feedback loop. O is the output of the fliptlop and O its complement (ie invert of Q). The S and R are the SET and RESET inputs respectively which set Q to logic 1 or reset it to logic O. Thus the present state of Q is femembered for as long as the S and A inputs do not chenge. ts operation is explained as follows, When S = A = 0 then according to the operation of a NOR gate, gate 1 will have @ at its output ond gate 2 will have O ax its output and so whatever values Q and O had would stay maintained by this input corcition. When S = 0 and R = 1 Q will become a O and if it was already O it will slay a5 0 while the output of gate 1 will become 1 io G = 1. When = 1 and R = it was already a Oit will stay as O © the ourput of gate 1 ie @ will become a 0 and E while the output of gate 2 ie Q will become a 1 and if it was already a 1 it will stay 5 eel ( 2. ool ae 01 \° \o \e Nor 0