=a) 19 PRACTICAL EXPERIMENTS PL. Familiarization of Xilinx software P1.2. Familiarization of FPGA/CPLD KIT Software Requirements: Xilinx ISE 9.1i and above series; Hardware Requirements: Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board; Verilog code simulation using Xilinx ISE 9.1i and downloading to FPGA/CPLD trainer kits To start ISE, double-click the desktop icon, or start ISE from the Start menu by selecting as below: Start — All Programs — Xilinx ISE 9. Navigator — Project Verilog Code execution undergoes the following steps © — Step 1: Create a New Project 20 MI Sem. Dip. Logic Design using Verilog (E&C © — Step 2: Creating a Verilog Source © — Step 3: Checking the Syntax of Module + Step 4: Design Simulation using “Test Benct Waveform” * Step 5: Simulating Design Functionality — Step 6: Downloading to FPGA/CPLD kit Step 1: Create a New Project Create a new ISE project which will target the FPGs device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File >New Project... The New Proje: Wizard appears. 2. “Type Project Name (here tutorialis project name): the Project Name field. 3. Enter or browse to a location (directory path) for ts new project. A tutorial subdirectory is create automatically. 4. Verify that HDL is selected from the Top-Leit Source Type list. Click Next to move to the device properties page Fill in the properties in the table as shown below y Product Category: All > Family: Spartan3 Device: XC3S200 vPrapeny Kame Prose Company > Package: FT256 > Speal Grade: 4 © (VHDL/Verilog) > Preferred Language: Verilog (or VHDL) Verify that Enable Enhanced Design Summary is selected. Leave the default values in the rem Step 2: Creating a Verilog Source source file for the project top-level Veril Click New Source in the New Project dialog box 1g Module as the source type in the New Source dialog box. Type in the file name (here counter is a file name) Verify that the Add to Project checkbox is selected. Click Next. Declare the ports for the file (counter) design by filling in the port information as shown below or simply click next: Mocs Nave [curwe | (Poe Kane cer. Jorzcron ‘COUNT.OUT | |23 a ray IN Sem. Dip. Logie Design using Verilog (ex Click Newt, nformation filetemplate. then Finish in Source jog box to complete the new source the New 8. Click Next, then Next, then Finish, The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below: 9. Place the cursor on the line above the endmodule and type your code. Follow the steps as in next section : Checking the Syntax of Module When the source files are complete, check the synig of the design to find errors and typos. 1. Verify that Synthesis/Implementation is selects from the drop-down list in the Sources window. Select the file name (counter) design source in tt Sources window to display the related processes in th Processes window. 3. Click the “+” next to the Synthesize-XST process expand the process group. 4. Double-click the Check Syntax process. Note: You must correct any errors found in yout source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid Syntax, you will not be able to simulate or synthesize your design. 5. Close the HDL file. Step 4: Design Simulation using “Test Bench Waveform” Verifying Functionality using Behavioral Simulation. Create a test bench waveform containing input st 4 ccan use to verify the functionality of the counte test bench waveform is a graphical view of imuius you T Module, The a test bench. Create the test bench waveform as follows: 1, Select the file name (counter) HDL, file Sources window. im the Zz,Qwwrse Content = 1 you are source 6. The Summary page added to the project type and name. source will be laysthe source opens. The requirements for this design are the following: > The counter must operate correctly with an input clock frequency = 25 MHz. > The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. + The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. ‘The design requirements correspond with the values below. the fields in the I with the following information: > Clock High Time: 20 ns. jalize Timing dialog box OupaVedDey 10 ote 105 Gnome PRADO, atria (100 bteihmoh a few deren (66H) / Vine Seate ve Di Astaorehonan Se Serre For combinational circuits select Combinational in Clock Information and press inish.ad Lens Te Buren 1000 Tre Styne a a a Click Finish to complete the timing initialization. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION Iow so that the counter count down. 10. Save the waveform. 11. In the Sources window, select the Behavior Simulation view to see that the test bench wavefor file is automatically added to your project. | ——— | &3 Sources | 98) Snapshots /@u > 12. Close the test bench waveformthe test bene! 3. To view your si tab and zoom Note: You can ignore any rows that start with TX. 4. Verify that the counter is counting u p and down as expected. Close the simulation view. If you are p the following message, “You have ned with n active board. le (counter) design Connect the SV DC power cable to the ‘on the demo board (J4). Connect the dow demo board (37) oad cable between the PC and Select Synthesis/Implementation the drop- down list in the Sources window Select file (counter) in the Sources window In the Processes window, expand the Generate Pro click the gramming File processes k the Configure Device (JMPACT) process. ‘The Xilinx WebTalk Di process. Click Decline. g box may open during this Select Disable the collection of device use ze statisties for this project only iMPACT opens and the Con is displayed. and click OK re Devices dialog box© Contenee dees te Benenden TAS) Amar ah core tea catle ext teaty Bournny Scan chan, Pracsee © Spe ACE Fae using Boundary-Scan (JTAG). that Automatically connect to a cable and identify Boundary-Scan chain is selected. 11. Click Finish 12. If you get a message saying that there are two devices id, click OK to continue. The devices connected the JTAG chain on the board will be detected and cisplayed in the IMPACT window. New Configuration File dialog box 13. The Ass appears. device HII Sem. Dip. Logic Design using Verilog (E&c) 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and selec: Program... The Programming Properties dialoz box opens. 17. Click OK to program the device. When programming is complete, Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. Bu xietlimeli(ausat (a) 18. Close iMPACT without saving. the Program