2nd International Conference on IoT, Communication & Automation Technology

128-bit Asynchronous Gray Code FIFO using

Verilog HDL
Abhishiek Shukla Jyotsana Singh R.K Chauhan
2024 International Conference on IoT, Communication and Automation Technology (ICICAT) | 979-8-3503-6810-9/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICICAT62666.2024.10923331

Electronic and Communication Electronic and Communication Electronic and Communication

Enigineering Enigineering Enigineering
Madan Mohan Malaviya Madan Mohan Malaviya Madan Mohan Malaviya
University Of Technology , University Of Technology University Of Technology
Gorakhpur ,India Gorakhpur ,India Gorakhpur ,India
[email protected] [email protected] [email protected]

Abstract— This paper presents the design and implementation A. Design

of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL.
The FIFO is designed for bidirectional transfer of data between The design of an asynchronous FIFO is illustrated in Figure
different clock domains using dual-port RAM memory and gray 1, which comprises several modules, including the write
code for specifying empty and full conditions. To avoid pointer, read pointer, write synchronizer, read synchronizer,
metastability, two 2D flip-flops are used as synchronizers. The and FIFO memory. The write pointer module operates within
design is optimized for speed and efficiency using universal gates the write clock domain, receiving input from the write clock,
and status flags Also, the simulation provides the threshold and interfaces with the FIFO memory through the write
status flags for write and read operations is 10% and 90%,
address and write full flag[7]. To ensure synchronization
respectively. The simulation and verification of the design are
performed using Xilinx Vivado software and virtually
between the write pointer and the read clock domain, it is also
implemented for the Artix 7 Low Voltage FPGA. The design is connected to the write synchronizers.
scalable for larger memory requirements. Both the read and write pointers are linked to the FIFO
memory, with the read pointer operating within the read clock
Keywords— FIFO, metastability, Verilog, threshold, Vivado. domain. The write data consists of an 8-bit data line used for
writing data into the FIFO memory. The circuit also
I. INTRODUCTION
incorporates various signals for managing FIFO operations,
Due to the advancements in IC design technology, the scale such as write, reset, read_reset, write_increment, and
of circuit design is increasing exponentially, leading to read_increment. This design can be modified to include
increased complexity in circuitry [1-6]. This has created a additional functionalities or to expand the FIFO memory
need for transferring data between different parts of a system capacity.
working on different clock domains. To address this issue,
Asynchronous FIFOs are used to handle complex data
transfers where data bits are written sequentially using one
clock domain and then read sequentially using another clock
domain from the same FIFO Memory. One of the most
effective techniques for designing an asynchronous FIFO is
using gray code as the pointer address to generate the FIFO
Full and FIFO Empty status signals.

FIFO, short for "First in First Out," indicates that the data
values written first will be read first. In asynchronous FIFOs, Fig 1. Design of Asynchronous FIFO
two pointers, namely the read and write pointer, keep track of
the addresses where data is to be written and read. The write
B. Modules in Asynchronous FIFO
pointer points to the address where the next data value is to
be written, while the read pointer points to the address from
where the next data value is to be read. In asynchronous An asynchronous FIFO design is divided into several
FIFOs, the read operation is done in the read clock cycle, sections, with each section developed as an independent
whereas the write operation is done in the write clock cycle. module. The top-level module then instantiates these
The read and write pointers are incremented after each clock modules and connects them through the appropriate signal
cycle to point to the next address, allowing the read and write lines[8]. The design consists of the following modules:
of data values, respectively. If the read and write operations
are done using the same clock signal, such types of FIFOs are
known as Synchronous FIFOs.

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I.Dual Port RAM Memory Module synchronized with the read clock domain.
The read pointer and the write clock domain are synchronized
II.Read Pointer Module
by the write synchronizer module. It receives a 5-bit read
III.Write Pointer Module pointer, which the write pointer uses to ascertain the FULL
FIFO's conditions. The write synchronizer is made up of two
IV.Read Synchronizer
D flip-flops that are synced with the writing clock domain,
V.Write Synchronizer same like the read synchronizer.[10]
C. EMPTY AND FULL CONDITIONS
I.Dual Port RAM Memory Module Read and write pointers are shown here, each of them
RAM memory with two ports for simultaneous reading and comprises a module that provides some level of operational
writing.This is in contrast to a single port RAM where only significance or effectiveness to the respective pointer. No
one operation can be performed at a particular clock cycle, sooner does the reader and the writer both place their writing
either a read operation or a write operation instruments on the table to rest than they notice that their
This model of FIFO uses a Dual Port RAM Memory with a respective document is similarly parked. When the read
size of 16 bytes, where each location can store 8 bits. pointer reaches the write pointer and tries to perform reading,
However, with minor modifications to the code, the size of the empty flag signal, read out of the read clock domain, is
the RAM Memory can be increased to 32 bytes, 128 bytes, 1 raised indicating that the FIFO is empty. At the same time, it
Megabyte, and so on. The module of the Dual Port RAM means the FIFO memory is full and the full flag from the
Memory is named as "memory_FIFO". [9] write clock domain will turn on, meaning the CPU write
The write operation is performed using the clock cycle of 10 pointer is as fast as the read pointer to a FIFO system. This
ns, which is provided using the testbench with the help of a adds a level of control that is necessary especially when one
"write_clk" signal line. Before performing the write is dealing with read and write operations so that there is no
operation, the module checks two conditions: whether the data loss or data overwrite[11].
FIFO is full or not, and whether the write enable signal is high The read pointer is contained in the FIFO memory with the
or not. If the FIFO is not full and the write enable signal is help of the read address, while the pointer module is
high, then the data is written into the FIFO Memory. The concerned with the FIFO write address and the FIFO write
address where the data is to be written is provided by the full flag. Read and write synchronizers make it possible to
write pointer. avoid mismatch in pointers of the two domains and thus
enable synchronization of operations. They also have control
over other operational aspects of the FIFO such as write_reset
II. Write and Read pointers Moduls and read_reset.
In the design, a Write pointer module is incorporated. In the
write clock domain, all the FIFO logic that is created is I. FIFO Empty Conditions
moved to the write pointer module, wherein the storage write
pointer module is designed. The storage write pointer module To elaborate more, there are two D flip-flops in the read
employs a gray code counter. There is transmitted to the synchronizer module which are used to synchronize the gray
FIFO memory a 4-bit write address which indicates the code version of the read pointer to the domain of the write
address to which the data values will be written to. Thus, the clock. This time, its gray code equivalent of the synchronized
binary address is increased in count by one bit to form a 5bit read pointer within the write synchronizer module is
pointer. This 5 bit pointer is then converted to gray code and subjected to a comparison. The method uses the initial two
fed to the read synchronizer[12]. There is thus also provided bits of the read pointer's gray code counterpart and compares
in the structure a read pointer module which is used to them with the last two bits of the gray code counterpart of the
indicate the address from which data is to be retrieved from write pointer[13]. If the first two bits match, the still unused
FIFO memory. There are also contained in the read pointer portion of the read pointer will have its bits compared to the
module all the FIFO logic that is generated in the read clock corresponding bits of the write pointer. A high empty flag is
domain and hence a complete circuit. The read pointer set which indicates that FIFO unattains its full status if all the
module fairly adds in gray code counter. The read address, bits are equal.
which is transmitted to the FIFO memory, is a 4-bit address II. FIFO Full Conditions
that pinpoints to the clock for which the data values are to be
fetched. The binary address is also appended with an When the write pointer catches up to the read pointer, the
additional bit, making it a 5-bit pointer, much likewrite memory is said to be full; when the pointers' MSBs differ and
pointer. After that, this 5-bit pointer is translated into gray the write pointer's last bits are in sync with the read pointer,
code and sent to the write synchronizer. the memory is said to be empty. The "write_synchronizer"
module uses two synchronizers to move the read pointer to
III. Write and Read Synchronizers the read clock domain. The write pointer's gray code and the
There are two synchronizers in use: the write and read write sync data that was obtained from the write synchronizer
synchronizers. The write pointer is synchronized into the read are compared[14]. The write pointer's gray code and the first
clock domain by the read synchronizer module. It is given a two bits are compared to see if they are equal. Because the
5-bit write pointer, which the read pointer uses to provide the fifth bit, which was added to convert the binary write pointer
circumstances necessary for an empty file system. Two D- to grey code, is '0,' the write_sync[4:3] bits are inverted to
flip flops make up the read synchronizer module, and they are verify this equality.

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2nd International Conference on IoT, Communication & Automation Technology

to our architecture. The flags can signal whether the FIFO is

getting close to capacity or empty
III.Why Gray Code?
The flags can be used to signal when the FIFO is getting close
A binary code known as "gray code" only has one bit change to capacity or closing altogether by setting the read and write
between each value. In order to guarantee that only one bit thresholds to user-defined percentages (like 10% or 90%). In
changes during counter incrementation, FIFOs employ gray real-time applications, this might be extremely crucial as it
code counters. This is crucial because when a binary counter enables more accurate data flow monitoring and
is increased, it is possible for several bits to change management. Furthermore, flexibility in threshold setting
simultaneously. As a result, inconsistent values may be based on the particular needs of the system is made possible
sampled in various clock domains because of disparate by the usage of percentages[16].
propagation delays. This may interfere with regular When precise control over the data flow is needed,
operations. Gray code counters, on the other hand, guarantee a variety of applications can benefit from the threshold status
a consistent counter value sampling since they are less prone flag. For instance, the threshold can assist in preventing data
to these timing problems[15]. Therefore, in order to assure overflow or underflow, which can result in data loss or dec
dependable functioning in this asynchronous FIFO system, reased performance, in applications for processing audio and
gray code counters are preferred. video that require massive volumes of data to be handled in
real-time. It may also be helpful in embedded systems, where
effective data buffer management is essential to the operation
D. RESULTS AND DISCUSSION
of the system .
A thorough examination of the outcomes from the various
design components—such as clock domains, status flags,
universal gates, simulation, and implementation—is given in
this section. It draws attention to the most important
conclusions and revelations from every field of study.

E. Different Clock Domains

It has been shown that an asynchronous FIFO can be
implemented by using two distinct clock domains, the
"write_clk" and the "read_clk". The read action is managed
by the read pointer and is carried out on the falling edge of
the read clock, whereas the write operation is carried out on
the rising edge of the write clock.
We have supplied a clock signal for the write operation that
has a frequency of 100 MHz, or 10 ns, to guarantee the proper
operation of the FIFO. Likewise, for the read operation, we Fig 2. Simulation Results
have supplied a clock signal at a frequency of 50 MHz, or a H. Simulation
duration of 20 ns.[17]
Figure 2 displays the design's successful simulation using
Verilog HDL in the Xilinx Vivado 2016.2 program. Through
the use of the write_clock domain to write 16 8-bit data into
F. Universal Gates the FIFO and the read_clock domain to read the same data
There is one operation involving one “AND” gate and one out of the FIFO, the simulation illustrates the receive and
“NOT” gate which has been made more efficient in the write write operations on distinct clock domains. The right output
pointer module. Four NAND gates were employed instead of is indicated by the read_empty and write_empy signals,
the overall gate configuration, which lowered the logical which are logic high when the FIFO is empty and full,
work and enhanced the rate at which the capacitors charged respectively. Also, the simulation provides the threshold
and discharged. Further, we are still looking for more ways status flags for write and read operations, which were fixed
of improving this modification as it has been very promising to be at 10% and 90%, respectively. This attests to the
so far by interlinking nor and NAND gates. Likewise, successful implementation of the threshold status flag
probability of enhancing the read pointer module has also providing useful information about the status of FIFO
improved by doing the same with the help of NAND gates to memory and hence good control of data flow. These
carry out the same work as in the case of read pointer module. simulation results proved that our FIFO memory design
By utilizing NAND gates, it was possible to increase the function properly and reliably in operation.
logical effort and the operations of enquiry pointer module
improved accordingly[18]. These advances have been great I. Implementation
indeed. Owing to the large number of clock domains we work The creation and implementation of the design were done
with and differences in cycle frequency of writing and using the Xilinx Vivado software. The utilization report
reading there, these optimizations have had special relevance. includes the details about how certain FPGA resources are
G. Status Flags being used [Table I][19]
As a useful tool for monitoring the condition of the FIFO
memory, the threshold status flag is a significant contribution

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 2nd International Conference on IoT, Communication & Automation Technology

Name Value

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TABLE III : ON-CHIP POWER REPORT
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TABLE IV : Compare Table Asynchronous FIFO Memory

TABLE I : Data With Varying Different Clock Frequency

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TABLE I : UTILIATION REPORT

J. Power Report
In the Power Report, the analysis of power consumption of
the implemented netlist is performed comprehensively. It
includes the information about the total power consumption Figure 3
of the design and the distribution of power by modules, Fig. 3 (a) Reported Data of FIFO verification using D-Flip
signals, and I/O ports relative to the resources utilized. The Flop [20], (b) simulation result
report also includes parameters that estimate the activity of
the modules and signal for the purpose of finding out the The resultant value is evolved after verifying and analysis of
dynamic power consumption of the design[19]. system data processed. It act as source for developing
functional approach of various terms and value sustained for
WŽǁĞƌZĞƉŽƌƚ resulting quality outcomes. As determined at proposed
WĂƌĂŵĞƚĞƌ system function it define value of certain stages of functional
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value determined to act according with objectives. It has
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:ƵŶĐƟŽŶdĞŵƉĞƌĂƚƵƌĞ ϯϲ͘ϴǑ of managing activity evolves by test bench approach.
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TABLE II. POWER REPORT

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2nd International Conference on IoT, Communication & Automation Technology

K. Future Scope(Modification) [3] B. Singh, S. Kumar, and R. K. Chauhan, "Minimization of

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