Lab Work Book of

Computer Org. & Architecture

(AL - 404)

Department of CSE - AIML

Lab Manual of
Computer Org. & Architecture
(AL - 404)

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 Lab Work Book
of

COmputEr Org. &

ArChitECturE
(AL - 404)

Name : ...........................................................................................

Enrollment No. : ...........................................................................................

Institute : ...........................................................................................

Academic Session : ...........................................................................................

Department of CSE - AIML

VISION & MISSION OF INSTITUTE

To develop as a centre of excellence in imparting quality education, to produce

technically and ethically competent, socially responsible and innovative technocrats in
Vision of the the field of engineering and management to cater the demand of contemporary
Institute industrial scenario.

M1: To create an ambience of learning for imparting quality education by delivering

in depth knowledge and giving practical exposure.
Mission of the M2: To impart training on recent technologies and professional ethics to make
Institute students highly analytical and innovative technocrats.
M3: To develop entrepreneurship ability and inculcate social ethics amongst the
students by conducting outreach, co-curricular & extracurricular activities.

VISION & MISSION OF DEPARMENT

To establish as an epicentre for scholarly achievement in the fields of machine learning,

Vision of the and artificial intelligence while offering students professional training and strong moral
Department principles.

Mission of the To enhance an ability to deal with challenges in computer science and engineering by
Department imparting knowledge of fundamental concepts and their applications through excellent
classroom instruction, cooperative professional activities, and ethical actions.
Program Outcomes (POs)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,

and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Program Specific Outcomes (PSO)

Graduates will be able to apply the knowledge of relevant mathematical principles in building
PSO 1 applications in machine learning.

Graduates will be able to employ assimilated learning and knowledge from curricular courses towards
PSO 2 personality development and grooming as responsible citizens.

Graduates will be able to deliver new solutions, using computational expertise and project
PSO 3 development abilities.

Program Educational Objectives (PEOs)

Graduate will become into a highly esteemed professional with strong ethical values in the fields of
PEO 1 machine learning and artificial intelligence.

Graduate will exhibit all technical and scientific proficiency required to work as an entrepreneur in
PEO 2 the machine learning and artificial intelligence fields while considering social and environmental
concerns into account.
Graduate will possess strong foundation in the field of Artificial Intelligence and Machine Learning to
PEO 3 be applied in their future researchandhigher studies.
 Computer Organisation and Architecture Lab (AL 404)

Course Outcomes (COs)

Students will be able to:

CO1: Identify various components of CPU organization.

CO2: Develop program to implement arithmetic operations.
CO3: Interpret the I/O sub-system along with interconnecting devices.
CO4: Elaborate memory mapping concept and various page replacement
algorithm.
CO5: Analyze instruction execution cycle and associated control signals.
 Index
S. Page
Experiment
No. No.
Study of Multiplexer and Demultiplexer.
01 1
Study of Half Adder and Subtractor
02 9
Study of Full Adder and Subtractor.
03 14
WAP to add two 8 bit numbers and store the result at memory location 2000.
04 20
WAP to multiply two 8 bit numbers stored at memory location 2000 and 2001 and
05 stores the result at memory location 2000 and 2001. 22

WAP to add two 16-bit numbers. Store the result at memory address starting from
06 2000. 25

WAP which tests if any bit is ‘0’ in a data byte specified at an address 2000. If it
07 is so, 00 would be stored at address 2001 and if not so then FF should be stored at 27
the same address.
Assume that 3 bytes of data are stored at consecutive memory addresses of the data
memory starting at 4100. Write a program which loads register C with [4100], i.e.
08 with data contained at 4100, Register D with [4101], E with [4102] and A with
28
[4101].
8085 Program to Copy 16 Data from One Location 4500H to another Location4600H
09 30
Write a program to add 10 bytes stored at memory location starting from 4300.
10 Store the result at memory location 430A and 430B. 33

Write a program to increment each of the 16 bytes stored at consecutive memory

addresses starting at 4130H. Store the incremented values at same memory
11 addresses. 37
 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 1
Study of Multiplexer and Demultiplexer.

Multiplexer is a digital switch which allows digital information from several sources to be routed onto
a single output line.  The basic multiplexer has several data input lines and a single output line.  The
selection of a particular input line is controlled by a set of selection lines.  Normally, there are 2n input lines
and n selector lines whose bit combinations determine which input is selected.  Therefore, multiplexer is
‘many into one’ and it provides the digital equivalent of an analog selector switch.
A Demultiplexer is a circuit that receives information on a single line and transmits this information
on one of 2n possible output lines.  The selection of specific output line is controlled by the values of n
selection lines.

DESIGN:
4 X 1 MULTIPLEXER

LOGIC SYMBOL:

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

TRUTH TABLE:

SELECTION INPUT OUTPUT

S. No

S1 S2 Y

1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3

PIN DIAGRAM OF IC 7411:

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

CIRCUIT DIAGRAM:

1X4 DEMULTIPLEXER

LOGIC SYMBOL:

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

TRUTH TABLE:

INPUT OUTPUT
S. No
S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1

CIRCUIT DIAGRAM:

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.

Demultiplexers:
The Demultiplexer is combinational logic circuit that performs the reverse operation of Multiplexer. It has
only one input, n selectors and 2n outputs. Depending on the combination of the select lines, one of the
outputs will be selected to take the state of the input.

The following figure shows the block diagram and the truth table for 1x4 Demultiplexer.
By applying logic ‘1’ to the input, the circuit will do the same function of the typical 2-to-4 Decoder.

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

VIVA QUESTIONS

Q.-1. What is a multiplexer?

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Q.-2. What is the function of an enable input on a multiplexer chip?
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Q.-3. Will multiplexing create additional harmonics in the system?
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Q.-4. Can i accidentally switch a dimmer to multiplex mode?
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Q.-5. Distinguish between the two basic multiplexing techniques?
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Q.-6. What is difference between Frequency Division multiplexing and Wave Division multiplexing?
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Q.-7. In what situation multiplexing is used?
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Experiment :- 2
Study of Half Adder and Subtractor

APPARATUS REQUIRED:
S. No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’ and
other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry signal from the
addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

LOGIC DIAGRAM:
HALF ADDER

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

LOGIC DIAGRAM:

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two
outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow
output can be implemented using an AND Gate and an inverter.

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

0 0 0 0
1 1 1 1
1 0 0 1
1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

viva questions

Q.-1. Write Boolean function for half adder.

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Q.-2. How many gates are used in half adder?
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Q.-3. How many Half Adder are used to make Full Adder?
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Q.-4. How many variables are used in K-Map for half Adder?
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 3
Study of Full Adder and Subtractor.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs
and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full
adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

LOGIC DIAGRAM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit
should have three inputs and two outputs. The two half subtractor put together gives a full subtractor
.The first half subtractor will be C and A B. The output will be difference output of full subtractor. The
expression AB assembles the borrow output of the half subtractor and the second term is the inverted
difference output of first X-OR.

LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

PROCEEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

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VIVA QUESTIONS

Q.-1. Write Boolean function for Full adder?

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Q.-2. How many inputs are used in Full Substractor.
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Q.-3. How many NAND gates are required to construct full substractor.
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Q.-4. Which digital logic gate is used to implement the sum circuit of Full Adders?
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Q.-5. How many bit counters will give the sum of Full adder as output.
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 4
Object:
WAP to add two 8 bit numbers and store the result at memory location 2000.

Apparatus Required:
Microprocessor-8085 Trainer kit

Assume Two 8 Bit No Are; 05H & 23H

Program
MVI A, 05H ;Move 05h in to register A

MVI B, 23H ;Move 23h into register B

ADD A,B ; A ---A + B

LXI H,2000H ;Load register pair HL with 2000H
MOV M,A ;Store the result of an Acumlator to the memory
Whose address specified by HL register
HLT

RESULT Check the status of Register which are used in Program

B=23H
A=28H

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

viva questions

Q.-1. Write a Program to add two 8 bit numbers and store the result at memory location.
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 5

Object:
WAP to multiply two 8 bit numbers stored at memory location 2000 and 2001 and stores the result at
memory location 2000 and 2001.

Apparatus Required:
Microprocessor-8085 Trainer kit

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

LXI H,2000H

MOV,B,M

INX H

MVI A,00H

MVI C,00H

L1: ADD M

JNC NXT

INR C

NXT: DCR B

JNZ L1

INX H

MOV M,A

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

INX H

MOV M,C

HLT

RESULT Check the status of

the memory

i. Before
execu-
tion of
the pro-
gram

ii. After
execu-
tion of
the pro-
gram

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 6

Object:
WAP to add two 16-bit numbers. Store the result at memory address starting from 2000.

Apparatus Required:
Microprocessor-8085 Trainer kit

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

LHLD 2000H

XCHG

LHLD 2002

MVI C,00H

DAD D

JNC LOOP

INR C

MOV A,C

STA 2000

LOOP; SHLD

HLT

RESULT 1. Check the status of memory at memory location 2000H, 2001H,

2002H, 2003H before the execution.
2. Check the status of memory at memory location 2000H,2001H
after the execution

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 7

Object:
WAP which tests if any bit is ‘0’ in a data byte specified at an address 2000. If it is so, 00 would be stored
at address 2001 and if not so then FF should be stored at the same address.

Apparatus Required:
Microprocessor-8085 Trainer kit

LDA 2000H Load Accumulator

JNZ LABEL1 Check the status of Accumulator

MVI A,00H

STA 2001H; If Data is zero display 00H at memory 2001

LABEL1: MVI A,FFH;

STA 2001H If Data is Non-zero Display FFh at memory 2001

HLT

RESULT If Data is zero display 00H at memory 2001

If Data is Non-zero Display FFh at memory 2001

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 8

Object:
Assume that 3 bytes of data are stored at consecutive memory addresses of the data memory starting at
4100. Write a program which loads register C with [4100], i.e. with data contained at 4100, Register D
with [4101], E with [4102] and A with [4101].

Apparatus Required:
Microprocessor-8085 Trainer kit
Algorithm
Start
Load HL pair with 4100
Copy data from M to accumulator
Increment address in HL pair
Copy data from M to reg D
Increment address in HL pair
Copy data from M to reg E
Load accumulator with the data byte at 4101
HLT

Program Code:
LXI H, 4100
MOV C,M
INX H
MOV D,M
INX H
MOV E,M
LDA 4101
HLT
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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

viva questions

Q.-1. Write instructions to load the 16 bit number 2050H in HL using LXI and MVI opcodes, and
explain the difference between two instructions.
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Q.-2. Write instructions to add the contents of memory location 2040H to Accumulator, and subtract
the contents of memory location 2041 H from the first sum. Assume the accumulator has 30 H, the
memory location 2040H has 68 H and 2041 H has 7FH.
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Q.-3. Write instructions to load 59H in memory location 2040H, and increment the contents of memory
location. Write instructions to load 90H in memory location 2041H, and decrement the contents of
memory location.
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 9
8085 Program to Copy 16 Data from One Location 4500H to
another Location4600H

Let us suppose that the 16 data are stored starting from 9000H and we are to move the data into location
starting from 9100H.

Algorithm:
Start.
Load into register pair HL from memory location 4500H which is the source location.
Load into register pair DE from 4600H which is the destination location.
Move 10 into register B which acts as counter (16 in decimal = 10 in hexadecimal).
Move content of memory M into accumulator A.
Store the content of accumulator into register pair DE.
Increment register pair HL by 1.
Increment register pair DE by 1.
Decrement registerB by 1.
If no zero is present, go to step 4 else go to 10.
Terminate the program.
Program Code:
LXI H, 4500H
LXI D, 4600H
MVI B, 10H
NEXT MOV A, M
STAX D
INX H
INX D
DCR B
JNZ NEXT
HLT

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

The HL register pair is loaded with memory location 9000H which is the source and the DE register
pair is loaded with memory location 9100H which is the destination. Now, 10H (which means 16 in
decimal) is moved into register C which is used as counter. Now, the content of memory M is moved
into accumulator A and now the content of accumulator is stored into memory location pointed by the
DE register pair. The register pair HL is incremented by 1 so that it points to the next data item and the
DE register pair is also incremented by 1 so that it points to the next location of memory where the data
is to be moved. The counter is decrement by 1. The data now pointed is again moved into accumulator
and the content of accumulator is stored into memory location pointed by the DE register pair. The HL
and DE register pair are again incremented by 1 and the counter is decremented by 1.
These steps are repeated as long as the counter is greater than 0.

OUTPUT

Here, the 16 data’s starting from memory address 4500H is moved into memory address starting from
9100H. Now, since memory address 4510 and 4511 are the 17th and 18th data so they are not copied into
memory address 4610 and 4611.
Exercise 1: A set of current readings is stored in memory location starting at 4150H. The end of the data
string is indicated by the data byte 00H. Add the set of readings. The answer may be larger than FFH.
Display the entire sum at 4250H and 4251H
Data : 32,52,F2,A5,00

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 10
Write a program to add 10 bytes stored at memory location starting from 4300.
Store the result at memory location 430A and 430B.

Algorithm:
1. Load HL register with the first source byte address.
2. Clear Accumulator
3. Clear Register B
4. Load C with count 1010=0A16
5. Add byte
6. Go to 7 if No Carry
7. Increment B as the ere is a carry
8. Fetch next byte by incrementing HL pair
9. Decrement Count by 1
10. Jump if not zero to step 5
11. Store the accumulator content (lower byte of sum) at 430A
12. Store the higher byte in 430B
13. Stop

Program Code:
LXI H, 4300
XRA A
MVI B, 00
MVI C, 0A
NEXTBYTE ADD M
JNC AHEAD
INR B
AHEAD INX H
DCR C
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

JNZ NEXTBYTE
STA 430A
MOV A,B
STA 430B
HLT

Output:
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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

DATA BYTES: 21,23,21,A1,B1,E0,0A,12,45,56

OUTPUT:
[430A] = 4E
[430B] = 03
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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

viva questions
Q.-1. Write a program to do the following:
Q.-a. Load the number 30 H in register B and 39 H in register C
Q.-b. Subtract 39 H from 30 H
Q.-c. Display the answer at 4500H
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Q.-2. Load hex numbers 9BH and A7H in register D and E respectively and add the numbers. If the
sum is greater than FFH then display 01H at address 4500H, otherwise display the sum.
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 LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Experiment :- 11
Write a program to increment each of the 16 bytes stored at consecutive memory
addresses starting at 4130H. Store the incremented values at same memory addresses.

Algorithm:
Start
Load the HL pair with source address
Load the DE pair with the destination pair
Load the count (1610=1016) in the register C
Copy the source data byte in Accumulator
Increment the data byte
Store this incremented value at destination address
Get next source byte address in HL
Increment destination address too
Decrement Count C by 1
If Count is not zero go to step 4, otherwise Stop
Program Code:
LXI H, 4130
LXI D, 4130
MVI C, 10
NEXT MOV A,M
INR A
STAX D
INX H
INX D
DCR C
JNZ NEXT
HLT

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LAB WORK BOOK | COMPUTER ORG. & ARCHITECTURE (AL-404)

Output:

Following bytes were saved at memory location 4130 onwards: 57,68,36,F2,57,E6,57,

8A,12,24,91,79,35,46,24,57
After executing above program memory location 4130 onwards shows following bytes:
58,69,37,F3,58,E7,58,8B,13,25,92,7A,36,47,25,58
Exercise 1: Write a program to decrement each of the 10 bytes stored at consecutive memory addresses
starting at 4130H. Store the decremented values at same memory addresses.

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