Interrupt Handling

Chapter 5
• Definition of Polling
• The input from I/O device can arrive at any moment requesting the
CPU to process it.
• Polling is a protocol that notifies CPU that a device needs its
attention. Unlike in interrupt, where device tells CPU that it needs
CPU processing, in polling CPU keeps asking the I/O device whether
it needs CPU processing.
• The CPU continuously test each and every device attached to it for
detecting whether any device needs CPU attention.
• Every device has a command-ready bit which indicates the status of
that device i.e. whether it has some command to be executed by CPU
or not.
• If command bit is set 1, then it has some command to be executed
else if the bit is 0, then it has no commands.
• CPU has a busy bit that indicates the status of CPU whether it is busy
or not.
• If the busy bit is set 1, then it is busy in executing the command of
some device, else it is 0.
• Algorithm for polling
• When a device has some command to be executed by CPU it
continuously checks the busy bit of CPU until it becomes clear (0).
• As the busy bit becomes clear, the device set write-bit in its
command register and writes a byte in data-out register.
• Now the device sets (1) the command-ready bit.
• When CPU checks the devices command-ready bit and finds it set (1),
it sets (1) its busy bit.
• The CPU then reads the command register of the device and
executes the command of the device.
• After command execution, CPU clears(0) the command-ready bit,
error bit of the device to indicate successful execution of the
command of the device and further it clears (0) its busy bit also to
indicate that the CPU is free to execute the command of some other
device.
• Definition of Interrupt
• An interrupt is a hardware mechanism that enables CPU to detect
that a device needs its attention. The CPU has a wire interrupt-
request line which is checked by CPU after execution of every single
instruction.
• When CPU senses an interrupt signal on the interrupt-request line,
CPU stops its currently executing task and respond to the interrupt
send by I/O device by passing the control to interrupt handler. The
interrupt handler resolves the interrupt by servicing the device.
• Although CPU is not aware when an interrupt would occur as it can
occur at any moment, but it has to respond to the interrupt whenever
it occurs.
• When the interrupt handler finishes executing the interrupt, then
the CPU resumes the execution of the task that it has stopped for
responding the interrupt.
• Software, hardware, user, some error in the program, etc. can also
generate an interrupt. Interrupts handling nature of CPU leads
to multitasking, i.e. a user can perform a number of different tasks at
the same time.
• If more than one interrupts are sent to the CPU, the interrupt
handler helps in managing the interrupts that are waiting to be
processed.
• As interrupt handler gets triggered by the reception of an interrupt,
it prioritizes the interrupts waiting to be processed by the CPU and
arranges them in a queue to get serviced.
• Classification of Interrupt
• Interrupt can be classified as:
1. Maskable Interrupt or Non-Maskable Interrupt
2. Vectored Interrupt or Non-Maskable Interrupt

Maskable Interrupt:
The interrupt which can be blocked or delayed by using instructions
are called maskable interrupts.
RESET interrupts (RST. 5.5, RST 6.5, RST 7.5) and INTR are maskable
interrupts.
They can be enabled or disabled by using instructions EI/DI.
• Non-maskable Interrupts
Those interrupts which cannot be blocked by instructions are termed
as non-maskable interrupts.
TRAP is only one non-maskable interrupt and it is used for power
failure and emergency cutoff.
Vectored Interrupt
The interrupt for which address ISR is already known to
microprocessor is called vectored interrupt.
Interrupt Vector Address (Hex)
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C

Non-vectored Interrupt
In non-vectored interrupt, the interrupting device needs to supply the
address of the ISR to the microprocessor.
INTR is a non-vectored interrupt.
 Interrupt processing sequence

Program Status Word

And Program Counter
• The occurrence of an interrupt fires a numbers of events both in
processor hardware and software.
• When an I/O device completes an I/O operation, the below sequence
of hardware events takes place:
• 1. The device issues an interrupt signal to processor.
• 2. Processor completes execution of current instruction before
responding to interrupt.
• 3. Processor tests for interrupts and sends an acknowledgement
signal to device that issued the interrupt.
• 4. The minimum information needed to be stored for task being
currently executed before CPU starts executing interrupt routine
(using its registers) are:
• (a) Status of processor that is contained in register known as program
status word (PSW), and
• (b) Location of next instruction to be executed, or of currently
executing program that is contained in program counter (PC).
• 5. Processor now loads PC with entry location of interrupt-handling
program which will respond to this interrupting condition.
• Once PC has been loaded, processor proceeds to execute next
instruction, which is the next instruction cycle that begins with an
instruction fetch. Since the instruction fetch is determined by
contents of the PC, result is that control is transferred to interrupt-
handler program. The execution results in the subsequent
operations:
6. The processor loads the program counter with the entry location of
the interrupt Handler.
7. The handler performs the interrupt processing
8. When interrupt processing is finish, saved register values are
retrieved from stack and restored to registers that are displayed in
Figure (b).
9. Final step is to restore values of PSW and PC from stack.
Consequently the instruction to be executed will be from previously
interrupted program.
Interrupt service routine
• Interrupt service routine (ISR) is actually a call back function
(program) in case of software or device driver (I/O device) in case of
hardware.
• Step 1: the interrupt process should be enabled by writing the EI
Instruction and disabled by DI instruction.
• EI: [ Enable Interrupt]
• 1 byte instruction
• It is used to enable interrupt
• DI: [ Disable Interrupt]
• 1 byte instruction
• It is used to disable interrupt
• Step 2: During execution of program in 8085 , microprocessor checks
the INTR (interrupt request ) line during execution of all instruction.

• Step 3: If INTR is high and interrupt is enabled, the microprocessor

completes current instruction and then disable Interrupt flip-flop
and then sends INTA (interrupt Acknowledge) (Active low signal). The
processor cannot accept any interrupt request until the interrupt
Flipflop is enabled again.

INTR
MUP Device
8085
INTA
• Step 4: The INTA’ is used to insert RST instruction through external
hardware.
• The RST Instruction is 1 byte instruction which transfers program
control (PC) to specific location (0000 H page)
• Step 5: When microprocessor receives RST instruction, it saves the
memory address to next instruction on the stack.
• Then program control get transferred to new location on 00H
location
• Step 6: After forming Interrupt task, microprocessor again jumps to
original program. That subroutine is known as ISR (Interrupt Service
Routine).
• Step 7: The ISR should include EI at the beginning
• Step 8: At the end of ISR, RETURN instruction retrieves the memory
address.
• ISR is responsible for doing the following things:
• 1. Saving the processor context
• Because the ISR and main program use the same processor registers,
it is the responsibility of the ISR to save the processor’s registers
before beginning any processing of the interrupt. The processor
context consists of the instruction pointer, registers, and any flags.
Some processors perform this step automatically.
• 2. Acknowledging the interrupt
• The ISR must clear the existing interrupt, which is done either in the
peripheral that generated the interrupt, in the interrupt controller, or
both.
• 3. Restoring the processor context
• After interrupt processing, in order to resume the main program, the
values that were saved prior to the ISR execution must be restored.
Some processors perform this step automatically.
Interrupts in 8085 microprocessor
• The 8085 interrupt is controlled by the Interrupt Enable flip-flop,
which is internal to processor and can be set or reset by using
software instructions. If the flip-flop is enabled and the input to the
interrupt signal INTR (pin 10) goes high, the microprocessor is
interrupted. This is a maskable interrupt and can be disabled. The
8085 has a non-maskable and d three additional vectored interrupt
signals as well.
• The best way to describe the 8085 interrupt process is to compare it
to a telephone with a blinking light instead of a ring.
• For us to receive and respond to a telephone call, the following steps
should occur.
1. The telephone system should be enabled, meaning that the receiver
should be on the hook.
2. We should glance at the light at certain intervals to check whether
someone is calling.
3. If we see a blinking light, we should pick up the receiver, we say
hello, and wait for a response. Once we pick up the phone, the line
is busy, and no more calls can be received until we replace the
receiver.
4. Assuming that the caller is our roommate, the request ,may be: it is
going to rain today. Will you please shut the windows in my room?
5. We insert a bookmark on the page we are reading.
6. We replace the receiver on the hook.
7. We shut our roommate’s windows.
8. We go back to our book, find our mark, and start reading again.

Step 6 and 7 may be interchanged, depending on the urgency of the

request. If the request is critical and we do not want to be interrupted
while attending to the request, we are likely to attend to the request
first, then we put the receiver back on the hook. The 8085 interrupt
process can be described in terms of those eight steps.
• 8085 interrupt process explained:
1. The interrupt process should be enabled by writing the instruction
EI in the main program. This is similar to keeping the phone
receiver on the hook. The EI sets the Interrupt Enable flip-flop. The
instruction DI resets the flip-flop and disables the interrupt process.

Instruction EI (Enable Interrupt)

- This is a 1-byte instruction
- The instruction sets the Interrupt Enable flip-flop and enables
the interrupt process
- system reset or an interrupt disables the interrupt process.
• Instruction DI (Disable Interrupt)
-This is a 1-byte instruction
-The instruction resets the Interrupt Enable flip-flop and disables the interrupt.
- It should be included in a program segment where an interrupt from an
outside source cannot be tolerated.

2. When the microprocessor is executing a program, it checks the INTR

line during the execution of each instruction.
3. If the line INTR is high and interrupt is enabled the microprocessor
completes the current instruction, disables the Interrupt Enable
flip-flop and sends a signal called INTA – Interrupt Acknowledge
(active low). The processor cannot accept any interrupt requests
until the interrupt flip-flop is enabled again.
4. The signal INTA is used to insert a restart (RST) instruction (or a call
instruction through external hardware. The RST instruction is a 1-
byte call instruction that transfers the program control a specific
memory location and restarts the execution at that memory
location after executing step 5.
5. When the microprocessor receives an RST instruction (or a Call
instruction), it saves the memory address of the next instruction on
the stack. This is similar to inserting a bookmark. The program is
transferred to the CALL location on page 00H.
6. Assuming that the task to be performed is written as a subroutine
at the specified location, the processor performs the task. This
subroutine is known as a service routine.
7. The service routine should include the instruction EI to enable the
interrupt again, this is similar to putting the receiver back on the
hook.
8. At the end of the subroutine, the RET instruction retrieves the
memory address where the program was interrupted and continues
the execution. This is similar to finding the page where we were
interrupted by the phone call and continuing to read.
• Introduction to 8259
• Programmable interrupt controllers are used to enhance the number
of interrupts of a microprocessor.
• 8259 is a programmable interrupt controller which shows
compatibility with 8085 microprocessor.
• It is also knows as a priority interrupt controller and was designed by
Intel to increase the interrupt handling ability of the microprocessor.
• 8259 combines the multi interrupt input sources into a single
interrupt output. Interfacing of single PIC provides 8 interrupts inputs
from IR0-IR7.
• For example, Interfacing of 8085 and 8259 increases the interrupt
handling capability of it from 5 to 8 interrupt levels.
• We can masked individual bits of interrupt request register.
• We can increase interrupt handling capability upto 64 interrupt level
by cascading further 8259 PIC.
• Clock cycle is not required.
• Block Diagram of 8259 PIC microprocessor
• The Block Diagram consists of 8 blocks which are – Data Bus Buffer,
Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority
Resolver and 3 registers- ISR, IRR, IMR.

• Data bus buffer –

This Block is used as a mediator between 8259 and 8085 microprocessor
by acting as a buffer.
• It takes the control word from the 8085 microprocessor and transfer it to
the control logic of 8259.
• Also, after selection of Interrupt by 8259 microprocessor, it transfer the
opcode of the selected Interrupt and address of the Interrupt service sub
routine to the other connected microprocessor.
• The data bus buffer consists of 8 bits represented as D0-D7 in the block
diagram. Thus, shows that a maximum of 8 bits data can be transferred at a
time.
• Read/Write logic –
This block works only when the value of pin CS is low (as this pin is
active low). This block is responsible for the flow of data depending
upon the inputs of RD and WR. These two pins are active low pins
used for read and write operations.
• Control logic –
It is the center of the 8259 and controls the functioning of every
block. It has pin INTR which is connected with microprocessor for
taking interrupt request and pin INT for giving the output. If 8259 is
enabled, and the other microprocessor Interrupt flag is high then this
causes the value of the output INT pin high and in this way 8259
responds to the request made by other microprocessor.
1.Interrupt request register (IRR) –
It keeps track of which interrupt input (IR0 – IR7) are asking for
services
If an interrupt input has an interrupt signal on it, then corresponding
bit in the interrupt request register will be set.

2. Interrupt mask register (IMR) –

it is used to Disable or Enable the individual interrupt input
3. Interrupt service Register:
This keeps track of which interrupt input are currently being serviced.
The corresponding bit will be set in the Interrupt register.

• Priority resolver –
It examines all the three registers and set the priority of interrupts
and according to the priority of the interrupts.
• Interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
• Cascade buffer –
To increase the Interrupt handling capability, we can further cascade
more number of pins by using cascade buffer.
• This block stores and compares the ID’s of all 8259 used in the
system.
• The 3 I/O pins CAS0 – CAS2 acts as output when 8259 used as Master.
• CAS0 – CAS2 acts as input when 8259 is in slave mode.
• If 8259 is in Master mode, it sends the ID of interrupting slave device
in these lines.
• Pin Diagram of 8259
• Pin Descriptions of 8259 PIC:
1.CS – when chip select pin is low, it enables RD & WR operation in the
8259
2.RD – a low signal allows 8259 to send command of a various status
signal on the data bus for CPU.
3.WR – low WR enables 8259 to accept command word from CPU.
4.D0 – D7 – bidirectional data bus controller. The control status and
interrupt vector information are transferred through this bus.
5.CAS0 – CAS2 (cascade lines): 8259 has 8 interrupts when no. of
interrupt requirement is more, multiple interrupt controller must be
connected in cascade. The CAS lines are used to control a multiple
8259 structure. These pins are O/P for master 8259 & i/p for a slave
8259.
6. SP/EN: slave program/enable buffer – dual when 8259 is used in
the buffered mode, it can be used on an o/p to control buffer. If not
in buffer mode, it is used to designate a master (SP=1) or (SP=0).
7. A0 = address line with RD, WR, CS
8. INT – It goes high when a validated interrupt request is appeared,
INT generally used to interrupt the CPU.
9. INTA – This goes high when a validated interrupt request is
associated, used to enable 8259 interrupt vectors onto the data-bus
by a sequence of interrupt ack trigger pulse.
10. IR0 – IR7 – each pin can be used to receive an interrupt request to
the CPU.