Unit-3 Lecture-1

Today’s Target
✓ Main features of 8086 microprocessor.
✓ Internal architecture: Bus Interface Unit, Execution unit, Memory
addressing, Memory Segmentation, Pipelining
✓ AKTU PYQs
 MICROPROCESSOR AND MICROCONTROLLER (BEE-602)

AKTU Syllabus : Unit-III

Architecture of Intel 8086:
Pin Diagram, Bus Interface Unit, Execution unit, Register organization, Memory
addressing, Memory Segmentation, Pipelining, Min & Max operating Modes 8086
Instruction set:
Format, Addressing Modes
Instruction Set Groups:
Data transfer, Arithmetic, Logic, String, Branch control transfer and Processor control.
Interrupts:
Hardware and software interrupts.
 Introduction to 8086 Microprocessor

MAIN FEATURES OF 8086 MICROPROCESSOR

1. It is 16-bit microprocessor
2. It has a 16-bit data bus, so it can read data from or write data to memory and ports
either 16-bit or 8-bit at a time.
3. It has 20 bit address bus and can access up to 220 memory locations (1 MB).
4. It can support up to 64K I/O ports
5. It provides 14, 16-bit registers
6. It has multiplexed address and data bus AD0-AD15 & A16-A19
7. It requires single phase clock with 33% duty cycle to provide internal timing.
8. Prefetches up to 6 instruction bytes from memory and queues them in order to
speed up the processing.
9. 8086 supports 2 modes of operation
a. Minimum mode
b. Maximum mode
ARCHITECTURE OF 8086 MICROPROCESSOR
 BIU and EU
Bus Interface Unit (BIU):
The BIU sends out addresses, fetches instructions from memory, reads data from ports and
memory, and writes data to ports and memory. In simple words, the BIU handles all transfers
of data and addresses on the buses for the execution unit.

The Execution Unit (EU): The execution unit of the 8086 tells the BIU where to fetch
instructions or data from, decodes instructions, and executes instructions. The EU contains
control circuitry, which directs internal operations. A decoder in the EU translates instructions
fetched from memory into a series of actions, which the EU carries out. The EU has a 16-bit
arithmetic logic unit (ALU) which can add, subtract, AND, OR, XOR, increment, decrement,
complement or shift binary numbers.
The main functions of EU are:
Decoding of Instructions
Execution of instructions
 PIPELINING:
The process of fetching the next instruction when the present instruction is being executed is
called as pipelining
 MEMORY SEGMENTATION
Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address. It is basically
used to enhance the speed of execution of the computer system, so that the processor is
able to fetch and execute the data from the memory easily and fast.
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned
below) called as Segment Registers.
Code segment register (CS): is used for addressing memory location in the code segment
of the memory, where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is
stored.
Extra Segment Register (ES): also refers to a segment in the memory which is another
data segment in the memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The
stack segment is that segment of memory which is used to store stack data.
 Need for Segmentation
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to
access one of the 1MB memory locations. The four segment registers actually contain the
upper 16 bits of the starting addresses of the four memory segments of 64 KB each with
which the 8086 is working at that instant of time. A segment is a logical unit of memory
that may be up to 64 kilobytes long. Each segment is made up of contiguous memory
locations. It is an independent, separately addressable unit. Starting address will always
be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However, it
works only with four 64KB segments within the whole 1MB memory.
 Types Of Segmentation

Overlapping Segment – A segment starts at a

particular address and its maximum size can go up
to 64kilobytes. But if another segment starts along
with this 64kilobytes location of the first segment,
then the two are said to be Overlapping Segment.
Non-Overlapped Segment – A segment starts at a
particular address and its maximum size can go up
to 64kilobytes. But if another segment starts before
this 64kilobytes location of the first segment, then
the two segments are said to be Non-Overlapped
Segment.
 CALCULATION OF PHYSICAL ADDRESS

1. Calculate the effective address for the following register:

SS: 3640H, SP: 1735H
Ans: Both SP and BP are the offsets for Stack Register (SS).
Therefore, the effective address is:
= (SS X 10H) + SP
= 3640H X 10H + 1735H
= 36400H + 1735H
= 38135H
 University Questions
1. With neat block diagram, describe the internal architecture of 8086?Explain the use of
instruction queue. Discuss about BIU and EU. (2015-16, 2017-18, 2022-23)
2. Explain the addressing capability of 8086? How 20 bit address of memory is addressed?
(2016-17)
3. What do you mean by pipelining and explain the concept of memory segmentation.
(2017-18)
4. What are the advantage of using memory segmentation? (2022-23)
5. Discuss the need of memory segmentation in 8086? (2015-16)
 Unit-3 Lecture-2

Today’s Target
✓ Internal architecture: 8086 Microprocessor Register organization.
✓ AKTU PYQs
REGISTER ORGANIZATION
 GENERAL PURPOSE REGISTERS
There are 4 general purpose registers in 8086 microprocessor.
AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH
and AL to also perform 8-bit instructions.
It is generally used for arithmetical and logical instructions but in 8086 microprocessor
it is not mandatory to have accumulator as the destination operand.
Example: ADD AX, AX (AX = AX + AX)
BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers BH
and BL to also perform 8-bit instructions.
It is used to store the value of the offset.
Example: MOV BL, [500] (BL = 500H)
CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH
and CL to also perform 8-bit instructions.
It is used in looping and rotation.
Example: MOV CX, 0005 LOOP
DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers DH
and DL to also perform 8-bit instructions.
It is used in multiplication an input/output port addressing.
Example: MUL BX (DX, AX = AX * BX)
 SPECIAL PURPOSE REGISTERS
Pointer & Index Registers
SP – This is the stack pointer. It is of 16 bits.
It points to the topmost item of the stack. If the stack is empty the stack pointer will
be (FFFE)H. It’s offset address relative to stack segment.
BP – This is the base pointer. It is of 16 bits.
It is primary used in accessing parameters passed by the stack. It’s offset address
relative to stack segment.
SI – This is the source index register. It is of 16 bits.
It is used in the pointer addressing of data and as a source in some string related
operations. It’s offset is relative to data segment.
DI – This is the destination index register. It is of 16 bits.
It is used in the pointer addressing of data and as a destination in some string
related operations. It’s offset is relative to extra segment.

Instruction Pointer (IP) holds the offset address of the next instruction to be
executed within the code segment. It, along with the Code Segment (CS) register,
determines the complete address of the next instruction to be fetched.
 Segment Registers
There are 4 segment registers in 8086 Microprocessor and each of them is of 16 bit.
The code and instructions are stored inside these different segments.
Code Segment (CS) Register:
The user cannot modify the content of these registers. Only the microprocessor's
compiler can do this.
Data Segment (DS) Register:
The user can modify the content of the data segment.
Stack Segment (SS) Registers:
The SS is used to store the information about the memory segment. The operations
of the SS are mainly Push and Pop.
Extra Segment (ES) Register:
By default, the control of the compiler remains in the DS where the user can add and
modify the instructions. If there is less space in that segment, then ES is used. ES is
also used for copying purpose.
 FLAG REGISTER
The Flag register is a 16-bit register which contains 9 flags, and the remaining 7 bits
are idle in this register. It is of 2 types
1. Status Flags - In 8086 there are 6 different flags which are set or reset after 8-bit
or 16-bit operations
2. Control Flags - In 8086 there are 3 different flags which are used to enable or
disable some basic operations of the microprocessor
 1. STATUS FLAGS

Flag Bit Function

S After any operation if the MSB is 1, then it indicates that the number is negative. And
this flag is set to 1
Z If the total register is zero, then only the Z flag is set

AC When some arithmetic operations generates carry after the lower half and sends it to
upper half, the AC will be 1
P This is even parity flag. When result has even number of 1, it will be set to 1,
otherwise 0 for odd number of 1s
CY This is carry bit. If some operations are generating carry after the operation this flag
is set to 1
O The overflow flag is set to 1 when the result of a signed operation is too large to fit.
 2. Control Flags

Flag Bit Function

D This is directional flag. This is used in string related operations. D = 1, then

the string will be accessed from higher memory address to lower memory
address, and if D = 0, it will do the reverse.

I This is interrupt flag. If I = 1, then MPU will recognize the interrupts from
peripherals. For I = 0, the interrupts will be ignored

T This trap flag is used for on-chip debugging. When T = 1, it will work in a
single step mode. After each instruction, one internal interrupt is
generated. It helps to execute some program instruction by instruction.
ARCHITECTURE OF 8086 MICROPROCESSOR
 University Questions

1. Draw architecture of 8086 explain its different unit. (2017-18)

2. Draw and explain the internal block diagram of 8086. (2022-23)
3. Discuss the flag registers of 8086? (2023-24)
 Unit-3 Lecture-3

Today’s Target
✓ Pin Diagram of the 8086 Microprocessor
✓ Min & Max operating Modes 8086
✓ AKTU PYQs
PIN DIAGRAM OF 8086 MICROPROCESSOR
1. Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses
ground at VSS pin 1 and 20 for its operation.
2. Clock signal
Clock signal is provided through Pin-19. It
provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz,
8MHz and 10MHz.
3. Address/data bus
AD0-AD15. These are 16 address/data bus.
AD0-AD7 carries low order byte data and AD8-AD15
carries higher order byte data. During the first clock
cycle, it carries 16-bit address and after that it carries
16-bit data.
4. Address/status bus
A16-A19/S3-S6. These are the 4 address/status
buses. During the first clock cycle, it carries 4-bit
address and later it carries status signals.
 4. Address/status bus
A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

S5 and S6 provide information about the processor's state, with S6 always being a logic 0
and S5 indicating the status of the Interrupt Enable Flag (IF).
5. INTR
It is available at pin 18. It is an interrupt
request signal, which is sampled during the last clock
cycle of each instruction to determine if the
processor considered this as an interrupt or not.
6. NMI
It stands for non-maskable interrupt and is
available at pin 17. It is an edge triggered input,
which causes an interrupt request to the
microprocessor.
7. INTA
It is an interrupt acknowledgement signal
and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
8. S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used
to indicate the transfer of data using data bus D8-D15. This signal is low
during the first clock cycle, thereafter it is active.
9. MN/MX’
This pin signal indicates what mode the processor will operate in
Minimum/Maximum mode.
10. TEST’
This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0),
execution will continue, else the processor remains in an idle state. The
input is internally synchronized during each of the clock cycle on leading
edge of the clock.
11. Ready
It is available at pin 22. It is an acknowledgement signal from I/O
devices that data is transferred. It is an active high signal. When it is high, it
indicates that the device is ready to transfer data. When it is low, it indicates
wait state.
12. RESET
It is available at pin 21 and is used to restart the execution. It
causes the processor to immediately terminate its present activity. This
signal is active high for the first 4 clock cycles to RESET the microprocessor.
13. Read(RD)
It is available at pin 32 and is used to read signal for
Read operation.

MAXIMUM MODE PINS OF 8086 MICROPROCESSOR

(Multi-Processor Mode)

1. RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the
other processors requesting the CPU to release the system
bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than
RQ/GT1.
2. LOCK
When this signal is active, it indicates to the other
processors not to ask the CPU to leave the system bus. It is
activated using the LOCK prefix on any instruction and is
available at pin 29.
3. S0, S1, S2
These are the status signals that provide the status of
operation, which is used by the Bus Controller 8288 to
generate memory & I/O control signals. These are
available at pin 26, 27, and 28. Following is the table
showing their status −

S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
4. QS1 and QS0
These are queue status signals and are available at pin 24
and 25. These signals provide the status of instruction
queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

MINIMUM MODE PINS OF 8086 MICROPROCESSOR
(Single Processor Mode)

1.WR
It stands for write signal and is available at
pin 29. It is used to write the data into the memory or
the output device depending on the status of M/IO
signal.
2. HLDA
It stands for Hold Acknowledgement signal
and is available at pin 30. This signal acknowledges
the HOLD signal.
3. HOLD
This signal indicates to the processor that
external devices are requesting to access the
address/data buses. It is available at pin 31.
4.ALE
It stands for address enable latch and is available
at pin 25. A positive pulse is generated each time the
processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines.
5. DEN
It stands for Data Enable and is available at pin 26.
It is used to enable Transreceiver 8286. The transreceiver
is a device used to separate data from the address/data
bus.
6. DT/R
It stands for Data Transmit/Receive signal and is
available at pin 27. It decides the direction of data flow
through the transreceiver. When it is high, data is
transmitted out and vice-a-versa.
7. M/IO
This signal is used to distinguish between memory
and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory
operation. It is available at pin 28
 University Questions

1. Explain the pin diagram of 8086 microprocessor? (2015-16, 2022-23)

 Unit-3 Lecture-4

Today’s Target
✓ Instruction Set (Data Transfer, Arithmetic & Logical Instructions)
✓ AKTU PYQs
 Types of Instructions in 8086

Data Transfer Instructions

Arithmetic & Logical Instructions

Shift & Rotate Instructions

Branch & Loop Instructions

String Instructions

Flag Manipulation Instructions

Processor(Machine) Control Instructions

 1. Data Transfer instruction
Instruction Description
MOV Moves data from register to register, register to memory, memory to register, memory
to accumulator, accumulator to memory, etc.
LDS Loads a word from the specified memory locations into specified register. It also loads
a word from the next two memory locations into DS register.
LES Loads a word from the specified memory locations into the specified register. It also
loads a word from next two memory locations into ES register.

LEA Loads offset address into the specified register.

LAHF Loads low order 8-bits of the flag register into AH register.
SAHF Stores the content of AH register into low order bits of the flags register.
XLAT/XLATB Reads a byte from the lookup table.
XCHG Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX
register, specified register or memory locations.
PUSH Pushes (sends, writes or moves) the content of a specified register or memory
location(s) onto the top of the stack.
POP Pops (reads) two bytes from the top of the stack and keeps them in a specified register,
or memory location(s).
ARITHMETIC INSTRUCTIONS
 2. Arithmetic Instructions

Instruction Description
ADD Adds data to the accumulator i.e. AL or AX register or memory
locations.
ADC Adds specified operands and the carry status (i.e. carry of the
previous stage).
SUB Subtract immediate data from accumulator, memory or register.
SBB Subtract immediate data with borrow from accumulator, memory or
register.
MUL Unsigned 8-bit or 16-bit multiplication.
IMUL Signed 8-bit or 16-bit multiplication.
DIV Unsigned 8-bit or 16-bit division.
IDIV Signed 8-bit or 16-bit division.
INC Increment Register or memory by 1.
DEC Decrement register or memory by 1.
DAA Decimal Adjust after BCD Addition: When two BCD numbers are added,
the DAA is used after ADD or ADC instruction to get correct answer in BCD.

DAS Decimal Adjust after BCD Subtraction: When two BCD numbers are
added, the DAS is used after SUB or SBB instruction to get correct answer in
BCD.
AAA ASCII Adjust for Addition: When ASCII codes of two decimal digits are
added, the AAA is used after addition to get correct answer in unpacked
BCD.
AAD Adjust AX Register for Division: It converts two unpacked BCD digits in AX
to the equivalent binary number. This adjustment is done before dividing
two unpacked BCD digits in AX by an unpacked BCD byte.

AAM Adjust result of BCD Multiplication: This instruction is used after the
multiplication of two unpacked BCD.
AAS ASCII Adjust for Subtraction: This instruction is used to get the correct
result in unpacked BCD after the subtraction of the ASCII code of a number
from ASCII code another number.
 ADD ADC

Adds data to the accumulator Adds specified operands and

i.e. AL or AX register or the carry status (i.e. carry of
memory locations. the previous stage).

All flags are affected All flags are affected.

Eg.- Eg.-
 ADD AX, 0100 H  ADC AX, 0100 H
 ADD AX, BX  ADC AX, [5000H]
 SUB SBB

Subtract immediate data from Subtract immediate data with

accumulator, memory or borrow from accumulator,
register. memory or register.

All flags are affected. All flags are affected.

Eg.- Eg.-

 SUB AX, 0100 H  SUB AX, 0100 H

 MUL IMUL
Unsigned 8-bit or 16-bit Signed 8-bit or 16-bit
multiplication. multiplication.
0-256 (8 bit) -128 to +127 (8 bit)
Immediate operand is not allowed Immediate operand is not
Eg.- allowed
1. MUL BH {AXAL*BH} Eg.-
2. MUL CX 1. IMUL BH {AXAL*BH}
{(DX)(AX)AX*CX} 2. IMUL CX
3. MUL [SI] {(DX)(AX)AX*CX}
{(DX)(AX)AX*[SI]} 3. IMUL [SI]
{(DX)(AX)AX*[SI]}
 DIV IDIV
 Unsigned 8-bit or 16-bit  Signed 8-bit or 16-bit division.
division.
Divisor will be saved in any
memory location while
Dividend in AX or DX.
Quotient can be saved in Al
and Remainder in AH.
INC DEC
Increment Register or memory Decrement register or memory
by 1. by 1.
Eg.-  Eg.-
INC AX DEC AX
INC [5000H] DEC [5000H]
 DAA(Decimal Adjust after Addition)
Operation
If the LS hex digit in A is <= 9 and AC flag is 0, the LS hex digit value will not be
altered.

If the LS hex digit is >9, or if AC flag is set to 1, it adds 6 to the LS hex digit of A. If
carry results, then it increments the MS hex digit if this addition resulted in a carry
to the MS digit position. In this process, the Cy flag will be set to 1 if the MS hex digit
was incremented from F to 0.

If the MS hex digit is <= 9 and Cy flag is 0, the MS hex digit will not be altered, and Cy
flag is reset to 0.

If the MS hex digit is > 9, or if Cy flag is set to 1, it adds 6 to the MS hex digit of A and
sets Cy flag to 1.
 38  0011 1000

+ 45  0100 0101

---- ------------- 1

83 0111 1101 0111 1101

---- ---- + 0110 (06H)

7 D ------------- 1000 0011  83

(Decimal sum)
 DAS(Decimal Adjust after Subtraction)

75  0111 0101

- 46  0100 0110

---- -------------

29 0010 1111 0010 1111

---- ---- - 0110 (06H)

2 F ------------- 0010 1001  29

(Decimal sum)
 AAA(ASCII Adjust for Addition)

You use AAA only after executing the form of an add instruction that stores a
two-BCD-digit byte result in the AL register. AAA then adjusts AL to contain
the correct decimal result. The top nibble of AL is set to 0. To convert AL to
an ASCII result, follow the AAA instruction with:

Carry Action
decimal carry AH + 1; CF and AF set to 1

no decimal carry AH unchanged; CF and AF cleared to 0

 AAA Case I. If lower nibble of AL >9 & AF=1,
38  0011 1000 AL=AL+06H and higher nibble of AL=0
+ 45  0100 0101 AH=AH+1 and AF=CF=1
---- ------------- Else AF=CF=0
0111 1101
---- ---- Case II. If lower nibble of AL <9,
AL = 7 D AL=AL and higher nibble of AL=0
AH=AH and AF=CF=0
LOGICAL INSTRUCTIONS
 Logical Instructions

AND Performs bit by bit logical AND operation of two operands

and places the result in the specified destination.

OR Performs bit by bit logical OR operation of two operands

and places the result in the specified destination.
XOR Performs bit by bit logical XOR operation of two operands
and places the result in the specified destination.
NOT Takes one's complement of the content of a specified
register or memory location(s).
 Unit-3 Lecture-5

Today’s Target
✓ Instruction Set (Rotate & Shift instructions)
✓ AKTU PYQs
ROTATE & SHIFT INSTRUCTIONS
 Rotate Instructions

Instruction Description

RCL Rotate all bits of the operand left by specified number of

bits through carry flag.

RCR Rotate all bits of the operand right by specified number of

bits through carry flag.

ROL Rotate all bits of the operand left by specified number of

bits.
ROR Rotate all bits of the operand right by specified number of
bits.
 ROL (Rotate Left without Carry)

 Rotate all bits of the operand left by specified number of bits.

 The PF,SF,ZF flags are left unchanged.

 ROR (Rotate Right without Carry)

 Rotate all bits of the operand right by specified number of bits.

 The PF,SF,ZF flags are left unchanged.

 RCL (Rotate Left through Carry)

Rotate all bits of the operand left by specified number of bits through
carry flag.

The PF,SF,ZF flags are left unchanged

 RCR (Rotate Right through Carry)

 Rotate all bits of the operand right by specified number of bits through
carry flag.

 The PF,SF,ZF flags are left unchanged

 Shift Instructions

Instruction Description

SAL or SHL Shifts each bit of operand left by specified number of

bits and put zero in LSB position.

SAR Shift each bit of any operand right by specified

number of bits. Copy old MSB into new MSB.

SHR Shift each bit of operand right by specified number of

bits and put zero in MSB position.
 SHL or SAL (Shift Logical/Arithmetic Left)
Shifts each bit of operand left by specified number of bits and put zero in
LSB position.

All flags are affected.

 SHR(Shift Logical Right)
 Shift each bit of operand right by specified number of bits and put zero in
MSB position.

 All flags are affected.

 SAR(Shift Arithmetic Right)
 Shift each bit of any operand right by specified number of bits. Copy old
MSB into new MSB.

 All condition flags are affected.

 Unit-3 Lecture-6

Today’s Target
✓ Instruction Set (Branch Control, String and Flag Manipulation
Instructions)
✓ AKTU PYQs
BRANCH CONTROL INSTRUCTIONS
OF
8086 MICROPROCESSOR
 Branch Instructions
 Normally the processor executes the program in a sequential manner, due to
continuous increment of IP (instruction pointer ).

Branch instructions in this 8086 microprocessor are that jumps to another

part of the program without executing in a sequential manner.

 The two types of branch control instructions are:

1. Unconditional branch instructions

2. Conditional branch instructions

 1. Unconditional Branch Instructions
Op code Operand Explanation Example

calls a subroutine and saves the return

CALL address CALL 2050
address on the stack

returns from the subroutine to the main

RET none RET
program

Causes the program execution to jump

JUMP address unconditionally to the memory address JUMP 2050
or label given in the instruction.

loops through a sequence of

instructions until CX=0 (Jump to
LOOP address LOOP 2050
defined label until CX = 0)
 2. Conditional Branch Instructions
Op code Operand Explanation Example
JC address jump if CF = 1 JC 2050
JNC address jump if CF = 0 JNC 2050
JZ address jump if ZF = 1 JZ 2050
JNZ address jump if ZF = 0 JNZ 2050
JO address jump if OF = 1 JO 2050
JNO address jump if OF = 0 JNO 2050
JPE address jump if PF = 1 JPE 2050
JPO address jump if PF = 0 JPO 2050
JS address jump if SF = 1 JS 2050
JNS address jump if SF = 0 JNS 2050
 Op code Operand Explanation Example
Jump if above, not below, or equal i.e.
JA/JNBE address JA 2050
when CF and ZF = 0
Jump if above, not below, equal or no
JAE/JNB/JNC address JAE 2050
carry i.e. when CF = 0
JE/JZ address Jump if zero or equal i.e. when ZF = 1 JE 2050
Jump if greater, not less or equal i.e. when
JG/JNLE address JG 2050
ZF = 0 and CF = OF
Jump if greater, not less or equal i.e. when
JGE/JNL address JGE 2050
SF = OF
Jump if less, not greater than or equal i.e.
JL/JNGE address JL 2050
when SF ≠ OF
 Op code Operand Explanation Example
Jump if less, equal or not greater i.e.
JLE/JNG address JLE 2050
when ZF = 1 and SF ≠ OF

JCXZ address Jump if CX register = 0 JCXZ 2050

Decrement CX register and jump if
LOOPE/LOOPZ address LOOPE 2050
CX ≠ 0 and ZF = 1.
Decrement CX register and jump if
LOOPNE/LOOPNZ address LOOPNE 2050
CX ≠ 0 and ZF = 0.
 STRING INSTRUCTIONS OF 8086 MICROPROCESSOR
A series of data byte or word available in memory at consecutive locations, to be
referred as Byte String or Word String.

For referring to a string instructions, two parameters are required.

I. Length of the String.

II. Starting and End Address of the String.

The length of the string is usually stored as count in the CX register.

The incrementing or decrementing of the pointer, in string instructions, depends upon

the Direction Flag (DF) Status. If it is a Byte string operation, the index registers are
updated by one. On the other hand, if it is a word string operation, the index registers
are updated by two.
 String Instructions
Instruction Description
MOVS/MOVSB/MOVSW Moves 8-bit or 16-bit data from the memory location(s) addressed
by SI register to the memory location addressed by DI register.
CMPS/CMPSB/CMPSW Compares the content of memory location addressed by DI register
with the content of memory location addressed by SI register.
SCAS/SCASB/SCASW Compares the content of accumulator with the content of memory
location addressed by DI register in the extra segment ES.
LODS/LODSB/LODSW Loads 8-bit or 16-bit data from memory location addressed by SI
register into AL or AX register.
STOS/STOSB/STOSW Stores 8-bit or 16-bit data from AL or AX register in the memory
location addressed by DI register.
REP Repeats the given instruction until CX ≠ 0
REPE/ REPZ Repeats the given instruction till CX ≠ 0 and ZF = 1
REPNE/REPNZ Repeats the given instruction till CX ≠ 0 and ZF = 0
FLAG MANIPULATION & PROCESSOR
CONTROL INSTRUCTIONS
OF
8086 MICROPROCESSOR
 Flag Manipulation and Processor Control Instructions
Instruction Description
CLC Clear Carry Flag: This instruction resets the carry flag CF to 0.
CLD Clear Direction Flag: This instruction resets the direction flag DF to 0.
CLI Clear Interrupt Flag: This instruction resets the interrupt flag IF to 0.
CMC This instruction take complement of carry flag CF.
STC Set carry flag CF to 1.
STD Set direction flag to 1.
STI Set interrupt flag IF to 1.
HLT Halt processing. It stops program execution.
NOP Performs no operation.
ESC Escape: makes bus free for external master like a coprocessor or peripheral device.
WAIT When WAIT instruction is executed, the processor enters an idle state in which the
processor does no processing.
LOCK It is a prefix instruction. It makes the LOCK pin low till the execution of the next
instruction.
 University Questions
 Explain the execution of the instructions in 8086-

i)PUSH S ii)SBB CX, BX? (2015-16)

Explain the following instructions of 8086 with example-

a)LDS b)SBB c)MUL d)IDIV

e)ADC f)CMPS g)TEST h)XOR

i)RCR (2016-17)

Differentiate between data and branch instructions in 8086? Explain the

branch instructions with example. (2016-17)
 Unit-3 Lecture-7

Today’s Target
✓ Instruction format, Addressing Modes of 8086
✓ AKTU PYQs
 8086(Machine Language Instruction Formats)

 A machine language instruction format has one or more number of fields

associated with it.
 The first field is called as operation code field or op-code field, which indicates the
type of operation to be performed by the CPU
 The instruction format also contains other fields known as operand fields
 The CPU executes the instruction using the information which reside in these fields
 There are six general formats of instructions in 8086 instruction set.
 The length of an instruction may vary from 1 byte to 6 bytes.
 Types of Instruction Format in 8086

1. One Byte Instruction

2. Register to Register

3. Register to/from memory with no displacement

4. Register to/from Memory with Displacement

5. Immediate Operand to Register

6. Immediate Operand to Memory with 16-bit displacement

1. One Byte Instruction:
 This format is only one byte long and may have the implied data or register
operands.
 The least significant 3-bits of the opcode are used for specifying the register
operand, if any.
 Otherwise, all the 8 bits form an opcode and the operands are implied
 Eg:- AAA , DAA, CLC

D7 D6 D5 D4 D3 D2 D1 D0
OPCODE REG
2. Register to Register:
 This format is 2 bytes long
 The first byte of the code specifies the operation code and width of the operand
specified by ‘w’ bit.
 The second byte of the code shows the register operands and R/M field, as shown
below .
 The register represented by the REG field is one of the operands.
 The R/M field specifies another register or memory location i.e. the other operand.
 Eg:- MOV AX, BX
ADD AX, BX
3. Register to/from memory with no displacement:
 This format is also 2 bytes long and similar to the Register to Register format
except for the MOD field as shown.
 The MOD field shows the mode of addressing. The MOD, R/M, REG and the ‘W’
fields are decided in Table.
 Eg:- MOV AX, [SI]
4. Register to/from Memory with Displacement:
 This type of instruction format requires 3 or 4 bytes for coding.
 This type of instruction format contains 1 or 2 additional bytes for displacement
along with 2 byte format of the register to/from memory without displacement.
The format is as shown below.
 Eg:- MOV AX, [SI+2000H]
5. Immediate Operand to Register:
 This type of instruction format requires 3 or 4 bytes for coding.
 In this format, the first byte as well as the 3-bits from the second byte which are
used for REG field in case of register to register format are used for opcode.
 It also contains one or two bytes of immediate data. The complete instruction
format is as shown below.
 Eg:- MOV AX, 1234H
6. Immediate Operand to Memory with 16-bit displacement:
 This type of instruction format requires 5 or 6 bytes for coding.
 The first 2 bytes contain the information regarding OPCODE, MOD and R/M
fields. The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of
data as shown.
 Eg:-
 The MOD field shows the mode of addressing. The MOD, R/M, REG and the ‘W’
fields are decided in Table
W-bit : Some instructions of 8086 can operate on byte or a word. The W-bit in the
opcode of such instruction specify whether instruction is a byte instruction (W = 0) or
a word instruction (W = 1).
D-bit : The D-bit in the opcode of the instruction indicates that the register specified
within the instruction is a source register (D = 0) or destination register (D =1).
 ADDRESSING MODES

There are 8 different addressing modes in 8086 programming

1. Immediate Addressing Mode
2. Direct Addressing Mode
3. Register Addressing Mode
4. Register Indirect Addressing Mode
5. Indexed Addressing Mode
6. Register Relative Addressing Mode
7. Base Indexed Addressing Mode
8. Relative Base Indexed Addressing Mode
 1. Immediate Addressing Mode

In this type of addressing, immediate data is a part of instruction, and

appears in the form of successive byte or bytes

Eg: MOV AX, 0005H

 2. Direct Addressing Mode

In the direct addressing mode, a 16-bit memory address (offset) is

directly specified in the instruction as a part of it.

Eg: MOV AX,[5000H],

(–Effective address= 10H*DS +5000H)

 3. Register Addressing Mode

 In the register addressing mode, the data is stored in a register

and it is referred using the particular register

 All the registers, except IP, may be used in this mode.

Eg: MOV AX, BX

 4. Register Indirect Addressing Mode

Sometimes, the address of the memory location which contains data or operand is
determined in an indirect way, using the offset registers. This mode of addressing is
known as register indirect mode

 In this addressing mode, the offset address of data is in either BX or SI or DI register.

The default segment is either DS or ES. The data is supposed to be available at the
address pointed to by the content of any of the above registers in the default data
segment.

Eg: MOV AX,[BX]

(–Effective address is 10H*DS+[BX])

 5. Indexed Addressing Mode

In this addressing mode, offset of the operand is stored in one of the Index registers.

 DS is the default segment for index registers SI and DI

 In the case of string instructions DS and ES are default segments for SI and DI
respectively.

 This mode is a special case of the above discussed register indirect addressing mode

Eg: MOV AX,[SI]

 (–Effective address is 10H*DS+[SI])

 6. Register Relative Addressing Mode

In this addressing mode, the data is available at an effective address formed by

adding an 8-bit or 16-bit displacement with the content of any one of the registers
BX, BP, SI and DI in the default (either DS or ES) segment.

Eg: MOV AX,50H[BX]

–Effective address is 10H*DS+50H+[BX]

 7. Base Indexed Addressing Mode

The effective address of the data is formed, in this addressing mode, by adding the
content of a base register (any one of BX or BP) to the content of an index register
(any one of SI or DI)

 The default segment register may be DS or ES

Eg: MOV AX,[BX][SI]

(-Effective address is 10H*DS +[BX]+[SI])

 8. Relative Base Indexed Addressing Mode

The effective address is formed by adding an 8-bit or 16-bit displacement with the
sum of contents of anyone of the base registers (BX or BP) and any one of the index
registers (SI or DI), in a default segment.

 Eg: MOV AX,50H[BX][SI]

 (–Effective address is 10H* DS+[BX]+[SI]+50H)

 University Questions

1. Specify the types of addressing modes used in following instructions-

i)MOV AX, [2050H] ii)IN AX,DX (2015-16)

2. Write about types of addressing modes in 8086/Explain all the addressing

modes of 8086. (2015-16, 2017-18, 2022-23, 2023-24)

3. Explain the instruction format of 8086? Explain the function of special bits
used in instruction format? (2016-17)
 Unit-3 Lecture-8
Today’s Target
✓ Hardware and software Interrupts of 8086.
✓ Minimum & Maximum operating Modes 8086
✓ AKTU PYQs
8086 INTERRUPTS
An interrupt is a condition that halts the microprocessor temporarily to work
on a different task and then return to its previous task. Interrupt is an event
or signal that request to attention of CPU. This halt allows peripheral devices
to access the microprocessor.
 1. Hardware Interrupts

 Hardware interrupts are those interrupts which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor. There are two hardware
interrupts in 8086 microprocessor. They are:

(A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware interrupt which
cannot be disabled. It is the highest priority interrupt in 8086 microprocessor. After its
execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008
H and CS is loaded from the word location 0000A H.

(B) INTR (Interrupt Request) – It provides a single interrupt request and is activated by I/O
port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive
any interrupt type, so the value of IP and CS will change on the interrupt type received.
 2. Software Interrupts
 These are instructions that are inserted within the
program to generate interrupts. There are 256
software interrupts in 8086 microprocessor. The
instructions are of the format INT type where type
ranges from 00 to FF. The starting address ranges
from 00000 H to 003FF H. These are 2 byte
instructions.

 Type 0-4: Dedicated interrupts

 Type 5-31: Reserved interrupts for INTEL

 Type 32-255: user defined interrupts

Some important software (dedicated) interrupts are:
 1. INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte
provides the interrupt type number. There are 256 interrupt types under this
group.

(A) TYPE 0 corresponds to division by zero(0).

(B) TYPE 1 is used for single step execution for debugging of program.

(C) TYPE 2 represents NMI and is used in power failure conditions.

(D) TYPE 3 represents a break-point interrupt.

(E) TYPE 4 is the overflow interrupt.

1. INT 3-Break Point Interrupt Instruction

 It is a 1-byte instruction having op-code is CCH. These instructions are

inserted into the program so that when the processor reaches there, then it
stops the normal execution of program and follows the break-point
procedure.
2. INTO (Type 4) - Interrupt on overflow instruction

 It is a 1-byte instruction and their mnemonic INTO. The op-code for this
instruction is CEH. As the name suggests it is a conditional interrupt
instruction, i.e. it is active only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt type number is 4. If the
overflow flag is reset then, the execution continues to the next instruction.
 Interrupt Service Routine

The processor can be interrupted in the following ways

 by an external signal generated by a peripheral,
 by an internal signal generated by a special instruction in the program,
 by an internal signal generated due to an exceptional condition which
occurs while executing an instruction. (For example, in 8086 processors,
divide by zero is an exceptional condition which initiates type 0 interrupt
and such an interrupt is also called execution).
In general, the process of interrupting the normal program execution to
carry out a specific task/work is referred to as interrupt.
 When a microprocessor receives an interrupt signal it stops executing
current normal program, save the status (or content) of various registers
(IP, CS and flag registers in case of 8086) in stack and then the processor
executes a subroutine/procedure in order to perform the specific
task/work requested by the interrupt.
 The subroutine/procedure that is executed in response to an interrupt is
also called Interrupt Service Subroutine. (ISR). At the end of ISR, the
stored status of registers in stack is restored to respective registers, and
the processor resumes the normal program execution from the point
{instruction) where it was interrupted.
Minimum operating Modes 8086
 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum
mode by strapping its MN//MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
 The remaining components in the system are latches, Tran receivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for
selecting memory or I/O devices, depending upon the address map of the system.
 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They
are used for separating the valid address from the multiplexed address/data signals
and are controlled by the ALE signal generated by 8086.
 Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
 They are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the processor. The
system contains memory for the monitor and users program storage.
 Usually, EPROM is used for monitor storage, while RAM for user’s program
storage. A system may contain I/O devices.
 The working of the minimum mode configuration system can be better
described in terms of the timing diagrams rather than qualitatively
describing the operations.
 The opcode fetch and read cycles are similar. Hence the timing diagram can
be categorized in two parts, the first is the timing diagram for read cycle and
the second is the timing diagram for write cycle.
 The read cycle begins in T1 with the assertion of address latch enable (ALE)
signal and also M / IO signal. During the negative going edge of this signal, the
valid address is latched on the local bus.
 The BHE and A0 signals address low, high or both bytes. From T1 to T4, the
M/IO signal indicates a memory or I/O operation.
 At T2, the address is removed from the local bus and is sent to the output.
The bus is then tristated. The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers.
After RD goes low, the valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor
returns the read signal to high level, the addressed device will again tri state
its bus drivers.
 A write cycle also begins with the assertion of ALE and the emission of the
address. The M/IO signal is again asserted to indicate a memory or I/O
operation. In T2, after sending the address in T1, the processor sends the
data to be written to the addressed location.
 The data remains on the bus until middle of T4 state. The WR becomes active
at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time
for floating).
 The BHE and A0 signals are used to select the proper byte or bytes of
memory or I/O word to be read or write.
 The M/IO, RD and WR signals indicate the type of data transfer as specified in
table below.
Maximum operating Modes 8086
 The Bus controller is introduced here due to the support of multiprocessor
environment of Maximum mode. The decoder is used to select desired
memory chips. The remaining components of this circuit are similar to 8088
minimum mode circuit, as shown in figure. Note that the bank high enable
signal is used to control the access of even or odd memory banks of 8086
system.
 The status codes (S0, S1, S2) of the CPU is used by the bus controller to
activate maximum mode memory control signals: These codes are
important for multiprocessor environment, supported by Maximum mode.
 University Questions

1. How many types of interrupts in 8086? Give its significance/Give the explanation
in details? (2016-17, 2023-24)

2. Explain the interrupt sequence and types of interrupts in 8086? (2016-17)

3. Explain the role of interrupts in programming. (2015-16)

4. Explain the interrupts sequence and types of interrupt in 8086. (2017-18)

5. Explain Minimum Mode operation of 8086 microprocessor with block diagram.

(2017-18)

6. Explain minimum and maximum operating modes of 8086 with timing diagram
(2017-18, 2022-23)
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