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Ee552 Icc2 Lab

The EE552 ICC2 lab involves synthesizing a GDS file using Design compiler output, with detailed steps for setting up the environment and executing commands in ICC2. Key steps include creating a library, reading Verilog files, initializing floorplans, placing components, and saving the GDS file. Observations and discussions focus on GUI screenshots and the purposes of various technology-related files.

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Malith Basnayake
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20 views4 pages

Ee552 Icc2 Lab

The EE552 ICC2 lab involves synthesizing a GDS file using Design compiler output, with detailed steps for setting up the environment and executing commands in ICC2. Key steps include creating a library, reading Verilog files, initializing floorplans, placing components, and saving the GDS file. Observations and discussions focus on GUI screenshots and the purposes of various technology-related files.

Uploaded by

Malith Basnayake
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE552 – ICC2 lab

In this lab, we will synthesize the GDS file using the Design compiler output.

Follow the steps given below;

Step 1:
Log in to the vlsi_lab account of server

Step 2:
Make a folder in the Documents folder in the following format (your folder):
EE552_E19xxx (registration number)

Step 3:
Copy the library files in “/home/vlsi_lab/Documents/sky130_library” directory to your folder.

Step 4:
Copy your Design compiler output Verilog file to your folder.

Step 5:
Open ICC2 using the following command and open the gui using “start_gui” command:
Step 6 :
Create a library in the following naming format using the skywater130_fd_sc_hd.tf technology
file. Using the following command:
Library name should be in the E19xxx format.

Once created save library using the following command:

Step 7 :
Check the current library using:

Step 8 :
Set the reference libraries using the following command ( point to the folder containing ndm
files)

Step 9:
Run the following command
Step 10:
Read the verilog file using: ( Take a screen shot of the gui )

Step 11:
Create a 100 MHz clock using create_clock command.
Step 12:
Initialize floorplan to set the boundaries and shape of the chip. ( Take a screen shot of the gui )
Make sure the boundary is large enough to accomadate all the components.

The Core utilization ratio should be below 100 %.


Step 13:
Define the parasitic values executing the following 2 command lines in order :

Step 14:
Place the components using the place_opt command. This command will take some time to
complete. ( Take a screen shot of the gui )
If completed the following will show the following:

Step 15:
Connect the components using “route_auto” command. ( Take a screen shot of the gui )

Step 16:
Save the GDS to library using the “save_lib” command.

Observations:
1. Images on the gui after executing steps 10, 12, 14 and 15.
2. Results from step 12, 14 and 15 similar to the once given above.
3. Power reports of ICC2 and Design compiler.

Discussion:
1. What are purposes of reading/initiating the following files:
a. Technology file (.tf)
b. tluplus file
c. map file

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