UNIVERSITY OF CALIFORNIA, DAVIS
Department of Electrical and Computer Engineering
EEC 018 DIGITAL SYSTEMS I FALL 2020
LAB 1: Introduction to Quartus Schematic Capture, ModelSim Simulation and the Intel
DE10-Lite Board
Objective:
This lab provides an introduction to a few of the tools you will be using in EEC180A including
the Quartus Prime design software, the Intel DE10-Lite board, and the ModelSim-Intel
simulation software. In this lab, you will use the Quartus schematic capture tool for design entry
and ModelSim to simulate your design. You will verify your design on the Intel DE10-Lite
board. This lab will be done as a self-paced tutorial.
Resources:
The Terasic webpage for the DE10-Lite board contains links to information and resources for the
board. These resources include:
• DE10-Lite User Manual, Version 1.6, Release Date 06-05-2020
• DE10-Lite CD-ROM, Version 2.1.0, Release Date 06-05-2020
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=4
Intel has various tutorials available at:
https://software.intel.com/content/www/us/en/develop/topics/fpga-academic/learn/tutorials.html#ifup-tut-dl
For example, a helpful tutorial is “Quartus Introduction Using Schematic Designs”.
A free version of Quartus Prime Lite Edition can be downloaded from Intel’s webpage:
http://dl.altera.com/?edition=lite
Use the same version of Quartus that is installed in 2110 Kemper (v16.1, Release date:
November, 2016) and use the AkamaiDLM3 Download Manager to download it. The only
device that you will need for this course is the MAX 10 FPGA. You should also get the
ModelSim-Intel simulation software.
I. Schematic Capture Using Quartus Prime
The ECE Department has Intel’s Quartus Prime Version 16.1.0 Standard Edition installed on the
Windows workstations in 2110. To use one of these PCs, you should log in and create a directory
for your projects. For example, you can create a folder eec180a in your My Documents folder.
Then add a folder lab1 under eec180a for this lab.
1. Start Quartus.
2. Click on File > New Project Wizard to start the project wizard. Click Next once you
have read the Introduction page.
- Browse to your working directory such as C:/Users/name/Documents/eec180a/lab1
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- Give the project and the top-level design entity the same name, such as lab1. Click
Next to move to the next page.
- For this tutorial, choose Empty project as the Project Type and then click Next to
move to the next page.
- You don’t need to Add Files to this project, so click Next to move to the next page.
- Under the Device family section, select MAX 10 (CA/DF/DC/SA/SC as the Family.
Under the Target device section, select Specific device selected in ‘Available
devices’ list and choose the device MAX10 10M50DAF484C7G since this is the
FPGA on the DE10-LITE board. The screen should look like Figure 1. Click Next to
move to the next page.
Figure 1 Choosing the Device Family and Device
- For Simulation, select the tool ModelSim-Altera from the drop-down box and
specify the format as Verilog, as shown in Figure 2. Note that Quartus will generate a
Verilog netlist from your schematic, allowing you to easily simulate your design.
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Figure 2 Choosing the ModelSim-Altera simulator
- Click Next to move to the final page. Click Finish once you have reviewed the
Summary page.
3. Open a new schematic page:
- Click File > New and select Block Diagram/Schematic File and click OK.
- Click File > Save As… and specify a file name such as lab1. Make sure the box Add
file to current project is checked and click Save.
4. Start placing components on your blank schematic page:
- Double-click on the blank schematic page to bring up the Symbol dialog box. You
can browse through the libraries to view the various components available.
- Enter 74190 as the Name and click OK. Place the component in the upper middle
portion of your schematic.
- Using the same procedure, add a 7447 to your schematic and align it so that QA – QD
pin labels of the 74190 are directly left of A-D pin labels on the 7447 as shown in
Figure 3.
- Connect the 74190 QA to the 7447 A, QB to B, QC to C and QD to D by selecting
the Orthogonal Node Tool from the menu bar. Click, Hold and Drag from one of the
endpoints to the other end point to make a connection. Tip: Moving the mouse
pointer over the tool icons will display their respective names. The Orthogonal Node
Tool icon looks like this: .
- Note: another way to make signal connections is just to move the arrow cursor
(selection tool) to hover over the end of a pin, such as QA. The arrow will change to a
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‘+’ and show the Orthogonal Node Tool icon. (If this doesn’t happen, make sure
nothing is currently selected by clicking on empty space in the schematic and then
moving the arrow over the pin end.) Once you have the ‘+’ cursor, click, hold and
drag the mouse button to the other endpoint in order to make a connection. The
advantage of this method is that you can automatically go between Selection mode
and Orthogonal Node Tool mode without manually switching back and forth.
- Add an output component to the schematic. Once the output component is on the
schematic, select and drag it until the connection point just touches the end of the
7447 OA pin end and then release the mouse button. Select the output component
again and move it to the right. You will notice that a wire will appear between the two
points, maintaining the connection. (This is known as “rubberbanding” and assumes
that “rubberbanding” or is enabled, which should be default. This is one of the
icons on the menu bar.)
- Continue to add and connect output components to 7447 OB – OG as shown in
Figure 3. You can also use Copy (Ctrl-C) and Paste (Ctrl-V) to add additional output
components.
- Name the output components HEX0[0] to HEX0[6] as shown in Figure 3. You can
double-click on the pin to bring up the Pin Properties dialog box or just click on the
pin name, right-click and select Properties.
- Add a vcc component to the schematic and connect it to the 74190 /LDN pin.
- Add a gnd component and connect it to the 74190 /GN and DNUP pins.
- Add an input component to the 74190 CLK pin and name the input KEY[0].
At this point, your schematic should look like the one shown below in Figure 3.
Figure 3. Initial Schematic
5. Make pin assignments for the DE10-LITE board.
- There are several ways to make pin assignments. One way is to select Assignments >
Assignment Editor and manually enter the pin assignment for each input and output
node. An easier way is to use the DE10-Lite System Builder tool to generate a .qsf
file containing the pin assignments. However, in order to use System Builder to create
pin assignments, you must name the input and output nodes using the default names
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used by System Builder. (These are the names used in Figure 3). These names are
specified in the DE10-Lite User’s Manual as well as in the System Builder output
files..
- Run the System Builder program. Specify the project name, such as lab1, and the I/O
devices that you will use in your project. An example screenshot is shown in Figure
4. There is no problem if you select I/O devices that are not used in your schematic.
Those pin assignments will just be ignored. For example, in Figure 4, the CLOCK,
LEDx10, Buttonx2, 7-Segmentx6 and Switchx10 are all selected, even though they
are not all needed in this design.
Figure 4. Generate Pin Assignments Using System Builder Program
- Click Generate and navigate to your Quartus project directory. Note that System
Builder will not use your Quartus project directory by default. In your project
directory, right click and select New > Folder and name the folder systembuilder.
Double-click on this folder and save the System Builder project in this directory. You
do not want to overwrite the project file, lab1.qpf, which you created earlier. You can
check the systembuilder\lab1.v file to see the default names used by System Builder
for the I/O ports.
- In Quartus, click on Assignments > Import Assignments and select the file
systembuilder\lab1.qsf. This will import the pin assignments generated by System
Builder into your project.
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6. Compile your design by clicking on the Start Compilation icon, , on the menu
toolbar. (You can also select Processing > Start Compilation.) Your design should
compile without errors. You can ignore any warnings.
Note: If you get an Error 275062, it means two components have the same instance
name. You can right-click one of the components and select Properties and give it a
unique instance name.
7. Click on Assignments > Assignment Editor to verify that the proper pin assignments
have been made. There should be a green check next to each port that has been assigned,
shown by the word Ok in Figure 5. The FPGA pin number in the Assignment Editor
should match the location specified in Tables 3-6 and 3-3 in the
DE10_Lite_User_Manual, as shown in Figures 6 and 7.
Ok HEX0[0] Location PIN_C14
Ok HEX0[1] Location PIN_E15
Ok HEX0[2] Location PIN_C15
Ok HEX0[3] Location PIN_C16
Ok HEX0[4] Location PIN_E16
Ok HEX0[5] Location PIN_D17
Ok HEX0[6] Location PIN_C17
Ok KEY[0] Location PIN_B8
Figure 5. Verify Pin Assignments in Assignment Editor
Figure 6. Pin Assignments for DE10-Lite board (see p. 28 in User Manual)
Figure 7. Pin Assignments for DE10-Lite board (see p. 25 in User Manual)
8. Plug the USB cable into the USB Blaster Port on the DE10-LITE board and connect the
other end of the USB cable to your PC. The USB cable will supply power to your DE10-
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Lite board. The USB-Blaster driver should be installed on your system to allow
communication between Quartus and the DE10-LITE board.
9. Click on the Programmer icon, , on the menu tool bar. Make sure the Hardware
Setup is specified as USB-Blaster [USB-0]. Click the Hardware Setup button, select the
Hardware Settings Tab, and verify that USB-Blaster [USB-0] is selected in the Currently
Selected Hardware field. If USB-Blaster is unavailable, that means Windows did not
recognize the device. Make sure your DE10-Lite Board is connected to the PC. If the
board is plugged in to the PC and Windows does not recognize it, you will need to install
the Blaster driver before proceeding. To install the Blaster device driver manually, follow
the Blaster Driver Installation Procedure in the Software Installation Guide handout.
After the Blaster Driver is installed, return to this point of the lab and continue with the
lab.
- Click the Add File… button and select the output file from the output_files folder in
your project folder. The correct output file will have the .sof extension (i.e. lab1.sof).
Your screen should look like Figure 8.
Figure 8. Device Programmer Configuration
- Click Start to load the program into the DE10-LITE board. You should see a “0” on
HEX0 seven segment display on the DE10-LITE board.
10. Press KEY0 on the DE10-LITE board to test your counter circuit. The circuit should
count from 0 to 9 and then roll over to 0 again.
11. Demonstrate your circuit to your TA and have him or her sign your verification
checksheet.
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II. ADDING A CLOCK SOURCE
Next we will add a clock signal to the example design. The Intel DE10-Lite board has two 50
MHz clock sources. (See the p. 24 of the Intel DE10-Lite_User_Manual.pdf). In order to clock
our circuit at a slower rate without the need for an external clock source, we will use another
74190 counter to enable our counter only on every 10th clock cycle.
For this section, create a new project, lab1b, and copy and rename the lab1 schematic in the new
project folder. Follow the same steps as in Part I to create the lab1b Quartus project.
1. Add the following components to your schematic and wire them up as shown below in
Figure 9.
• 74190
• nand2
• not
• vcc
• gnd
• input
• output (6)
Figure 9. Using 50 MHz Clock Signal
Note that you will need to rewire the /GN input of your original circuit so that the counter
is only enabled every 10th clock cycle of the 50 MHz clock. Thus, the original mod-10
counter will operate with an effective clock rate of 5.0 MHz. A solid dark purple circle
represents a wire-to-wire connection, while the absence of the dark solid purple circle
means there is no connection between intersecting wires.
Make sure to give the input and output pins the names shown in Figure 9:
Inputs: SW[0], MAX10_CLK1_50
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Outputs: GPIO[0] – GPIO[5], HEX0[0] – HEX0[6]
These names correspond to the names of the I/O devices used by System Builder. You
could monitor outputs GPIO[0] to GPIO[5] with an oscilloscope or logic analyzer. In the
next section, we will observe these signals in simulation.
2. Import the pin assignments as before. Since we included GPIO, CLOCK and SW signals
in the System Builder configuration for part I, you can import the lab1.qsf file from your
lab1 systembuilder folder. Verify the pin assignments using the Assignment Editor.
3. Compile the new design and program it into the DE10-Lite board as before. Now the
counter will be incrementing at a frequency of 5.0 MHz, which is much too fast to
observe on the 7-segment display. When the counter is counting, the HEX0 7-segment
display will show an 8, since all of the segments will be turning on and off at a very high
rate. However, by disabling the counter by putting SW0 in the ON position, you can stop
the counter and view the current count value. Since the counter is counting so fast, this
circuit acts as a random number generator – stopping the counter will produce a number
between 0 and 9 with essentially equal probability.
III. MODELSIM SIMULATION
Once your schematic has been drawn in Quartus, it is important to verify the functionality of the
design. For small scale designs, it might be simpler to directly implement the design rather than
simulate its functionality. However, in real world designs, logic circuits are often encompass tens
of millions of logic gates making the design impossible to cost effectively implement and test.
For this section, you will reuse the counter circuit from Part II, Figure 9. Since we
specified ModelSim-Altera as the simulation tool when we created the project, the project should
be configured to run ModelSim-Altera.
1. From the Quartus pull-down menu, select Tools > Run Simulation Tool > Gate Level
Simulation. Make sure any previous ModelSim windows are closed.
2. ModelSim will open and your design will be automatically transferred to ModelSim.
Verify this by looking at "work" folder in the Library list window. If the Library
window is not open, select View > Library to open it. Click on the + to expand the work
library. You should see your lab1b project name, which is a Verilog netlist output file, in
the work Library, as shown in Figure 10.
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Figure 10. ModelSim-Altera
3. To simulate your design, select Simulate > Start Simulation… from the toolbar menu.
Click on the Design tab and select your design file in the work library. In Figure 11, the
Verilog netlist file, lab1b, has been selected.
Figure 11. Selecting your Verilog netlist output file to simulate
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10. Next, click the Libraries tab in the same Start Simulation dialog box. Click the Add…
button to the left of the Search Libraries (-L) pane. A Select Library dialog box will pop
up. Select the down arrow and scroll down through the list of libraries. Select
altera_ver and fiftyfivenm_ver, as shown in Figure 12.
Figure 12. Selecting the libraries
11. Click OK to close the dialog box. You can ignore the warnings. Your screen will update
and show you the "sim-Default" and the "Objects" windows.
12. You may or may not have the waveform viewer open. If not, click on View and select
Wave. This will display the waveform viewer window.
13. You are now ready to simulate and view the values of the signals in your design. Let's
add some signals we want to inspect into the Wave window. With your top-level design
file highlighted in the sim-Default window, drag and drop the GPIO, SW, HEX0 and
MAX10_CLK1_50 signals from the Objects window into the Wave window. (Another
method is to select GPIO, SW, HEX0 and MAX10_CLK1_50 in the Objects window,
right-click and select Add Wave). To make the simulation easier to read, right click on
GPIO and change the Radix to Hexadecimal. Do the same for HEX0.
14. For the simulation to function, you need to set up the input stimulus on the input pins of
your design. Right-click on the MAX10_CLK1_50 signal, and select Clock... The
Define Clock window will pop up and from here we can set parameters of the clock. Set
the clock period to 20 ns. Since picoseconds is the default time unit, you need to either
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enter 20000 or 20 ns. This period corresponds to our 50 MHz clock frequency. Leave the
other settings at their default values and select OK to close the Define Clock window.
14. Right-click on the SW signal and select Force... The Force Selected Signal window will
pop up. This window is used to force signals in your design to logic 0 or logic 1. Enter
the digit 0 (zero) in the Value field and select Drive in the Kind field. Press OK to save
changes and close the window.
15. You are now finished with setting up the input stimulus. Enter 220 ns in the simulation
time in order to simulate 11 clock cycles, and click the Run icon, . You can also type
in the command line 'run 220 ns' (without quotes) and the simulation will run for 220 ns.
Another option is to press the F9 hotkey.
16. Select View > Zoom > Zoom Full in order to display the full 11 clock cycles in the
Wave window. After 22 clock cycles, your output should match the waves shown below
in Figure 13.
Figure 13. ModelSim Wave Window
17. Continue to simulate your design and change the input stimulus to determine whether or
not your design functions as expected.
- Does each waveform match the behavior of the corresponding signal when the circuit
operates on the DE10-LITE board?
Demonstrate to your TA that you can simulate the circuit in ModelSim by demonstrating that
you can reproduce Figure 13 and have your TA sign your lab verification sheet.
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