Department of Electrical Engineering
Faculty Member:____________________ Dated: ________________
Semester: 2nd semester Section: BSCS 14-A
Group No. : 09
EE-221: Digital Logic Design
Lab 2: Introduction to Verilog
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performance of data in Tool Usage Safety and Team marks
Lab Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
Saneha Akhtar 517085
Hammad Asim 513776
Azka Hafeez 501760
Muhammad Murtaza 503477
EE-221: Digital Logic Design Page 1
Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
Implementation of Basic Logic Circuit
This Lab has been divided into two parts.
In first part you will be introduced to Verilog and Gate-Level Modeling.
The next part is the hardware implementation of a Boolean function given to you.
Objectives:
Understand HDL and compare it with normal programming languages.
Simulate Basic Gates using Verilog with ModelSim
Write stimulus using Verilog
Derive algebraic expression for a Boolean function from the given schematics.
Hardware Implementation of Logic Circuit
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
The lab report will be uploaded on LMS three days before scheduled lab date. The students will
get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it
with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed
lab report on LMS for grading.
The students failing to submit Pre-Lab will not be allowed to perform Lab work.
The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
The students will complete lab task and submit complete report to Lab Engineer before leaving
lab. Verilog tutorial part is non-printable and for reference only.
There are related questions at the end of this activity. Give complete answers.
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Pre-Lab Task: (To be done before coming to the lab) (2 marks)
1. Read the manual Getting Started with Verilog and answer the following questions.
a) HDL stands for
Hardware Description Languages
b) Two standard versions of HDL are
VHDL and Verilog HDL
c) Give the different levels of abstraction in Verilog HDL
Gate Level Modeling
Dataflow Modeling
Behavioral Modeling
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Lab Tasks: (8 marks)
Lab Task 1: (2 marks)
Model and simulate the basic gates i.e. NOT, AND & OR in Verilog (Gate level) using Modelsim. Compare
the simulation waveform results with truth table in the space given below.
OR:
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AND:
NOT:
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Lab Task 2: (2 marks)
Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well
as stimulus below:
Simulate below circuit on Proteus and perform it on hardware.
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CODE:
module task2(sum ,carry, A , B);
input A,B;
output sum,carry;
not a1(out , in1 ,in2);
wire w1,w2,w3,w4;
not not1(w1,A);
and and1(w3,w1,B);
not not2(w2,B);
and and2(w4,w2,A);
or or1(sum,w3,w4);
and and3(carry,A.B);
endmodule
module test04;
reg A,B;
wire sum,carry;
task1 t1(sum,carry,A,B);
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initial
begin #100 A=1'b0;B=1'b0;
#100 A=1'b0;B=1'b1;
#100 A=1'b1;B=1'b0;
#100 A=1'b1;B=1'b1;
End
endmodule
WAVE FORM
PROTEUS DIAGRAMS:
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Lab Task 3: (2 marks)
Label each gate output in the above circuit and derive algebraic expressions for SUM and Carry Out. Fill in
the following truth table and determine the function performed by the circuit.
Truth Table:
x y Sum Carry Out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Lab Task 4: (2 marks)
After determining the function performed by the circuit given in Lab Task 2, write the Verilog description of
the circuit in dataflow. Comment on the two different modeling levels you used to model the same circuit.
(Paste snapshots of the codes and stimuluses below)
CODE:
module add(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = (a & ~b) ^ (~a & b);
assign carry = a & b;
endmodule
module task2;
reg IN1, IN2;
wire SUM,CARRY;
add a1(IN1, IN2, SUM, CARRY);
initial
begin
#100 IN1 = 1'b0; IN2 = 1'b0;
#100 IN1 = 1'b0; IN2 = 1'b1;
#100 IN1 = 1'b1; IN2 = 1'b0;
#100 IN1 = 1'b1; IN2 = 1'b1;
end
endmodule
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Observations/Comments:
In conclusion, we found that Dataflow modeling was more effective compared to
the Gate Modeling Level. Dataflow modeling was simpler, more readable, and
easier to understand, making it better for designing and analyzing systems.
Its clarity also makes development and debugging easier, making it the preferred
choice over Gate Modeling
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