Array Multiplier

An array multiplier is a digital combinational circuit used for multiplying two binary numbers by
employing an array of full adders and half adders. This array is used for the nearly simultaneous
addition of the various product terms involved. To form the various product terms, an array of
AND gates is used before the Adder array.

Checking the bits of the multiplier one at a time and forming partial products is a sequential
operation that requires a sequence of add and shift micro-operations. The multiplication of two
binary numbers can be done with one micro-operation by means of a combinational circuit that
forms the product bits all at once. This is a fast way of multiplying two numbers since all it takes
is the time for the signals to propagate through the gates that form the multiplication array.
However, an array multiplier requires a large number of gates, and for this reason it was not
economical until the development of integrated circuits.

For implementation of array multiplier with a combinational circuit, consider the multiplication
of two 2-bit numbers as shown in figure. The multiplicand bits are b1 and b0, the multiplier bits
are a1 and a0, and the product is c3c2c1c0

Assuming A = a1a0 and B= b1b0, the various bits of the final product term P can be written as:-

1. P(0)= a0b0

2. P(1)=a1b0 + b1a0

3. P(2) = a1b1 + c1 where c1 is the carry generated during the addition for the P(1) term.

4. P(3) = c2 where c2 is the carry generated during the addition for the P(2) term.

For the above multiplication, an array of four AND gates is required to form the various product
terms like a0b0 etc. and then an adder array is required to calculate the sums involving the
various product terms and carry combinations mentioned in the above equations in order to
get the final Product bits.
 1. The first partial product is formed by multiplying a0 by b1, b0. The multiplication of two
bits such as a0 and b0 produces a 1 if both bits are 1; otherwise, it produces 0. This is
identical to an AND operation and can be implemented with an AND gate.
2. The first partial product is formed by means of two AND gates.
3. The second partial product is formed by multiplying a1 by b1b0 and is shifted one
position to the left.
4. The above two partial products are added with two half-adder(HA) circuits. Usually
there are more bits in the partial products and it will be necessary to use full-adders to
produce the sum.
5. Note that the least significant bit of the product does not have to go through an adder
since it is formed by the output of the first AND gate.

A combinational circuit binary multiplier with more bits can be constructed in similar fashion. A
bit of the multiplier is ANDed with each bit of the multiplicand in as many levels as there are
bits in the multiplier. The binary output in each level of AND gates is added in parallel with the
partial product of the previous level to form a new partial product. The last level produces the
product. For j multiplier bits and k multiplicand we need j*k AND gates and (j-1) k-bit adders to
produce a product of j+k bits.
 RISC vs CISC

RISC CISC
Focus on software Focus on hardware
Uses only Hardwired control unit Uses both hardwired and microprogrammed
control unit
Transistors are used for more registers Transistors are used for storing complex
Instructions
Fixed sized instructions Variable sized instructions
Can perform only Register to Register Can perform REG to REG or REG to MEM or
Arithmetic operations MEM to MEM
Requires more number of registers Requires less number of registers
Code size is large Code size is small
An instruction executed in a single clock cycle Instruction takes more than one clock cycle
An instruction fit in one word. Instructions are larger than the size of one
word
Simple and limited addressing modes. Complex and more addressing modes.
RISC is Reduced Instruction Cycle. CISC is Complex Instruction Cycle.
The number of instructions are less as The number of instructions are more as
compared to CISC. compared to RISC.
It consumes the low power. It consumes more/high power.
RISC is highly pipelined. CISC is less pipelined.
RISC required more RAM . CISC required less RAM.
Here, Addressing modes are less. Here, Addressing modes are more.
 Carry Look Ahead adders
A carry-look ahead adder (CLA) is a type of adder used in digital logic. A carry-look ahead adder
improves speed by reducing the amount of time required to determine carry bits. The carry-
look ahead adder calculates one or more carry bits before the sum, which reduces the wait
time to calculate the result of the larger value bits.

CLA – Concept

 To reduce the computation time, there are faster ways to add two binary numbers by using
carry lookahead adders.

 They work by creating two signals P and G known to be Carry Propagator and Carry
Generator.

 The carry propagator is propagated to the next level whereas the carry generator is used to
generate the output carry regardless of input carry.

 The block diagram of a 4-bit Carry Lookahead Adder is shown here below
Design Issues

The corresponding boolean expressions are given here to construct a carry lookahead adder. In
the carry-lookahead circuit we ned to generate the two signals carry propagator(P) and carry
generator(G),

 Pi = Ai ⊕ Bi
 Gi = Ai · Bi

The output sum and carry can be expressed as

 Sumi = Pi ⊕ Ci
 Ci+1 = Gi + ( Pi · Ci)

Having these we could design the circuit.

We can now write the Boolean function for the carry output of each stage and substitute for
each Ci its value from the previous equations:

 C1 = G0 + P0 · C0
 C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0
 C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0
 C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0
 A B C-out
0 0 0 “kill”
0 1 C-in “propagate”
1 0 C-in “propagate”
1 1 1 “generate”

Generate: Cout = 1 independent of C

 G =A • B

Propagate: Cout = C

Kill: Cout = 0 independent of C

 K =~A • ~B

Cout = G + P.Cin

Algebraic calculations for carry out

• ci+1 = gi + pici

c1 = g0 + p0c0

c2 = g1 + p1c1

= g1 + p1(g0 + p0c0)

= g1 + p1g0 + p1p0c0

c3 = g2 + p2c2

= g2 + p2(g1 + p1g0 + p1p0c0)

= g2 + p2g1 + p2p1g0 + p2p1p0c0

c4 = g3 + p3c3

= g3 + p3(g2 + p2g1 + p2p1g0 + p2p1p0c0)

= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0