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Introduction to AVR Microcontrollers

AVR microcontrollers are a family of 8-bit RISC-based microcontrollers widely used in
embedded systems. They are known for their high performance, efficient power consumption,
and flexibility in programming and application.
Definition:
AVR microcontrollers are 8-bit RISC (Reduced Instruction Set Computer) microcontrollers
designed for embedded applications. They use an enhanced RISC architecture, enabling most
instructions to execute in a single clock cycle, which boosts processing speed and efficiency.
Key Features
1. High Performance (1 MIPS/MHz Throughput)
• Single-Cycle Execution: Most instructions on AVR microcontrollers execute in a single
clock cycle, allowing the device to achieve up to 1 Million Instructions Per Second
(MIPS) per MHz of clock frequency. For example, an 8 MHz AVR can deliver up to 8 MIPS.
• Comparison: This is significantly faster than many comparable microcontrollers, such
as PIC, which typically require multiple clock cycles per instruction.
• Optimized ALU: The optimized Arithmetic Logic Unit (ALU) and 32 general-purpose
registers contribute to this high throughput.
2. Low Power Consumption
• Multiple Power Modes: AVR microcontrollers support several power-saving modes,
including Idle, Standby, Power-Down, and ADC Noise Reduction modes.
• Active Mode: Full operation, highest power consumption.
• Idle Mode: CPU halted, peripherals active; reduces consumption to about 25%
of active mode.
• Power-Down Mode: Most of the chip is powered off except for essential
functions; current can drop to as low as 100 nA.
• ADC Noise Reduction Mode: Minimizes digital noise during analog-to-digital
conversions for more accurate readings.
• Real-World Example: At 1 MHz and 1.8V, an ATmega328P consumes about 300 μA in
active mode, 40 μA in idle, 0.7 μA in power save, and 100 nA in power-down mode.
3. In-System Programmable (ISP) Flash Memory
• Self-Programmable Flash: AVR microcontrollers feature non-volatile Flash memory
that can be programmed and reprogrammed while the chip is installed in a system,
using ISP techniques.
• True Read-While-Write: Some AVR devices allow code execution from one section of
Flash while another section is being programmed.
• Memory Endurance: Flash memory typically supports 10,000 write/erase cycles and
data retention of up to 100 years at room temperature.
 • Bootloader Support: Many AVRs include a boot code section for secure and flexible
firmware updates.
Summary Table

Feature Details

Architecture 8-bit RISC, single-cycle instruction execution

Throughput Up to 1 MIPS/MHz (e.g., 16 MIPS at 16 MHz)

Power Modes Active, Idle, Standby, Power-Down, ADC Noise Reduction

Flash Memory In-system programmable, high endurance, supports bootloader

Application Widely used in robotics, automation, consumer electronics, and IoT

AVR microcontrollers are popular due to their blend of speed, power efficiency, and ease of use,
making them ideal for a wide range of embedded applications

Mega AVR Series: ATmega16/32 and Related Features

The Mega AVR series is a prominent family within the AVR microcontroller lineup, including
models like ATmega16, ATmega32, ATmega328, and others. These microcontrollers are widely
used in embedded systems for their robust features, high performance, and versatility.
Key Features of ATmega16/32
• Architecture and Performance
• 8-bit AVR enhanced RISC architecture.
• Executes most instructions in a single clock cycle, achieving up to 1 MIPS/MHz
for efficient processing.
• Operates at up to 16 MHz clock frequency.
• Memory
• Flash Memory:
• ATmega16: 16 KB in-system programmable Flash with Read-While-Write
capability.
• ATmega32: 32 KB in-system programmable Flash.
• SRAM:
• ATmega16: 1 KB.
• ATmega32: 2 KB.
 • EEPROM:
• ATmega16: 512 bytes.
• ATmega32: 1024 bytes.
• I/O and Package
• 40-pin Dual Inline Package (DIP) and 44-pin TQFP/SMD packages available.
• 32 programmable general-purpose I/O lines, supporting a wide range of digital
interfacing.
• Peripheral Features
• Timers/Counters: Three flexible timers (two 8-bit, one 16-bit) with compare
modes.
• ADC: 8-channel, 10-bit Analog-to-Digital Converter (ADC) for analog sensor
interfacing.
• Communication Interfaces:
• USART (Universal Synchronous/Asynchronous Receiver/Transmitter).
• SPI (Serial Peripheral Interface).
• I2C (Two-wire Serial Interface).
• JTAG Interface: For on-chip debugging and boundary scan.
• Watchdog Timer: With internal oscillator for system reliability.
• Interrupts: Internal and external interrupts for responsive system design.
• Power and Operating Conditions
• Operating voltage: 2.7V to 5.5V.
• Multiple power-saving modes for energy-efficient applications.

Summary Table: ATmega16 vs ATmega32

Feature ATmega16 ATmega32

Flash Memory 16 KB 32 KB

SRAM 1 KB 2 KB

EEPROM 512 bytes 1024 bytes

I/O Pins 32 32

Timers/Counters 3 (2 x 8-bit, 1 x 16-bit) 3 (2 x 8-bit, 1 x 16-bit)

Feature ATmega16 ATmega32

ADC Channels 8 (10-bit) 8 (10-bit)

Max Clock Speed 16 MHz 16 MHz

Package 40-pin DIP, 44-pin TQFP 40-pin DIP, 44-pin TQFP

Communication USART, SPI, I2C, JTAG USART, SPI, I2C, JTAG

Operating Voltage 2.7V – 5.5V 2.7V – 5.5V

Notable Advantages
• Scalability: The Mega AVR series offers a range of memory sizes and features, making it
easy to scale designs up or down.
• Versatility: With rich peripherals and robust I/O, these microcontrollers are suitable for
automation, robotics, consumer electronics, and more.
• Ease of Programming: In-system programmable Flash and comprehensive
development tools support rapid prototyping and deployment.
The ATmega16/32 microcontrollers exemplify the Mega AVR series' strengths, providing a
balanced mix of memory, speed, and peripheral support ideal for a wide variety of embedded
applications

ATmega16/32 Architecture
The ATmega16 and ATmega32 microcontrollers are based on the AVR family’s advanced RISC
architecture, which is designed for high efficiency and performance in embedded applications.
1. Harvard Architecture
• Definition:
The ATmega16/32 uses a Harvard architecture, meaning it has separate memory spaces
and buses for program instructions (Flash memory) and data (SRAM, EEPROM).
• Advantages:
• Parallel Access: The CPU can fetch instructions and perform data operations
simultaneously, increasing throughput.
• Faster Execution: Most instructions execute in a single clock cycle.
2. Core Components
a) Arithmetic Logic Unit (ALU)
• Function:
The ALU performs arithmetic operations (addition, subtraction, multiplication, division)
and logic operations (AND, OR, NOT, XOR).
• Role in CPU:
It processes data from the general-purpose registers and is central to executing
instructions.
b) 32 General-Purpose Registers
• Description:
• The ATmega16/32 features 32 x 8-bit general-purpose working registers (R0–
R31).
• These registers are directly connected to the ALU, allowing two registers to be
accessed in a single clock cycle.
• Benefit:
• Reduces the need for frequent memory access, making operations faster and
more efficient.
c) Interrupt Unit
• Interrupt Sources:
• The ATmega16/32 can handle more than 21 different interrupt sources,
including:
• External interrupts (e.g., INT0, INT1, INT2)
• Timer/Counter interrupts (overflow, compare match)
• ADC conversion complete
• USART, SPI, and other peripheral interrupts
• Interrupt Vector Table:
• Each interrupt source has a dedicated vector address in program memory,
allowing the microcontroller to quickly jump to the appropriate Interrupt Service
Routine (ISR).
• Benefits:
• Enables responsive, real-time event handling.
• Reduces CPU idle time by responding to hardware events immediately.
3. Additional Architectural Features
• Program Memory (Flash):
• Non-volatile, stores the application code (16 KB for ATmega16, 32 KB for
ATmega32).
 • Data Memory (SRAM):
• Volatile, used for temporary data storage during program execution.
• EEPROM:
• Non-volatile, used for storing data that must be retained even when power is off.
• I/O Ports:
• 32 programmable I/O lines, grouped into PORTA, PORTB, PORTC, and PORTD.
• Peripheral Modules:
• Timers/Counters, ADC, USART, SPI, I2C, and Watchdog Timer are integrated into
the architecture.
Block Diagram Overview (Textual Description)
Summary Table

Component Description

Harvard Architecture Separate program and data memory buses for faster operation

ALU Performs arithmetic and logic operations

32 Registers Fast data access, reduces memory bottleneck

Interrupt Unit Handles 21+ interrupt sources for real-time responsiveness

Flash Memory Stores program code (16/32 KB)

SRAM Temporary data storage (1/2 KB)

EEPROM Non-volatile data storage (512/1024 Bytes)

I/O Ports 32 programmable lines for interfacing

Peripherals Timers, ADC, USART, SPI, I2C, etc.

In summary:
The ATmega16/32 architecture is designed for high speed and efficiency, combining a powerful
ALU, a large register set, flexible interrupt handling, and a Harvard architecture to deliver robust
performance for embedded systems.

ATmega16/32 Pin Configuration and I/O Registers

Pin Types and Their Functions

Pin Type Functionality Examples

General-purpose I/O, alternate functions (ADC,

I/O Ports PWM, etc.) PORTA, PORTB, PORTC, PORTD

Power Pins Supply voltage and ground VCC (Pin 10), GND (Pin 11, Pin 31)

MOSI (Pin 6), TXD (Pin 15), SCL

Communication Serial protocols (SPI, USART, TWI/I2C) (Pin 22)
 • I/O Ports: 32 pins divided into four 8-bit ports (PORTA, PORTB, PORTC, PORTD). Each
pin can serve as a general-purpose I/O or have alternate functions like ADC input, PWM
output, SPI, USART, etc.
• Power Pins: VCC (typically 5V) and multiple GND pins for reliable operation. Additional
pins like AVCC and AREF are used for analog functions.
• Communication Pins: Dedicated pins for serial interfaces-SPI (Pins 5–8), USART (Pins
14–15), TWI/I2C (Pins 22–23).
I/O Port Registers
Each port is controlled by three key 8-bit registers:

Register Purpose Example (for Port B)

DDRx Data Direction Register: Sets pin as input (0) or output (1) DDRB = 0xFF; (all output)

Output Register: Sets output value or enables pull-up PORTB = 0x0F; (lower 4 pins
PORTx resistor HIGH)

PINx Input Register: Reads logic level on the port pins value = PINB;

• DDRx:
• Writing 1 configures the pin as output, 0 as input.
• Example: DDRD = 0xFF; sets all pins of PORTD as output.
• PORTx:
• For output pins: Sets the output value (HIGH/LOW).
• For input pins: Writing 1 enables the internal pull-up resistor.
• Example: PORTD = 0x0F; sets PD0–PD3 HIGH.
• PINx:
• Reads the current logic value of the port pins.
• Example: port_value = PIND; reads all 8 pins of PORTD.
Programming Examples
Set All Pins of PORTB as Output and Set Lower 4 Pins HIGH
DDRB = 0xFF; // Set PORTB as output
PORTB = 0x0F; // Set PB0–PB3 HIGH, PB4–PB7 LOW
Configure Individual Pins
• Set PD3 as Output, PD2 as Input, Enable Pull-up on PD2:
DDRD = DDRD | (1<<3); // Make PD3 output
DDRD = DDRD & (~(1<<2)); // Make PD2 input
PORTD = PORTD | (1<<2); // Enable pull-up on PD2
• Read Input Pin Status:
int pin_status;
pin_status = PIND & (1<<2); // Read status of PD2
Special Notes
• Many I/O pins have multiple functions (e.g., ADC, PWM, interrupts, serial
communication). If a pin is used for an alternate function, it cannot be used as a
general-purpose I/O at the same time.
• Internal pull-up resistors can be enabled for input pins by writing 1 to the corresponding
bit in the PORTx register while the pin is configured as input.
Summary:
ATmega16/32 microcontrollers feature 32 flexible I/O pins managed via three registers per port
(DDRx, PORTx, PINx), supporting both digital I/O and alternate functions. Proper configuration of
these registers enables straightforward interfacing with LEDs, sensors, switches, and
communication modules.

Interrupts in ATmega16/32
Interrupts allow the ATmega16/32 microcontroller to respond immediately to important events,
pausing the main program flow to execute a special function called an Interrupt Service Routine
(ISR). This mechanism is crucial for real-time and responsive embedded systems.
Types of Interrupts
1. External Interrupts
• INT0, INT1, INT2:
• Located on pins PD2 (INT0), PD3 (INT1), and PB2 (INT2).
• Triggered by external signals, such as a button press or sensor output.
• INT0 and INT1 can be configured as level-triggered or edge-triggered; INT2 is only
edge-triggered.
• Enable/disable using the GICR register.
2. Timer/Counter Interrupts
• Generated by the internal timers/counters.
• Types include:
• Overflow Interrupts: Triggered when the timer/counter exceeds its maximum
value.
• Compare Match Interrupts: Triggered when the timer value matches a set
compare value.
• Used for precise timing operations, PWM, and event counting.
3. ADC Conversion Complete Interrupt
• Triggered when an Analog-to-Digital Conversion is finished.
• Allows the microcontroller to process sensor data as soon as it is available without
polling.
Interrupt Vector Table
• The interrupt vector table is a section of program memory that holds the addresses of
all ISRs.
• When an interrupt occurs, the microcontroller:
1. Completes the current instruction.
2. Saves the address of the next instruction (program counter) on the stack.
3. Jumps to the ISR address specified in the interrupt vector table.
• Each interrupt source has a unique vector (fixed memory address) for its ISR.
• Example (ATmega32):
• Vector 2: INT0 (INT0_vect)
• Vector 3: INT1 (INT1_vect)
• Vector 14: Timer1 Overflow (TIMER1_OVF_vect)
• Vector 22: ADC Conversion Complete (ADC_vect).
Key Points on Interrupt Handling
• The global interrupt enable/disable is controlled by the I-bit (bit 7) in the Status Register
(SREG). Use SEI (Set Interrupt) to enable and CLI (Clear Interrupt) to disable all
interrupts.
• Each interrupt has an enable bit in a specific control register (e.g., GICR for external
interrupts).
• ISRs should be kept as short and efficient as possible to avoid missing other interrupts.

Summary Table: Common Interrupts and Vectors (ATmega32)

Interrupt Source Vector Name Typical Use

External INT0 INT0_vect Respond to external event on PD2

External INT1 INT1_vect Respond to external event on PD3

External INT2 INT2_vect Respond to external event on PB2

Timer/Counter Overflow TIMERx_OVF_vect Timer-based tasks, periodic interrupts

Interrupt Source Vector Name Typical Use

Timer Compare Match TIMERx_COMP_vect Precise timing, PWM control

ADC Conversion Complete ADC_vect Process sensor data as soon as ready

In summary:
ATmega16/32 supports multiple interrupt types (external, timer/counter, ADC, etc.), each
mapped to a unique vector in the interrupt vector table. This system enables the microcontroller
to handle asynchronous events efficiently and reliably

ADC (Analog-to-Digital Converter) in ATmega16/32

Overview
• Resolution: 10-bit (digital output ranges from 0 to 1023).
• Channels: 8 multiplexed input channels (ADC0–ADC7), allowing up to 8 analog signals
to be sampled via PORTA.
• Step Size: With a 5V reference, each step is approximately 4.88 mV; with a 2.56V
reference, each step is about 2.5 mV.
Key Features
• Input Pins: ADC channels are mapped to PORTA (pins 33–40 on ATmega32).
• Reference Voltage: Selectable as AVcc (external 5V), internal 2.56V, or external voltage
via the AREF pin.
• Output Registers: The 10-bit result is stored across two registers: ADCL (low byte) and
ADCH (high byte).
• Conversion Time: Determined by the ADC clock, which must be less than 200 kHz for
accuracy. Use a prescaler to divide the main clock to an appropriate frequency.
Main ADC Registers

Register Function

ADMUX Selects input channel (ADC0–ADC7) and reference voltage.

ADCSRA Controls ADC enable, start conversion, prescaler selection, and interrupt enable.

ADCH/ADCL Hold the 10-bit conversion result (ADCH: high 2 bits, ADCL: low 8 bits).

ADMUX Register
• Bits 0–4: Channel selection (00000 for ADC0, 00001 for ADC1, ..., 00111 for ADC7).
• Bits 6–7: Reference voltage selection (e.g., AVcc, internal 2.56V, AREF pin).
 • Bit 5: Adjusts result left/right in ADCH/ADCL.
ADCSRA Register
• ADEN: ADC Enable.
• ADSC: Start Conversion.
• ADPS2:0: Prescaler selection for ADC clock (e.g., 128 for 16 MHz system clock).
• ADIF: ADC Interrupt Flag (set when conversion completes).
ADC Operation Steps
1. Set the ADC channel pin as input.
2. Configure ADMUX for channel and reference voltage.
3. Set ADCSRA to enable ADC, select prescaler, and optionally enable interrupt.
4. Start conversion by setting ADSC in ADCSRA.
5. Wait for conversion to complete (poll ADIF or use interrupt).
6. Read the result from ADCL and ADCH.
Example: Reading ADC Value
uint16_t read_adc(uint8_t channel) {
ADMUX = (ADMUX & 0xF0) | (channel & 0x0F); // Select channel
ADCSRA |= (1 << ADSC); // Start conversion
while (ADCSRA & (1 << ADSC)); // Wait for completion
return ADCW; // Read 10-bit result
}
Timers/Counters in ATmega16/32
ATmega16/32 features three flexible timers/counters for timing, counting, and waveform
generation.

Timer Size Modes Supported Key Registers

0 8-bit Normal, CTC, Fast PWM TCCR0, TCNT0, OCR0

1 16-bit Normal, CTC, Input Capture, PWM TCCR1A, TCCR1B, ICR1, OCR1A/B

2 8-bit Normal, CTC, Fast PWM, Asynchronous TCCR2, TCNT2, OCR2, ASSR

Timer/Counter Functions
• Normal Mode: Simple counting, generates overflow interrupts.
• CTC (Clear Timer on Compare Match): Timer resets when it matches a preset value,
useful for precise time intervals.
 • PWM (Pulse Width Modulation): Generates PWM signals for controlling motors, LEDs,
etc.
• Input Capture (Timer1 only): Captures the timer value at the moment an external event
occurs (useful for measuring pulse widths).
• Asynchronous Operation (Timer2): Can use an external clock source for real-time
clock applications.
Key Registers
• TCCRn (Timer/Counter Control Register): Configures mode and prescaler.
• TCNTn (Timer/Counter Register): Holds the current count value.
• OCRn (Output Compare Register): Used for CTC and PWM modes.
• ICR1 (Input Capture Register, Timer1 only): Captures timer value on input event.
Summary Table

Feature ADC Timer/Counter 0 Timer/Counter 1 Timer/Counter 2

Resolution 10-bit (0–1023) 8-bit 16-bit 8-bit

Channels 8 (ADC0–ADC7) N/A N/A N/A

Key ADMUX, ADCSRA, TCCR0, TCNT0, TCCR1A/B, ICR1, TCCR2, TCNT2,

Registers ADCH, ADCL OCR0 OCR1A/B OCR2, ASSR

Single conversion, Normal, CTC, Normal, CTC, Input Normal, CTC, PWM,
Modes Free running PWM Capture, PWM Async

Sensor interfacing, Timing, PWM, Input

Applications data acquisition Timing, PWM Capture Timing, PWM, RTC

In summary:
The ATmega16/32 provides a powerful 10-bit, 8-channel ADC for analog interfacing, with flexible
configuration via ADMUX and ADCSRA registers. Its three timers/counters (two 8-bit, one 16-bit)
support multiple modes for timing, counting, PWM, and input capture, making them essential
for real-time and control applications
Communication Protocols in ATmega16/32
SPI (Serial Peripheral Interface)
Overview:
SPI is a synchronous, full-duplex serial communication protocol used for short-distance
communication, primarily in embedded systems. It allows a single master device to
communicate with one or more slave devices using four main lines: MOSI, MISO, SCK, and SS.
Pin Functions:
• MOSI (Master Out Slave In): Data sent from master to slave.
• MISO (Master In Slave Out): Data sent from slave to master.
• SCK (Serial Clock): Clock signal generated by the master.
• SS (Slave Select): Selects the slave device (active low).

SPI Pin ATmega16 Pin Master Mode Direction Slave Mode Direction

MISO 7 Input Output

MOSI 6 Output Input

SCK 8 Output Input

SS 5 Output Input

Operation:
• Both master and slave have 8-bit shift registers for data transfer.
• Data is exchanged simultaneously (full-duplex) with each clock pulse.
• The master initiates communication by pulling SS low and generating clock pulses on
SCK.
Key Registers:
• SPCR (SPI Control Register):
• Enables/disables SPI, selects master/slave mode, sets clock polarity, phase,
and data order.
• Key bits: SPE (SPI Enable), MSTR (Master/Slave Select), SPR1:0 (Clock Rate
Select), SPIE (Interrupt Enable).
• SPSR (SPI Status Register):
• Indicates transfer completion (SPIF), write collision (WCOL), and double speed
option (SPI2X).
 • SPDR (SPI Data Register):
• Holds data to be transmitted or received. Writing to SPDR starts the
transmission.
Typical SPI Master Write Sequence:
1. Set SS, MOSI, SCK as outputs; MISO as input.
2. Configure SPCR for master mode and desired clock rate.
3. Write data to SPDR.
4. Wait for SPIF flag in SPSR to indicate transfer completion.
5. Read SPDR to clear the flag.
USART (Universal Synchronous/Asynchronous Receiver/Transmitter)
Overview:
USART provides full-duplex serial communication and can operate in both synchronous and
asynchronous modes. It is used to connect the microcontroller to devices like computers,
GSM/GPS modules, or other microcontrollers.
Key Features:
• Full-duplex: Simultaneous transmission and reception.
• Configurable: Supports various baud rates, data bits, parity, and stop bits.
Baud Rate Setting:
• Baud rate is set using the UBRR (USART Baud Rate Register), which is split into UBRRH
(high byte) and UBRRL (low byte).
• Formula for baud rate:

Key Registers:
• UBRRH/UBRRL: Set baud rate.
• UCSRB: Enables transmission (TXEN), reception (RXEN), and interrupts.
• UCSRC: Configures frame format (data bits, parity, stop bits).
• UDR: Data register for sending/receiving bytes.
• UCSRA: Status register; flags for transmission/reception completion (TXC, RXC), and
data register empty (UDRE).
Typical Initialization Steps:
1. Set baud rate in UBRRH and UBRRL.
 2. Configure frame format in UCSRC.
3. Enable transmitter and/or receiver in UCSRB.
4. Use UDR for data transmission and reception.
Summary Table

Protocol Mode Pins Used Key Registers Features

SPI Sync, duplex MOSI, MISO, SCK, SS SPCR, SPSR, SPDR Fast, multi-slave, full-duplex

USART Sync/Async TXD, RXD UBRRH/L, UCSRB/C, UDR Configurable, full-duplex

In summary:
SPI and USART are essential communication protocols in ATmega16/32. SPI enables fast,
synchronous, multi-device communication using MOSI, MISO, SCK, and SS, managed by SPCR,
SPSR, and SPDR registers. USART supports configurable, full-duplex serial communication, with
baud rate set via UBRR and data handled through UDR, UCSRB, and UCSRC

Memory Programming in ATmega16/32

ATmega16/32 microcontrollers feature three main types of on-chip memory: Flash, SRAM, and
EEPROM. Each serves a distinct purpose in embedded applications and can be programmed
using In-System Programming (ISP) or JTAG methods.
1. Flash Memory
• Purpose: Stores program code (firmware).
• Size: 16 KB (ATmega16) or 32 KB (ATmega32).
• Organization: Divided into Application and Boot sections; supports Read-While-Write
operations, allowing code execution while new code is written to a different section.
• Endurance: Minimum of 10,000 write/erase cycles.
• Programming: Can be programmed in-system using ISP (via SPI) or JTAG.
• Security: Boot Lock bits protect the bootloader and application code.
2. SRAM (Static RAM)
• Purpose: Temporary, volatile data storage during program execution.
• Size: 1 KB (ATmega16) or 2 KB (ATmega32).
• Features: Fast access; data lost when power is removed.
• Usage: Stores variables, stack, and runtime data.
3. EEPROM (Electrically Erasable Programmable Read-Only Memory)
• Purpose: Non-volatile storage for data that must persist after power-off (e.g., calibration
constants, settings).
 • Size: 512 bytes (ATmega16) or 1024 bytes (ATmega32).
• Endurance: Up to 100,000 write/erase cycles.
• Access: Byte-wise read/write operations; slower than SRAM.
• Programming: Can be accessed and modified in-system by the running program.
Programming Methods
A. ISP (In-System Programming) via SPI
• How it works: Uses the SPI interface to program the microcontroller directly on the
target board without removing it.
• Tools: USBASP, AVRISP, or similar programmers.
• Applications: Firmware updates, production programming.
B. JTAG (Joint Test Action Group)
• How it works: Provides high-speed programming and in-system debugging.
• Features: Allows breakpoints, memory inspection, and code stepping for debugging.
• Tools: JTAG-ICE, compatible programmers/debuggers.
Example Applications
1. GPIO Control (LED Blinking, Button Input)
• Description: Use I/O pins to control LEDs or read switches.
• Example:

DDRD |= (1 << 3); // Set PD3 as output (LED)

DDRD &= ~(1 << 2); // Set PD2 as input (Button)
PORTD |= (1 << 2); // Enable pull-up resistor on PD2
while(1) {
if (PIND & (1 << 2)) PORTD |= (1 << 3); // If button pressed, turn on LED
else PORTD &= ~(1 << 3); // Else, turn off LED
}

2. ADC (Reading Sensor Data)

• Description: Read analog signals (e.g., temperature sensors) using the ADC.
• Example:
• Configure ADC registers to select channel and start conversion.
• Wait for conversion to complete and read the result.
3. Timer PWM (Motor Speed Control)
 • Description: Use timer in PWM mode to control motor speed or LED brightness.
• Example:
• Set timer registers for PWM mode.
• Adjust duty cycle to vary speed or brightness.
Summary Table

Memory Size (ATmega16/32) Volatility Typical Use Endurance

Flash 16/32 KB Non-volatile Program code storage 10,000 cycles

SRAM 1/2 KB Volatile Variables, stack, runtime data N/A

EEPROM 512/1024 Bytes Non-volatile Persistent data (settings) 100,000 cycles

In summary:
ATmega16/32 microcontrollers offer robust memory options for program code (Flash), runtime
data (SRAM), and persistent storage (EEPROM). Programming is accomplished using ISP (SPI) or
JTAG, supporting both firmware updates and in-system debugging. These features enable a wide
range of applications, from basic GPIO control to advanced sensor interfacing and PWM-based
motor control