Combinational Logic Circuit - Book

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Static CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Bubble Pushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Compound Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Input Ordering Delay Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Asymmetric Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Skewed Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Multiple Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 P/N Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Ratioed Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Pseudo-nMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Ganged CMOS (Symmetric2 NOR) . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Cascode Voltage Switch Logic (CVSL) . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1
1 Introduction
This section introduces the motivation for exploring alternative logic families beyond static
CMOS.

1. Why Do We Need More Than Static CMOS?

Static CMOS is widely used because it is fast, robust, and easy to design. However, in appli-
cations where:

• higher speed,

• smaller area,

• lower power, or

• higher logic density

are required, static CMOS may not be sufficient. This drives the use of alternative circuit
families.

2. What Are Circuit Families?

Circuit families are alternative logic styles that differ from static CMOS. These include:

• Ratioed Logic

• Dynamic Logic

• Pass-Transistor Logic

• Current Mode Logic (CML)

These styles are often used when static CMOS does not meet performance goals.

3. What Determines Gate Delay?

Gate delay is approximated by:
C
t≈ ∆V
I
Where:

• C is the load capacitance,

• I is the drive current, and

• ∆V is the voltage swing.

To reduce delay:

• Decrease C,

• Increase I,

• Reduce ∆V .

2
4. Limitations of Static CMOS
• Requires both nMOS and pMOS for each input ⇒ higher capacitance.

• Full rail-to-rail voltage swing (0 to VDD ) increases delay and power.

• pMOS transistors are slower, increasing logical effort.

• Pulling output high is slower due to weak pMOS drive.

5. Alternatives to Static CMOS

To overcome these limitations, other logic families are introduced that:

• Use only nMOS devices (e.g., pseudo-NMOS),

• Reduce output swing,

• Employ charge-sharing techniques (dynamic logic),

• Use SOI to reduce parasitics,

• Operate in the subthreshold regime for ultra-low power.

6. Caution with Alternative Families

Each alternative comes with challenges:

• Leakage,

• Charge sharing,

• Threshold voltage drops,

• Increased sensitivity to process variation.

Designers must understand the failure mechanisms and verify correctness under all conditions.

7. What’s Covered in This Chapter

This chapter introduces:

• Section 9.2: Common alternative families (ratioed, dynamic, pass-transistor),

• Section 9.3: Failure mechanisms and pathologies,

• Section 9.4: Rare and exploratory circuit styles,

• Section 9.5: SOI considerations,

• Section 9.6: Subthreshold logic and ultra-low-power design.

Summary
Static CMOS is preferred for general-purpose logic, but when constraints on speed, area, or
power exist, designers must turn to alternative circuit families that offer trade-offs in complexity
and robustness.

3
2 Circuit Families
Static CMOS circuits, built using complementary nMOS pulldown and pMOS pullup networks,
are the dominant style for logic gates in integrated circuits. This is due to their many advan-
tages:

• Good noise margins,

• Low power consumption,

• High speed,

• Robustness against process variations,

• Ease of design and simulation,

• Wide support in CAD tools,

• Availability in standard cell libraries.

When small noise glitches occur, static CMOS circuits may temporarily produce incorrect
outputs, but the final output will eventually settle to the correct value. As a result, most
modern design teams use static CMOS exclusively for implementing combinational logic.

Examples of Circuit Families

1. Dynamic Logic: The most important alternative to static CMOS. It achieves higher
performance but introduces complexities such as precharge/evaluate phases and sensitiv-
ity to noise and leakage.

2. Ratioed Logic: Simpler and provides a useful conceptual transition between static and
dynamic styles. It is discussed first in this chapter.

3. Pass-Transistor Logic: Gained popularity in the 1990s for general-purpose logic. Though
less common now, it is still used in certain specialized, high-performance applications.

3 Static CMOS
Designers familiar with AND/OR logic must adapt to using NAND and NOR when imple-
menting logic in static CMOS. This is because CMOS gates are inherently inverting, and
NAND/NOR structures are more efficient in CMOS technology.

Compound gates are useful for creating complex logic with minimal logical effort. When
a particular input is critical (e.g., timing-sensitive), the gate can be optimized to favor that
input. Similarly, gates can be optimized for rising or falling edge delays as needed.

To reduce power, area, and delay, smaller pMOS transistors are often used. Furthermore,
technologies that offer multiple threshold voltages enable designers to create different variants
of a gate to optimize the trade-off between speed, leakage, and power.

4
3.1 Bubble Pushing
Because CMOS stages are inverting, AND and OR gates are typically built using NANDs and
NORs. This is enabled by DeMorgan’s Law:

A · B = A + B, A+B =A·B
These transformations allow us to implement logic using only NAND/NOR gates with
inverted inputs and outputs. The act of rearranging the inversion bubbles visually to simplify
logic design is referred to as bubble pushing. It is a common whiteboard technique during
CMOS schematic optimization.

Example 9.1 – Bubble Pushing Logic Simplification

Problem: Design a logic circuit to compute:

F = AB + CD

using only NAND and NOR gates.

Solution Outline:

• Figure 9.2(a): Original implementation using two AND gates and one OR gate.

• Figure 9.2(b): Convert ANDs to NAND + inverter, and OR to NOR + inverter, re-
sulting in several gates with many bubbles.

• Figure 9.2(c): Apply bubble pushing to reduce the number of inverters and reorganize
the gates.

• Figure 9.2(d): Final optimized version using only three NAND gates to implement
the same function efficiently.

Key Insight: By using DeMorgan’s Law and bubble pushing, we can significantly reduce
the complexity of a CMOS implementation, optimizing for fewer gates, less power, and lower
propagation delay.

Figure 1: Example 9

5
3.2 Compound Gates
As described in Section 1.4.5, static CMOS can efficiently implement compound gates that
compute various inverting combinations of AND/OR functions in a single CMOS stage.
For example, the function:
F = AB + CD
can be computed using an AND-OR-Invert-22 (AOI22) gate followed by an inverter:

F = AB + CD → AOI22 → Inverter

Compound gates are more compact and reduce the number of logic stages, thereby improving
delay and area efficiency.

Logical Effort Logical effort g is defined as the ratio of the input capacitance of a gate to
the input capacitance of a reference inverter providing the same drive strength:
Input Capacitance of Gate
g=
Input Capacitance of Inverter
Figure 9.4 shows logical efforts for several compound AOI gates:

• Inverter: g = 3
3
=1

• AOI21:
6
– Inputs A, B: g = 3
=2
5
– Input C: g = 3
≈ 1.67

• AOI22: All inputs have g = 6

3
=2

• Complex AOI: Inputs vary depending on transistor configuration (e.g., stack depth and
width)

Parasitic Delay Parasitic delay p is an estimate of internal delay caused by the diffusion
capacitance at the output node. It is calculated by summing the sizes of all transistors connected
to the output: X
p= (Output-connected transistor widths)
Example parasitic delays from Figure 9.4:

• Inverter: p = 3
3
=1

• AOI21: p = 7
3
≈ 2.33

• AOI22: p = 12
3
=4

• Complex AOI: p = 16
3
≈ 5.33

6
Conclusion Compound gates such as AOI22, AOI21, and more complex versions enable
efficient static CMOS implementations by reducing logic depth and improving performance.
Logical effort and parasitic delay must be considered when evaluating the delay of such gates
using the delay model:
t=g·h+p
where h is the electrical effort.

Figure 2: Logical efforts and parasitic delays of AOI gates

3.3 Input Ordering Delay Effect

The logical effort and parasitic delay of different gate inputs are not always equal. For some
logic gates, especially compound ones like AOI21, the structure is inherently asymmetric,
meaning that different inputs may have different contributions to delay.
Even nominally symmetric gates such as NANDs and NORs exhibit slight differences in
delay and logical effort for different input positions due to the transistor stacking order and
internal capacitances.

Example: 2-Input NAND Gate Consider the falling output transition in a 2-input NAND
gate (see Figure 9.6). Suppose one input is stable at logic high, and the other rises from 0 to
1. Two scenarios are analyzed:

• Case 1: Input B rises, Input A held high

Node x is initially at VDD (charged through the nMOS controlled by A). When B rises,
the discharge path is activated through both nMOS transistors. The Elmore delay is:
R
t= (2C) + R(6C) = 7RC = 2.33τ
2

• Case 2: Input A rises, Input B held high

Node x is already at 0 V because B has discharged it. Now A turns ON, and no charge
must be removed. The delay becomes:

t = R(6C) = 6RC = 2τ

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Input Position Definitions
• Outer input: Closer to VDD (e.g., Input B)
• Inner input: Closer to the output (e.g., Input A)
In general, the parasitic delay is lower when the inner input switches last, because interme-
diate nodes have already been discharged. If signal arrival times are known, connecting faster
signals to the inner inputs minimizes delay.

Design Insight This effect is important in timing-critical paths. For example:

• Logical effort can vary slightly across inputs.
• Inner input tends to have a lower parasitic delay.
• Input ordering can be exploited for faster transitions.
Though often negligible in typical designs, the designer may benefit from considering this
when optimizing paths with high fan-out or tight setup constraints.

3.4 Asymmetric Gates

In digital circuits, some inputs may be more critical than others in terms of timing. When this
is the case, even symmetric gates like NANDs or NORs can be intentionally made asymmetric
to favor the more critical (late-arriving) input. This is achieved by resizing transistors such
that the critical input path experiences lower delay.

Design Technique
• In a series network, the early input is placed at the outermost position and its transistor
is made wider to reduce resistance when the late input arrives.
• In a parallel network, the early input is connected to a narrower transistor to reduce
parasitic capacitance on the output node.

Example: Resettable Buffer (Figure 9.7) Consider a buffer from A to Y , with an optional
reset control. Since reset occurs infrequently, the design should optimize the path from A to Y
and tolerate slower reset behavior.
• Figure 9.7(b) shows an asymmetric NAND gate implementation.
• Input A is assigned a wider nMOS transistor (size 4/3).
• The reset input uses a unit-size transistor (1).

Resistance and Logical Effort The total pull-down resistance of the series nMOS stack is:
R 3 7
Rtotal = +R= R+R= R
4/3 4 4
Capacitance on input A is approximately 10/3, so its logical effort is:
10
gA =
3
This is significantly better than the typical NAND gate logical effort of 4/3. As a result,
the gate offers lower logical effort for input A at the cost of increased effort on the reset input.

8
Reset Path Consideration

• The reset path is slower due to smaller transistor sizing.

• However, this is acceptable because reset occurs infrequently.

• Additionally, the pMOS for reset is also minimized to reduce parasitic diffusion capaci-
tance.

Velocity Saturation and Equivalent Resistance CMOS transistors typically operate in

the velocity saturation region. In this regime, series stacks of transistors behave as a single
equivalent transistor. The effective length N is computed by summing the reciprocals of the
transistor widths, and total drive current is calculated using:
V
Ieq =
R(N )

As a result, careful transistor sizing in asymmetric gates reduces delay on the critical input
path while tolerating degraded performance on less critical ones.

Conclusion Asymmetric gates are a powerful technique to:

• Prioritize critical signal paths,

• Reduce logical effort and delay for selected inputs,

• Optimize performance without increasing gate count.

3.5 Skewed Gates

In certain digital circuits, one type of output transition (either rising or falling) is more crit-
ical than the other. Skewed gates are designed to favor the critical transition by resizing
transistors to reduce the logical effort for that transition.

Types of Skewed Gates

• HI-skew gates: Favor the rising output transition (faster pull-up). Achieved by increas-
ing pMOS size and reducing nMOS size.

• LO-skew gates: Favor the falling output transition (faster pull-down). Achieved by
increasing nMOS size and reducing pMOS size.

Definition of Logical Efforts Let gu and gd denote the logical efforts for the rising and
falling transitions, respectively. These are defined as the ratio of the input capacitance of the
skewed gate to that of an unskewed inverter with equal drive strength for the corresponding
transition.

9
Example: HI-skew Inverter (Figure 9.9) The inverter is skewed to favor the rising edge:

• pMOS size: 2 (strong)

• nMOS size: 0.5 (weak)

1. Rising Transition:

Input Cap. (HI-skew) 2.5 5

gu = = =
Input Cap. (Unskewed, equal rise resistance) 3 6

2. Falling Transition: Compared against a smaller unskewed inverter with the same fall
resistance (pMOS = 1, nMOS = 1.5):
2.5 5
gd = =
1.5 3

Trade-offs and Design Considerations

• Skewing improves performance for one transition at the expense of the other.

• A typical skew factor (ratio of strong to weak drive) is 2.

• Skewed gates are useful in timing-critical paths where only one edge matters.

• Skewed gates are sometimes annotated in schematics with a small H (HI-skew) or L (LO-
skew) on the symbol.

Conclusion Skewed gates reduce the logical effort for timing-critical transitions by adjusting
transistor sizes. This allows designers to optimize delay where it matters, without increasing
the number of gates or logic depth.

Figure 3: catalog of skewed gates

10
3.6 Multiple Threshold Voltages
Modern CMOS processes often support two or more threshold voltage (VT ) options for transis-
tors. These options allow designers to balance performance and power consumption:

• Low-VT transistors:

– Provide higher ON current (faster switching).

– Suffer from significantly higher OFF-state leakage current.

• High-VT transistors:

– Switch more slowly due to lower ON current.

– Exhibit lower leakage when turned OFF.

Design Strategy Cell libraries typically provide both high-VT and low-VT versions of stan-
dard gates. To optimize performance:

• Use low-VT gates only on critical paths to reduce delay.

• Retain high-VT gates on non-critical paths to minimize leakage power.

• In skewed gates, apply low-VT only to the critical transistors within the gate to limit
leakage while enhancing speed.

Conclusion The use of multiple threshold voltages enables fine-tuned trade-offs between speed
and leakage power. By selectively applying low-VT transistors only where high performance is
needed, designers can achieve timing closure while minimizing power consumption.

3.7 P/N Ratios

The P/N ratio refers to the ratio of pMOS width to nMOS width in a CMOS logic gate. This
ratio significantly impacts the gate’s:

• Rise and fall delays,

• Input capacitance,

• Area and power consumption,

• Noise margins.

Effect of High P/N Ratio In unskewed gates, pMOS transistors are typically made wider
to match the pull-up strength with the nMOS pull-down. This ensures balanced rise and fall
delays but results in:

• Larger pMOS transistors,

• Increased input capacitance,

• Higher area and power usage.

11
 √
Improving Average Delay By downsizing the pMOS (e.g., from 2 to 2 ≈ 1.4), the
inverter achieves the lowest theoretical average delay. This reduces both area and power con-
sumption while:

• Only slightly degrading delay (typically by 3%),

• Potentially causing unequal rise/fall delays,

• Lowering noise margin and switching threshold.

Example: LO-skew NOR2 Gate In a LO-skew NOR2 gate:

• pMOS transistors are made smaller,

• Rising transitions are slower,

• Input capacitance is reduced,

• Average logical effort improves compared to unskewed design.

Design Guidelines

• In standard cell libraries, the achievable P/N ratio is influenced by cell height constraints.

• Typical inverter designs use P/N ratios in the range:

1.5 ≤ P/N ratio ≤ 2

• The ratio should be selected based on area, power, and reliability, not just delay
symmetry.

• For NOR gates, aggressively reducing pMOS size can significantly enhance both delay
and area efficiency.

Conclusion The P/N ratio is a key design knob in CMOS gate optimization. By carefully
selecting the ratio, designers can achieve better average delay, lower power, and reduced area,
while accepting controlled asymmetry in edge speeds.

12
Summary of Section 9.2.1 – Static CMOS Circuit Optimization Tech-
niques
• Bubble Pushing (1): CMOS gates are inverting; therefore, logic is implemented us-
ing NAND/NOR plus inverters. DeMorgan’s laws and bubble pushing simplify logic by
eliminating redundant inversions, leading to more efficient designs.

• Compound Gates (2): Gates like AOI21 and AOI22 combine multiple logic functions
into a single stage. This reduces delay and area. Input logical effort and parasitic delay
vary based on transistor stacking and path complexity.

• Input Ordering Delay Effect (3): In stacked configurations (e.g., NAND), the order
in which inputs switch affects delay. Inner inputs (closer to output) generally result in
faster transitions. Designers may assign late signals to inner inputs for optimization.

• Asymmetric Gates (4): Gates are intentionally unbalanced to prioritize critical signals.
Wider transistors are placed on critical paths to reduce delay, while less critical paths are
downsized to reduce capacitance and area.

• Skewed Gates (5): Gates are skewed to favor one type of transition:

– HI-skew: Faster rising edge (larger pMOS).

– LO-skew: Faster falling edge (larger nMOS).

Logical effort is reduced for the preferred edge and increased for the other.

• P/N Ratios (6): The ratio of pMOS to nMOS

√ widths affects delay symmetry, area, and
power. Reducing pMOS size (from 2 to 2 ≈ 1.4) improves average delay and reduces
capacitance. Practical designs use P/N ratios of 1.5–2.

• Multiple Threshold Voltages (7): CMOS technologies may offer both high-VT and
low-VT transistors:

– Low-VT : Faster but leakier.

– High-VT : Slower but energy-efficient.

Low-VT gates are selectively applied to timing-critical paths or transistors within skewed
gates to enhance performance without excessive leakage.

13
4 Ratioed Circuits
Ratioed logic circuits rely on a proper size ratio between the pulldown network and a static
load device to ensure correct functionality. These circuits were common before CMOS became
the dominant logic style, especially in the 1970s and early 1980s.

Basic Operation A ratioed gate consists of:

• An nMOS pulldown network to produce logic 0,

• A static pull-up device (load) to restore logic 1 when the pulldown is OFF.

When the pulldown network is OFF, the load pulls the output high. When it is ON, the
pull-down path must be strong enough to overpower the static load and bring the output low.

Design Constraint The circuit’s correct operation depends on the ratio of the strengths of
the load and pull-down networks. A stronger pull-down improves speed and reduces VOL , but:

• Increases static power consumption,

• Degrades noise margins,

• Requires careful sizing.

Static Load Implementations (Figure 9.12)

• (a) Resistor Load: Simple but consumes large silicon area.

• (b) nMOS Load with Gate Tied to VGG : More compact, but subject to body effect.
If VGG = VDD , the load only pulls up to VDD − VT .

• (c) Depletion-mode nMOS: Gate tied to source, always weakly ON (VGS = 0). These
devices are created via ion implantation to give a negative threshold voltage.

Summary Ratioed logic is simpler and area-efficient, but suffers from:

• Static power dissipation,

• Limited voltage swing,

• Dependence on transistor sizing.

While largely obsolete in modern CMOS design due to power inefficiency, ratioed circuits
remain useful in special applications where simplicity or specific trade-offs are acceptable.

4.1 Pseudo-nMOS
Pseudo-nMOS logic is a simplified form of ratioed logic where the pull-up network consists of
a single pMOS transistor with its gate tied to ground, making it always ON. The pull-down
network is a standard nMOS logic configuration.

Circuit Behavior When the nMOS network is OFF, the pMOS pulls the output HIGH.
When the nMOS network is ON, it must overpower the always-on pMOS to pull the output
LOW. The operation relies on the sizing ratio between pull-up and pull-down devices.

14
Transfer Characteristics (Figure 9.13) The output voltage Vout for a given input Vin is
determined by solving:
Idn (Vin , Vout ) = Idp (Vin , Vout )
for various values of Vin . The resulting DC transfer curve shows how the shape of the transition
depends on the size of the pMOS transistor (denoted P ).

• Larger P provides faster rising outputs.

• However, this increases VOL , raises static current, and degrades noise margins.

• Figures 9.13(b–d) illustrate how increasing P affects current curves and switching behav-
ior.

Sizing Guidelines To achieve a balance between performance and power:

• pMOS size should be about 1
4
the strength (or 1
2
the width) of the nMOS network.

• A practical ratio is in the range:

1 1
pMOS width = to × nMOS network width
3 6

Conclusion Pseudo-nMOS gates are efficient in layout and logic density, but require careful
transistor sizing due to static power consumption and degraded noise margin. They are still
useful in low-complexity or specialized applications.

Logical Effort and Parasitic Delay To estimate logical effort, compare a pseudo-nMOS
gate to a unit CMOS inverter driving equal current. Assume:
• pMOS contributes 1
3
of full drive current,

• nMOS contributes full I,

• Input capacitance = 4/3.

For the falling edge:
4/3 4 4/3
gd = = , and for rising edge: gu = =4
1 3 1/3
Parasitic delay is estimated using diffusion capacitance. For instance, in a pseudo-nMOS
NOR:
• Pull-down path has parasitic delay ≈ 10/9,

• Pull-up (via pMOS) has parasitic delay ≈ 10/3.

Replica Biasing to Improve Robustness To prevent failure in process corners (e.g., slow
nMOS, fast pMOS), a replica bias circuit can set Vbias for the pMOS gate.
This circuit:
• Uses transistors N1 , N2 , P1 , and P2 to establish a current ratio,

• Ensures pMOS gate pulls up with 31 I and nMOS pulls down with I,

• Is independent of mobility mismatch.

15
Power Saving Consideration To reduce power during idle periods or testing:

• The pMOS can be disconnected from VDD using a gating transistor,

• This is useful in IDDQ testing and power-gated modes.

Conclusion Pseudo-nMOS logic is a compact ratioed design style well-suited for wide NORs
and ROM/PLA applications, but requires careful sizing or biasing to manage noise margin,
static power, and process variation.

4.2 Ganged CMOS (Symmetric2 NOR)

Ganged CMOS, also known as symmetric2 NOR or Ganged CMOS, refers to a circuit
where pairs of CMOS inverters are ganged (combined) to implement a logic function—typically
a NOR gate.

• Structure: Two CMOS inverters are ganged together such that:

– Input A controls transistors P1 (pMOS) and N1 (nMOS).

– Input B controls transistors P2 (pMOS) and N2 (nMOS).

• Operation:

– When both inputs are 0: Both pMOS transistors (P1, P2) are ON, and both nMOS
transistors are OFF. The output is pulled high quickly.
– When one input is 0 and the other is 1: One pMOS and one nMOS are ON, creating
a pseudo-nMOS behavior. The output is pulled down.
– When both inputs are 1: Both pMOS transistors are OFF, and both nMOS transis-
tors are ON, pulling the output fully low.

• Truth Table:

A B N1 P1 N2 P2 Y
0 0 OFF ON OFF ON 1
0 1 OFF ON ON OFF ∼0
1 0 ON OFF OFF ON ∼0
1 1 ON OFF ON OFF 0

Table 1: Operation of symmetric NOR gate

• Transistor Sizing:
1
– pMOS transistors are sized to be about 4
the strength of nMOS transistors.
– The pull-down strength matches that of a unit inverter.

• Logical Effort:
2 5
gu = 1, gd = , gavg =
3 6
• Advantages:

– Faster pull-up when either input is 0 (due to dual pMOS).

16
 – No static power dissipation when both inputs are 1 (both pMOS OFF).
– More energy-efficient and faster than pseudo-nMOS NOR gates.

• Scalability:

– Symmetric NOR design can be extended to 3-input gates.

– Works well for NOR logic; however, less attractive for NAND due to increased logical
effort.

Note: Do not confuse this use of “symmetric” with the gate sizing concepts from Sec-
tion 9.2.1.4. “Symmetric2 ” refers to the architectural structure of the ganged inverters.

17
5 Cascode Voltage Switch Logic (CVSL)
Cascode Voltage Switch Logic (CVSL) aims to achieve the performance benefits of ratioed
circuits without incurring static power consumption. CVSL circuits use:
• Both true and complementary input signals,
• A pair of nMOS pulldown networks for logic computation,
• pMOS pullup transistors for complementary outputs.

Working Principle:
• One nMOS pulldown network (f ) receives regular inputs and evaluates the logic function.
• The other network (f¯) receives inverted inputs to generate the complement.
• For any input combination:
– One pulldown network turns ON, pulling its output LOW.
– This LOW output activates its associated pMOS transistor, pulling the opposite
output HIGH.
– The other pMOS turns OFF, eliminating static power draw.

Design Insights:
• Pulldown networks are arranged in a complementary configuration (e.g., parallel in
one branch, series in the other).
• Input sharing (e.g., sharing A and Ā transistors) reduces transistor count and area.

Advantages:
• High speed: All logic is nMOS-based ⇒ lower input capacitance and faster transitions.
• No static power: Only one pMOS is ON at a time; the other is OFF.
• Full swing outputs: Unlike pseudo-nMOS, pMOS feedback ensures valid logic levels.

Drawbacks:
• Requires both true and complemented inputs.
• Slow pull-up due to pMOS sizing (large pMOS needed for good pull-up speed).
• High contention current during transitions.
• Poor scalability: Not efficient for general NAND/NOR or XOR gates.
• Consumes more power than static CMOS for certain functions.

Applications:
• Well-suited for dual-rail domino logic and complementary pass-transistor logic.
• Less favorable for XORs and wide NAND/NOR functions due to speed/power trade-offs.

18
5.1 Dynamic Circuits
Dynamic circuits improve upon ratioed circuits by replacing the static pMOS pullup with a
clocked transistor, addressing several shortcomings of ratioed designs such as:

• slow rising transitions,

• contention on falling transitions,

• static power dissipation,

• and nonzero VOL .

Operating Principle
Dynamic circuits operate in two phases, as shown in Figure 9.22:

• Precharge Phase (ϕ = 0): The clocked pMOS transistor is ON and charges the output
node to HIGH (Y = 1).

• Evaluation Phase (ϕ = 1): The pMOS turns OFF, and depending on the inputs, the
output is either discharged through the nMOS network or retained.

Footed vs. Unfooted

• Unfooted gates: In these, contention may occur during precharge if an input is HIGH,
causing both pullup and pulldown paths to conduct.

• Footed gates: Add a clocked transistor (called a foot) at the bottom of the nMOS stack
to prevent contention during precharge (see Figure 9.23).

Design Characteristics
• Lower input capacitance and no switching contention make dynamic logic very fast.

• However, they suffer from:

– sensitivity to noise during evaluation,

– dynamic power consumption,
– and clocking complexity.

• Footed gates have higher logical effort than unfooted ones due to increased resistance and
slower precharge, but both are more efficient than static logic.

• Velocity saturation and reduced contention further improve the performance beyond ini-
tial estimates.

Applications
• Suitable for wide-input gates such as NORs or multiplexers.

• Logic effort is independent of the number of inputs, making dynamic gates ideal for
performance-critical circuits.

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Monotonicity Requirement in Dynamic Circuits
A critical challenge in dynamic logic is the monotonicity requirement. During the evaluation
phase, the inputs to a dynamic gate must transition in a monotonically rising manner. This
means inputs can:

• Stay LOW,

• Go from LOW to HIGH,

• Stay HIGH,

but must not transition from HIGH to LOW.

Violation Scenario: As illustrated in Figure 9.26:

• During precharge (ϕ = 0), the pMOS precharge transistor pulls the output HIGH.

• During evaluation (ϕ = 1), if the input A is HIGH, it turns ON the nMOS network,
discharging the output to LOW.

• If A then falls from HIGH to LOW, the nMOS path is cut off, but since the pMOS is also
OFF, the output cannot rise again—it floats and remains LOW.

Implication: This incorrect output arises due to the violation of monotonicity. Such a dy-
namic gate cannot compute the correct logic function if any input falls during evaluation.

Domino Logic Issue: When dynamic gates are cascaded, the output of one gate may fall
during evaluation, violating the input requirement of the next stage. This is known as the
domino problem, discussed further in the next section.

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