Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

UNIT
Introduction to Microprocessor

SYLLABUS
Introduction to Microprocessor: Microprocessor architecture and its operations, Memory, Input
& output devices, the 8085 MPU- architecture, Pins and signals, Timing Diagrams, Logic devices for
interfacing, Memory interfacing, Interfacing output displays, Interfacing input devices, Memory
mapped I/O.

1.1 Introduction to Microprocessor:

The 8085 Microprocessor is an 8-bit microprocessor with an 80-instruction set, capable of
interfacing with various peripherals and memory. It was introduced by Intel in 1976 and played
a significant role in the early development of personal computers and embedded systems. It
succeeded the 8080 microprocessor and was one of the earliest microprocessors widely used in
various applications. The 8085 typically operates at a clock speed of 3 MHz, although some
variations and implementations may have different clock speeds. It can access up to 64KB of
memory, making it suitable for a variety of applications. Memory interfacing is a crucial aspect of
working with the 8085.

The 8085 microprocessor is typically programmed using assembly language, which provides low-
level control over its operations. Programmers write code in assembly language and then
assemble it into machine code for execution. It has historical significance in the world of
computing and served as a stepping stone for the development of more advanced
microprocessors and microcontrollers.

1.1.1 Microcomputer:

Figure 1.1: Microcomputer

Microcomputer system consists of four components:
1. Microprocessor (The microprocessor is the heart of microcomputer.)
2. Memory
3. Input and
4. Output
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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

The microcomputer is a programmable digital device, designed with registers, flip-flops and
timing elements. It is designed for general-purpose computing tasks and can be used for various
applications.

1.1.2. Microprocessor:
A microprocessor is a specific component within a microcomputer, and it serves as the central
processing unit (CPU) of the system.

Fig. 1.2: Block diagram of Microprocessor.

• The microprocessor mainly contains (CPU)

i. The Arithmetic & Logic unit (ALU)
ii. The control unit and
iii. General-purpose registers.
It does not have built-in RAM, ROM, I/O ports etc. on the chip.
• The microprocessors are commonly referred to as general-purpose microprocessor.
Examples:
Intel: 8086, 80286, 80386, 80486, Pentium etc.
Motorola: 68000, 68010, 68020, 68030 etc.

1.1.3. Operations performed by Microprocessor:

The Operations performed by Microprocessor are
1. Microprocessor-initiated operations
2. Internal operations
3. Peripheral operations or externally initiated operations

1. Microprocessor initiated operations:

The Microprocessor unit (MPU) performs primarily four operations:
i. Memory Read: Read data or Instructions from memory.
ii. Memory write: Writes data or instructions into memory.
iii. I/O Read: Accept data from input devices.
iv. I/O write: Sends data to output devices.

2. Internal operations or 8085 Microprocessor internal data operation:

The internal data operations in 8085 microprocessor are
• Store 8-bit data.
• Perform arithmetic and logical operations.
• Test for conditions.
• Sequence the execution of instructions.
• Store data temporarily during the execution in the defined R/W memory locations called
the stack.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

3. Peripherals or Externally Initiated operations:

The external devices or signals can initiate the following operations using the 8085
Microprocessor Pins: Reset, Interrupt, Ready and Hold.

Reset IN: When the reset pin is activated by an external key, all the internal operations are
suspended and the program counter is cleared i.e. PC = 0000 H. Now, the program execution
will begin from the address 0000 H.

Interrupt: The microprocessor can be interrupted from the execution of instructions and
asked to execute some other instructions called an Interrupt Service Routine (ISR). The
microprocessor resumes it operation after completing the Interrupt service routine.

Ready: It is used by the microprocessor to sense whether a peripheral is ready to transfer data
or not.
If Ready = 1, the peripheral is ready.
If Ready = 0, the microprocessor waits till it goes high.

Hold: When the HOLD pin is activated by an external signal, the microprocessor relinquishes
control of buses and allows the external peripheral to use them. For example: The HOLD signal
is used in Direct Memory Access (DMA) data transfer.

1.1.4. 8085 Microprocessor Bus organization:

Figure 1.3: The 8085-bus structure

The 8085 microprocessor performs operation using three sets of communication lines called
buses:

1 The Address : The 8085 microprocessor uses a 16-bit address bus to access
bus memory locations. This provides a maximum addressable memory
space of 64 KB (kilobytes). This address bus is used for memory
addressing, allowing the microprocessor to fetch. The 8085 MPU
with its 16-bit address lines is capable of addressing 216 = 65.536
memory location (64 Kb) instructions and data from memory and
to write data to memory.

2 The data bus : The 8085 microprocessor has an 8-bit bi-directional data bus. Data
bus can transfer data in 8-bit chunks or one byte between the
microprocessor and memory, input/output (I/O) devices, and
other components.
3 The control bus : • The control bus is comprised of various single lines that carry
synchronization signals. The control bus is not a group of lines
like Address bus or data bus, but individual lines that provide a
pulse to indicate an MPU operation.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

• The control bus in the Intel 8085 microprocessor is a set of

signals that are used to control various operations within the
microprocessor. These control signals coordinate actions such
as memory read and write operations, input/output (I/O)
operations, and the sequencing of instructions.

Figure 1.4: Memory Read operation

• To communicate with a memory, for example, to read an instruction from a memory

location, the MPU unit places the 16-bit address on the address bus s shown in figure 1.
The address on the bus is decoded by an external logic circuit.
• The MPU unit sends a pulse called Memory Read as the control signal. The pulse activates
the memory chip, and the contents of the memory location i.e. 8-bit data are placed on the
data bus and brought inside the microprocessor.

1.2. Features of 8085 Microprocessor:

The features of 8085 Microprocessor are:
• 8-bit general purpose µp
• Capable of addressing 64 k of memory
• It has 40 pins
• Requires +5 v power supply
• Can operate with 3 MHz clock
• The clock cycle is 200 ns
• It has 80 basic instructions

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1.2.1. 8085 Microprocessor architecture:

Figure 1.5: 8085 Microprocessor internal architecture

Figure 1.5 shows the 8085 Microprocessor internal architecture.

The various units of a microprocessor are listed below

• Arithmetic and logic Unit
• Accumulator
• General purpose register
• Program counter
• Stack pointer
• Temporary Register
• Status Register (Flags)
• Timing and Control Unit
• Instruction Register and Decoder
• Register array
• Address bus and Data bus

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Arithmetic & Logic Unit (ALU):

The ALU unit performs the arithmetic and logical operations like addition, subtraction, Logical
AND, Logical OR, Complement, Increment, Decrement clear etc.

Accumulator
• Accumulator is an 8-bit register which can hold 8-bit data.
• Accumulator is a special register used for temporary data storage and manipulation
during arithmetic and logical operations.
• It also stores the result of the operation carried out by the Arithmetic and Logic unit.

General purpose register:

Figure 1.6: shows the General-Purpose register

General Purpose Registers

• Apart from accumulator 8085 consists of six special registers called General Purpose
Registers.
• These general-purpose registers are used to hold data like any other registers.
• The general-purpose registers in 8085 processors are B, C, D, E, H & L and each register
can hold 8-bit data.
• These registers can also be used to work in pairs to hold 16-bit data such as B-C, D-E and
H-L to store 16-bit data.
• The H-L pair works as a memory pointer.
• A memory pointer holds the address of a particular memory location and can store 16-bit
address as they work in pair.

Program Counter (PC):

• The Program Counter is a 16-bit register which points to the address of the next
instruction to be executed.
• It automatically increments after fetching each instruction byte.
• When the 8085 microprocessor is reset, the default value of PC is 0000H, indicating the
beginning of the program memory.

STACK:
The stack is a region of memory used for storing data temporarily during program execution.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Stack Pointer (SP):

• The Stack pointer is also a 16-bit register which is used as a memory pointer.
• The stack is a section of RAM used by the CPU to store information temporarily. This
information could be data or an address.
• The register used to access the stack is called the stack pointer (SP) register.
• The last memory location of the occupied portion of the stack is called stack top.
• The storing of a CPU register in the stack is called a PUSH, and loading the contents of the
stack back into a CPU register is called a POP.

Temporary register:
Temporary register is an 8-bit register. This register acts as a temporary memory during the
arithmetic and logical operations. This temporary register can only be accessed by the
microprocessor and it is completely inaccessible to programmers.

Status Register (Flags) or Program Status Word (PSW)

Flags are a set of five flip-flops and are associated with arithmetic and logic operations. These
flags can hold a 1-bit value, either a logic 1 or 0, based on certain conditions that arise during
arithmetic and logic operations.

D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘
Figure 1.7: 8085 microprocessor Flags

The five bits indicate the five-status flag and three bits are undefined. The combinations of these
8-bits are called Program Status Word (PSW). The 5 flags bits are Carry (CY), Zero (Z), Sign (S),
Parity (P) and Auxiliary Carry (AC)

CARRY (CY):
• After performing arithmetic & logic operation if there is a carryout from the MSB (D 7 i.e.
7th bit) then CY = 1, otherwise CY = 0.
• If there is a borrow from subtraction or comparison, the carry flag CY=1; otherwise CY=0.

PARITY FLAG (P):

After performing arithmetic & logic operation if the result in the accumulator has an even
number of 1’s then P=1; otherwise P=0. (i.e. if the result in the accumulator has an odd number
of 1’s then P= 0.)

AUXILIARY CARRY FLAG (AC):

After performing arithmetic & logic operation if a carry is generated from D3 to D4 bit then AC
= 1, otherwise AC = 0.
(This flag is used only internally for BCD operations and is not available for the
programmer).

ZERO FLAG:
After performing arithmetic & logic operation if the result in the accumulator is zero, then Z=1
and if the result in the accumulator is non-zero then Z=0.

SIGN FLAG:
After performing arithmetic & logic operation if the most significant bit (MSB) of the result in
accumulator is 1 i.e. MSB=1, then S=1; otherwise S=0. (if MSB=1, then S=1 & if MSB=0, then S=0).

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

TIMING AND CONTROL UNIT

The Timing and Control Unit plays a crucial role in synchronizing all microprocessor operations
with the clock and generating essential control signals required for communication between the
microprocessor and peripherals. The 𝐑𝐃̅̅̅̅ and 𝐖𝐑
̅̅̅̅̅ signals serve as sync pulses that indicate the
availability of data on the data bus.

INSTRUCTION REGISTER AND DECODER

The instruction register and the decoder are part of the ALU. When an instruction is fetched from
memory, it is loaded in the instruction register. The decoder decodes the instruction and
establishes the sequence of events to follow. The instruction register is not programmable
and cannot be accessed through any instruction.

REGISTER ARRAY
Two additional registers, called temporary registers 𝐖 and 𝐙, are included in the register array
and they are used internally by 8085 microprocessor. These registers are not available to the
programmer. These registers are used to hold 8-bit data during the execution of some
instructions.

ADDRESS BUS AND DATA BUS:

ADDRESS BUS:
• The address bus is a set of physical lines that carry the memory address information. It
specifies the location in memory or a peripheral device where data needs to be read from
or written to.
• In 8085 microprocessor address bus is 16-bit A0 to A15.
• The lower address lines are multiplexed address and data lines i.e. AD0 to AD7 and
higher address line are A8 to A15.
• The address bus is unidirectional. The width of the address bus determines the range of
memory addresses that can be accessed, allowing access to 64 KB of memory locations
(i.e. 216 = 64 KB).

DATA BUS:
• The data bus is set of physical lines that carry the actual data being transferred between
the microprocessor and memory or peripheral devices.
• In 8085 microprocessor data bus is 8-bit bidirectional allowing it to transfer 8-bits of
data at a time.

NUMERICAL ON FLAGs

1. Determine the flag bits in the 8085 microprocessor after adding 80H and 60H.
SOLUTION:
CY D7 D6 D5 D4 D3 D2 D1 D0

80 0 1 0 0 0 0 0 0 0

+ 60 + 0 1 1 0 0 0 0 0

E0 1 1 1 0 0 0 0 0

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

Carry Flag (CY) : There's no carry, so CY = 0.

Parity Flag (P) : E0H has 3 set bits, which is odd, so P = 0.
Auxiliary Carry : There's no carry from D3 to D4 bit, so AC = 0.
Flag (AC) OR
Theirs is no carry from the low nibble (4 bits) to the high nibble, so
AC = 0.
Zero Flag (Z) : The result (E0H) is not zero, so Z = 0.
Sign Flag (S) : The leftmost bit (Most Significant Bit - MSB) is 1, it indicates a
negative number i.e. result is E0H. so S = 1.

So, after adding 80H and 60H, the flag values are:
D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘
1 0 0 0 0

2. Determine the flag bits in the 8085 microprocessor after adding CB H and E9 H.
SOLUTION:
CY D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1

CB 1 1 0 0 1 0 1 1

+ E9 + 1 1 1 0 1 0 0 1

1B4 1 1 0 1 1 0 1 0 0

Carry Flag (CY) : There's carry, so CY = 1.

Parity Flag (P) : B4 H has 4 set bits, which is even, so P = 1.
Auxiliary Carry : There's carry from D3 to D4 bit, so AC = 1.
Flag (AC) OR
Theirs is carry from the low nibble (4 bits) to the high nibble, so AC =
1.
Zero Flag (Z) : The result (B4 H) is not zero, so Z = 0.
Sign Flag (S) : The leftmost bit (Most Significant Bit - MSB) is 1, it indicates a
negative number i.e. result is E0H. so S = 1.

So, after adding CB H and E9 H, the flag values are:

D7 D6 D5 D4 D3 D2 D1 D0
𝐒 𝐙 𝐀𝐂 𝐏 𝐂𝐘
1 0 1 1 1

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

1.2.2. PIN DIAGRAM OF 8085 MICROPROCESSOR:

Figure 1.8 (a): Pin diagram of 8085 Figure 1.8 (b): Functional Pin diagram

The pins of 8085 microprocessor are as below:

Pin
Pin Name Description
No.
• Crystal (or either RC network or LC network) is connected
at these two pins to set the frequency of internal clock
generator.
1-2 X 1 & X2
• The frequency is internally divided by two. The 8085
microprocessor operates at a frequency of 3MHz, so a 6MHz
crystal is connected externally.
It indicates that the MPU is being reset. The signal can be used to
3 RESETOUT
reset other devices.
The 8085 has two pins for serial Communication: Serial Input Data
(SID) & Serial Output Data (SOD).
SOD (Serial Output Data):
4& Serial I/O Ports
SOD is the serial output data pin. It is used for transmitting data
5 SOD & SID
serially from the microprocessor to external devices or peripherals.
Data is sent bit by bit through this pin in a sequential manner.
SID (Serial Input Data):

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

SID is the serial input data pin. It is used for receiving serial data
from external devices or peripherals and transferring it to the
microprocessor. Data is received bit by bit through this pin.
In the 8085 microprocessor, interrupts are mechanisms used to
temporarily pause the normal program execution and handle
specific events or requests from external devices. The 8085
microprocessor has five interrupt signals that can be used to
interrupt program execution. These interrupt signals are:
TRAP or TRAP Interrupt:
• TRAP is a non-maskable interrupt (NMI) that is generated by
an external device, such as a power failure or a hardware
malfunction.
• When TRAP is triggered, the microprocessor jumps to a
specific memory location address 0024 to execute a
predefined routine.
• The TRAP interrupt has the highest priority and cannot be
disabled.

RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt that is
generated by a software instruction. RST 7.5 can be enabled
or disabled by the microprocessor.
• When RST 7.5 is triggered, the microprocessor jumps to a
specific memory location address 002C to execute a
predefined routine.
(INTERRUPTS) • It has the second highest priority.

TRAP RST 6.5:

RST 7.5 • The RST 6.5 interrupt is a maskable interrupt that is
6-11
RST 6.5 generated by a software instruction. RST 6.5 can be enabled
RST 5.5 or disabled by the microprocessor.
INTR • When RST 6.5 is triggered, the microprocessor jumps to a
̅̅̅̅̅̅̅
𝐈𝐍𝐓𝐀 specific memory location address 0034 to execute a
predefined routine.
• It has the third highest priority.

RST 5.5:
• The RST 5.5 interrupt is a maskable interrupt that is
generated by a software instruction. RST 5.5 can be enabled
or disabled by the microprocessor.
• When RST 5.5 is triggered, the microprocessor jumps to a
specific memory location address 003C to execute a
predefined routine.
• It has the fourth highest priority.

INTR (Interrupt Request):

• INTR is a maskable interrupt request generated by external
devices, such as a keyboard or a mouse.
• INTR is enabled or disabled by software.
• It has the lowest priority and can be disabled.
INTA (Interrupt Acknowledge):
• INTA is not an interrupt.
• It is an interrupt acknowledgement sent by the
microprocessor after INTR is received.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

• When the microprocessor acknowledges the interrupt, it

proceeds to execute the corresponding interrupt service
routine.

SUMMARY OF INTERRUPTS
Address
Maskable or Non-
Interrupt Priority order or
Maskable
Location
1 (Highest Non-maskable
TRAP 0024
priority) (NMI)
RST 7.5 2 Maskable 003C
RST 6.5 3 Maskable 0034
RST 5.5 4 Maskable 002C
5 (Lowest No
INTR Maskable
priority) specific

AD0 to AD7:
• AD0 to AD7 are multiplexed address and data lines that form
the lower byte of the 16-bit Address/Data bus. AD0 – AD7 are
8-bit bi-directional and serve as both A0 – A7 and D0 – D7
simultaneously.
12- • They are used to send both address and data between the
AD0-AD7
19 microprocessor and memory or peripheral devices
• During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts
of the execution, they carry the 8 data bits.

20 GND or VSS Ground

A8 to A15:
• A8-A15 are a set of eight unidirectional lines that form the
21-
A8-A15 upper part of the 16-bit Address bus.
28
• They are used to transmit the most significant bits of the
memory address during memory read and write operations.

ALE (Address Latch Enable):

• When ALE = 1, AD0 to AD7 serve as address lines (A0-A7),
allowing the microprocessor to use them for addressing
30 ALE
memory locations.
• When ALE = 0, AD0 to AD7 serve as data lines (D0-D7),
enabling the microprocessor to send or receive data.
• ̅̅̅̅̅
𝐖𝐑 is an active low signal used to initiate the write
operation when interfacing with memory or peripheral
31 ̅̅̅̅̅
𝐖𝐑 devices.
• When ̅̅̅̅̅
𝐖𝐑 = 0, It indicates that the data on the data bus are
to be written into a selected memory or I/O location.
• ̅̅̅̅
𝐑𝐃 is an active low signal used to initiate the read operation
when interfacing with memory or peripheral devices.
32 ̅̅̅̅
𝐑𝐃
• When 𝐑𝐃̅̅̅̅ = 0, it indicates that the selected I/O or memory
device is to be read and data are available on the data bus.

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Microprocessor & Microcontroller Unit-1: Introduction to Microprocessor

These are the status signals sent by microprocessor to distinguish

the various types of operations as mentioned below.
S1 S0 Operations
29 &
S0 & S1 0 0 HALT (No operation)
33
0 1 WRITE
1 0 READ
1 1 FETCH
• I0/ 𝐌
̅ is a status signal used to differentiate whether the
address is for I/O or memory operations.
̅ • When I0/ 𝐌 ̅ = 1, the address on the address bus is for I/O
34 I0/ 𝐌
devices.
• When I0/ 𝐌 ̅ = 0, the address on the address bus is for the
memory.
• READY signal is used by the microprocessor to sense whether a
peripheral is ready to transfer data or not.
35 READY
• If READY = 1, the peripheral is ready
• If READY = 0, the microprocessor waits till it goes high.

• When ̅̅̅̅̅̅̅̅̅
𝐑𝐄𝐒𝐄𝐓 ̅̅̅𝐈𝐍 = 𝟎, the microprocessor enters a reset state.
36 ̅̅̅̅̅̅̅̅̅ 𝐈𝐍
𝐑𝐄𝐒𝐄𝐓 ̅̅̅ • During this state, all registers and flags are cleared, and the
program counter (PC=00) is typically set to its initial value.
• CLK OUT in the 8085 microprocessor is an output signal that
37 CLK (OUT) carries the microprocessor's clock frequency. This signal can be
used as the system clock for other devices.
HLDA (Hold Acknowledge):
• HLDA is a signal used to acknowledge a HOLD request.
38 HLDA • It indicates that the HOLD request has been received.
• The microprocessor takes over the buses after the removal of
the HOLD request when HLDA goes low.
HOLD (Hold Request):
• It indicates that another device is requesting the use of the
address and data bus.
• After receiving a HOLD request, the microprocessor
39 HOLD
relinquishes (hands over) the use of the buses as soon as the
current machine cycle is completed.
• The microprocessor regains the buses after the removal of the
HOLD signal.
40 VCC +5V DC supply

Note:
In the 8085 microprocessor, "HOLD" and "HLDA" (Hold Acknowledge) are control
signals used to manage external requests for control of the system bus.

Status signals and the status of data bus

̅
I0/ 𝐌 S1 S2 Data Bus Status (Output)

0 0 0 Halt

0 0 1 Memory WRITE

0 1 0 Memory READ

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1 0 1 IO WRITE

1 1 0 IO READ

0 1 1 Op code fetch

1 1 1 Interrupt acknowledge

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

UNIT
Basic Programming concepts

SYLLABUS
Basic Programming concepts: Flow chart symbols, Data Transfer operations, Arithmetic
operations, Logic Operations, Branch operation, Writing assembly language programs,
Programming techniques: looping, counting and indexing. Additional data transfer and 16-bit
arithmetic instruction, Logic operation: rotate, compare, counter and time delays, 8085 Interrupts.

FLOW CHART SYMBOLS

SYMBOL SHAPE MEANING
An oval shape indicates the beginning or
OVAL SHAPE
end of a program.

Arrow indicates the direction of the

ARROW
program execution.

RECTANGLE A rectangle represents a process.

A parallelogram represents input or

PARALLELOGRAM
output.

A diamond indicates a decision or

DIAMOND
branching point.

DOUBLE SIDED Represents a predefined process such as

RECTANGE a subroutine.

CIRCLE WITH AN Represents continuation (an entry or

ARROW exit) to a different page.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
ADDRESSING MODES:
The CPU can access data in various ways. The data could be in a memory or in register or it may
be an immediate value (CONSTANT). The various ways of accessing these data are called
addressing mode.

There are 5 addressing modes in 8051

1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Implied Addressing Mode

1. IMMEDIATE ADDRESSING MODE:

• In immediate addressing mode the 8-bit or 16-bit data (operand) is specified within
the instruction itself.
• The immediate addressing instructions are either 2 bytes or 3 bytes long.
• In 2-byte instruction, the first byte is OPCODE, and the second byte is the 8-bit data.
• In 3-byte instruction, the first byte is OPCODE, second and third bytes are 16-bit data.
• The instruction containing the letter “I” indicate immediate addressing mode.
Examples:
Instruction Comment
MVI A, 42 H ; Move 42 H in register A
ADI 05 H ; Add 05 H to the content of the accumulator.
LXI H, C300 H ; This instruction transfers 16-bit immediate data C300 to HL register
pair. Lower order data (00 H) to L register and high order data
(C3 H) to H register.

2. REGISTER ADDRESSING MODE:

• In register addressing mode, the source and destination operands are in the
general-purpose registers.
• The register addressing instructions are generally of 1 byte i.e. OPCODE only.
• The OPCODE specifies the operation and registers to be used to perform the operation.
Examples:
Instruction Comment
MOV A, B ; Move the content of register B to register A
ADD B ; This instruction adds the content of the B register and A register, the
data is present in both B and A registers. The result is stored in the
accumulator.
PCHL ; This instruction will transfer the content of register pair HL to the PC
(Program Counter).

3. DIRECT ADDRESSING MODE:

• In direct addressing mode, the 16-bit address of the data (operand) is given within
the instruction itself.
• The instruction in the direct addressing mode is 3-byte instructions. The first byte is
OPCODE, the second lower order address mode, and the third is the higher-order address
mode.
• For I/O instruction that uses direct addressing mode is 2-byte as the address if I/O is one
byte.
Examples:
Instruction Comment
LDA C300 H ; Load accumulator directly from the memory location. In this
instruction, the contents of the C300 H memory location are
transferred to the accumulator.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
STA 2500 H ; Store accumulator directly to memory location. In this instruction,
the content of the accumulator is stored at memory location 2500 H.
IN 02 H ; Read data from the PORT B. (Here 02 H is the address of PORT C).

4. REGISTER INDIRECT ADDRESSING MODE:

• In register indirect addressing mode, the address of the data (operand) is specified
by a register pair (i.e. the memory address where the operand is located is specified
by the content of a register pair).

Example 1:
Instruction Comment
LXI H, 3500 H ; Load the H-L pair with 3500 H
MOV A, M ; Move the content of the memory location, whose address is in H-L
pair i.e. 3500 H, to the accumulator
HLT ; Halt

Example 2:
Instruction Comment
LXI H, 3500 H ; Load the H-L pair with 3500 H
ADD A, M ; Add the content of the memory location, whose address is in H-L pair
i.e. 3500 H, to the content of the accumulator
HLT ; Halt

Example 3:
Instruction Comment
LDAX B ; The BC register pair is used as an address and the content of the
memory location specified by the BC pair is copied to the
accumulator.

5. IMPLIED ADDRESSING MODE:

• The implied mode of addressing does not require any data (operand) or memory
address.
• The data is specified within Instruction (OPCODE) itself.
• Generally, the implied addressing mode instruction is a 1-byte instruction.
• The data is supposed to be present generally in the accumulator.

Examples:
Instruction Comment
CMA ; Complement Accumulator. The CMA instruction complements (flips)
all the bits in the accumulator. It changes 0s to 1s and 1s to 0s.
RAL ; Rotate Accumulator Left through Carry. The RAL instruction rotates
the bits in the accumulator to the left through the carry flag. The carry
flag is shifted into the least significant bit (LSB), and the LSB is shifted
into the carry flag.
NOP : This instruction does nothing and is used for creating delays in a
program.

INSTRUCTION & INSTRUCTION FORMAT:

INSTRUCTION
• An instruction is a command to the microprocessor to perform a specific operation.
• Each Instruction has two parts
i. OPCODE (operation code): Operation or Task to be performed.
ii. OPERAND: The data to be operated

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
INSTRUCTION FORMAT:
OPCODE OPERAND1, OPERAND 2
• Each instruction has two parts: one is task to be performed, called the operation code
(opcode), and the second is the data to be operated on, called the operand. It may
have more than operand.
• The operand (or data) can be specified in various ways. It may include 8-bit or 16-bit
data, an internal register, a memory location, or 8-bit or 16-bit address. In some
instructions, the operand is implicit.

INSTRUCTION WORD SIZE IN 8085:

The 8085-instruction set is classified into three groups based on the size of the instruction
• One-word or 1-byte instructions
• Two-word or 2-byte instructions
• Three-word or 3-byte instructions
Examples:
1 Byte Instruction 2 Byte Instruction 3 Byte Instruction
NOP LDA 2050H LHLD 3050H
HLT MVI A, 3CH STA 4090H
DI INR D LXI H, 3050H

CLASSIFICATION OF INSTRUCTIONs:
These instructions can be classified into five different groups:
1. Data Transfer Group
2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. I/O and Machine Control Group

1. DATA TRANSFER GROUP INSTRUCTIONS:

• These operations simply COPY the data from the source to the destination.
• The data in the source is not changed.
• Data transfer instructions do not affect the flags.
(Examples: MOV, MVI, LDA, STA etc.)
Example:
• The "MOV" (move) instruction is a common data transfer instruction. It transfers data
from one location to another, such as from memory to a register or between registers.
Note:
They transfer:
✓ Data between registers.
✓ Data Byte to a register or memory location.
✓ Data between a memory location and a register.
✓ Data between an I\O Device and the accumulator.

2. ARITHMETIC GROUP INSTRUCTIONS:

Instructions in this group perform various mathematical operations, including addition,
subtraction, multiplication, and division. They manipulate numerical data and perform
arithmetic calculations.
Example:
• The "ADD B" instruction adds the contents of B register with Accumulator and the result
is stored in the accumulator.

3. LOGICAL GROUP INSTRUCTIONS:

Logical group instructions perform logical operations on data stored in the accumulator (A) and
sometimes other registers. These instructions are used to perform logical AND, OR, XOR,
complement (NOT), and rotate operations.

Page | 4
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Example:
• The "AND" instruction performs a bitwise AND operation on two operands, setting the
result to 1 in each bit position where both operands have a 1.

4. BRANCH GROUP INSTRUCTIONS:

Instructions in this group control program flow by allowing conditional or unconditional
branching. They determine the sequence in which instructions are executed based on certain
conditions or jump to specific locations in the program.
Example:
• The "JUMP IF ZERO" instruction checks if a specific condition (e.g., the result of a previous
calculation is zero) is met. If true, it branches to a specified address; otherwise, it
continues to the next instruction.

5. I/O MACHINE GROUP INSTRUCTIONS:

These instructions manage input and output operations, as well as control various machine-level
functions. They are responsible for interacting with external devices and controlling the
computer's hardware.
Example:
• Input/output instructions may include commands to read data from a keyboard or write
data to a display.
• Machine control instructions can include commands to reset the computer or put it in a
specific power-saving mode.

Page | 5
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

SYMBOLS & ABBREVIATIONS

A Accumulator
A, B, C, D, E, H, L 8-bit register
H-L Register Pair H-L
B-C Register Pair B-C
D-E Register Pair D-E
PSW Program Status Word (Flags)
M Memory whose address is in H-L pair
H 2000 H indicates the hexadecimal number (It is not a register).
16-bit Program counter, PCH is the higher order 8-bit and PCL is the lower
PC
order 8-bits of register PC.
C Carry flag
addr 16-bit address of the memory location
data 8-bit data available in the instruction.
data 16 16-bit data available in the instruction.
Rs Source register
Rd Destination register
Register Pair
B represents B-C pair; B is higher order register & C is lower order
register.
D represents D-E pair; D is higher order register & E is lower order
rp register.
H represents H-L pair; H is higher order register & L is lower order
register.
SP represents 16-bit stack pointer; SPH is higher order 8-bits & SPL is
lower order 8-bits of register SP.
rh The higher order register of a register pair
rl The lower order register of a register pair
() The content of a register identified within the bracket.
The content of the memory location whose address is in the register pair
(( ))
identified within brackets.
Exchange contents
^ or . (dot) AND operation
ᵛ OR Operation
⊕ EXCLUSIVE OR Operation
H at the end of an instruction, it indicates that the number is in
H
hexadecimal (base-16) notation.

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Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
DATA TRANSFER INSTRUCTIONS
Note: XX is unknown value

affected

Bytes
Flags
Syntax Operation Description Example

MOV A, B
Move or copy the content of source
Move or copy
register B to destination register A.
the content of
source register

None
MOV Rd, Rs (Rd)  (Rs) Before Execution: 1
Rs to
Let A = XX H & B = 04 H
destination
After Execution:
register Rd.
A = 04 H & B = 04 H

MOV M, B
Move or copy Move or copy the content of source
the content of register B to destination memory
source register location pointed by register M
Rs to (H-L).

None
MOV M, Rs (M)  (Rs) destination Before Execution: 1
memory Let M (H-L) = 3000 H &
location pointed B = 04 H
by register M 3000 H = XX
(H-L). After Execution:
3000 H = 04 H & B = 04 H
MOV B, M
Move or copy the content of the
Move or copy memory location pointed by
the content of register M (H-L) to destination
the memory register B.
location pointed Before Execution:

None
MOV Rd, M (Rd)  (M) by register pair Let M (H-L) = 3000 H & 1
M 3000 H = 55 H
(H-L) to B = XX
destination
register Rd. After Execution:
B= 55H & 3000 H = 55 H

MVI A, 55 H
Move 8-bit immediate data 55 H to
Move 8-bit
the destination register A
immediate data
None

MVI Rd, 8-bit (A)  8-bit data to the 2

Before Execution:
destination
Let A = XX H & B = 04 H
register
After Execution:
A = 04 H & B = 04 H

MVI M, 55 H
Move 8-bit immediate data 55 H to
Move 8-bit the memory location pointed by
immediate data register M (H-L)
to the memory
location pointed Before Execution:
None

MVI M, data M  8-bit data 1

by register M Let M (H-L) = 3000 H
(H-L) 3000 H = XX
55 H is 8-bit data

After Execution:
3000 H = 55 H

Page | 7
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

affected

Bytes
Flags
Syntax Operation Description Example

The contents of
a memory
LDA 3000 H
location,
The contents of a memory location,
specified by a
3000 H, is copied to the accumulator
16-bit address
LDA 16-bit in the operand,
Before Execution:
address is copied to the
Let M (H-L) = 3000 H
A  (16-bit accumulator.

None
3000 H = 55 H 3
(Load address) or
A = XX
Accumulator Load the
Directly) content (8-bit
After Execution:
data) of the
A = 55
specified
3000 H = 55 H
memory
location into
accumulator.
LDAX B
Load the accumulator (A) with the
contents of the memory location
Load the pointed to by the register pair B-C
accumulator (A)
with the Before Execution:
contents of the Let B (B-C) = 3000 H

None
LDAX rp A  (rp) 1
memory B=30 H & C=00 H
location pointed 3000 H = 55 H
to by the A = XX
register pair
After Execution:
A = 55
3000 H = 55 H
LXI H, 3000 H
Loads the HL register pair with the
16-bit hexadecimal value 3000H.
LXI rp, 16-bit
data Loads 16-bit Before Execution:
data in the Let H (H-L) = XXXX
(rp)  16-bit
None

Load Register specified H=XX H & L=XX H 3

data
Pair register pair
Immediate (B or D or H) After Execution:
H-L = 3000 H
H = 30 H (the high byte of 3000H)
L = 00 H (the low byte of 3000H)

LHLD 3000 H
Load the content of the memory
location 3000 H into register L and
the content of the next memory
Load the
location 3001 H is loaded into
content of the
register H
(L)  (16-bit memory
LHLD 16-bit
address) location into
address Before Execution:
register L and
Let 3000 H = 11 H
None

(H)  (16-bit the content of 3

Load HL pair 3001 H = 22 H
address + 1 i.e. the next
to the content L = XX & H = XX i.e. HL = XXXX
next memory memory
of the address
location) location is
After Execution:
loaded into
3000 H = 11 H
register H
3001 H = 22 H
L = 11 H & H = 22 H
i.e. HL = 2211 H

Page | 8
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

affected

Bytes
Flags
Syntax Operation Description Example

SHLD 3000 H
Stores the contents of the HL
register pair into the memory
Stores the locations
contents of the i.e. content of L register in 3000 H
HL register pair and the content of H register in
into the 3001 H.
memory
SHLD 16-bit locations Before Execution:

None
(address)  (L)
3
address (address+ 1)  (H) i.e. content of L Let 3000 H = XX
register in 3001 H = XX
address and the L = 11 & H = 22 i.e. HL = 2211 H
content of H
register in After Execution:
address +1. 3000 H = 11 H
3001 H = 22 H
HL = 2211 H

STA 3000 H
The content of the accumulator is
STA 16-bit stored in the memory location
The content of
address 3000 H.
the accumulator
Before Execution:
is stored in the
Let 3000 H = XX

None
(address)  (A) memory 3
Store A = 55 H
location
accumulator
specified in the
content to After Execution:
instruction.
direct address 3000 H = 55 H
A = 55 H

Store the STAX B

contents of the Store the contents of the
accumulator (A) accumulator (A) in the memory
in the memory location whose address is in the
location whose register pair B-C
STAX rp
address is in the
register pair Before Execution:
None

Store ((rp))  (a) 1

Let B=30 H & C= 00 H
accumulator
The "rp" can be i.e. BC = 3000 H
indirect
one of the A = 55 H
following 3000 H = XX
register pairs:
BC & DE After Execution:
3000 H = 55 H
XCHG
The contents of H-L pair are
exchanged with the contents of
D-E pair.
Before Execution:
XCHG Let H = 11 H & L = 22 H
The contents of
(H) (D) i.e. H-L = 1122 H
H-L pair are
Exchange the
None

exchanged with Let D = 33 H & E = 44 H 1

content of H (L) (E) the contents of i.e. D-E = 3344 H &
and L with D
D-E pair.
and E pair
After Execution:
H = 33 H & L = 44 H
i.e. H-L = 3344 H
D = 11 H & E = 22 H
i.e. D-E = 1122 H

Page | 9
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
ARITHMETIC GROUP

affected
Bytes
Flags
Syntax Operation Description Example

ADD B
Before Execution:
Let A = 9A H
B = 89 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0

Execution:
The contents of 9A H= 1001 1010
register are added 89 H= 1000 1001

All Flags
to the contents of 23 H= 0010 0011
A  (A) +
ADD R accumulator. 1
(Reg)
The result is After Execution:
stored in A = 23 H
accumulator. B = 89 H
Flag: S=0, Z=0, AC=1, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADD M

Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Execution:
20 H= 0010 0000
The contents of
08 H= 0000 1000
memory are
28 H= 0010 1000
added to the
All Flags

A  (A)+ contents of
ADD M 1
(Memory) accumulator.
After Execution:
The result is
A = 28 H
stored in
HL = 2500 H
accumulator.
Flag: S=0, Z=0, AC=0, P=1, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

A  (A)+ 8-bit The 8-bit ADI B2 H

Flag
All

ADI 8-bit 2
s

Data immediate data is Before Execution:

Page | 10
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
added to the Let A = C4 H
contents of Immediate Data = B2 H
accumulator. Flag: S=0, Z=0, AC=0, P=0, and CY=0
The result is
stored in Execution:
accumulator. C4 H= 1100 0100
B2 H= 1011 0010
76 H= 0111 0110

After Execution:
A = 76 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADC B
Before Execution:
Let A = 9A H
B = 89 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

The contents of Execution:

register and Carry 9A H= 1001 1010
Flag (CY) are 89 H= 1000 1001

All Flags
added to the CY 1
A  (A)+
ADC R contents of 24 H= 0010 0100

1
(Reg)+(CY)
accumulator.
The result is
stored in After Execution:
accumulator. A = 24 H
B = 89 H
Flag: S=0, Z=0, AC=1, P=1, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

ADC M
Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H 75 H
2500 H 08 H
The contents of
2501 H 21 H
memory and
2502 H 13 H
Carry Flag (CY)
All Flags

A  (A)+ are added to the

ADC M (Memory)+(C contents of Execution:
1

Y) accumulator. 20 H= 0010 0000

The result is 08 H= 0000 1000
stored in CY 1
accumulator. 29 H= 0010 1001

After Execution:
A = 29 H
HL = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=0

Memory

Page | 11
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

ACI B2 H

Before Execution:
Let A = C4 H
Immediate Data = B2 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Execution:
The 8-bit
C4 H= 1100 0100
immediate data
B2 H= 1011 0010
and the Carry Flag
CY 1

All Flags
(CY) are added to
A  (A)+ 8- 77 H= 0111 0111
ACI 8-bit the contents of

2
bits Data+(CY)
accumulator.
The result is
After Execution:
stored in
A = 77 H
accumulator.
Flag: S=0, Z=0, AC=0, P=1, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

DAD B

Before Execution:
Let HL = 2233 H
BC = 1122 H
Flag: CY=1

The 16-bit Execution:

contents of the 2233 H
register pair are 1122 H
Carry Flag

HL  (Reg. added to the 3355 H

DAD Rp
1

Pair) +(HL) contents of H-L

pair. After Execution:
The result is HL = 3355 H
stored in H-L pair. BC = 1122 H

Flag: CY=0

Note: NO flags are affected except

carry flag.

SUB B
The contents of
Before Execution:
All Flags

the register are

Let A = 9A H
SUB R A  (A)- (R) subtracted from
1

B = 89 H
the contents of
Flag: S=0, Z=0, AC=0, P=0, and CY=0
the accumulator.

Page | 12
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
The result is Execution:
stored in 9A H= 1001 1010
accumulator. 89 H= 1000 1001
11 H= 0001 0001

After Execution:
A = 11 H
B = 89 H
Flag: S=0, Z=0, AC=0, P=1, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

SUB M
Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

The contents of Execution:

the memory 20 H= 0010 0000
location are 08 H= 0000 1000

All Flags
subtracted from 18 H= 0001 1000
SUB M A  (A)- (M) the contents of

1
the accumulator.
The result is After Execution:
stored in A = 18 H
accumulator. HL = 2500 H

Flag: S=0, Z=0, AC=1, P=1, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

SUI 13 H
Before Execution:
Let A = 05 H
Immediate data= 13 H
Flag: S=0, Z=0, AC=0, P=0, and CY=0
The 8-bit
immediate data is Execution:
subtracted from 05 H= 0000 0101
All Flags

A  (A)- 8 the contents of 13 H= 0001 0011

SUI 8-bit
2

bits Data the accumulator. F2 H= 1111 0010

The result is
stored in After Execution:
accumulator. A = F2 H

Flag: S=1, Z=0, AC=0, P=0, and CY=1

Note: All flags are affected during the

execution of arithmetic instruction.

Page | 13
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

SBB B
Before Execution:
Let A = 25 H
B = 13 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1
The contents of
the register and Execution:
Borrow Flag (i.e. 25 H= 0010 0101
CY) are 13 H= 0001 0011

All Flags
A  (A)- (R)- subtracted from CY 1
SBB R

1
(CY) the contents of 11 H= 0001 0001
the accumulator.
The result is After Execution:
stored in A = 11 H
accumulator.
Flag: S=0, Z=0, AC=0, P=1, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

SBB M
Before Execution:
Let A = 20 H
HL = 2500 H
Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H
The contents of
Execution:
the memory
20 H= 0010 0000
location and
08 H= 0000 1000
Borrow Flag (i.e.
CY 1

All Flags
CY) are
A  (A)- (M)- 17 H= 0001 0111
SBB M subtracted from

1
(CY)
the contents of
the accumulator.
After Execution:
The result is
A = 17 H
stored in
HL = 2500 H
accumulator.
Flag: S=0, Z=0, AC=1, P=1, and CY=0

Memory
24FF H 75 H
2500 H 08 H
2501 H 21 H
2502 H 13 H

Note: All flags are affected during the

execution of arithmetic instruction.

SBI 13 H
The 8-bit Before Execution:
immediate data Let A = 18 H
All Flags

and the Borrow Immediate data= 13 H

A  (A)- 8
SBI 8-bits Flag (i.e. CY) is Flag: S=0, Z=0, AC=0, P=0, and CY=1
2

bits data -(CY)

subtracted from
the contents of Execution:
the accumulator. 18 H= 0001 1000
13 H= 0001 0011

Page | 14
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
The result is CY 1
stored in F2 H= 0000 0100
accumulator.
After Execution:
A = 04 H

Flag: S=0, Z=0, AC=0, P=0, and CY=0

Note: All flags are affected during the

execution of arithmetic instruction.

INR E
Before Execution:
Let E = 1C H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

All flags, except Cy flag

Execution:
The contents of 1C H= 0001 1100
register are + 1
incremented by 1. 1D H= 0001 1101
INR R R  (R)+ 1

1
The result is
stored in the same After Execution:
place. E= 1D H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
INR M
Before Execution:
Let HL = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H XX H
2500 H 1C H
2501 H XX H
2502 H XX H
All flags, except Cy flag

Execution:
The contents of
1C H= 0001 1100
memory location
+ 1
are incremented
1D H= 0001 1101
INR M M  (M)+ 1 by 1.
1

The result is
After Execution:
stored in the same
HL= 2500 H
place.
Memory
24FF H XX H
2500 H 1D H
2501 H XX H
2502 H XX H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced

Page | 15
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
INX B
Before Execution:
Let BC = 2050 H

Execution:
The contents of 2050 H= 0010 0000 0101 0000
the designated + 1
register pair are 2051 H= 0010 0000 0101 0001

None
INX Rp Rp  (Rp)+ 1 incremented by 1

1
and their result is After Execution:
stored at the same BC= 2051 H
place.
Flag: S=0, Z=0, AC=0, P=1, and CY=NO
CHANGE

Note: Flag bits are not at all affected

by the execution of this instruction.
DCR B
Before Execution:
Let B = 1C H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

All flags, except Cy flag

Execution:
The contents of
1C H= 0001 1100
the designated
- 1
register are
1B H= 0001 1011
DCR R R  (R)- 1 decremented by 1

1
and their result is
After Execution:
stored at the same
B= 1B H
place.
Flag: S=0, Z=0, AC=0, P=1, and CY=NO
CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
DCR M
Before Execution:
Let HL = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

Memory
24FF H XX H
2500 H 1C H
All flags, except Cy flag

2501 H XX H
The contents of
2502 H XX H
the designated
memory are
Execution:
DCR M M  (M)- 1 decremented by 1
1

1C H= 0001 1100
and their result is
- 1
stored at the same
1B H= 0001 1011
place.
After Execution:
HL= 2500 H

Memory
24FF H XX H
2500 H 1B H
2501 H XX H
2502 H XX H

Page | 16
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
Flag: S=0, Z=0, AC=0, P=1, and CY=NO
CHANGE

Note: All flags, except Cy flag, are

affected depending on the result thus
produced
DCX B
Before Execution:
Let BC = 2500 H

Flag: S=0, Z=0, AC=0, P=0, and CY=1

The contents of Execution:

the designated 2500 H= 0010 0101 0000 0000
register pair are - 1

None
DCX Rp Rp  (Rp)- 1 decremented by 1 24FF H= 0010 0100 1111 1111

1
and their result is
stored at the same After Execution:
place. HL= 24FF H

Flag: S=0, Z=0, AC=0, P=1, and CY=NO

CHANGE

Note: Flags are not at all affected by

the execution of this instruction
Description:
The contents of the accumulator are changed from a binary
value to two 4-bit binary-coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary flag (internally) to
perform the binary-to-BCD conversion; the conversion
procedure is described below.
Instruction DAA converts the binary contents of the
accumulator as follows:
1 If the value of the low-order four bits
(𝐷3 − 𝐷0 ) in the accumulator is greater than 9 or if AC flag
is set, the instruction adds 6(06) to the low-order four bits.
2 If the value of the high-order four bits
(𝐷7 − 𝐷4 ) in the accumulator is greater than 9 or if the Carry
flag is set, the instruction adds 6(60) to the high-order four
bits.

Example:
DAA ADD decimal number 13 to the accumulator, which
contains 38
A (BCD Value) In In
(Decimal
ALL

 A(Binary
1

adjust Decimal Hex

Value) 3 8 38
accumulator
) + 1 3 + 13
5 1 4B H

D7 D6 D5 D4 D3 D2 D1 D0
1 1

A 3 8 = 0 0 1 1 1 0 0 0
+ 1 3 = 0 0 0 1 0 0 1 1
4 B = 0 1 0 0 1 0 1 1
Result in Accumulator is 4B H and not an BCD.

The result, initially 4BH, is not in BCD format. After applying

the DAA instruction, the value of the lower-order four bits is
greater than 9, we add 6H to those bits to ensure the result is
in proper BCD format

Page | 17
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

D7

D6

D5

D4

D3

D2

D1

D0
1 1 1

A 4 B = 0 1 0 0 1 0 1 1
+ 0 6 = 0 0 0 0 0 1 1 0
A 5 1 = 0 1 0 1 0 0 0 1
Result in Accumulator is BCD 51.

Page | 18
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
LOGICAL GROUP

affected
Bytes
Flags
Syntax Operation Description Example

(A) (A) ^ ANA B

(r) Performs a logical AND operation between
ANA r
the contents of A and the B register, and the
performs a
Note: result is stored back in accumulator A.
bitwise AND
AND symbol
operation
→^ Before Execution:
between the ALL
A = 55 H
ANA r binary values in
B = 65 H
the accumulator (Z,
AND (A) and the S,
Where "r" After Execution: 1
register specified P,
can be any of A = 41 H
with register (r) & CY
the following B = 65 H
accumulator the result is &
registers:
stored back in AC)
B, C, D, E, H,
the
L or M
accumulator.
(Indirect
addressing
using the HL
pair)
Perform a ANA M
logical AND
operation Before Execution:
between the A = 55 H
contents of the M = HL = 3000 H ALL
ANA M accumulator (A) 3000 = 65 H
and the data (Z,
(A) (A)
AND stored in the After Execution: S,
^ (M) 1
memory memory A = 41 H P,
with location pointed 3000 = 65 H CY
accumulator to by the HL &
register pair & AC)
the result is
stored back in
the
accumulator.
Perform a ANI 3C H
logical AND ALL
ANI 8-bit data operation Before Execution:
between the A = A7 H (Z,
(A) (A) ^
AND accumulator (A) data → 3C H S,
(data) 1
immediate and an 8-bit P,
data with data value & the After Execution: CY
accumulator result is stored A = 24 H &
back in the AC)
accumulator.
(A) (A) ORA B
ORA r
v (r) Performs a logical OR operation between the
performs a
contents of A and the B register, and the
bitwise OR
Note: result is stored back in accumulator A.
operation ALL
OR symbol
between the
ORA r →ᴠ Before Execution:
binary values in (Z,
A = 55 H
the accumulator S,
OR register B = 65 H 1
(A) and the P,
with
specified CY
accumulator Where "r" After Execution:
register (r) & &
can be any of A = 75 H
the result is AC)
the following B = 65 H
stored back in
registers:
the
B, C, D, E, H,
accumulator.
L or M

Page | 19
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
(Indirect
addressing
using the HL
pair)

affected
Bytes
Flags
Syntax Operation Description Example

Perform a ORA M
logical OR
operation Before Execution:
between the A = 55 H
contents of the M = HL = 3000 H ALL
accumulator (A) 3000 = 65 H
ORA M
and the data (Z,
(A) (A)
stored in the After Execution: S,
OR memory v (M) 1
memory A = 75 H P,
with
location pointed 3000 = 65 H CY
accumulator
to by the HL &
register pair & AC)
the result is
stored back in
the
accumulator.
Perform a ORI 65 H
logical OR ALL
ORI 8-bit data operation Before Execution:
between the A = 55 H (Z,
(A) (A) v
OR accumulator (A) data → 65 H S,
(data) 1
immediate and an 8-bit P,
data with data value & the After Execution: CY
accumulator result is stored A = 75 H &
back in the AC)
accumulator.
(A) (A) ⊕ XRA B
(r) Performs a logical EX-OR operation between
the contents of A and the B register, and the
XRA r
Note: result is stored back in accumulator A.
performs a
EX-OR symbol
bitwise EX-OR
→⊕ Before Execution:
operation ALL
A = 55 H
XRA r between the
B = 65 H
binary values in (Z,
EX-OR the accumulator S,
Where "r" After Execution: 1
register (A) and the P,
can be any of A = 30 H
with specified CY
the following B = 65 H
accumulator register (r) & &
registers:
the result is AC)
B, C, D, E,
stored back in
H, L or M
the
(Indirect
accumulator.
addressing
using the
HL pair)
XRA M XRA M
(A) (A) ⊕ perform a
(M) bitwise XOR Before Execution: ALL
XRA M (exclusive OR) A = 55 H
Note: operation M = HL = 3000 H (Z,
EX-OR EX-OR symbol between the 3000 = 65 H S,
1
memory →⊕ contents of the P,
with accumulator (A) After Execution: CY
accumulator and the data A = 30 H &
stored in the 3000 = 65 H AC)
memory
location pointed

Page | 20
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
to by the HL
register pair
(indirect
addressing) &
the result is
stored back in
the
accumulator.
XRI 8-bit data XRI 65 H
perform a
logical XOR Before Execution:
(exclusive OR) A = 55 H ALL
(A) (A) ⊕ 8- operation
bit data between the After Execution: (Z,
contents of the A = 30 H S,
XRI 8-bit data 1
Note: accumulator (A) P,
EX-OR symbol and an 8-bit CY
→⊕ immediate data &
value & the AC)
result is stored
back in the
accumulator.
CMA CMA
(Complement
Accumulator) Before Execution:
instruction is A = 0F H
used to perform
ALL
a bitwise After Execution:
CMA complement A = F0 H
(Z,
̅) (bitwise NOT)
(A)  (𝑨 S,
Complement operation on the 1
P,
the contents of the
CY
accumulator accumulator (A).
&
This means that
AC)
all the bits in the
accumulator are
inverted: 0s
become 1s, and
1s become 0s.
CMC is used to CMC
complement Before Execution:
CMC (toggle) the CY = 0 (one bit)
state of the
(CY) 
Complement Carry Flag (CY) After Execution:
(̅̅̅̅
𝑪𝒀) CY 1
the carry bit in the status CY = 1 (one bit)
(CY) register.

Other flags are

not affected
CMP r CMP B
used to compare Before Execution:
the contents of A = 55 H
the accumulator B = 56 H
(A) with the ALL
contents of a After Execution:
CMP r
specified A = 55 H (Z,
(A) - (r) register (r) B = 56 H S,
Compare 1
without P,
register with
actually Zero Flag (Z): Set if A = B CY
accumulator
changing the Sign Flag (S): Set if the result is negative (A < &
contents of the B). AC)
accumulator. It Carry Flag (CY): Set if a borrow occurred
sets the flags in during subtraction (A < B).
the status Parity Flag (P): Set if the number of set bits
register based in the result is even.

Page | 21
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
on the result of Auxiliary Carry Flag (AC): Set if a borrow
the occurred from bit 4 to bit 3 during
comparison. subtraction.

The contents of
the A & r
remain
unchanged.
CMP M
Before Execution:
CMP M M (HL) = 3000 H
instruction is A = 55 H
used to compare 3000 H = 56 H
the contents of
the accumulator After Execution:
(A) with the A = 55 H ALL
data stored in 3000 = 56 H
CMP M
the memory (Z,
(A) - (M) location pointed S,
Compare 1
to by the HL Zero Flag (Z): Set if A = M P,
memory with
register pair Sign Flag (S): Set if the result is negative (A < CY
accumulator
(indirect M). &
addressing). Carry Flag (CY): Set if a borrow occurred AC)
during subtraction (A < M).
The contents of Parity Flag (P): Set if the number of set bits
the A & M in the result is even.
remain Auxiliary Carry Flag (AC): Set if a borrow
unchanged. occurred from bit 4 to bit 3 during
subtraction.

CPI 56 H

Before Execution:
(A) = 55 H
8-bit data = 56 H
CPI 8-bit data
After Execution:
A = 55 H
Compare the
3000 = 56 H
contents of the
CY = 1 (one Bit)
accumulator (A)
with an 8-bit ALL
Zero Flag (Z): Set if A = 8-bit data value.
immediate data
Sign Flag (S): Set if the result is negative (A <
value (8-bit (Z,
data).
(A) - 8-bit constant). It S,
CPI 8-bit data Carry Flag (CY): Set if a borrow occurred 1
data performs a P,
during subtraction (A < data).
subtraction CY
Parity Flag (P): Set if the number of set bits
between the &
in the result is even.
accumulator and AC)
Auxiliary Carry Flag (AC): Set if a borrow
the immediate
occurred from bit 4 to bit 3 during
data value
subtraction.
without altering
the contents of
the accumulator.

RLC (CY)  A7 The contents of the accumulator and the Carry flag will be
ALL
A7  A6 updated as follows:
Rotate A0  A7 1
(Z,
accumulator ✓ Each binary bit of the accumulator is rotated left by one
S,
left position.
P,

Page | 22
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
✓ Bit A7 (MSB) is placed in the position of A0 as well as in the CY
Carry flag. &
✓ CY is modified according to bit A7. AC)

Before Execution:
A = 55 H
CY = X

After Execution:
A = AA H
CY = 0

The contents of the accumulator and the Carry flag will be

updated as follows:

✓ Each binary bit of the accumulator is rotated right by one

position.
✓ Bit A0 (LSB) is placed in the position of A7 as well as in the
Carry flag.
✓ CY is modified according to bit A0.

Before Execution:
A = 55 H
CY = X
ALL
RRC
(Z,
(CY)  A0
S,
Rotate A7  A0 1
P,
accumulator A6  A7
CY
right
&
AC)
After Execution:
A = AA H
CY = 1

RAL ALL
The contents of the accumulator and the Carry flag will be
CY  A7
updated as follows:
A0  CY (Z, 1
✓ Each binary bit of the accumulator is rotated left by one
Rotate the A1  A0 S,
position through the Carry flag.
accumulator P,

Page | 23
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
left through ✓ Bit A7 is placed in the Carry flag, and the Carry flag is placed CY
carry in the least significant position A0. &
✓ CY is modified according to bit A7. AC)
Before Execution:
A = 55 H
CY = 1

After Execution:
A = AB H
CY = 0

The contents of the accumulator and the Carry flag will be

updated as follows:
✓ Each binary bit of the accumulator is rotated right by one
position through the Carry flag.
✓ Bit A0 is placed in the Carry flag, and the Carry flag is placed
in the most significant position A7.
✓ CY is modified according to bit A0.
Before Execution:
A = 55 H
CY = 0
RAR ALL

(Z,
CY  A0
Rotate the S,
A7  CY 1
accumulator P,
A0  A1
right through CY
carry &
After Execution:
AC)
A = 21 H
CY = 1

Page | 24
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
BRANCH CONTROL GROUP
Jump (Unconditional and Conditional)

affected

Bytes
Flags
Syntax Operation Description Example

JMP 2050
Before Execution:
2041 X
2042 JMP 2050
2045 X
. X
Transfers the 204F X
program 2050 X
Jumps to the sequence to 2051 X
JMP 16-Bit

None
address the described 3
Address
memory After Execution:
address. 2041 X
2042 JMP 2050
2045 X
. X
204F X
2050 X
2051 X

JC 2050
Before Execution:
2041 X
2042 JC 2050
2045 X
. X
204F X
If condition is
true address→ 2050 X
PC (Program 2051 X
JC 16-Bit Jump, if carry

None
Counter) 3
Address flag is set. After Execution:
If condition is
false PC  PC+3 2041 X If If
True False
2042 JC 2050
2045 X
. X
204F X
2050 X
2051 X
JNC 2050
Before Execution:
2041 X
2042 JNC 2050
2045 X
If condition is . X
true address→ 204F X
PC (Program Jump, if carry 2050 X
JNC 16-Bit
None

Counter) flag is not set 2051 X 3

Address
If condition is (reset).
false PC  PC+3 After Execution:
2041 X If If
True False
2042 JNC 2050
2045 X
. X
204F X

Page | 25
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
2050 X
2051 X
JZ 2050
Before Execution:
2041 X
2042 JZ 2050
2045 X
. X
If condition is 204F X
true address→ 2050 X
PC (Program 2051 X
JZ 16-Bit Jump, if zero

None
Counter) 3
Address flag is set. After Execution:
If condition is
false PC  PC+3 2041 X If If
True False
2042 JZ 2050
2045 X
. X
204F X
2050 X
2051 X
JNZ 2050
Before Execution:
2041 X
2042 JNZ 2050
2045 X
. X
If condition is 204F X
true address→ 2050 X
PC (Program Jump, if zero 2051 X
JNZ 16-Bit

None
Counter) flag is not set 3
Address
If condition is (reset). After Execution:
false PC  PC+3 2041 X If If
True False
2042 JNZ 2050
2045 X
. X
204F X
2050 X
2051 X
JP 2050
Before Execution:
2041 X
2042 JP 2050
2045 X
. X
If condition is 204F X
true address→ 2050 X
PC (Program Jump, if 2051 X
JP 16-Bit Counter) positive i.e. 3
None

Address If condition is sign flag is After Execution:

false PC  PC+3 reset. 2041 X If If
True False
2042 JP 2050
2045 X
. X
204F X
2050 X
2051 X

Page | 26
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
JM 2050
Before Execution:
2041 X
2042 JM 2050
2045 X
. X
204F X
If condition is
true address→ 2050 X
PC (Program Jump, if 2051 X
JM 16-Bit

None
Counter) minus i.e. sign 3
Address After Execution:
If condition is flag is set.
false PC  PC+3 2041 X If If
True False
2042 JM 2050
2045 X
. X
204F X
2050 X
2051 X
JPE 2050
Before Execution:
2041 X
2042 JPE 2050
2045 X
. X
204F X
If condition is 2050 X
true address→ 2051 X
Jump, if
PC (Program
JPE 16-Bit parity even

None
Counter) After Execution: 3
Address i.e. parity flag
If condition is 2041 X If If
is set.
false PC  PC+3 True False
2042 JPE 2050
2045 X
. X
204F X
2050 X
2051 X

JPO 2050
Before Execution:
2041 X
2042 JPO 2050
2045 X
. X
204F X
2050 X
If condition is
2051 X
true address→
Jump, if
PC (Program
JPO 16-Bit parity odd i.e. After Execution:
None

Counter) 3
Address parity flag is 2041 X If If
If condition is
reset. True False
false PC  PC+3
2042 JPO 2050
2045 X
. X
204F X
2050 X
2051 X

Page | 27
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

CALL (Unconditional and Conditional)

affected

Bytes
Flags
Syntax Operation Description Example

CALL 3050
Before Execution:
2041 X
2042 CALL
3050
2045 X
. X
Program 204F X
sequence Jumps 2050 X
This 2051 X
to the
instruction is SP=2573 H
subroutine
used to PC=2042 H
address
branch to the After Execution:
CALL 16-Bit subroutine

None
PC (Higher 2041 X Subroutine 3
Address whose 16-bit 2042 CALL 3050
byte)→ (SP-1)
address is 3050
PC (Lower
provided in 2045 X
byte)→ (SP-2)
the
(SP-2)→ SP . X
instruction.
16 Bit 204F X
Address→PC 2050 X
2051 X

SP-1=2572H=45H
SP-2=2571H=20H
SP=2571 H
PC=3050 H

Page | 28
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CC 3050
Before Execution:
2041 X
2042 CC 3050
2045 X
. X
If CY=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CC
CC 16-Bit

None
byte)→ (SP-2) subroutine if 3050 3050 3
Address (SP-2)→ SP carry status 2045 X (If True
16 Bit CY=1 . X CY=1)
Address→PC
204F X
If CY=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program CY=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
CY=0 SP=2573 H

CNC 3050
Before Execution:
2041 X
2042 CNC 3050
2045 X
. X
If CY=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CNC
CNC 16-Bit 3050 3050
None

byte)→ (SP-2) subroutine if 3

Address (SP-2)→ SP carry status 2045 X (If True
16 Bit CY=0 . X CY=0)
Address→PC 204F X
If CY=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program CY=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC=3050 H
PC= No Change
If PC=2045 H
CY=1 SP=2573 H

Page | 29
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CZ 3050
Before Execution:
2041 X
2042 CZ 3050
2045 X
. X
If flag Z=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CZ
CZ 16-Bit

None
byte)→ (SP-2) subroutine if 3050 3050 3
Address (SP-2)→ SP zero status 2045 X (If True
16 Bit flag Z=1 . X Z=1)
Address→PC 204F X
If flag Z=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program Z=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
Z=0 SP=2573 H

CNZ 3050
Before Execution:
2041 X
2042 CNZ 3050
2045 X
. X
If flag Z=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CNZ
CNZ 16-Bit
None

byte)→ (SP-2) subroutine if 3050 3050 3

Address (SP-2)→ SP Zero status
2045 X (If True
16 Bit flag Z=0 Z=0)
. X
Address→PC
204F X
If flag Z=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program Z=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
Z=1 SP=2573 H

Page | 30
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CP 3050
Before Execution:
2041 X
2042 CP 3050
2045 X
. X
If flag S=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CP
CP 16-Bit

None
byte)→ (SP-2) subroutine if 3050 3050 3
Address (SP-2)→ SP sign status 2045 X (If True
16 Bit flag S=0 . X S=0)
Address→PC 204F X
If flag S=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program S=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC=3050 H
PC= No Change
If PC=2045 H
S=1 SP=2573 H

CM 3050
Before Execution:
2041 X
2042 CM 3050
2045 X
. X
If flag S=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CM
CM 16-Bit
None

byte)→ (SP-2) subroutine if 3050 3050 3

Address (SP-2)→ SP sign status
2045 X (If True
16 Bit flag S=1 S=1)
. X
Address→PC
204F X
If flag S=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program S=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
S=0 SP=2573 H

Page | 31
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
CPE 3050
Before Execution:
2041 X
2042 CPE 3050
2045 X
. X
If flag P=1, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CPE
CPE 16-Bit

None
byte)→ (SP-2) subroutine if 3050 3050 3
Address (SP-2)→ SP parity status
2045 X (If True
16 Bit flag P=1 P=1)
. X
Address→PC
204F X
If flag P=0, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program P=1 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
P=0 SP=2573 H

CP0 3050
Before Execution:
2041 X
2042 CPO 3050
2045 X
. X
If flag P=0, 204F X
Program 2050 X
sequence Jumps 2051 X
to the SP=2573 H
subroutine PC=2042 H
address After Execution:
PC (Higher
byte)→ (SP-1) Subroutine
PC (Lower Call 2042 CPO
CPO 16-Bit
None

byte)→ (SP-2) subroutine if 3050 3050 3

Address (SP-2)→ SP parity status
2045 X (If True
16 Bit flag P=0 P=0)
. X
Address→PC
204F X
If flag P=1, 2050 X
program flow
continues in the If SP-1=2572H=45H
main program P=0 SP-2=2571H=20H
sequentially. SP=2571 H
PC= No Change PC=3050 H
If PC=2045 H
P=1 SP=2573 H

Page | 32
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Return (unconditional and conditional)

affected

Bytes
Flags
Syntax Operation Description Example

The program
sequence is RET
transferred
from the Before Execution:
subroutine to
RET stands for
the calling If SP=2095H
return from the
program. Memory
subroutine.
2095 50
The two bytes 2096 20
PC (Lower

None
RET from the top 1
byte) (SP)
of stack are PC=XXXX H
PC (Higher
copied into After Execution:
byte) (SP+1)
the program
SP SP+2
counter and PC=2050 H
the program SP=2097 H
counter
execution
begins at the
new address.
RC
If condition Before Execution:
(CY=1) is If SP=2095H
true, it Memory
returns to the 2095 50
calling
2096 20
program

None
RC Return on Carry 1
PC=3000 H
If condition
After Execution:
(CY!=1) is not
IF CY=1 IF CY=0
true, it
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

RNC
If condition Before Execution:
(CY=0) is If SP=2095H
true, it Memory
returns to the 2095 50
calling
2096 20
RNC Return with No program
None

1
Carry
PC=3000 H
If condition
After Execution:
(CY!=0) is not
IF CY=0 IF CY=1
true, it
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

If condition RP
(S=0) is true,
it returns to Before Execution:
the calling If SP=2095H
Return on
None

RP program Memory 1
positive
2095 50
If condition 2096 20
(S!=0) is not
true, it PC=3000 H

Page | 33
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
continues the After Execution:
sequence IF S=0 IF S=1
PC=2050 H PC=3000 H
SP=2097 H SP=2095 H

RM

If condition Before Execution:

(S=1) is true, If SP=2095H
it returns to Memory
the calling 2095 50
program 2096 20

None
RM Return on minus 1
If condition PC=3000 H
(S!=1) is not After Execution:
true, it IF S=1 IF S=0
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

RPE
If condition
(P=1) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
Return on Parity

None
RPE 2096 20 1
Even
If condition
(P!=1) is not PC=3000 H
true, it After Execution:
continues the IF P=1 IF P=0
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H
RPO
If condition
(P=0) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
Return on Parity
None

RPO 2096 20 1
Odd
If condition
(P!=0) is not PC=3000 H
true, it After Execution:
continues the IF P=0 IF P=1
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H
RZ
If condition
(Z=1) is true, Before Execution:
it returns to If SP=2095H
the calling Memory
program 2095 50
None

RZ Return on Zero 2096 20 1

If condition
(Z!=1) is not PC=3000 H
true, it After Execution:
continues the IF Z=1 IF Z=0
sequence PC=2050 H PC=3000 H
SP=2097 H SP=2095 H

Page | 34
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
RNZ

If condition Before Execution:

(Z=0) is true, If SP=2095H
it returns to Memory
the calling 2095 50
program 2096 20
Return on NO

None
RNZ 1
Zero
If condition PC=3000 H
(Z!=0) is not After Execution:
true, it IF Z=0 IF Z=1
continues the PC=2050 H PC=3000 H
sequence SP=2097 H SP=2095 H

Page | 35
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
STACK, I/O and MACHINE CONTROL GROUP

affected
Bytes
Flags
Syntax Operation Description Example

Example 1:
PUSH B

Before Execution:
Push the Let SP = 3000 H
content of B = 55 H
register pair C = 66 H
rp to stack
((SP-1))  (rh) After Execution:
((SP-2))  (rl) ((SP-1))  (B)
((SP-2))  (C)
The stack
(SP)  (SP)-2
pointer register
(SP)  (SP)-2
PUSH rp is decremented
and the
The "rp" can be 2FFF = 55 H
contents of the
one of the 2FFE = 66 H
high order
following register SP = 2FFD H
Push the register (B, D,

None
pairs: 1
content of H, A) are copied
Example 2:
register pair into that
BC PUSH PSW
rp to stack location. The
DE
stack pointer
HL Before Execution:
register is
PSW (Program Let SP = 3000 H
decremented
Status Word, A = 77 H
again and the
which includes PSW = 88 H
contents of
the accumulator
the low-order After Execution:
and flags)
register (C, E, L, ((SP-1))  (A)
flags) are ((SP-2))  (PSW)
copied to that
location. (SP)  (SP)-2

2FFF = 77 H
2FFE = 88 H
SP = 2FFD H
Example 1:
(rl)  ((SP)) POP B
(rh)  ((SP+1))
The contents of Before Execution:
(SP)  (SP)+2 the memory Let SP = 3000 H
location 3000 = 55 H
pointed out by 3001 = 66 H
POP (retrieve) a the stack
POP rp 16-bit value from pointer register B = XX H
the stack and load is copied to the C = XX H
it into the low-order
POP specified register register (C, E, L, After Execution:
(retrieve) a pairs (rp). The status flags) of (rl)  ((3000))
None

(rh)  ((3000 + 1)) 1

16-bit value "rp" can be one of the operand.
from the the following The stack
stack and register pairs: pointer is (SP)  (3000) +2
load it into incremented
rp BC by 1 and the C = 55 H
DE contents of that B = 66 H
HL memory BC = 6655 H
PSW (Program location are SP = 3002 H
Status Word, copied to
which includes the high-order
the accumulator register (B, D,
and flags) H, A) of the Example 2:
POP PSW

Page | 36
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
operand. The
stack Before Execution:
pointer register Let SP = 3000 H
is again 3000 = 55 H
incremented by 3001 = 66 H
1.
PSW = XX H
A = XX H

After Execution:
(PSW)  ((3000))
(A)  ((3000 + 1))

(SP)  (3000) +2

PSW = 55 H
A = 66 H
SP = 3002 H
SPHL
Copy H and L SPHL
Copy H and

None
(SP) (HL) registers to the The value stored in the HL register pair 1
L registers
stack pointer. is copied into the stack pointer (SP).
to the stack
pointer
XTHL
The contents of the L register are
exchanged with the stack
Exchange the
(L) (SP) location pointed out by the contents of
values of the HL
the stack pointer

None
XTHL register pair 1
(H) (SP+1) register. The contents of the H register
with the stack's
are exchanged with
top two bytes.
the next stack location (SP+1);
however, the contents of the
stack pointer register is not altered.
(A)  (Port Example:
address)
IN Port IN instruction
address Port address is reads data from IN 10 H
the 8-bit the specified None
Input immediate value input port and IN instruction reads data from the 2
accumulator that represents loads it into the input port with an address of 10H and
from I/O the address of accumulator stores the data in the accumulator (A)
Port the input port (A).
from which data
is to be read.
(Port address)
(A)
OUT instruction
OUT Port
address
sends the data Example:
Port address" is
stored in the OUT 20 H
the 8-bit
accumulator to
None

Output from immediate value 2

accumulator the output port OUT instruction sends the data stored
that represents
to I/O Port address in the accumulator to the output port
the address of
specified in the with an address of 20H.
the output port
instruction
to which data is
to be sent
EI Enable Interrupt used to enable interrupts in the 8085 microprocessor
except the TRAP interrupt. When interrupts are enabled using the "EI"
None

1
Enable instruction, the microprocessor will respond to interrupt requests from
Interrupts external devices.
DI Disable Interrupt is used to disable interrupts in the 8085 microprocessor
temporarily except the TRAP interrupt. When interrupts are disabled using
None

1
Disable the "DI" instruction, the microprocessor will not respond to interrupt
Interrupts requests from external devices.

Page | 37
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
This is a
multipurpose
instruction used
to read the status
of
interrupts 7.5, 6.5,
RIM
5.5 and read
serial data input

None
Read 1
bit. The
Interrupt
instruction loads
Mask
eight bits in the
accumulator with
the
following Figure 1
interpretations as
shown in figure 1
This is a
multipurpose
instruction and
used to
implement the
SIM
8085 interrupts
7.5, 6.5, 5.5, and

None
Set 1
serial data output.
Interrupt
The
Mask
instruction
interprets the
Figure 2
accumulator
contents as
shown in figure 2
NOP
No operation is performed when this instruction is executed. The registers and

None
flags and memory remain unaffected. The purpose of the "NOP" instruction is 1
No
to provide a delay.
operation
"Halt" is used to halt or stops the execution of the microprocessor and put it
HLT into a halt state. When the microprocessor is in a halt state, it stops fetching
and executing instructions until it is reset or interrupted.

None
Halt and NOTE: 1
enter wait The "HLT" instruction is often used to save power when the microprocessor is
state not actively performing tasks and needs to wait for external events or
interrupts to resume processing.

Page | 38
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
8085 Assembly Language Program
Steps to write a program
• Analyze the problem
• Develop program Logic
• Write an Algorithm
• Make a Flowchart
• Write program Instructions using Assembly language of 8085

Problem Statement 1:
Load the accumulator A with the data byte 72H (the letter H indicates Hexadecimal number), and
save the data in register B.
Steps:
1. Load register A with the data byte 72H.
2. Copy the number from A to B
3. End of the program

Label Mnemonics Comments

MVI A, 72H; Load A with data 72H
MOV B, A; Copy A to B
HLT; End of the program

Problem Statement 2:
Write assembly language program to Load the contents of memory locations 2100 H and 2101 H
in B-register and C-register respectively. The content of memory locations 2100 H and 2101H are
16 H and 19 H respectively.
Steps:
1. Copy from memory 2100 H to the Accumulator register A
2. Copy the content of accumulator A to register B
3. Copy from memory 2101 H to the Accumulator register A
4. Copy the content of accumulator A to register C
5. End of the program

Label Mnemonics Comments

LDA 2100H; Load accumulator directly from memory location 2100 H
MOV B, A; Copy A to B
LDA 2101H; Load accumulator directly from memory location 2101 H
MOV C, A; Copy A to C
HLT; End of the program

Problem Statement 3:
Write an assembly language program to interchange (swap) the contents of two memory
locations 2100 H and 2101 H.
Steps: Method 1
1. Copy from memory 2100 H to the Accumulator register A
2. Copy the content of accumulator A to register B
3. Copy from memory 2101 H to the Accumulator register A
4. Data transfer (copy) from accumulator A to memory location 2100H
5. Copy the content of register B to accumulator A
6. Data transfer (copy) from accumulator A to memory location 2101H
7. End of the program

Label Mnemonics Comments

LDA 2100H; Load accumulator directly from memory location 2100 H
MOV B, A; Copy A to B

Page | 39
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
LDA 2101H; Load accumulator directly from memory location 2101 H
Data transfer (copy) from the microprocessor register
STA 2100H;
accumulator to memory location 2100H
MOV A, B; Moves the content of B-register to accumulator A
Data transfer (copy) from the microprocessor register
STA 2101;
accumulator to memory location 2101H
HLT; End of the program

Steps: Method 2
1. Set pointer HL register pair to 2100H memory location
2. Set pointer DE register pair to 2101H memory location
3. Get the contents of memory location 2100H pointed by HL register pair into B register
4. Get the contents of memory location 2101H pointed by DE register pair into A register
5. Store the contents of A register into memory location 2100H pointed by HL register pair.
6. Copy the contents of B register into accumulator A
7. Store the contents of A register into memory location 2101H pointed by DE register pair.
8. End of the program

Label Mnemonics Comments

LXI H 2100H; Initialize HL register pair as a pointer to memory location 2100H
LXI D 2101H; Initialize DE register pair as a pointer to memory location 2101H
MOV B, M; Get the contents of memory location 2100H into B register
LDAX D; Get the contents of memory location 2101H into A register
MOV M, A; Store the contents of A register into memory location 2100H.
MOV A, B; Copy the contents of B register into accumulator A
STAX D; Store the contents of A register into memory location 2101H
HLT; End of the program

Problem Statement 4:
Load the hexadecimal number 44H in register B, and display the number at the output port
labelled PORT1.
Note: No instruction available in 8085 to send the data from register B to the output port. In
instruction set, instruction OUT sends data from the accumulator to an output port.
Steps:
1. Load register B with 44H
2. Copy the number from B to A
3. Send the number to the output -Port 01H
4. End of the program
Label Mnemonics Comments
MVI B, 44H; Load B with data 44H
MOV A, B; Copy B to A
OUT PORT1; Display accumulator contents (44H) at Port1
HLT; End of the program
Problem Statement 5:
Find the l's complement of the 8-bit number stored at memory location4400H and store the
complemented number at memory location 4300H.
Steps:
1. Get number into accumulator from memory location 4400H
2. Complement number
3. Store complemented number into memory location 4300H
4. End of the program

Label Mnemonics Comments

LDA 4400B Load accumulator directly from memory location 4400 H
CMA Complement number, A Complement(A)
STA 4300H Copy from the register accumulator to memory location 4300H
Page | 40
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
HLT End of the program

Problem Statement 6:
Find the 2's complement of the 8-bit number stored at memory location4400H and store the
complemented number at memory location 4300H
Steps:
1. Get number into accumulator from memory location 4400H
2. Complement number
3. Add 01 to the 1’S complemented value
4. Store 2’s complemented number into memory location 4300H
5. End of the program
Label Mnemonics Comments
LDA 4400B Load accumulator directly from memory location 4400 H
CMA Complement number, A Complement(A)
ADI, 01 H Add 01 to accumulator value, A A+01H
STA 4300H Copy from the register accumulator to memory location 4300H
HLT End of the program

Problem Statement 7: 1’s complement of 16-bit number.

Find the l's complement of the 16-bit number stored at memory location 3000H and store the
complemented number at memory location 3002H.
Steps:
1. Load H-L pair with operand from 3000H.
2. Move the lower-order from reg. L to reg. A.
3. Complement accumulator.
4. Move the result from reg. A to reg. L.
5. Move the higher-order from reg. H to reg. A.
6. Complement accumulator
7. Move the result from reg. A to reg. H.
8. Store the result at address 3002H.
9. Lower-order of 3002H.
10. Higher-order of 3003H
11. End of the program
Label Mnemonics
LHLD 3000H
MOV A, L
CMA
MOV L, A
MOV A, H
CMA
MOV H, A
Problem Statement 8: 2’s SHLD 3002H complement of 16-bit number.
Find the 2's complement of the HLT 16-bit number stored at
memory location 3000H and store the complemented
number at memory location 3002H.
Steps:
1. Load H-L pair with operand from 3000H.
2. Move the lower-order from reg. L to reg. A.
3. Complement accumulator.
4. Move the result from reg. A to reg. L.
5. Move the higher-order from reg. H to reg. A.
6. Complement accumulator
7. Move the result from reg. A to reg. H.
8. Increment H-L pair to find 2’s complement.
9. Store the result at address 3002H.
10. Lower-order of 3002H.

Page | 41
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
11. Higher-order of 3003H
12. End of the program
Label Mnemonics
LHLD 3000H
MOV A, L
CMA
MOV L, A
MOV A, H
CMA
MOV H, A
INX H
SHLD 3002H
HLT
Problem Statement 9:
Write 8085 Assembly language program to add two 8-bit numbers (1st number available in
4000H and 2nd number available in 4001H) and store the result at locations 4050H and 4051H.
Steps:
1. Set pointer HL register pair to 4000H memory location
2. Get number into accumulator from memory location pointed by HL register pair
3. Increment HL pair by one
4. Get number into register B from memory location pointed by HL register pair
5. Initialize one register (C) with 00h for to store carry value after addition
6. Addition of accumulator register A and register B
7. If carry increment C register by 01H, If not don’t increment
8. Store SUM result, accumulator value into 4050H
9. Copy register C value to accumulator A
10. Store CARRY result accumulator value into 4051H
11. End of the program
Label Mnemonics Comments
LXI H, 4000H Initialize HL register pair as a pointer to memory location 4000H
Get the contents of memory location 4000H into Accumulator A
MOV A, M
register
INX H Increment content of HL register
MOV B, M Get the contents of memory location 4001H into B register
MVI C,00H Clear C register for to store carry value after addition operation
Addition register A and register B, and store results in accumulator A
ADD B
A A + B
JNC NEXT If no carry jump to NEXT
INR C If carry increment C register
NEXT: STA 4050H Store from the register accumulator to memory location 4050H
MOV A, C Copy register C to accumulator A
STA 4051H Store from the register accumulator to memory location 4051H
HLT End of the program

Problem Statement 10:

Write a program to perform the following functions, and verify the output.
a. Load the number 8BH in register D
b. Load the number 8BH in register C
c. Increment the content of register C by one
d. Add the contents of registers C and D and display the sum at the output PORT1.
Steps:
1. Load the 8BH in register D
2. Load the 6FH in register C
3. Increment C
4. Copy C to accumulator A
5. Add accumulator value and register D

Page | 42
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
6. Display accumulator content at Port1
7. End of the program

Label Mnemonics Comments

MVI D, 8B H; Load the 8BH in register D
MVI C, 6FH Load the 6FH in register C
INR C Increment C
MOV A, C Copy C to accumulator A
ADD D Add A and register D value, A A+D
OUT PORT1 Display accumulator content at Port1
HLT; End of the program

Problem Statement 11:

Write an assembly language program to add two 16 bits numbers by using:
a. 8-bit operation
b. 16-bit operation
Steps:
Addition of 16-bit numbers using 8-bit operation:
1. Load the lower part of the first number in the B register.
2. Load the lower part of the second number in A (accumulator).
3. Add both the numbers and store.
4. Load the higher part of the first number in the B register.
5. Load the higher part of the second number in A (accumulator).
6. Add both the numbers with carrying from the lower bytes (if any) and store them at
the next location.

Label Mnemonics Comments

LDA 2050 stores the value at 2050 in A (accumulator)
MOV B, A stores the value of A into the B register
LDA 2052 stores the value at 2052 in A
ADD B add the contents of B and A and store them in A
STA 3050 stores the result in memory location 3050
LDA 2051 stores the value at 2051 in A
MOV B, A stores the value of A into the B register
LDA 2053 stores the value at 2053 in A
adds the contents of B, A, and carry from the lower bit addition and
ADC B
store in A
STA 3051 stores the result in memory location 3051
HLT; End of the program

Addition of 16 bits numbers using 16-bit operation:

It is a very short method and less memory is also required as compared to 8-bit operations.
Steps:
1. Load both the lower and the higher bits of the first number at once.
2. Copy the first number to another registered pair.
3. Load both the lower and the higher bits of second number at once.
4. Add both the register pairs and store the result in a memory location.

Label Mnemonics Comments

loads the value at 2050 in L register and that in 2051 in the H register
LHLD 2050
(first number)
XCHG copies the content of the H to D register and L to E register
loads the value at 2052 in L register and that in 2053 in the H register
LHLD 2052
(second number)
DAD D adds the value of H with D and L with E and stores the result in H and L

Page | 43
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
SHLD 3050 stores the result at memory location 3050
HLT; End of the program

Problem Statement 12:

To perform the subtraction of two 8-bit numbers using 8085.
Steps:
1. Initialize Counter register with value 00
2. Start the program by loading the first data into Accumulator. Move the data to a register
(B register).
3. Get the second data and load into Accumulator.
4. Subtract the two register contents.
5. Check for carry, If carry is present take 2’s complement of Accumulator.
6. Store the value of borrow in memory location.
7. Store the difference value (present in Accumulator) to a memory
8. location and terminate the program
Label Mnemonics Comments
MVI C, 00H Initialize C to 00
LDA 4150 Load the value to Acc.
MOV B, A Move the content of Acc to B register.
LDA 4151 Load the Value to Acc
SUB B Subtract A-B
JNC LOOP Jump on no carry.
CMA Complement Accumulator contents.
INR A Increment value in Accumulator.
INR C Increment value in register C
LOOP: STA 4152 Store the value of A-reg to memory address.
MOV A, C Move contents of register C to Accumulator.
STA 4153 Store the value of Accumulator memory address.
HLT; Terminate the program.

Problem Statement 13:

Sixteen bytes of data are stored in memory locations at 2050 H to 205F H. Transfer the entire
block of data to new memory locations staring at 2070H.

Label Mnemonics Comments

LXI H, 2050 H Set up HL as a pointer for the source memory
LXI D, 2070 H Set up DE as a pointer for the destination memory
MVI B, 10H Set counter register B=10 H
NEXT: MOV A, M Get data from source memory
STAX D Store the data in destination memory
INX H Increment HL
INX D Increment DL
DCR B Decrement count register B
JNZ NEXT Go back to get next number, If counter B !=0
HLT; End of the program

Problem Statement 14:

Write an assembly language program to check the even parity or the odd parity of the
number stored in memory location 2010 H. Send 00 H or EE H at the output port 02 H if the
parity is odd or even respectively.

Label Mnemonics Comments

LXI H, 2010H Initializes the H-L register pair with the address of the location
MOV A, M Moves the number to accumulator
ORing of A with A will load the same number to accumulator.
ORA A
The parity flag will be affected with this operation
Page | 44
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
JPO ODD Jump to ODD if parity is odd
MVI A, EEH Load EE H to accumulator for even parity
OUT 02H EE is sent to output port 02H
JMP END Jump to END
ODD: MVI A,00H Load 00 H to accumulator for odd parity
OUT 02H 00 is sent to output port 02H
END: HLT; End of the program

Problem Statement 15:

To find the largest number in an array of data using 8085 instructions set.

ALGORITHM:
Steps:
1. Load the address of the first element of the array in HL pair
2. Move the count to B – reg
3. Increment the pointer
4. Get the first data in A – reg.
5. Decrement the count.
6. Increment the pointer
7. Compare the content of memory addressed by HL pair with that of A - reg.
8. If Carry = 0, go to step 10 or if Carry = 1 go to step 9
9. Move the content of memory addressed by HL to A – reg.
10. Decrement the count
11. Check for Zero of the count. If ZF = 0, go to step 6, or if ZF = 1 go to next step.
12. Store the largest data in memory.
13. Terminate the program.

Label Mnemonics Comments

LXI H,4200 Set pointer for array
MOV B, M Load the Count
INX H Increment pointer
MOV A, M Set 1st element as largest data
DCR B Decrements the count
LOOP: INX H Increment pointer for next data
CMP M If A- reg > M go to AHEAD
JNC AHEAD
MOV A, M Set the new value as largest
AHEAD: DCR B
JNZ LOOP Repeat comparisons till count = 0
STA 4300 Store the largest value at 4300
HLT; End of the program

Problem Statement 16:

To find the smallest number in an array of data using 8085 instructions set.
Steps:
1. Load the address of the first element of the array in HL pair
2. Move the count to B – reg.
3. Increment the pointer
4. Get the first data in A – reg.
5. Decrement the count.
6. Increment the pointer
7. Compare the content of memory addressed by HL pair with that of A -reg.
8. If carry = 1, go to step 10 or if Carry = 0 go to step 9
9. Move the content of memory addressed by HL to A – reg.
10. Decrement the count
11. Check for Zero of the count. If ZF = 0, go to step 6, or if ZF = 1 go to next step.

Page | 45
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts
12. Store the smallest data in memory.
13. Terminate the program.
Label Mnemonics
LXI H,4200
MOV B, M
INX H
MOV A, M
DCR B
LOOP: INX H
CMP M
JC AHEAD
MOV A, M
AHEAD: DCR B
JNZ LOOP
STA 4300
HLT;

Problem Statement 17:

Shift left 8-bit number by 1 bit.

Label Mnemonics Comments

LDA 3000H Load H-L pair with data from 3000H.
RAL Shift left accumulator.
STA 3001H Store the result at memory location 3001H
HLT; End of the program

Problem Statement 18:

Program to Shift Left 8-bit Number by 2 Bit

Label Mnemonics
LDA 3000 H
RAL
RAL
STA 3001 H
HLT;

Problem Statement 19:

Shift right 8-bit number by 1 bit.

Label Mnemonics
LDA 3000H
RAR
STA 3001H
HLT;

Problem Statement 20:

Shift right 8-bit number by 2 bit.

Page | 46
Microprocessor & Microcontroller Unit-2: Basic Programming Concepts

Label Mnemonics
LDA 3000H
RAR
RAR
STA 3001H
HLT;
Problem Statement 21:
Transfer block of N-bytes in reverse order from source to destination.

Label Mnemonics
MVI C, 05H
LXI H, 3000H
LXI D, 3504H
MOV A, M
STAX D
INX H
DCX D
DCR C
JNZ 2008H
HLT;

Problem Statement 22:

To perform the multiplication of two 8-bit numbers using 8085.

Steps:

1. Start the program by loading HL register pair with address of memory location.
2. Move the data to a register (B register).
3. Get the second data and load into Accumulator, Add the two register contents
4. Check for carry. Increment the value of carry.
5. Check whether repeated addition is over and store the value of product and carry in
memory location.
6. Terminate the program.
Label Mnemonics
MVI D,00
MVI A, 00H
LXI H,4150H
MOV B, M
INX H
MOV C, M
LOOP: ADD B
JNC NEXT
INR D
NEXT: DCR C
JNZ LOOP
STA 4152H
MOV A, D
STA 4153 H
HLT

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Microprocessor lectures Interrupts 11th lecture

Interrupts
Lecture objectives: at the end of this lecture the student will able to:
1- Define the interrupts.
2- Determine the overall structure of interrupts.
3- Explain the operation of control interrupt instructions.
11.1 Introduction
It is necessary executing one of service routines automatically to serve special task
for certain conditions. For example, each time when we type a character on a keyboard, a
keyboard services routine is called. It transfers the character you typed from keyboard
port into processor and then to a data buffer in memory.
The microprocessor have two ways to response any demand service requested by
any one of peripherals devices, these two ways are:
Polling way where the microprocessor's software simply checks each of the I/O
devices every so often. During this check, the processor tests to see if any device needs
servicing. The second way is the interrupt way which it is requested asynchronously by
the external devices using hardware. This request would inform the processor to complete
whatever instruction that is currently being executed and then fetch a new routine that
will service the requesting devices. Once this servicing is completed, the processor would
resume exactly where it left off.
11.2 Definition of interrupts:
It is a request introduced for microprocessor by user or peripheral devices by using
hardware or software to serve a task through executing certain service routine. It is
classified into two types:
A- Single levels interrupts: In single level interrupts there can be many interrupting
devices. But all interrupt requests are made via a single input pin of the microprocessor.
B- Multilevel Interrupts: In multilevel interrupts, the I/O devices are tied to the
individual interrupt pins of processor. Thus, the interrupts can be immediately identified
by the processor upon receiving an interrupt request from it. When the external
asynchronous input (interrupt input) is asserted ( a signal is sent to the interrupt input), a
special sequence in the control logic begins.
1. The processor completes its current instruction. No instruction is cut-off in the
middle of its execution.
2. The program counter's current contents are stored on the stack.
3. The PC is loaded with the address of an interrupt service routine.
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Microprocessor lectures Interrupts 11th lecture
4. program execution continuous with the instruction taken from the memory location
pointed by the new program counter contents.
5. The interrupt program (service routine) continuous to execute until a return
instruction is executed.

11.3 Maskable and Non-maskable interrupt

Masking is preventing the interrupt from disturbing the main program. When an
interrupt is masked the processor will not accept the interrupt signal. By setting or
resetting particular flip-flops in the processor, interrupt can be masked or unmasked,
respectively. Also, some of interrupt can be masked by using software where these
interrupts called maskable interrupt, while the interrupt that not masked by software is
called non-maskable interrupt. In 8085 microprocessor all interrupts except TRAP are
maskable interrupts.

11.4 Vectored and non vectored interrupt

In vectored interrupts, the processor automatically branches to the specific address
in response to an interrupt. But in non-vectored interrupts the interrupted device should
give the address of the interrupt service routine (ISR). All interrupts except restart
interrupt are vectored.

11.5 8085 microprocessor interrupts

11.5.1 Types of interrupts
The 8085 has multilevel interrupt system. It supports two types of interrupts:
A-Hardware: Some pins on the 8085 allow peripheral device to interrupt the
main program for I/O operations.
B-Software: In software interrupts, the cause of the interrupt is an execution of
the instruction. These are special instructions supported by microprocessor.

11.5.2 Overall Interrupt Structure

1. Hardware interrupt in 8085
The 8085 has five hardware interrupts:
a- TRAP b- RST 7.5 c- RST 6.5 d- RST 5.5 e- INTR
When any of these pins, except INTR, is active, the internal control circuit of
8085 produce a CALL to a predetermined memory location (vector location) and
these interrupts called (vectored interrupts). The INTR interrupt is not vectored
interrupt. It receives the address of the subroutine from external devices. The Fig.
11.1 shows the interrupt structure of 8085. The figure indicates that, the 8085 is
designed to respond to edge triggering, level triggering or both.

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Microprocessor lectures Interrupts 11th lecture
Priority input Pin Circuit of execution condition Memory location
Pin 6 (0024)
1
TRAP Mask
from pin7 D Q
CLR From SIM (003C)
2 Pin 7 Reset instructio
n
RST7.5 RST7.5 Interrupt
Recognized

3 Pin 8 from pin8

RST6.5
From SIM (0034)
instruction
4 Pin 9 from pin9
RST5.5
From SIM (002C)
instruction

Pin 10 EI ins. S Q (0038)

5 INTR
Reset
DI R (0030)
any Interrupt Get restart
Recognized Interrupt interrupt from (0028)
Enable external (0020)
hardware
(0018)
From pin 10 (INTR)
(0010)
(0008)
(0000)

Figure (11.1): 8085 microprocessor interrupt structure

a- TRAP interrupt: it is non masked and vectored interrupt with high priority can
execute by supplying edge and level triggered on pin 6 of microprocessor, this mean
that the TRAP must go high and remain high until it is acknowledged. This avoids
false triggering caused by noise and transient (see in Fig. (11-1)). When this interrupt
activated, the microprocessor loads PC with vectored address 0024 after completes
execution of current instruction and store the PC contents in stack memory.

b- RST 7.5 interrupt: it is maskable and vectored interrupt with second priority can
executed by satisfying the following conditions, execution EI(Enable Interrupt)
instruction in program ,not mask this interrupt, don’t execution DI(Disable Interrupt)
before execution this interrupt, and microprocessor don't execute any other interrupt,
before supplying positive edge triggered on pin 7 of microprocessor. When this
interrupt activated, the microprocessor loads PC with vectored address 003C after
completes execution of current instruction and store the PC contents in stack memory.
c- RST 6.5 interrupt: it is maskable and vectored interrupt with third priority can
execute by satisfying the following conditions, execution EI(Enable Interrupt)
instruction in program ,not mask this interrupt, don’t execution DI(Disable Interrupt)
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Microprocessor lectures Interrupts 11th lecture
before execution this interrupt, and microprocessor is don't execute any other
interrupt, before supplying level triggered signal on pin 8 of microprocessor. When
this interrupt activated, the microprocessor loads PC with vectored address 0034 after
completes execution of current instruction and store the PC contents in stack memory.
d- RST 5.5 interrupt: it is maskable and vectored interrupt with fourth priority can
execute by satisfying the following conditions, execution EI(Enable Interrupt)
instruction in program ,not mask this interrupt, don’t execution DI(Disable Interrupt)
before execution this interrupt, and microprocessor is don't execute any other
interrupt, before supplying level triggered signal on pin 9 of microprocessor. When
this interrupt activated, the microprocessor loads PC with vectored address 002C after
completes execution of current instruction and store the PC contents in stack memory.

e- INTR: It is a non vectored and maskable interrupt with lowest priority. The following
sequence of events occur when INTR signal goes high:
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. if INTR is high, then the processor completes its current instruction and sends
an active low interrupt acknowledge signal (INTA) if the interrupt is enable.
3. In response to the INTA signal, external logic circuit places an instruction
Opcode on the data bus.
4. On receiving the instruction, the processor transfer (PC) to the stack memory
and executes received instruction.
The Fig. 11.2 shows the diagram of external logic that gives the RST 5 instruction
Opcode on interrupt acknowledge.

2. Software interrupt in 8085

The 8085 has eight software interrupts from RST0 to RST7. The vector address
for these interrupts can be calculated as follow:
Interrupt number 8=vector address
28=16=(10H)
Table 11.1 shows the vectored address of RST interrupt.

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Microprocessor lectures Interrupts 11th lecture
Table 11.1: vectors addresses of RST interrupt
Restart interrupts Hexadecimal code Calling location of memory

RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038

The RST interrupts can be executed by two methods:

A- By software where can execute any one of RST interrupts by written interrupt as
instruction in program, where this instruction will execute in similar way to
CALL instruction execution.
B- By external hardware where to execution any one of RST interrupts must insert
the code to this RST interrupt to microprocessor by using external hardware and
some control signals as shown in Fig.11.2 (6.8 of the book):
The external hardware to RST 5 interrupt is shown in Fig. 11.2, where outputs of try
state gate is connect for the data bus. When user wants drive this interrupt, INTR pin
must enable with high level signal, then the microprocessor will supply low level
signal on INTA pin where this signal supplied to enable of try state gates and this
lead to load the states of gats output to the data bus then to microprocessor then
execute this interrupt.
+ 5V

1
DI7
1
DI6
1
DI5 0
DI4
1
EF to
DI3 data Bus
1
DI2
1
DI1
1
DI0

Enable

INTA from µP

Figure(11.2): logic circuit to execution the restart interrupt

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Microprocessor lectures Interrupts 11th lecture
By analysis of RST interrupt codes can getting that, three bits (A5, A4, A3) only
changed in all codes and other bits are constant as shown in Table 11.2. Therefore,
encoder and three tri states gates are used to driven the three changed bits in codes. The
priority can getting by encoder where this logic component has priority from high (eighth
input) to low (first input).
Table 11.2: RST interrupts codes representation
interrupt Code (H) A7 A6 A5 A4 A3 A2 A1 A0
RST0 C7 1 1 0 0 0 1 1 1
RST1 CF 1 1 0 0 1 1 1 1
RST2 D7 1 1 0 1 0 1 1 1
RST3 DF 1 1 0 1 1 1 1 1
RST4 E7 1 1 1 0 0 1 1 1
RST5 EF 1 1 1 0 1 1 1 1
RST6 F7 1 1 1 1 0 1 1 1
RST7 FF 1 1 1 1 1 1 1 1

circuit shown in Fig. 11.3 can used to execution any one from restart interrupt with
priority
+ 5V
RST 7 7
6.8 KΩ
RST 6 6 D7
8x3

D6
3x8Encoder

RST 5 5

to data Bus
A2 D5
Encoder

RST 4 4
D4
A1
RST 3 3 D3
A0 D2
RST 2 2
D1
RST 1 1 D0
RST 0 0
Enable

INTA from µP
Figure (11.3): Logic circuit to execution the RST interrupt with priority

11.5.3 Masking/Unmasking of Interrupt

Masking and unmasking operations of maskable interrupt using program control
are shown in this section. There are four instructions used for control of interrupts:
A. SIM B. RIM C. EI D. DI

A. SIM instruction: (Set Interrupt Mask) is one byte instruction used to

a- Set mask for RST 7.5, RST 6.5, RST 5.5 interrupts, where this ins. enables or
disable the interrupts according to the status of bits D3, D2, D1 and D0 as
shown in Fig. (11.4).
b- Reset RST7.5 flip-flop by set D4, see Fig. (11.4).
c- Implement serial I/O of data, see Fig. (11.4).
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Microprocessor lectures Interrupts 11th lecture
D7 D6 D5 D4 D3 D2 D1 D0
SOD SED xxx R7.5 MSE M7.5 M6.5 M5.5

ignored
RST7.5 Mask If 0 available if 1
RST6.5 Mask masked
RST5.5 Mask
Mask Set Enable If 0, bits(D2, D1, D0) is ignored. if 1, mask is set.

Reset RST7.5: if 1RST7.5 f.f. is reset

Serial Data Enable, if 1, bit D7 is O/P to serial output data latch
Serial output data, ignored if bit D6=0

Figure (11.4): operation of SIM instruction

B. Pending interrupts: When one interrupt is being served other interrupts may
occur resulting in a pending request. When more than one interrupt occur
simultaneously the interrupt with higher priority is served and interrupts with lower
priority remain pending. The 8085 has an instruction RIM used by the programmer
to know the current status of the pending maskable interrupts.
C. RIM instruction: (Read Interrupt Mask) is one byte instruction. RIM instruction
is transfer of interrupt control status to accumulator for knowing the interrupts
pending. RIM instruction has following functions:
a- Read interrupt mask status and transfer it to accumulator, see Fig.(11.5).
b- Identify the pending interrupts, see fig.(11.5).
c- Receiving data serially, see fig.(11.5).
D7 D6 D5 D4 D3 D2 D1 D0
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

RST7.5 Mask
If 0 available if 1
RST6.5 Mask masked
RST5.5 Mask
Interrupt Enable flag, If 1 then it enable
Pending interrupt, if 1 that means this interrupt is pending

Serial input data

Figure (11.5): Bit Diagram of RIM instruction

All interrupt except TRAP is disabled by resetting the Interrupt Enable F.F., where this
F.F. can be reset by one of three methods as below:
a- Execution DI (Disabled Interrupt) instruction see Fig.(11.1).
b- System reset see Fig.(11.1).
c- Recognition of any interrupt request see Fig.(11.1).

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Microprocessor lectures Interrupts 11th lecture
D. EI instruction: (Enable Interrupt) is used to enable all types of interrupts where
write in beginning of main program. See Fig. (11.5).

E. DI instruction: (Disable Interrupt) is used to disable all types of interrupt except

TRAP interrupt, This instruction used in beginning of service routine to stopping the
execution all interrupt except TRAP interrupt during this service routine. See
Fig.(11.5).

Example/ write ALP to display real time clock. Assume that a periodic signal is
interrupting RST 7.5 signal after every 0.5 seconds

Solution:

main program

MVI C, 00H
LXI H. 0000H
MVI D, 00H
MVI A, 0BH
EI
A1: JMP A1

ISR - Interrupt Service Routine

INR C
MOV A,C
CPI, 02H
JNZ A2 JNZ A2
MVI C,00H MVI H, 00H
MOV A,L MOV A,D
ADI 01H ADI 01H
DAA DAA
MOV L,A MOV D,A
CPI 3CH CPI 18H
JNZ A2 JNZ A2
MVI L,00H MVI D, 00H
MOV A,H A2: CALL DISPLAY
ADI 01H EI
DAA RET
MOV H,A
CPI 3CH

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Microprocessor Lectures Time Delay and Counter 6th lecture
Time Delay and Counter

Lecture objectives: at the end of this lecture the student will able to:
1- Define the time delay.
2- Study types of time delay.
3- Design all types of counters.

6.1 Time Delay:

6.1.1 Definition of time delay: it is number of instructions that written to keep a track for
certain interval. Time delay or (software delay) can be designed through executing group of
instruction number of times. Flow chart as an example of time delay is shown in Fig. (6-1)
below.

Loading delay
in register

Exe. some of
instructions

Decrement
delay register

No Is
Register
=0

Yes
End

Figure (6-1): Example of time delay.

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Microprocessor Lectures Time Delay and Counter 6th lecture
6.1.2 Types of time delay: there are three types of time delay as shown below:
A. Time Delay using NOP instruction: NOP instruction does nothing but take 4 T-states of
processor time to execute. So by executing NOP instruction between two instructions we can
get delay of 4 T-state where:

6.1

B. Time Delay Using Counter: Time delay can be created using counting process which means
executing number of instructions many times where the initial value of counter required to get
specific time delay can be determined. there are two types of delay using counter as below:
B.1 time delay using one register (8-bit counter): in this type of time delay the register
delay is one register loaded with 8-bit number in one loop as shown in program 6.1below :

Program 6.1

MVI C,37 (delay reg.)

LOOP1 MVI A, 33
RAR (some ins.)
DCR C (decrement delay reg.)
JNZ LOOP1 (condition)
HLT

B. 2 time delay using register pair: in this type of time delay the register delay is register
pair loaded with 16-bit number in one loop as shown in program 6.2 below:

Program 6.2

LXI B,234B (delay reg.)

LOOP1 MVI A, 33
RAR (some ins.)
DCX B (decrement delay reg.)
MOV A,C
ORA B
JNZ LOOP1 (condition)
HLT

C. time delay using loop with in loop: this time delay is used two loop one internal and the
other loop is external, these two loops can be designed by using one register or register pair
as shown in program 6.3 below:

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Microprocessor Lectures Time Delay and Counter 6th lecture
Program 6.3

MVI B,37 (delay reg. external loop)

LOOP 2 MVID,FF (delay reg. internal loop)
LOOP1 MVI A, 33
RAR (some ins.)
DCR D (decrement delay reg. int. loop)
JNZ LOOP1 (condition)
DCR B (decrement delay reg. ext. loop)
JNZ LOOP2 (condition)
HLT
6.1.3 Calculation of time delay: the interval of any program can be calculated by using the equation
below:

6.2

Where Tt is total time interval. To is the out loop instructions time. Ti is in loop instructions time.

6.3

6.4

Where N10 is the number that loaded in delay register in decimal. t is the processor time clock.

Example 6.1: Calculate the time delay to programs (6.4, 6.5 and 6.6) below, (let the microprocessor
frequency is 1MHz)
Solution:
First t=1/F=1/1*106 =1µS

Program 6.4

MVI C,37 (delay reg.) 7Tstate

LOOP1 MVI A, 33 7Tstate
RAR (some ins.) 4Tstate
DCR C (decr. delay reg.) 4Tstate
JNZ LOOP1 (condition) 10/7Tstate
HLT 6Tstate

Tt =To + Ti
To = [7Tstate (MVI C,37) + 7Tstate (JNZ loop1) + 6Tstate (HLT)]*t
=20 Tstate*1 µS =20 µS
Ti=[7Tstate (MVI A,33) + 4Tstate (RAR) + 4Tstate (DCR C) + 10Tstate (JNZ loop1)]*t*55
=[25Tstate]*t*55
=[25 µS]*55=1375 µS
Tt=20 µS+1375 µS=1395 µS =1.395 mS

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Microprocessor Lectures Time Delay and Counter 6th lecture
Program 6.6
Program 6.5
MVI B,37 (delay reg. external loop) 7Tstate
LXI B,234B (delay reg.) 10Tstate LOOP 2 MVI D,FF (delay reg. internal loop) 7Tstate
LOOP1 MVI A, 33 7Tstate LOOP1 MVI A, 33 7Tstate
RAR (some ins.) 6Tstate RAR (some ins.) 6Tstate
DCX B (decr. delay reg.) 4Tstate DCR D (decr. delay reg. int. loop) 4Tstate
MOV A,C 4Tstate JNZ LOOP1 10/7Tstate
ORA B 4Tstate DCR B (decr. delay reg. ext. loop) 4Tstate
JNZ LOOP1 (condition) 10/7Tstate JNZ LOOP2 (condition) 10/7Tstate
HLT 6Tstate HLT 6Tstate

For program 6.5

To=[10Tstate (LXI B,234B) + 7Tstate (JNZ loop) + 6Tstate (HLT)] = 23 µS

Ti=[7Tstate (MVI A,33) +4Tstate (RAR) + 4Tstate (DCX B) + 4Tstate (MOV A,C) +4Tstate (ORA B) +
10Tstate (JNZ loop1)]*9035 = (33 Tstate)*9035=(33 µS)*9035=298155 µS
Tt=23 µS+298155 µS=298178 µS=298.178ms

For program 6.6

To=[7Tstate (MVI B,37) + 7Tstate (JNZ loop2) + 6Tstate (HLT)]

=20 Tstate=20 µS
Ti=[7Tstate (MVI D,FF) + {7Tstate (MVI A,33) + 4Tstate (RAR) + 4Tstate (DCR D)} * 255 + {10Tstate (JNZ Comment [DS1]: Internal loop

loop1) * 254}+ 7Tstate (JNZ loop1) +4Tstate (DCR B)] * 55 +10Tstate (JNZ loop2)*54 Comment [DS2]: External loop

=[7Tstate (MVI D,FF) + {3825 Tstate }+{2450 Tstate}+7Tstate (JNZ loop1) +4Tstate (DCR B)]*55 + 540
= [18 + 3825 + 2450] * 55 + 540
= 346,115 + 540
=346500 Tstate=346,655 µS
Tt=To + Ti =20 µS+346,655 µS=346,675 µS=346.68ms

6.2 Counters:

6.2.1 Definition of counter: A counter program is an program written to design a counter (all
types of counter such as up, down, Johnson, serial, parallel, decimal, etc.) with flexibility in
controlling of time interval between counting states.
Example 6.2: write ALP (Assembly Language Program) to design down counter mod (255) and
display the counting states on out port with time delay (1ms) for each counting
state. Let the processor operate with frequency 2MHz.
Solution: Fig. (6.2) show the flow chat of the counter program

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Microprocessor Lectures Time Delay and Counter 6th lecture
Initialize
counter

Counting state
display

Time delay
1ms

Update count

No

Is count
complete

Yes
End

Figure (6.2): flow chart of Ex.6.2

MVI A,FF 7Tstate

A1: OUT 02 10Tstate
MVI D, XX 7Tstate
A2: DCR D 4Tstate
Now, must loading register D with certain number
JNZ A2(delay) 10/7Tstate
to get the time delay 1ms, this number calculated as below:
DCR A 4Tstate
First Tstate = 1/F = 1/2*106 = 0.5µS
JNZ A1(Count display)
10/7Tstate
Tt=To + Ti
HLT 6Tstate
Where Tt=1ms
To=[10Tstate (OUT 02) + 7Tstate (MVI DXX) + 7Tstate (JNZ A2)+ 4Tstate (DCR A) +10Tstate (JNZ A1)]*
0.5µS
=[38 Tstate] * 0.5µS=19 µS
Ti=[(4Tstate (DCR D) * N10)+ (10Tstate (JNZ A2) * (N10-1))]*0.5 µS
=(2* N10)+5* (N10-1)
=(7 N10-5) µS
By return to initial equation
Tt=To + Ti
1000 µS=19 µS+ (7 N10-5) µS
1000 µS=19 µS+7 N10 µS-5 µS

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Microprocessor Lectures Time Delay and Counter 6th lecture
1000 µS=14 µS+7 N10 µS
N10=(1000-14)/7=140.857=141
Therefore must loading equivalent to 141 in hexadecimal which equal (8D) in register D.

other solution:
Tt = [10T (OUT 02) + 7T (MVI D, XX) + 4T*N10 (DCR D) + 10T*N10-1 (JNZ A2) + 7T (JNZ A2) +
4T (DCR A) + 10T (JNZ A1) ] * 0.5S
1000S =[ 38T + 4T*N10 + 10T* (N10-1)] * 0.5S
1000S = 19S + 2*N10 S+ 5*N10 S- 5S
1000S = 14S + 7*N10 S
N10 = (1000 - 14)/7 = 140.857=141
Therefore must loading equivalent to 141 in hexadecimal which equal (8D) in register D.

Home work:
1- Calculate the required time to execute the JPE instruction if the condition is satisfying. Let the
processor operate with 4 MHz frequency.

2- Write ALP to make the microprocessor working as up/down counter mod (32) with time delay
2ms between each two counting states. (let the frequency is 2 MHz)

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