UNIT - I Introduction to 80386 Syllabus Brief History of Intel Processors, 80386 DX Features and Architecture, Programmers Model, Operating modes, Addressing modes and data types. Contents 1.1. Brief History of intel Processors 1.2 80386DX Features May-10,13, 1.3 80386DX Architecture May-2000,06,11,12,13, ce cte eee ee sees, DOG-05,11,13, Nov.-12, 1.4 Programmers Mode! : Dec.-03,14,19, - . May-10,13,19, 1.5 Operating Modes 1.6 Addressing Modes... . - . Dec.-14,17, May-18, 1.7. Data Types se aE 1 -. May-14,19, © scanned with OKEN ScannerMicroprocessor 1-2 Introduction to 80386 Brief History of Intel Processors * The world’s first microprocessor, the Intel 4004, was a 4-bit microprocessor. {A bit is a binary digit with a value zero or one and 4-bit microprocessor means the microprocessor can process 4-bit word in one cycle. It has 12-bit address lines to access 4096 4-bit wide memory locations. The 4004 microprocessor has only 45 instructions. * The Intel released the 4040, as updated version of 4004 with enhancement in speed, and without any improvement in word length and memory ze. * In 1972 announced the 8008, 8-bit and faster version of 4004. This version came up with expanded memory size upto 16 kbytes and additional instructions to make total of 48 instructions. (A byte is 8-bit binary number and a K is 1024) * In 1974 Intel came out with 8080 was a considerable improvement over its predecessors. © The 8080 had a much larger instruction set and since NMOS technology used, it is much faster than 8008, © In 1977, Intel introduced updated version of 8080-8085. © The Table 1.1.1 shows the improvement of 8080 over 8008 and 8085 over 8080. Parameter Processor 8008 8080 8085 Speed Requires 20 us for Requires 2 ys for Requires 1.3 ys for execution one execution one execution of one instruction instruction i (10 times faster) Memory size 16 kbytes 64 kbytes 64 Kbytes (4 times more) ‘TTL compatibility Not directly compatible | Compatible ‘Compatible Interfacing More costly and Easier and less More easier and less complex expensive ‘expensive as it contains internal clock generator and internal system controller Table 1.1.1 * The next generation was 8086 processor, a 16-bit processor, with advanced architecture and instruction set. At the same time Intel introduced processor 8088. The 8088 is an 8-bit version of the 8086 which has fewer data lines but retains all of the processing features of the 8086. The programs that run on 8088 will also run, without modification on the 8086, The 8086/88 pair were the first members of TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-3 Introduction to 80386 iAPX 86, family of microprocessors. This pair has 20 address lines to address upto 1 Mbyte of memory (1 Mbyte = 1024 kbyte) and also supported with 4 or 6 byte instruction queue to implement pipelining feature. (Feature of fetching the next instruction while the current instruction is executing is called pipelining). This pair belongs to CISC (complex instruction set computers) because of the number and complexity of instructions, © In 1983 the next version was announced, the 80186/88 very similar to 8086/8088 pair. The 80186/88 included many useful peripheral 1/O functions as an integral part of the microprocessor. The improved instruction set of 80186/88 supports these peripheral 1/O functions. Although the 80186 provided increased functionality, it maintained compatibility with the 8086, ensuring that it could execute 8086 programs. * After 80186/88, Intel has announced 80286, which is 16-bit processor like 8086. The 80286 was the first family member designed specifically for use as a CPU in a multi-user microcomputer. It contains many advanced modes of operations not supported by 8086. The 80286 boosted a new mode of operation-protected mode. Due to this the entire concept of memory segmentation was changed. The virtual memory management circuitry were included in the 80286, which allow an 80286 to operate in either real address mode or protected virtual address mode. * In 1986, the next advanced processor, the 80386DX, was introduced. As expected, 80386DX is faster than any of its predecessors, with a minimum operating frequency of 16 MHz. It is an 32-bit processor with 32-bit register set, address bus and data bus. Internal Chip Introduction Data bus Address bus Number of cache instructions executed memory per second - 4004 171 4 8 50000 - 8008 1972 8 8 50000 Ba 8080 1974 8 16, 500000, - 8085 1977 8 16 7630 i 8086/88 1978 16/8 20 2.5 million = 80186188 1982 16/8 2 TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-4 Introduction to 80386 3 80286 1983 16 4 4.0 million - 80386DX 1986 2 2 25 million 803865X 1988 16 4 25 million 8K 80486Dx 1989 2 2 50 million (with coprocessor) 8K ——_-804865X 1989 2 2 50 million (Without coprocessor) Table 1.1.2 80X86 family tree During 1988, an “economy version” of the 80386, called the 80386SX was introduced by Intel. This processor had the same outside connections as the 80286, but inside it was a 386-processor supporting the 386’s expanded instruction set and various operating modes. The Table 1.1.2 shows the 80X86 family tree. Early in 1989, Intel introduced the 80486DX, the more highly integrated microprocessor with built-in coprocessor. Meanwhile, Intel has also developed step-down version 80486SX (without coprocessor and lower clock speed). The Pentium, introduced in 1993, was similar to the 80386 and 80486 microprocessors. It contained larger internal cache and data bus width is extended to 64-bit. The Table 1.1.3 shows the comparison between various pentium processors. Processor Released Databus Memory L1cache 12 Bus year width size Data-Code cache transfer speed Pentium 60 MHz 1993 Oo 4 GByte 8K-8K - 60 - 66 MHz 66 MHz 120 MHz 133 MHz 233 MHz Pentium Pro 1995 64 64GByte 8K-8K 256K 60 - 66 MHz 150-166 MHz Pentium 11350 MHz 1997 a 64GByte 16K-16K 512K 100 MHz 400 MHz 450 MHz Pentium II Xeon 1998 64 64GByte 16K-16K 512Kor 100 MHz, 1M TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-5 Introduction to 80386 Pentium Ill 1 GHz 1998 64 64.GByte 16K-16K 512K 100 MHz Slot 1 version Pentium Ill 1 GHz 1998 6 64.GByte 16K-16K 256K 100 MHz Flip chip version Pentium Ill 1 GHz 1998 6 64.GByte 16K-16K 256K 66 MHz Celeron Pentium IV 1.3GHz 2000 6 64.GByte 16K-16K 256K 100 MHz 1.4 GHz 1.5 GHz Table 1.1.3 Comparison between pentium processors Pentium IV uses the RAMBUS memory technology in place of SDRAM technology used in other pentium processors. 1. Explain in brief history of Intel Processors. Give comparison between 8008, 8080 and 8085 Processors 3. Give comparison between various Intel Processors. 80386DX Features The 80386 processor is available in two different versions, the 80386DX and the 80386SX. The 80386DX has 32-bit address bus and a 32-bit data bus. However, 80386SX has only 24-bit address bus and a 16-bit data bus. 1. The 80386DX is a 32-bit processor. The 32-bit ALU allows to process 32-bit data. 2. It has 32-bit address bus. So it can access up to 4 Gbyte (2 ) physical memory or 64 terabyte (2"° ) of virtual memory. 3. The 80386DX runs with speed up to 20 MHz instructions per second, 4. The pipelined architecture of the 80386DX, allows simultaneous instruction fetching, decoding, execution and memory management. Instruction pipelining, a high bus bandwidth and on-chip address translation significantly shorten the average instruction execution time of 80386DX. These architectural design features enable the 80386DX to execute 3 to 4 million instructions per second. 5. It allows programmers to switch between different operating systems such as PC-DOS and UNIX. 6. It can operate on 17 different data types. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-6 Introduction to 80386 7.1t has built-in virtual memory management circuitry and protection circuitry required to operate an 80386DX in these modes. 8. The 80386DX can operate in real mode, protected mode or a variation of protected mode called virtual 8086 mode. In real mode it functions basically as a fast 8086 or real mode 80286. The protection mode operation provides paging, virtual addressing, multilevel protection and multitasking and debugging capabilities. 9. The 80386DX microprocessor is compatible with their earlier 8086, 8088, 80186, 80188 and 80286 chips. Virtually anything that runs under these microprocessors will also run under the 80386. 1. List the features of 80386DX. 80386DX Architecture [QW The Internal Architecture of 80386DX is divided into 3 sections : * Central Processing Unit (CPU) = Execution unit -2000,06,11,12,13, Dec.-05,11,13, Nov.-12 = Instruction decode unit * Memory Management Unit (MMU) = Segmentation unit = Paging unit * Bus Control Unit The central processing unit is further divided into execution unit and instruction unit. ‘The Memory management unit consists of a segmentation unit and a paging unit. These units operate in parallel. Fetching, decoding, execution, memory management and bus s for several instructions are performed simultaneously. This parallel operation is called pipelined instructions processing. Execution Unit access The execution unit reads the instruction from the instruction queue and executes the instructions. It consists of three subunits : Control unit, data unit and protection test unit. 1. Control unit: It contains microcode and special hardware. The microcode and special hardware allows 80386DX to reduce time required for execution of multiply and divide instructions. It also speeds the effective address calculation. 2. Data unit : The data unit contains the ALU, eight 32-bit general purpose registers and a 64-bit barrel shifter. The barrel shifter is used for multiple bit shifts in one clock. TECHNICAL PUBLICATIONS” - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-7 Introduction to 80386 Thus it increases the speed of all shift and rotate operations. The multiply/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time. ‘The entire data unit is responsible for data operations requested by the control unit. 3. Protection test unit: The protection test unit checks for segmentation violations under the control of the microcode. Instruction Decode Unit The instruction decode unit takes instruction bytes from the code prefetch queue and translates them into microcode. The decoded instructions are then stored in the instruction queue. They are passed to the control section for deriving the necessary control signals. Segmentation Unit The segmentation unit translates logical addresses into linear addresses at the request of the execution unit. The segmentation unit compares the effective address for the length limit specified in the segment descriptor. The segment unit adds the segment base and the effective address to generate linear address. Before calculation of linear address it also checks for access rights. It provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program. Paging Unit When the 80386DX paging mechanism is enabled, the paging unit translates linear addresses generated by the segmentation unit or the code prefetch unit into physical addresses. If paging unit is not enabled, the physical address is the same as the linear address, and no translation is necessary. The paging unit gives physical address to the Bus Interface Unit to perform memory and 1/O accesses. It organizes the physical memory in terms of pages of 4 kbytes size each. The control and attribute PLA checks the privileges at the page level. Each of the pages maintains the paging information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in the memory segments. Bus Control Unit The Bus Control Unit is the 80386DX’s communication with the outside world. It provides a full 32-bit bi-directional data bus and 32-bit address bus. The bus control unit is responsible for following operations : 1. It accepts internal requests for code fetch and for data transfers from the code fetch unit and from the execution unit. It then prioritize the request with the help of prioritizer and generates signals to perform bus cycles. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-8 Introduction to 80386 z eBs wy B Ele? ols Ie per » aldisle = w= chiske gee < {eee Pia Be sskB 5 g & 8 é 3 3 3 a ie =< se 8H 8 3 S 55 ze 3| 222 [88 5 8| 238 |2 =lz 5) Ses las ge Ee : a: 2g = z 3 £ 5 =—| 5 ]3s- 183 i Pg eee |3 E 5 28 |82° 38 4 - ——_I= 2 az * a g Fig. 1.3.1 80386DX architecture 2. It sends address, data and control signals to communicate with memory and I/O devices. The address driver drives the bus enable and address signal Ay - As) and the transreceiver interface the internal data bus with the system bus. TECHNICAL PUBLICATIONS” - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-9 Introduction to 80386 3. It controls the interface to external bus maste1 s and coprocessors. 4. It also provides the address relocation facility. Instruction Prefetch Unit The instruction prefetch unit fetches sequentially the instruction byte stream from the memory. It uses bus control unit to fetch instruction bytes when the bus control unit is not performing bus cycles to execute an instruction. These prefetched instruction bytes are stored in the 16-byte code queue. A 16-byte code queue holds these instructions until the decoder needs them. The prefetcher always fetches instructions in the order in which th at a time, not caring whether it’s bringing in complete instructions or pieces of two instructions with each access. When jump or call instructions are executed, the contents of the prefetched and decode queues are cleared out. In this case, prefetcher again starts filling up its queue. y appear in the memory. In fact, the prefetcher simply reads code one double word Instruction Predecode Unit The instruction predecode unit takes instruction bytes from the instruction prefetch queue and translates them into microcode. The decoded instructions are then stored in the instruction queue Review Questions 1. Draw the functional block diagram of 80386DX and explain the main functional units. Ese 2. Explain the function of central processing unit of 80386DX. 3. Explain the function of memory management unit of 80386DX. 4. What is the necessity of prefetch queue ? SUES en ee) 5. What is BIU in 80386 processor ? What are the functions of BIU ? Ses 6. How does queue work in JUMP and CALL instruction execution ? 7. Draw the functional block diagram of 80386DX and explain the main functional units. Programmers Model * The programming model of the 80386DX considered to be program visible because its registers are used during application programming and are specified by the instructions. Other registers, are considered to be program invisible because they TECHNICAL PUBLICATIONS” An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-10 Introduction to 80386 are not addressable directly during 31 ‘B03860X applications programming, but may EP } be used indirectly during system cs programming. Some of them are Ds used to control and operate the ss protected memory system. fs © Fig. 1.4.1 illustrates the programming cs model of the 80386DX. “ es 7 EAX AHA] ax © It consists of EBX BH BL BX ECX cH | cL_] cx = General purpose / Multi-purpose EDX DHCTODL] ox registers at 15 o — | ESP sP = Special purpose registers EBP BP Es! si = EFLAGS register eb! D = Segment registers Pr 0 eracs (I) Fig. 1.4.1 80386 register set General Purpose / Multipurpose Registers © EAX (accumulator) : EAX is referenced as a 32-bit register (EAX), as a 16-bit register (AX), or as either of two 8-bit registers (AH and AL). Note that if an 8 - or 16-bit register is addressed, only that portion of the 32-bit register changes without affecting the remaining bits. The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions. For these instructions, the accumulator has a special purpose, but is generally considered to be a multipurpose register. The EAX register may also hold the offset address of a location in the memory system. * EBX (base index) : EBX is addressable as EBX, BX, BH, or BL. The BX register sometimes holds the offset address of a location in the memory system. The EBX also can address memory data * ECX (count) : ECX is a general-purpose register that also holds the count for various instructions. The ECX register also can hold the offset address of memory data. Instructions that use a count are the repeated string instructions (REP/REPE/REPNE); and shift, rotate, and LOOP/LOOPD instructions. The shift and rotate instructions use CL as the count, the repeated string instructions use CX, and the LOOP/LOOPD instructions use either CX or ECX. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-11 Introduction to 80386 * EDX (data) : EDX is a general-purpose register that also holds a part of the result from a multiplication or part of the dividend before a division. This register can also address memory data. * EBP (base pointer) : EBP points to a memory location for memory data transfers. This register is addressed as either BP or EBP. * EDI (destination index) : EDI often addresses string destination data for the string instructions. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register. * ESI (source index) : ESI is used as either ESI or SI. The source index register often addresses source string data for the string instructions. Like EDI, ESI also functions as a general-purpose register. As a 16-bit register, it is addressed as SI; as a 32-bit register, it is addressed as ESI. Special - Purpose Registers * The special-purpose registers include EIP, ESP, EFLAGS; and the segment registers CS, DS, ES, SS, FS, and GS. * EIP (instruction pointer) : EIP addresses the next instruction in a section of memory defined as a code segment. This register is IP (16 bits) when the microprocessor operates in the real mode and EIP (32 bits) when the 80386 operate in the protected mode. The instruction pointer, which points to the next instruction in a program, is used by the microprocessor to find the next sequential instruction in a program located within the code segment. The instruction pointer can be modified with a jump or a call instruction. * ESP (stack pointer) : ESP addresses an area of memory called the stack. The stack memory stores data through this pointer. This register is referred to as SP if used as a 16-hit register and ESP if referred to as a 32-bit register. EFLAGS A Flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU. The EFLAG register contains thirteen flags. Fig 1.4.2 shows the bit pattern of the EFLAG register. These flags can be categorized in three different groups. 1. Status flags : These flags reflect the state of a particular program. 2. Control flags : These flags directly affect the operation of few instructions. 3. System flags : These flags reflect the current status of the machine and which are usually used by operating system than by application programs. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-12 Introduction to 80386 3 15 7 0 Licro) «7m (16) RF PF (2) (14) NT AF (4) (12,13) PL 2F 6) (11 oF seq) (10) DF ae) IF (9) [Bf reserves [J newnags Fig, 1.4.2 Bit pattern of EFLAG register Status Flags : The status flags are : CF (Carry Flag), PF (Parity Flag ), AF (Auxiliary carry Flag), ZF (Zero Flag), SF (Sign Flag), and OF (Overflow Flag). These flags indicate some condition produced by the execution of arithmetic or logical instructions. These flags provide necessary information for arithmetic and logical control decisions. CF (Carry flag) : This bit is set by arithmetic instructions that generate either a carry or a borrow. This bit can also be set, cleared, or inverted with the STC, CLC or CMC instructions, respectively. Carry flag is also used in shift and rotate instructions to contain the bit shifted or rotated out of the register. PF (Parity flag) : The parity bit is set by most instructions if the least significant 8-bit of the result contain even number of one’s. AF (Auxiliary carry flag) : This bit is set when there is a carry or borrow after a nibble addition or subtraction, respectively. The programmer can’t access this bit directly, but this bit is internally used for BCD arithmetic. 2F (Zero flag) : Zero flag is set to 1, if the result of an operation is zero. SF (Sign flag) : The signed numbers are represented by combination of sign and magnitude. The Most Significant Bit (MSB) indicates sign of the number. For negative number MSB is 1. Sign flag is set to 1, if the result of an operation is negative (MSB = 1). OF (Overflow flag) : In 2's complemented arithmetic, most significant bit is used to represent sign and a remaining bits are used to represent magnitude of a Moonlude number (see Fig. 1.4.3). This flag is set if the result of a ., we , , ee a |. Fig. 1.4.3 Sign and magnitude signed operation is too large to fit in the number of bits representation available (7-bits for 8-bit number) to represent it s For example, if you add the 8-bit signed number 01110110 (+118 decimal) and the 8-bit signed number 00110110 (+54 decimal). The result will be 10101100 (+172 decimal), TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-13 Introduction to 80386 which is correct binary result. But in this case, it is too large to fit in the 7-bits allowed for the magnitude in an 8-bit signed number. The overflow flag will be set after this operation to indicate that the result of the addition has overflowed into the sign bit. Control Flags DF ( Direction flag) : ‘The direction flag controls the direction of string operations. When the D flag is cleared these operations process strings from low memory up towards high memory. This means that offset pointers (usually SI and DI) are incremented by 1 after each operation in the string instructions when D flag is cleared. If the D flag is set, then SI and DI are decremented by 1 after each operation to process strings from high to low memory. System Flags VM (Virtual Memory) flag : This flag indicates operating mode of 80386. When VM flag is set, 80386 switches from protected mode to virtual 8086 mode. R (Resume) flag/Restart flag : This flag, when set allows selective masking of some exceptions at the time of debugging. NT (Nested flag): This flag is set when one system task invokes another task. (ie. nested task). IOPL (VO Privilege level) : The two bits in the IOPL are used by the processor and the operating system to determine your application's access to I/O facilities. It holds privilege level, from 0 to 3, at which the current code is running, in order to execute any 1/O related instruction. IF (Interrupt Flag): When interrupt flag is set, the 80386 recognizes and handles external hardware interrupts on its INTR pin. If the interrupt flag is cleared, 80386 ignores any inputs on this pin. The IF flag is set and cleared with the STI and CLI instructions, respectively. TF (Trap Flag): Trap flag allows user to single-step through programs. When an 80386 detects that this flag is set, it executes one instruction and then automatically generates an internal exception 1. After servicing the exception, the processor executes the next instruction and repeats the process. This single stepping continues until program code resets this flag for debugging programs single step facility is used TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-14 Introduction to 80386 Segment Registers © The 80386 has a 1 Mbyte address gi 45 - space in real mode. But all of this —————————— memory cannot be active at one ei cose asm time. ‘The 80386 supports six DS Data segment simultaneously accessible memory SS Stack segment blocks called segments. ES Extra segment © A segment — represents an 5 Ets sopmrent independently accessible block of ean sega memory consisting of + 64K Fig. 1.4.4 Segment registers consecutive byte-wide __ storage locations. These segments are addressed by 16-bit registers : CS, DS, ES, $5, FS and GS. These registers are called segment registers, generate memory addresses when combined with other registers in the microprocessor. A segment register functions differently in the real mode when compared to the protected mode operation of the 80386DX. * Fig. 1.4.4 shows the segment registers. CS (Code Segment) and CS Register * The code segment is a section of memory that holds the code (programs and procedures) used by the 80386DX. * The CS (Code Segment) register defines the starting address of the section of memory holding currently active code segment. * In real mode operation, it defines the start of a 64K-byte section of memory; in protected mode, it selects a descriptor that describes the starting address and length of a section of memory holding code. * The code segment is limited to 4G bytes in the 80386 when it operates in the protected mode. DS (Data Segment) and DS Register * The data segment is a section of memory that contains most data used by a program. Data are accessed in the data segment by an offset address or the contents of other registers that hold the offset address. * The DS (Data Segment) register is used to hold the address of currently active data segment. * The data segment is limited to 4G bytes in the 80386 when it operates in the protected mode. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-15 Introduction to 80386 ES (Extra Segment) and ES Register © The extra segment is an additional data segment that is used by some of the string instructions to hold destination data. © The ES (Extra Segment) is used as general data segment register. This register holds the base addresses of memory segment. SS (Stack Segment) and SS Register ‘* The stack segment defines the area of memory used for the stack. The stack entry point is determined by the stack segment and stack pointer registers. The BP register also addresses data within the stack segment. FS and GS © The FS and GS segments are supplemental segment registers. * The FS, and GS registers are used as general data segment registers. These registers hold the base addresses of two different memory segments. These segments are referred as to Extra Segments. Segments and Offsets « A combination of a segment address and an offset address, access a memory location in the real mode. All real mode memory addresses must consist of a segment address plus an offset address. This is illustrated in Fig. 1.4.5. 19 430 Base | 16-bit segment selector 0000] + 19 1615 o Offset | 0000 | 16-biteffective address Fig, 1.4.5 Memory addressing in real mode + The segment address, located within one of the segment registers, defines the beginning address of any 64K-byte memory segment. The offset address selects any location within the 64K byte memory segment. Segments in the real mode always have a length of 64K bytes. * Table 1.4.1 and 1.4.2 show the default 16-bit and 32-bit segment and offset address combinations, respectively. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-16 Introduction to 80386 Segment Offset Special Purpose cs IP Instruction address ss ‘SP or BP Stack address. Ds BX, DI, SI, an S-bit number Data address or a 16-bit number ES DI for string instructions String destination address. ult 16-bit segment and offset address combinations Segme Offset Special Purpose nt cs EIP Instruction address. ss ESP or EBP Stack address ps EBX, EDI, FSI, EAX, Data address ECK, EDX an 8-bit number or a 32-bit number ES. EDI for string, String destination instructions ‘address, FS No default General address cs No default General address Table 1.4.2 Default 32-bit segment and offset address combinations 1. Draw and explain the programmer's model of 80386DX. List the different registers in 80386. 3. Describe 80386 flag register with significance of each and every bit in detail. Sena SCE Explain the function of segments and segment registers of 80386. Describe following different flags defined in 80386 processor a) DF b) VM c) NT d) RF . With the help of diagram explain 80386 applications register set. [RODS CMEC TECHNICAL PUBLICATIONS” - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-17 Introduction to 80386 Operating Modes * The operating mode of the 80386 also determines the features that are accessible. ‘The 80386 has three operating modes : = Real-Address Mode = Protected Mode. = Virtual 8086 (V86) Mode © Real-address mode (often called just "real mode") is the mode of the processor immediately after RESET. In real mode the 80386 appears to programmers as a fast 8086 with some new instructions. Most applications of the 80386 will use real mode for initialization only. * Protected mode is the natural 32-bit environment of the 80386 processor. In this mode all instructions and features are available. * Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the processor can switch repeatedly and rapidly between V86 mode and protected mode. The CPU enters V86 mode from protected mode to execute an 8086 program, then leaves V86 mode and enters protected mode to continue executing a native 80386 program. 1. Write a short note on operating modes of 80386DX processor. Addressing Modes Sane As a part of programming flexibility, processor provides different ways to access these operands from different locations. The different ways by which processor can access data are referred to as addressing modes. The 80386DX provides a total of 11 addressing modes for instructions to specify operands. These addressing modes can be categorized in three groups : © Register operand addressing * Immediate operand addressing * Memory operand addressing. Immediate Operands Certain instructions use data from the instruction itself as operands. Such an operand is called an immediate operand. The operand may be 32-, 16-, or 8-bits long. TECHNICAL PUBLICATIONS” - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-18 Introduction to 80386 Example : For 8-bit operand : MOV AL, 20H : This instruction copies 20H in the lower byte of EAX register. For 16-bit operand: MOV AX, 1020 H : This instruction copies 1020H in the lower word of EAX register For 32-bit operand: MOV EAX, 10B89C20H : This instruction copies 10B89C20H in the EAX register. Register Operands Operands may be located in one of the 32-bit general registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP), in one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general registers (AH, BH, CH, DH, AL, BL, CL, or DL). Examples : For 8-bit operand : MOV AL, DL : This instruction copies the lower byte contents of the EDX register to the lower byte of the EAX register. Both source and destination operands are the internal registers of 80386DX. For 16-bit operand: MOV AX, DX : This instruction copies the lower word contents of EDX register to the lower word of the EAX register. For 32-bit operand: MOV EAX, EDX : This instruction copies the contents of EDX register to the EAX register. Memory Operands The remaining 9 addressing modes provide a mechanism for specifying the physical address of an operand. In 80386DX, physical address is calculated before any read or write operation. The physical address consists of two components : The segment base address and an effective address. The effective address can be specified in a variety of ways. One way is to encode the effective address of the operand directly in the instruction. This represents direct addressing mode. The effective address can be generated with the combinations of four addressing elements : Base, Index, Scale factor and Displacement. where, Base : The contents of any general purpose register. Index : The contents of any general purpose register. The index registers are used to access the elements of an array, or a string of characters. TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-19 Introduction to 80386 Scale : The index register’s value can be multiplied by a scale factor either 1, 2, 4 or 8. Scaled index mode is especially useful for accessing arrays or structures. Displacement : An 8, 16 or 32-bit immediate value following the instruction. The general formula for generating effective address is given as follows : EA = Base + (Index x Scaling factor) + Displacement The Fig. 1.6.1 shows the registers that can be used to hold the values of segment base, base, and index. Physical Address = Segment Base Address + Effective Address (PA) = SBA + EA PA = SBA: {Base + (Index x Scale factor ) + Displacement } cs ax 1 BX ss cx nel 2 8,16 or Ds x cx 32-bit pa-< ES. + |< ox} x + } () Packed and unpacked BCD (aietiog 194847 +845 4 43 12 +10 ating point (Supported by 80387) Fig. 1.7.1 Data types supported by 80386DX TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 1-24 Introduction to 80386 * Fig. 1.7.1 illustrates the data types supported by the Intel386 DX and the Intel387 DX numeric coprocessor. 1. Explain the data types supported by 80386. List fundamental data types of 80386. gaa TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerUNIT - I Applications Instruction Set Syllabus Applications Instruction Set : Data Movement Instructions, Binary Arithmetic Instructions, Decimal Arithmetic Instructions, Logical Instructions, Control Transfer Instructions, String and Character Transfer Instructions, Instructions for Block Structured Language, Flag Control Instructions, Coprocessor Interface Instructions, Segment Register Instructions, Miscellaneous Instructions. Contents 2.1 Introduction 2.2. Instruction Set of 80386 Dec.-13,14,15,17,18,19, . May-14,15,16,17,19, (2-1) © scanned with OKEN ScannerMicroprocessor 2-2 Applications Instruction Set EZ introduction Instruction set of 80386 can be categorized as data movement instructions, binary arithmetic instructions, decimal arithmetic instructions, logical instructions, control transfer instructions, string and character transfer instructions, instructions for block structured language, flag control instructions, coprocessor interface instructions, segment register instructions, miscellaneous instructions. Data Movement Instructions These instructions provide convenient methods for moving bytes, words, or doublewords of data between memory and the registers of the base architecture. They fall into the following classes: 1. General-purpose data movement instructions : MOV and XCHG 2. 3. Stack manipulation instructions : PUSH, POP, PUSHA and POPA ‘Type-conversion instructions : CWD, CDQ, CBW, CWDE, MOVSX and MOVZX Binary Arithmetic Instructions The arithmetic instructions of the 80386 processor simplify the manipulation of numeric data that is encoded in binary. Operations include the standard add, subtract, multiply, and divide as well as increment, decrement, compare, and change sign. Both signed and unsigned binary integers are supported. ‘The binary arithmetic instructions may also be used as one step in the process of performing arithmetic on decimal integers. 1 2. 3. 4. 5. Addition instructions : ADD, ADC, INC, AAA, and DAA. Subtraction instructions SUB, SBB, DEC, AAS, DAS, CMP, and NEG Comparison and Sign Change Instruction: CMP and NEG Multiplication Instructions : MUL and IMUL. Division Instructions : DIV and IDIV Decimal Arithmetic Instructions The decimal arithmetic instructions are classified as : A, 2. Packed BCD Adjustment Instructions : DAA and DAS Unpacked BCD Adjustment Instructions : AAA, AAS, AAM and AAD TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN ScannerMicroprocessor 2-3 Applications Instruction Set Logical Instructions The group of logical instructions includes: 1, The Boolean operation instructions : AND, OR, XOR and NOT 2. Bit test and modify instructions : BIT, BTS, BTR and BTC 3. Bit scan instructions : BSF and BSR 4. Shift instructions : SAL, SHL, SAR, SHR, SHLD and SHRD 5. Rotate instructions : ROL, ROR, RCL and RCR 6. Byte set on condition : SETcc 7. Test Instruction : TEST Control Transfer Instructions The 80386 provides both conditional and unconditional control transfer instructions to direct the flow of execution. Conditional control transfers depend on the results of operations that affect the flag register. Unconditional control transfers are always executed. 1, Jump Instruction : JMP 2. Call Instruction : CALL 3. Return and Return-From-Interrupt Instruction : RET and IRET 4. Unsigned Conditional Transfers ; JA/JNBE, JAE/JNB, JB/JNAE, JBE/JNA, JC, JE/JZ, JNE/JNZ,JNP/JPO and JP/JPE 5. Signed Conditional Transfers : JG/JNLE, JGE/JNL, JL/JNGE, JLE/JNG, JNO, JO and JS 6. Loop Instructions : LOOP, LOOPE and LOOPNE 7. Executing a Loop or Repeat Zero Times : JCXZ 8, Software-Generated Interrupts : INT n, INTO, and BOUND String and Character Translation Instructions 1. A set of primitive string operations : MOVS, CMPS, SCAS, LODS and STOS 2. Control flag instructions: CLD and STD 3. Repeat prefixes : REP, REPE/REPZ, REPNE/REPNZ TECHNICAL PUBLICATIONS® - An up thrust for knowledge © scanned with OKEN Scanner