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Basic Computer Architecture

Prof. Smruti Ranjan Sarangi
IIT Delhi

Chapter 7: A Primer On Digital Logic

1
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 Outline

Transistors and Gates

Combinational Logic

 Sequential Logic

 SRAM/ DRAM Cells

3
Disclaimer: This chapter is only to
get a high level overview ...
 We assume some background in logic gates,
transistors, combinational and sequential
logic
 The aim of this chapter is to only provide a
high level overview
 For a deeper understanding consult any of
the classic textbooks on digital logic
Atoms and Molecules of Circuits

The Transistor

• It is just a switch.
• It is either switched on (current can
flow), or switched off (no current flow)
 How is a Transistor Made?
 It is made of Silicon
 Silicon is a semi-conductor.
 We can change its properties:
 Add a little bit of impurities → doping
 Dope it with Group III elements
 Boron, Aluminum and Gallium
 It is called a p-type semiconductor
 Or, dope it with Group V elements
 Phosphorus or Arsenic
 It is called a n-type semiconductor
 Silicon Lattice

Si Si Si

Si Si Si

Si Si Si

 This is a typical silicon lattice. Each Si atom is

connected to 4 other atoms.
 P-Type Doping

Si Si Si

Si B Si

Si Si Si

 If there is a Boron atom in the lattice. It will create bonds

with the rest of the atoms.
 There will be one less electron (hole)
 Holes can flow. They are associated with +ve charge. (see
the animation)
 N-Type Doping

Si Si Si

Si P Si

Si Si Si

 If there is a Phosphorus atom in the lattice. It will create

bonds with the rest of the atoms.
 There will be one more electron (electron)
 Electrons can flow. They are associated with -ve charge.
(see the animation)
 Let us make a transistor.
gate
source drain

channel
n-type n-type

p-type

 NMOS transistor → Put two n-type wells in a p-type substrate

 Now, assume that we apply +ve charge to the gate.
 Channel → This forms because electrons move towards the
positive charge. Forms a conductive layer that can conduct
current.
 NMOS Transistor
drain

gate
Apply a +ve voltage Current flows from the drain to source

Apply a 0 or -ve No current flow.

voltage

source
 We thus have a switch
 Apply a +ve voltage at the gate → make the transistor
conduct
 Apply a –ve or 0 voltage at the gate → transistor is off (no
current flow across it)
 PMOS Transistor
gate
source drain

channel
p-type p-type

n-type

 PMOS transistor → Put two p-type wells in an n-type

substrate
 Now, assume we apply 0 or -ve charge to the gate.
 Channel → This forms because holes move towards the
gate. This channel can conduct current.
 PMOS Transistor

source

gate Current flows from the source to the

Apply a 0 or -ve
voltage drain

Apply a +ve voltage No current flow.

drain
 We thus have a switch
 Apply a +ve voltage at the gate → transistor is off (no current
flow across it)
 Apply a –ve or 0 voltage at the gate →transistor conducts
 Let us make an inverter

A A

Vcc If A = 1 (+ve voltage)

T1 is on, T2 is off
T2 Thus, the output will be connected to
A A the ground, and it will be a logical 0

T1 If A = 0 (0 voltage)
T1 is off, T2 is on
Thus, the output will be connected to
the supply (Vcc), and it will be a logical 1
 NOR Gate
Vcc

B T4 A
A NOR B
B
A T3

Out
T1 T2
A B

A B T1 T2 T3 T4 Out
0 0 off off on on 1
1 0 on off off on 0
0 1 off on on off 0
1 1 on on off off 0
 NAND Gate
Vcc

A T3 T4 B

Out
B T2 A
B A NAND B
A T1

A B T1 T2 T3 T4 Out
0 0 off off on on 1
1 0 on off off on 1
0 1 off on on off 1
1 1 on on off off 0
 Summary of Logic Gates

A
A
A OR B
B A AND B B
A
A
A NOR B
B A NAND B B

A A
 Outline

Transistors and Gates

Combinational Logic

 Sequential Logic

 SRAM/ DRAM Cells

18
 Multiplexer
Given n inputs, choose one based
on the select bits. log(n) select bits
Example: Given 8 inputs, 3 select
bits, choose 1 among them

Output

n inputs MUX

19
 Design of a Multiplexer
A
B
X 00 Select bits: A and B
A
B
X 01
inputs A Output
X 10 B
A
X 11 B

 Generate all combinations of select bits

 𝐴ഥ . 𝐵, ത 𝐴.ҧ 𝐵, 𝐴. 𝐵
ഥ 𝐴. 𝐵,
 Only one of the combinations is true.
 For this combination the output of the AND gate is equal to the input (XAB),
rest of the outputs of the AND gates are 0
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 The output is equal to (XAB OR 0 OR 0 OR 0) = XAB
 Demultiplexer
Given 1 input, make it appear on
one of n outputs. The output is
decided by log(n) select bits
A Outputs
B
A
B
Input
A
B
A
B

21
 Working of a Demultiplexer
 Same logic
 Generate all combinations of A, B, 𝐴,ҧ and 𝐵ത
 Only one combination is TRUE
 The output of that AND gate is equal to: X AND 1 = X
Here, X is the input
 The outputs of the rest of the AND gates are 0
 Decoder
Set one of the n outputs to 1. The
output is decided by log(n) select
bits
A Outputs
B
A
B
A
B
A
B
Operation is similar to a demultiplexer 23
 Encoder
Given n inputs, assume only one of them is 1. Find its id.
For example: if the 6th input out of 8 inputs is 1. The output
should be 110

log(n) bits
Encoder
n inputs
 Example of a 3-bit Encoder
Output bits

Input bit Bit2 Bit1 Bit0

b0 0 0 0
b1 0 0 1
b2 0 1 0
b3 0 1 1
b4 1 0 0
b5 1 0 1
b6 1 1 0
b7 1 1 1

Here, the + symbol Bit2 = b4 + b5 + b6 + b7

stands for OR
Bit1 = b2 + b3 + b6 + b7

Bit0 = b1 + b3 + b5 + b7
Example of a 3-bit Encoder - II

b4
b5
Bit2
b6
b7

b2
b3 Bit1 Outputs
8-bit input b6
b7

b1 Bit0
b3
b5
b7
 Outline

Transistors and Gates

Combinational Logic

 Sequential Logic

 SRAM/ DRAM Cells

27
 SR Latch
Use a cross-coupled pair of NAND gates to store a stable value.

S → Set
S R → Reset
Q

Q
R

 S = 1, R = 0, Q = 1 Set the Understand

 S = 0, R = 1, Q = 0 values these points

 S = 0, R = 0, <maintain old values>

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 Clocked SR Latch
S
Q

Clock

Q
R

 Let us add a clock signal.

 When the clock is 1, outputs of the NAND gates are 𝑆ҧ and
𝑅ത respectively (same as the classic SR latch)
 Clock is 0 → they are 1 and 1 respectively (maintain old
values)
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 D Flip Flop
I1
D
Q
Clk

I2 Q

D = 1, Q = 1
D = 0, Q = 0

• Let us not have two inputs: S and R

• Let us consider a single input, D, and modify the clocked SR latched
appropriately
ഥ , I2 = D → Essentially, this sets Q to D
• If Clk = 1, I1 = 𝐷
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• If Clk = 0, I1 = I2 = 1 (maintain old values)
 Master Slave D Flip Flop
Connect two D flip flops
one after the other
master D' slave
D
Q
Clk Clk

1
D’ = D Note the importance
Clk 0 of the negative edge
Q = D’

• When the Clk = 1, the value of D gets transferred to

the slave (D’)
• Then when the Clk transitions to 0 (1 → 0)
• The value of D’ gets transferred to the output (Q) 31
 Master Slave J-K Flip Flop
master slave
T1
J I1
Q
Clk Clk

Q
K I2 𝑇1

master is active slave is active

J K I1 I2 T1 Clk J K T1 Clk Q
0 0 1 1 Q 1 0 0 old Q 0 old Q
1 0 Q 1 1 1 1 0 1 0 1
0 1 1 𝑄ത 0 1 0 1 0 0 0
1 1 Q 𝑄ത 𝑄ത 1 1 1 𝑜𝑙𝑑 𝑄 0 𝑜𝑙𝑑 𝑄
Maintain, Set, Reset, or Transfer the input to the
Toggle output
 Outline

Transistors and Gates

Combinational Logic

 Sequential Logic

 SRAM/ DRAM Cells

33
 SRAM Cell

• We want to reduce the number of transistors required

to store a single bit
• Instead of using a cross-coupled pair of NAND gates,
use a cross coupled pair of inverters

A pair of inverters
stores 1 bit

• Problems: Need extra circuitry to read and write values

 SRAM Cell

Word line (WL)

vdd

W1 W2

cross coupled
BL pair of inverters BL
(Bit line)

35
 SRAM Cell (Alternative
Representation) 6 Transistor
SRAM cell

V 𝑉ത
BL W1 W2
BL

word line
 The word line signal turns W1 and W2 on
Not connected to
 The inverter pair gets connected to the bit lines ground or Vcc
 Read mode:
ത
 The values of BL and 𝐵𝐿 are set to V and 𝑉respectively. The bit lines are kept floating.
 Write mode:
 The values of the terminals, V and 𝑉,ത are set to the values of BL and 𝐵𝐿 respectively.
The bit lines are charged by strong driver circuits.
 Array of SRAM Cells
To save space, we arrange SRAM cells
into rows and columns
Use a decoder to set BL BL
WL
only one word line to
1 (based on the D SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell

address) E Setting a word

C WL line enables all
Address O SRAM SRAM SRAM SRAM the cells in a row
D cell cell cell cell

E Only one row can

R be enabled at a
WL time
SRAM SRAM SRAM SRAM
cell cell cell cell

Choose a subset
Column mux/demux of columns to
Address Write
driver
Write
driver read or write
Data in Data in
Sense amplifier Sense amplifier

Data out
37
Operating an Array of SRAM Cells
 Write mode:
 Use a driver circuit to set the values of BL and 𝐵𝐿
 Simultaneously enable the word line
 The values in BL and 𝐵𝐿 will get transferred to the SRAM cell
(thus a write)
 Read:
 Disconnect the bit lines from supply and ground using
transistors (floating)
 Enable the word line
 The values of (BL and 𝐵𝐿) will get set to logical 1 and 0
respectively if the value stored in the SRAM cell is 1, or vice-
versa
 Pre-charging
 Issues with the simple design:
 The bit lines are very long, and are connected to a lot of SRAM cells
 They thus have a lot of resistance and capacitance
 Driving them to a logical 0 or 1 (typically 1V) will take a long time
 This will make the SRAM slow
 Can we do something better
 Observe:
 Let us pre-charge both the bitlines to 0.5 V (assuming logical 1 is 1V)
using strong pre-charge driver circuits
 Let us then enable the word line
 One of the bit lines will move towards 0V and the other towards 1V
 IDEA: Monitor the difference in voltages between the bit lines
 Pre-charging - II
 Should we wait for one of the bit lines to reach 0V
and the other to reach 1V
 Answer: NO
 If we know the outcome: why wait
 Monitor the difference: Δ = 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐵𝐿 −
𝑉𝑜𝑙𝑡𝑎𝑔𝑒(𝐵𝐿)
 There can be some amount of electrical noise that might cause a
little bit of fluctuation in the voltages of the bit line. Define a noise
threshold, T.
 The moment: | Δ| > T, declare the result
 If Δ is +ve, infer a logical 1
 Else, infer a logical 0

A very fast method of reading

 Array of SRAM Cells
BL BL
WL
Pre-charge
D SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell drivers
E
C WL
Address O SRAM SRAM SRAM SRAM

D cell cell cell cell

E
R
WL
SRAM SRAM SRAM SRAM
cell cell cell cell

Column mux/demux
Address Write Write Write
driver driver
drivers
Data in Data in
Sense amplifier Sense amplifier Sense amplifiers to
monitor the difference in
Data out
voltages 41
DRAM Cell (even smaller)

Word line (WL)

Capacitor is charged
→ logical 1
No charge across the
capacitor → 0

BL
(Bit line)

42
 Array of DRAM Cells
 Features
 There is a single bit line
 For writing → Enable the word line and charge the bit
line with a driver circuit
 For reading → pre charge the bit line to 0.5 V, enable the
word line, and monitor the difference of the voltage w.r.t
0.5 V
 If the difference in voltages exceeds a threshold
 Infer a logical 0 or 1 depending on the sign of the difference
 DRAM Refresh
 Problems
 After every read, we lose some charge from the capacitor
 Periodically, charge from the capacitor leaks out
 Hence, it is necessary to:
 Periodically read each and every DRAM cell
 And write the same data back
 Example: The charge across the capacitor reduces from 1 V to
0.7 V over time.
 Let’s say, this is enough to infer a logical 1.
 Read the value (logical 1 in this case)
 And write the same value again. We thus restore the charge on the
capacitor to 1 V.

This is known as DRAM refresh

 Array of DRAM Cells
BL
WL
DRAM DRAM DRAM DRAM
cell cell cell cell

Decoder
WL
Address
DRAM DRAM DRAM DRAM
cell cell cell cell

WL
DRAM DRAM DRAM DRAM
cell cell cell cell

Address
Column mux/demux
Refresh Refresh
Note the refresh
Write Write
driver driver circuits
Data in Data in
Sense amplifier Sense Amplifier The rest is the same
Data out as the SRAM array
45
Instead of enabling cells by their CAM Cell
address, can we find them by Content Addressable
their contents? Memory → CAM

A SRAM cell Case: A == V

BL BL
A ത one of
In the pair (A, 𝑉),
Word line (WL) the values has to be 0 →
vdd
Either T3 or T4 is off

Similarly, in the pair (𝐴,ҧ V),

one of the values has to
W1 W2
be 0 → Either T1 or T2 is
off
Thus, match is floating
V V

match
T1 T3

T2 T4

Content matching 46
circuit
Instead of enabling cells by their CAM Cell
address, can we find them by Content Addressable
their contents? Memory → CAM

A SRAM cell Case: A ≠ V

A
BL BL ത or (𝐴,ҧ V) is
Either (A, 𝑉),
Word line (WL)
vdd
equal to (1,1).

This connects the match

line to the ground (sets its
W1 W2 voltage to 0 volts)

If there is a mismatch, the

V V match line is driven to 0 V

match
T1 T3

T2 T4

Content matching 47
circuit
 Array of CAM Cells
A1 A1 A2 A2 An An
CAM mode
BL BL BL BL BL BL Pre-charge all the
WL
CAM CAM CAM
match lines to 1
cell cell cell
Decoder match

Address
WL If there is a content
CAM
cell
CAM
cell
CAM
cell
match, one of the
match lines will be 1

The OR gate will thus

WL
compute 1 (else 0 if none
CAM CAM CAM
cell cell cell of the rows match)
Address
Column mux/demux
Write Write
driver driver

Data in Data in
Sense amplifier Sense amplifier
match
Data out
48
 Array of CAM Cells - II
A1 A1 A2 A2 An An
CAM mode BL BL BL
BL BL BL
WL
CAM CAM CAM
cell cell cell
Decoder match

WL
Address
CAM CAM CAM
cell cell cell

Use an encoder to find

WL
the id of the row that
CAM CAM CAM
cell cell cell matched.
Address
Column mux/demux
Write Write

Encoder
driver driver

Data in Data in
Sense amplifier Sense amplifier
Id of the row
Data out that matched
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THE END

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