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UNIT-4

Programmable Interrupt Controller (8259)

8259 microprocessor is defined as Programmable Interrupt Controller

(PIC) microprocessor. There are 5 hardware interrupts and 2 hardware
interrupts in 8085 and 8086 respectively. But by connecting 8259, we can
increase the interrupt handling capability. 8259 combines the multi interrupt
input sources into a single interrupt output. Interfacing of single PIC provides 8
interrupts inputs from IR0-IR7.
For example, Interfacing of 8085 and 8259 increases the interrupt handling
capability of 8085 microprocessor from 5 to 8 interrupt levels.
Features of 8259 PIC microprocessor –
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered
interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by
cascading further 8259 PIC.
5. Clock cycle is not required.
Pin Diagram of 8259 –

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Pin Diagram Description of 8259

Symbol Pin No. Type Name and function of Pin

Vcc 28 Input(I) Supply : +5V supply

GND 14 i Ground

Chip Select : A low on this pin enables RD*

and WR* communication between the CPU
CS* 1 I
and the 8259A. INTA functions are
independent of CS.

Write: A low on this pin when CS is low

WR* 2 I enables the 8259A to accept command words
from the CPU.

Read :When the CS pin is low, a low signal on

RD* 3 I this pin allows the 8259A to transfer status
information onto the data bus for the CPU.

Bidirectional data bus : Information related

D7-D0 4-11 I/O to control, status, and interrupt vectors flows
through this bus.

Cascade lines: The CAS lines from a private

CAS0- 8259A bus to control a multiple 8259A
12,13,15 I/O
CAS2 structure. These pins are outputs for a master
8259A and input for a slave 8259A.

Slave program/Enable buffer: This is a

SP*/EN* 16 I/O
dual function pin. When in the buffered mode

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Symbol Pin No. Type Name and function of Pin

it can be used as an output to control

buffer transceivers(EN).When not in the
buffered mode it is used as an input to
designate a master(SP =1) or Slave(SP = 0).

Interrupt: This pin goes high whenever a

valid interrupt request is asserted. It is used
INT 17 O
to interrupt the CPU, thus it is connected to
the CPU’s interrupt pin.

Interrupt Request : Asynchronous inputs.

An interrupt request is executed raising an IR
input(low to high), and holding it high until it
IR0-IR7 18-25 I
is acknowledged(Edge triggered mode), or
just by a high level on an IR input(Level
Triggered Mode).

Interrupt Acknowledge: This pin is used to

enable 8259A interrupt-vector data onto the
INTA* 26 I
data bus by a sequence of interrupt
acknowledge pulses issued by the CPU.

AO Address line: This pin acts in conjunction

with the CS*, WR* and RD* pins. It is used by
the 8259 to decipher various command words
A0 27 I
the CPU writes and status the CPU weighs to
read. It’s usually linked to the CPU’s A0
address line (A1 for 8086, 8088).

Block Diagram of 8259 PIC microprocessor –

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The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write
Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3
registers- ISR, IRR, IMR.

1. Data bus buffer – This Block is used as a mediator between 8259 and
8085/8086 microprocessor by acting as a buffer. It takes the control
word from the 8085 microprocessor and transfer it to the control logic
of 8259 microprocessor. After selection of Interrupt by 8259
microprocessor (based on priority of the interrupt), it transfer the
opcode of the selected Interrupt and address of the Interrupt service
sub routine to the other connected microprocessor. The data bus buffer
consists of 8 bits represented as D0-D7 in the block diagram. Thus,
shows that a maximum of 8 bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is
low (as this pin is active low). This block is responsible for the flow of
data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.

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3. Control logic – It is the center of the PIC and controls the functioning
of every block. It has pin INTR which is connected with other
microprocessor for taking interrupt request and pin INT for giving the
output. If 8259 is enabled, and the other microprocessor Interrupt flag
is high then this causes the value of the output INT pin high and in this
way 8259 responds to the request made by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level
which are requesting for Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level which
are currently being executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which
have to be masked by storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the
priority of interrupts and according to the priority of the interrupts,
interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we
can further cascade more number of pins by using cascade buffer. So,
during increment of interrupt capability, CSA lines are used to control
multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify
whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used
as an output to enable data bus

The events occur as follows in an MCS-80/85 system:

1. One or more of the INTERRUPT REQUEST lines (IR7 – 0) are raised

high, setting the corresponding IRR bit(s).

2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.

3. The CPU acknowledges the INT and responds with an INTA pulse.

4. Upon receiving an INTA from the CPU group, the highest priority ISR bit
is set, and the corresponding IRR bit is reset. The 8259A will also release a
CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 – 0

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pins.6.

5 . This CALL instruction will initiate two more INTA pulses to be sent to the
8259A from the CPU group.

6 . These two INTA pulses allow the 8259A to release its

preprogrammed subroutine address onto the Data Bus. The lower 8-bit
address is released at the first INTA pulse and the higher 8-bit address is
released at the second INTA pulse.

7. This completes the 3-byte CALL instruction released by the 8259A. In

the AEOI mode the ISR bit is reset at the end of the third INTA pulse.
Otherwise, the ISR bit remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.