A Project Report on

64-bit FPGA Based ALU Employing Reversible Logic

Submitted to
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY,
ANANTHAPURAMU
In Partial fulfilment of the requirements for the award of degree of
BACHELOR OF TECHNOLOGY
In
Electronics & Communication Engineering
By

S. BHAVYA SREE (22KB5A0411)

C. RUCHITHA (21KB1A0427)

Y. ADI SHANKAR REDDY (21KB1A04G9)

S. VENKATA PRAVEEN KUMAR (21KB1A04E3)

Under the esteemed Guidance of

Dr. G. HARINATHA REDDY. M.E., Ph.D.

Professor, Head of the Department of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

N.B.K.R. INSTITUTE OF SCIENCE AND TECHNOLOGY

(Approved by AICTE: Accredited by NBA: Affiliated to JNTUA, Ananthapuramu)
An ISO 9001-2000 Certified Institution
Vidyanagar -524413, Tirupati District, Andhra Pradesh, India.
 Website: www.nbkrist.org Ph: 08624-228257

Email: [email protected] Fax: 08624-228257

N.B.K.R. INSTITUTE OF SCIENCE & TECHNOLOGY

(AUTONOMOUS)
(Approved by AICTE: Accredited by NBA: Affiliated to JNTUA, Ananthapuramu)
An ISO 9001-2000 Certified Institution Vidyanagar -524413, Tirupati District, Andhra
Pradesh, India.
------------------------------------------------------------------------------------------------------------
BONAFIDE CERTIFICATE
This is to certify that the project work entitled “64-bit FPGA Based ALU Employing
Reversible Logic” is a Bonafide work done by S. BHAVYA SREE (22KB5A0411), C.
RUCHITHA (21KB1A0427), Y. ADI SHANKAR REDDY (21KB1A04G9), S. VENKATA
PRAVEEN KUMAR (21KB1A04E3) in the department of Electronics & Communication
Engineering, N.B.K.R. Institute of Science and Technology, Vidyanagar and is submitted
to JNTUA, Ananthapuramu in the partial fulfilment for the award of B.Tech degree in
Electronics & Communication Engineering. This work has been carried out under my
supervision.

Dr. G. HARINATHA REDDY M.E., Ph.D.

Professor & Head of the Department,
Department of ECE,
N.B.K.R.I.S.T, Vidyanagar.

Submitted for the Viva-Voice Examination held on_________________

Internal Examiner External Examiner

 ACKNOWLEDGEMENT
The satisfaction that accompanies the successful completion of a project would be
incomplete without the people who made it possible. Their constant guidance and
encouragement crowned our efforts with success.

We would like to express our profound sense of gratitude to our project guide, Dr. G.
HARINATHA REDDY, Professor & Head of the Department, Electronics and
Communication Engineering, N.B.K.R. Institute of Science and Technology (Affiliated to
JNTUA, Ananthapuramu), Vidyanagar, for his masterful guidance and the constant
encouragement throughout the project and for providing exceptional facilities for successful
completion of our project work. Our sincere appreciation for his suggestion and unmatched
services without which this work would have been an unfulfilled dream.

We are grateful to Dr. V. VIJAYA KUMAR REDDY, Director, N.B.K.R. Institute of

Science and Technology for allowing us to use all the facilities in the college.

We convey our special thanks to SRI. N. RAM KUMAR REDDY, Correspondent,

N.B.K.R Institute of Science and Technology, for providing excellent infrastructure in our
campus for the completion of the project.

We would like to convey our heartful thanks to staff members, Lab technicians, and our
friends, who extended their cooperation in making this project a successful one. We would like
to thank one and all who have helped us, directly and indirectly, to complete this project
successfully.

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 ABSTRACT
The Arithmetic Logic Unit (ALU) is a fundamental component of processors, performing
essential arithmetic and logical operations in digital system design. This study introduces the
design and implementation of a 64-bit ALU using reversible gates, developed in Verilog HDL,
and synthesized on the Xilinx ISE 14.7 platform with an FPGA kit. Reversible gates, capable
of producing distinct output vectors for each input vector and vice versa, address the issue of
data erosion and associated power loss in circuits with irreversible gates.

This design achieves enhanced speed and reduced power consumption compared to traditional
logic gate-based ALU architectures. A library of reversible gates, including AND, OR, NAND,
NOR, and XOR, is developed using Verilog HDL. These gates facilitate the design of arithmetic
and combinational logic components, such as full adder, full subtractor, decoder (2:4), decoder
(3:8), multiplier, and comparator.

The proposed reversible logic-based ALU demonstrates its effectiveness through synthesis and
simulation using Xilinx VIVADO, highlighting its advantages in low power VLSI design and
its superiority over conventional ALU architectures.

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 TABLE OF CONTENTS

S.NO. CONTENTS PAGE NO.

1. i
ACKNOWLEDGEMENT

2. ABSTRACT
ii
3. TABLE OF CONTENTS
iii-iv
4. TABLE OF FIGURES
v-vi
5. LIST OF TABLES vii

6. LIST OF ABBREVIATIONS viii

1-4
CHAPTER-1 : INTRODUCTION

1.1 Introduction 2-4

CHAPTER-2 : LITERATURE REVIEW 5-8

2.1 Literature Review 6-8

CHAPTER-3 : CONVENTIONAL 9-15

APPROACH
3.1 ALU with Reversible Gates 10-15

3.2 Limitations 15

CHAPTER-4 : SUGGESTED 16-20

APPROACH
4.1 Introduction 17

4.2 Reversible Logic in 64-bit ALU Design 18

4.3 Architecture of 64-bit ALU 18-19

4.4 Advantages & Applications 19-20

CHAPTER-5 : XILINX VIVADO AND 21-44

VERILOG HDL
5.1 History of Verilog 22

iii
5.2 Introduction 22-23

5.3 Design Styles 23

5.4 Features of Verilog HDL 24

5.5 VLSI Design Flow 24-26

5.6 Module 27-29

5.7 Modeling Concepts 29-35

5.8 Xilinx Verilog HDL Tutorial 35-42

5.9 Simulation Procedure 42-44

CHAPTER-6 : RESULTS & ANALYSIS 45-53

6.1 Results & Analysis 46-53

CHAPTER-7 : CONCLUSION & 54-56

FUTURE SCOPE
7.1 Conclusion 55

7.2 Future Scope 56

57-58
CHAPTER-8 : REFERENCES

8.1 References 58

PUBLICATION PAPER

iv
 TABLE OF FIGURES
FIG NO. NAME OF THE FIGURE PAGE NO.

1.1 Block Diagram of ALU 3

3.1.1 Block Diagram of Feynman Gate 11

3.1.2 Block Diagram of Peres Gate 12

3.1.3 12
Block Diagram of Toffoli Gate

3.1.4 Block Diagram of Fredkin Gate 13

13
3.1.5 Functional Diagram of 1-bit ALU

3.1.6 Block Diagram of 32-bit ALU 14

4.3.1 Block Diagram of 64-bit ALU 19

24
5.5.1 VLSI Design Flow

37
5.8.2.1 Project Type Page

39
5.8.2.2 Implemented Design

41
5.8.2.3 Project Settings Dialog Box

43
5.9 Schematic Window

5.9.1 44
Project Summary

6.1.1 47
32-bit RTL Schematic

6.1.2 47
64-bit RTL Schematic

6.1.3 48
Detail View of the RTL Schematic

6.1.4 49
32-bit Technology Schematic

6.1.5 49
64-bit Technology Schematic

v
6.1.6 50
32-bit Simulation Waveforms

6.1.7 50
64-bit Simulation Waveforms

6.1.12 53
32-bit Power Values

6.1.13 53
64-bit Power Values

vi
 LIST OF TABLES
TABLE NO NAME OF THE TABLE PAGE NO.

17
4.1 16 operations using 4-bit control signal

5.7.1.1 Description of Relational Operators 32

32
5.7.1.2 Description of Bitwise Operators

33
5.7.1.3 Description of Logical Operators

5.7.1.4 Description of Reduction Operators 34

5.7.1.5 34
Description of Shift Operators

5.7.1.6 Operator Precedence 35

6.1.8 32-bit Area Values 51

6.1.9 64-bit Area Values 51

6.1.10 32-bit Delay Values 52

6.1.11 64-bit Delay Values 52

vii
 LIST OF ABBREVIATIONS
S.NO. ABBREVIATION FULL FORM

1. VLSI Very Large Scale Integration

2. ALU Arithmetic Logical Unit

3. FPGA Field Programmable Gate Array

4. HDL Hardware Description Language

5. ASIC Application Specific Integrated Circuits

6. N-MOS N-Type Metal Oxide Semiconductor

7. RISC Reduced Instruction Set Computer

8. RTL Register Transfer Level

9. CPLD Complex Programmable Logic Device

10. IDE Integrated Development Environment

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 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC

CHAPTER-1

INTRODUCTION

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1.1 INTRODUCTION

The widespread utilization of microprocessors and signal processors has spurred the persistent
quest for high-performance arithmetic hardware, marking it as a perennially appealing design
challenge in the realm of computer architecture. At the heart of this pursuit lies the Arithmetic and
Logic Unit (ALU), a pivotal component that acts as the workhorse of microprocessors. The ALU
plays a defining role in determining the overall speed and efficiency of the processor by executing
a wide range of arithmetic and logical operations.
These encompass fundamental computations like addition, subtraction, multiplication, and
division, as well as crucial logical operations such as AND, OR, XOR, and NOT. Its design and
optimization for speed, energy efficiency, and parallelism are pivotal in enhancing a processor's
performance, with advanced techniques including pipelining and specialized instruction sets,
which accelerate specific operations. Moreover, in contemporary computing, processors are
equipped with on-chip memory, or cache memory, serving as a high-speed buffer.

The primary purpose of cache memory is to expedite data access, thus significantly enhancing
the overall performance of the processor. By storing frequently accessed data and instructions,
cache memory mitigates the delays associated with retrieving data from the relatively slower main
memory. The result is a more responsive and efficient processing environment that ranges from
general-purpose computing to scientific simulations, artificial intelligence, and embedded systems,
all of which rely on high-performance ALUs and efficient cache memory to maximize their
computational capabilities while minimizing power consumption.

This enduring pursuit of efficient arithmetic hardware and the strategic use of cache memory
continue to shape and drive innovation in the domain of computer architecture, with profound
implications for the performance and capabilities of modern computing systems. The key objective
of this work is to address the design of the functional blocks. An Arithmetic Logical Unit is the
very important subsystem in the digital system design. It is an integral part of a computer processor
and a combinational logic unit that performs its arithmetic and logic operations. ALUs of various
fixed bit-widths and full precision bit width are frequently required in very large-scale integrated
circuits (VLSI) from processors to application specific integrated circuits (ASICs).
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Nowadays ALU is getting smaller and more complex to enable the development of a more
powerful but smaller computer and processors. The need for high speed, less power consumption
and compatible processors has been increasing as a result of computer, digital signal processing
and networking applications. Arithmetic operations such as multiplication, addition, division and
subtraction and logical operations such as AND, OR, NOT, XOR are using all type of processors
used in various applications.

Fig:1.1. Block diagram of ALU

A. Overview of ALU

In digital electronics, an arithmetic logic unit (ALU) is a digital circuit that performs
arithmetic and bitwise logical operations on integer binary numbers. It is a fundamental building
block of the central processing unit found in many computers. The designed ALU circuit performs
addition/subtraction and comparator operations and some logic functions. The block diagram of
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the ALU is in Figure 1.1 above. The full adder/subtractor has 3 inputs so we take three inputs
namely A.B and Cin. Other than adder/subtractor all the operations only need 2 inputs. The
functions are selected by multiplexer with select line. And then we obtain the output.

B. Arithmetic Operations

Arithmetic is the oldest and most elementary branch of mathematics. It consists of the study
of numbers, especially the properties of the traditional operations between them - addition,
subtraction, multiplication and division. Arithmetic is an elementary part of number theory, and
number theory is considered to be one of the top-level divisions of modern mathematics, along
with algebra, geometry and analysis. The designed arithmetic logic unit does the arithmetic
operations of addition, subtraction and comparison operations. The comparator consists of lesser,
greater and equal operations.

C. Logical Operations

A digital Logic Gate is an electronic device that makes logical decisions based on the
different combinations of digital signals present on its inputs. Digital logic gates may have more
than one input but generally only have one digital output. Individual logic gates can be connected
together to form combinational or sequential circuits, larger logic gate functions. The ALU circuit
does various logic operations such as AND, OR, NOT and XOR.

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CHAPTER-2

LITERATURE REVIEW

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2.1 LITERATURE REVIEW

Ravindran N & Regeena, Mary (2015): An optimum VLSI design of a 16-BIT ALU.

The key parameters for the performance measure of any VLSI design are logic delay, power
consumption and chip area. This paper describes the VLSI design of a 16 Bit ALU and design is
optimized in terms of Speed, Power Consumption and Chip Area. Different logic families are used
in the design for various logic modules. The choice of logic families for each module is determined
by considering speed and power consumption as the important parameters offered by each logic
family. The adder circuit being the most important module used by the arithmetic operations of an
ALU, detailed analysis of the variety of adder circuit configurations are carried out and the best
suited configuration for the ALU design i.e. Carry Skip Adder configuration is used to design the
optimum ALU. Finally, a 16 bit Arithmetic Logic unit is designed using mixed logic families such
as CMOS for basic logic functions, pseudo-NMOS for AND logic and Pass Transistor logic for
multiplexers, in order to optimize the overall performance of the design. Schematic editor DSCH
is used to validate the design at gate level implementation and IC Layout editor Micro wind is used
to implement the chip level design.

Summary: This paper describes the VLSI design of a 16 Bit ALU and design is optimized in terms
of Speed, Power Consumption and Chip Area .

Kumar, Praveen & Singh, Kunal (2021): Design and comparison of low power high speed 4
bit-ALU.

This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using
Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its
advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle.
Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared
against the conventional static CMOS logic counterpart to identify its adiabatic power advantage.
Finally, A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and
comparisons have been made. The analysis is carried out using the industry standard EDA design
environment using 250 nm technology libraries from Tanner. The results prove that the CEPAL
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4-bit ALU is 55% more power efficient than the CMOS 4-bit ALU at 100MHz and at 2.5V
operating voltage.
Summary: A 4-bit Arithmetic Logic Unit (ALU) is implemented with both the technologies and
comparisons have been made.

Rengasamy, Dr. Dhanabal & Bharathi, Venuturla & Salim, Saira & Thomas, Bincy &
Soman, Hyma & Sahoo, Sarat Kumar (2013): Design of 16-bit low power ALU-DBGPU.
Intern. J. Eng. Technol.

Arithmetic and Logic Unit (ALU) is one of the common and the most crucial components of an
embedded system. Power consumption is a major design issue in the case of embedded systems.
Usually, ALU's consists of a number of functional units for different arithmetic and logic
operations which are realized using combinational circuits. Each of the functional unit performs a
specific arithmetic or logic operation. In this paper the main concern is given for reducing the
power of the adder and multiplier modules which are important functional units of ALU thereby
reducing the overall power consumption without compromising the speed of the processor. The
ALU circuit ensures the execution of either arithmetic or logic operation only at a time so that only
one set of circuits is active at a time thus ensuring low power consumption. The entire ALU circuit
is realized using Verilog HDL and power analysis is obtained through same.

Summary: In this paper the main concern is given for reducing the power of the adder and
multiplier modules which are important functional units of ALU .

Buddhini, Piyumi & Wijesinghe, Susantha (2016): Implementation of a 16-bit

Microprocessor on an FPGA.

Today’s world most essential part of the various applications, system is embedded with processing
unit. One of the most reliable, low power consumption way to implement those systems are using
FPGAs. When used FPGAs, output can decide while designing process and devices can
reprogrammable. So may be more accurate if using FPGAs. In this project comprise the designing
process and hardware implementation of simple 16-bit RISC processor on an FPGA which can
perform a basic ALU operations. Its components modeling using Verilog language. Here, for the

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implementation Xilinx Spartan 3E development board was used. The board is coming up with
features that can implement even a very complex systems on it. This 16-bit processor runs on
Xilinx XC3S500E Spartan-3E FPGA. The source codes of the processing system are very simple.
Inside of the system I/O transferring based on stack machine system that is LIFO (Last-In First-
Out). In this research work, RISC architecture was used on this design, so only basic instructions
ware implemented. All the instructions were in same size, so that it may be fetched in a single
operation. The instruction set adopted here is extremely simple that gives an insight into the kind
of hardware which should be able to execute the set of instructions properly. The processor’s
architecture features 16-bit instruction words.

Summary: In this project comprise the designing process and hardware implementation of simple
16-bit RISC processor on an FPGA which can perform a basic ALU operations.

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CHAPTER-3

CONVENTIONAL APPROACH

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3.1 ALU WITH REVERSIBLE GATES

In ALU architecture, a high performance arithmetic hardware with minimum possible

clock cycles capable of computing square, square root and inverse in addition to basic arithmetic
operations. Design of ALU was undertaken in this thesis in the context of high performance and
testability. Architectures with high degree of parallelism were explored for design of high-speed
arithmetic unit. For simplicity, functional units were designed with 8-bit capability. Due to
architectural parallelism, increase in operand size would only require replication of hardware
parallel to existing circuitry. The ALU has stand-alone hardware for performing basic integer
arithmetic operations and is capable of computing square, square root and inverse as well. A logic
unit performing 8-bit logic operations was built using logic cells available in the IC cell library
and was found to have a high operating frequency close to 1GHz. Hardware for addition and
subtraction was implemented as a combined ADD/SUB unit. Subtraction is generally performed
using two’s complement addition. Two’s complement of a number is obtained by negation of the
operand followed by an increment-by-1. The XOR gate inverts the other input if the CTRL input
is ‘High’. The CTRL signal is applied to Cin to perform the increment needed to complete two’s
complement calculation. When CTRL signal is ‘Low’, the unit performs addition.

A. REVERSIBLE LOGIC GATES

Reversible logic gates are a specialized class of digital logic gates designed to have a
unique property: they ensure that both the input and output states of the system are one-to-one,
meaning each input state uniquely maps to a specific output state, and vice versa. This reversibility
property stands in contrast to conventional (irreversible) logic gates, where multiple input states
can map to the same output state, resulting in information loss, heat dissipation, and a lack of
reversibility.

Reversible logic gates are a fascinating area of study within the field of digital logic and
computing due to their potential applications in various emerging technologies, such as quantum
computing, low-power electronics, and nanotechnology. These gates offer the ability to perform
computations in an energy-efficient manner while preserving the integrity of information.

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The concept of reversibility is central to reversible logic gates, and it holds immense
significance in quantum computing, where maintaining the coherence of quantum states is vital.
In this domain, these gates enable operations that can be undone, ensuring the precise handling of
quantum information. Reversible logic gates come in various forms, including the Toffoli gate, the
Fredkin gate, and the Peres gate, each designed to perform specific reversible operations.

In this introduction to reversible logic gates, we explore the fundamental principles,

applications, and advantages of these gates, providing insights into their pivotal role in shaping the
future of computing and information processing.

✓ FEYNMAN Gate:
Feynman gate is also known as 2X2 reversible gate. The input and output vectors for
Feynman gate is In (A, B) and Out (P, Q) respectively. The outputs of FEYMAN gate are
denoted as P=A, Q=A XOR B and Quantum cost of a Feynman gate is one. The application
of this gate is used in many circuits because of low cost of the FEYMAN gates.

Fig:3.1.1. Block Diagram of Feynman Gate

✓ PERES Gate:

It is also called as 3X3 reversible gate. The input and output vector for PERES gate is In (A,
B, C) and Out (P, Q, R) respectively. The output is defined as P = A, Q = A XOR B and
R=AB XOR C and the Quantum cost of Peres gate is 4. Because of its lowest quantum cost
in many designs Peres gate is used. half adder is designed by Single Peres gate .

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Fig:3.1.2. Block Diagram of Peres Gate

✓ TOFFOLI Gate:

Let I and O be the input and output vector of a 3X3 Toffoli Gate (TG) respectively, where I =
(A, B, C) and O = (P=A, Q=B, R=AB⊕ C).

Fig:3.1.3. Block Diagram of Toffoli Gate

✓ FREDKIN Gate:
Let us consider I and O be the input and output vector of a 3X3 Fredkin Gate
respectively, where I = (A,B,C) and O = (X=A,Y=A’B XOR AC , Z=A’C XOR AB)

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Fig:3.1.4. Block Diagram of Fredkin Gate

B. 1 BIT REVERSIBLE LOGIC GATE ALU

AND gate is replaced with Peres gate, by giving C as 1’b0.

FULL ADDER ,having XOR gate is replaced by Feynman Gate also AND gate with Peres gate.

Fig:3.1.5. Functional Diagram of 1-bit ALU

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C. 32 BIT REVERSIBLE LOGIC GATE ALU

Here's a basic outline of a 32-bit reversible ALU:

Inputs:

Two 32-bit binary numbers A and B.

Control inputs to specify the operation (e.g., Addition, AND, OR, input A etc.).

Outputs:

A 32-bit result of the selected operation.

Fig:3.1.6. Block Diagram of 32-bit ALU

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The reversible logic gate ALU can perform a wide range of arithmetic and logical operations.
These operations are executed using reversible gates, ensuring that the input data can be precisely
reconstructed from the output. Here We perform Addition, AND, OR for input data.

3.2 LIMITATIONS

➢ Very few operations.

➢ Delay increases as the computation time of output increases.
➢ As size increases performance of the circuit decreases.

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CHAPTER-4

SUGGESTED APPROACH

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4.1 INTRODUCTION

In the Existing method, 1-bit ALU is designed to perform only 4 operations using 2bit
control signals using Reversible logic gates. So, in the Proposed method ALU is designed to
perform 16 operations. Below table consists of 16 operations using 4 bit control signal using
Reversible Logic Gates.

Control signal Operation

0000 sum
0001 a-b
0010 a*b
0011 a|b
0100 ~a
0101 R0
0110 ~(a ^ b)
0111 ~(a & b)
1000 32'd0
1001 ~(a | b)
1010 a&b
1011 IO_STS
1100 INC
1101 b*1
1110 a^b
1111 a*1
Table 4.1: 16 operations using 4-bit control signal
The proposed 64-bit ALU is designed using Reversible Logic Gates, addressing the
limitations of conventional ALUs by reducing power dissipation and heat generation, which are
critical challenges in modern VLSI design. This ALU performs 16 arithmetic and logical
operations, controlled by a 4-bit control signal, ensuring higher computational efficiency while
maintaining low power consumption.
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4.2 REVERSIBLE LOGIC IN 64-BIT ALU DESIGN

Reversible logic is a computing paradigm where no information is lost during computation,

minimizing power dissipation. Unlike conventional logic gates, reversible gates ensure that the
input can be uniquely determined from the output, reducing energy loss.

Key Reversible Logic Gates Used in 64-bit ALU:

➢ Feynman Gate – Used for buffer and XOR operations.

➢ Toffoli Gate – Used for AND & other logical operations.
➢ Fredkin Gate – Used for multiplexer-based operations.
➢ Peres Gate – Used for addition and XOR computations.
➢ HNG (Haghparast-Navi Gate) - Optimized for full-adder circuits in arithmetic operations.

These gates help implement high-speed and low-power operations, making the 64-bit ALU highly
efficient.

4.3 ARCHITECTURE OF 64-BIT ALU

The 64-bit ALU is built using multiple one-bit reversible ALU units, forming a hierarchical
structure to process 64-bit operands. The design includes:

➢ Arithmetic unit: Performs addition, subtraction, multiplication, and division using

reversible full adders and multipliers.
➢ Logical Unit: Executes AND, OR, XOR, NAND, NOR, and NOT operations using
Feynman and Toffoli gates.
➢ Shift and Rotate Unit: Implements logical/arithmetic shifts and rotations efficiently.
➢ Comparison and Selection Unit: Supports magnitude comparison, equality check, and
multiplexing operations.

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Fig:4.3.1. Block Diagram of 64-bit ALU

Each of these functional blocks is designed using reversible logic, ensuring minimal power loss
and enhanced performance.

4.4 ADVANTAGES & APPLICATIONS

Advantages:

✓ Energy consumption is optimized.

✓ No of operations are increased.
✓ Computational delay is reduced with improved accuracy of output.

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Applications:

✓ Digital signal processors

✓ Low-Power Electronics
✓ Calculators, cell phones, and computers
✓ MAC & Arithmetic circuits.

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CHAPTER-5

XILINX VIVADO AND VERILOG HDL

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5.1 HISTORY OF VERILOG

Verilog was started initially as a proprietary hardware modeling language by Gateway

Design Automation Inc. around 1984. It is rumored that the original language was designed by
taking features from the most popular HDL language of the time, called HiLo, as well as from
traditional computer languages such as C. At that time, Verilog was not standardized and the
language modified itself in almost all the revisions that came out within 1984 to 1990.

Verilog simulator was first used beginning in 1985 and was extended substantially through
1987. The implementation was the Verilog simulator sold by Gateway. The first major extension
was Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which
was a very efficient method for doing gate-level simulation.

The time was late 1990. Cadence Design System, whose primary product at that time
included thin film process simulator, decided to acquire Gateway Automation System. Along with
other Gateway products, Cadence now became the owner of the Verilog language, and continued
to market Verilog as both a language and a simulator.

At the same time, Synopsys was marketing the top-down design methodology, using
Verilog. This was a powerful combination. In 1990, Cadence recognized that if Verilog remained
a closed language, the pressures of standardization would eventually cause the industry to shift to
VHDL. Consequently, Cadence organized the Open Verilog International (OVI), and in 1991 gave
it the documentation for the Verilog Hardware Description Language. This was the event which
"opened" the language.

5.2 INTRODUCTION

➢ Hardware Description Language is an abbreviation of HDL. Any digital system can be

represented in a REGISTER TRANSFER LEVEL (RTL) and HDLs are used to describe
this RTL.

➢ Verilog is one such HDL and it is a general-purpose language, easy to learn and use. Its
syntax is similar to C.

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➢ The idea is to specify how the data flows between registers and how the design processes
the data.

➢ To define RTL, hierarchical design concepts play a very significant role. Hierarchical
design methodology facilitates the digital design flow with several levels of abstraction.

➢ Verilog HDL can utilize these levels of abstraction to produce a simplified and efficient
representation of the RTL description of any digital design.

➢ For example, an HDL might describe the layout of the wires, resistors and transistors on
an Integrated Circuit (IC) chip, i.e., the switch level or, it may describe the design at a more
micro level in terms of logical gates and flip flops in a digital system, i.e., the gate level.
Verilog supports all of these levels.

5.3 DESIGN STYLES

Any hardware description language like Verilog can be design in two ways one is bottom-
up design and other one is top-down design.

✓ Bottom-Up Design:

The traditional method of electronic design is bottom-up (designing from transistors and
moving to a higher level of gates and, finally, the system). But with the increase in design
complexity traditional bottom-up designs have to give way to new structural, hierarchical design
methods.

✓ Top-Down Design:

For HDL representation it is convenient and efficient to adapt this design-style. A real top-
down design allows early testing, fabrication technology independence, a structured system design
and offers many other advantages. But it is very difficult to follow a pure top-down design. Due
to this fact most designs are mix of both the methods, implementing some key elements of both
design styles.

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5.4 FEATURES OF VERILOG HDL

✓ Verilog is case sensitive.

✓ Ability to mix different levels of abstract freely.

✓ One language for all aspects of design, testing, and verification.

✓ In Verilog, Keywords are defined in lower case.

✓ In Verilog, most of the syntax is adopted from "C" language.

✓ Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

✓ There is no concept of package in Verilog.

✓ It also supports advanced simulation features like TEXTIO, PLI, and UDPs.

5.5 VLSI DESIGN FLOW

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of steps,
and eventually produces a packaged chip.

Fig:5.5.1. VLSI Design Flow

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1. System Specification:
➢ The first step of any design process is to lay down the specifications of the system.
System specification is a high level representation of the system. The factors to be
considered in this process include: performance, functionality, and physical
dimensions like size of the chip.
➢ The specification of a system is a compromise between market requirements,
technology and economic viability. The end results are specifications for the size,
speed, power, and functionality of the VLSI system.
2. Architectural Design:
➢ The basic architecture of the system is designed in this step. This includes, such
decisions as RISC (Reduced Instruction Set Computer) versus CISC (Complex
Instruction Set Computer), number of ALUs, Floating Point units, number and
structure of pipelines, and size of caches among others. The outcome of
architectural design is a Micro-Architectural Specification (MAS).
3. Behavioral or Functional Design:
➢ In this step, main functional units of the system are identified. This also identifies
the interconnect requirements between the units. The area, power, and other
parameters of each unit are estimated.
➢ Module: The key idea is to specify behavior, in terms of input, output and timing
of each unit, without specifying its internal structure.
➢ The outcome of functional design is usually a timing diagram or other relationships
between units.
4. Logic Design:
➢ In this step the control flow, word widths, register allocation, arithmetic operations,
and logic operations of the design that represent the functional design are derived
and tested.
➢ This description is called Register Transfer Level (RTL) description. RTL is
expressed in a Hardware Description Language (HDL), such as VHDL or Verilog.
This description can be used in simulation and verification

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5. Circuit Design:
➢ The purpose of circuit design is to develop a circuit representation based on the
logic design. The Boolean expressions are converted into a circuit representation
by taking into consideration the speed and power requirements of the original
design. Circuit Simulation is used to verify the correctness and timing of each
component
➢ The circuit design is usually expressed in a detailed circuit diagram. This diagram
shows the circuit elements (cells, macros, gates, transistors) and interconnection
between these elements. This representation is also called a netlist. And each stage
verification of logic is done.
6. Physical design:
➢ In this step the circuit representation (or netlist) is converted into a geometric
representation. As stated earlier, this geometric representation of a circuit is called
a layout.
➢ Layout is created by converting each logic component (cells, macros, gates,
transistors) into a geometric representation (specific shapes in multiple layers),
which perform the intended logic function of the corresponding component.
Connections between different components are also expressed as geometric
patterns typically lines in multiple layers.
7. Layout verification:
➢ Physical design can be completely or partially automated and layout can be
generated directly from netlist by Layout Synthesis tools. Layout synthesis tools,
while fast, do have an area and performance penalty, which limit their use to some
designs. These are verified.
8. Fabrication and Testing:
➢ Silicon crystals are grown and sliced to produce wafers. The wafer is fabricated and
diced into individual chips in a fabrication facility. Each chip is then packaged and
tested to ensure that it meets all the design specifications and that it functions
properly.

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5.6 MODULE

A module is the basic building block in Verilog. It can be an element or a collection of low level
design blocks. Typically, elements are grouped into modules to provide common functionality
used in places of the design through its port interfaces, but hides the internal implementation.

SYNTAX:

module<module name> (<module_port_list>);

…..

<module internals> //contents of the module

….

Endmodule

5.6.1 INSTANCES

A module provides a template from where one can create objects. When a module is invoked
Verilog creates a unique object from the template, each having its own name, variables, parameters
and I/O interfaces. These are known as instances.

5.6.2 PORTS

• Ports allow communication between a module and its environment.

• All but the top-level modules in a hierarchy have ports.

• Ports can be associated by order or by name.

You declare ports to be Input or Output or In-out. The port declaration syntax is:

Input [range_val:range_var] list_of_identifiers;

Output[range_val:range_var] list_of_identifiers;

In-out[range_val:range_var] list_of_identifiers;

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5.6.3 IDENTIFIERS

✓ Identifiers are user-defined words for variables, function names, module names, and
instance names. Identifiers can be composed of letters, digits, and the underscore character.

✓ The first character of an identifier cannot be a number. Identifiers can be any length.

✓ Identifiers are case-sensitive, and all characters are significant.

An identifier that contains special characters, begins with numbers, or has the same name as a
keyword can be specified as an escaped identifier. An escaped identifier starts with the backslash
character(\) followed by a sequence of characters, followed by white space.

5.6.4 KEYWORDS

✓ Verilog uses keywords to interpret an input file.

✓ You cannot use these words as user variable names unless you use an escaped identifier.

✓ Keywords are reserved identifiers, which are used to define language constructs.

✓ Some of the keywords are always, case, assign, begin, case, end and end case etc.

5.6.5 DATA TYPES

Verilog Language has two primary data types:

✓ Nets - represents structural connections between components.

✓ Registers - represent variables used to store data.

Every signal has a data type associated with it. Data types are:

➢ Explicitly declared with a declaration in the Verilog code.

➢ Implicitly declared with no declaration but used to connect structural building blocks in
the code. Implicit declarations are always net type "wire" and only one bit wide.

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Register Data Types:

✓ Registers store the last value assigned to them until another assignment statement changes
their value.

✓ Registers represent data storage constructs.

✓ Register arrays are called memories.

✓ Register data types are used as variables in procedural blocks.

✓ A register data type is required if a signal is assigned a value within a procedural block

✓ Procedural blocks begin with keyword initial and always.

The data types that are used in register are register, integer, time and real.

5.7 MODELING CONCEPTS

Abstraction Levels:

1. Behavioral level

2. Register-Transfer Level

3. Gate Level

4. Switch level

1. Behavioral or algorithmic Level

▪ This level describes a system by concurrent algorithms (Behavioral).

▪ Each algorithm itself is sequential meaning that it consists of a set of instructions that
are executed one after the other.

▪ The blocks used in this level are ‘initial’, ‘always’ ,‘functions’ and ‘tasks’ blocks

▪ The intricacies of the system are not elaborated at this stage and only the functional
description of the individual blocks is prescribed.
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▪ In this way the whole logic synthesis gets highly simplified and at the same time more
efficient.

2. Register-Transfer Level

▪ Designs using the Register-Transfer Level specify the characteristics of a circuit by

operations and the transfer of data between the registers.

▪ An explicit clock is used. RTL design contains exact timing possibility, operations are
scheduled to occur at certain times.

▪ Modern definition of an RTL code is "Any code that is synthesizable is called RTL
code".

3. Gate Level

▪ Within the logic level the characteristics of a system are described by logical links and
their timing properties.

▪ All signals are discrete signals. They can only have definite logical values (`0', `1', `X',
`Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates).

▪ It must be indicated here that using the gate level modeling may not be a good idea in
logic design.

▪ Gate level code is generated by tools like synthesis tools in the form of netlists which
are used for gate level simulation and for backend.

4. Switch Level

▪ This is the lowest level of abstraction. A module can be implemented in terms of

switches, storage nodes and interconnection between them. However, as has been
mentioned earlier, one can mix and match all the levels of abstraction in a design. RTL
is frequently used for Verilog description that is a combination of behavioral and
dataflow while being acceptable for synthesis.

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5.7.1 OPERATORS

Verilog provided many different operators types. Operators can be,

✓ Arithmetic Operators

✓ Relational Operators

✓ Bit-wise Operators

✓ Logical Operators

✓ Reduction Operators

✓ Shift Operators

✓ Concatenation Operator

1. Arithmetic Operators:

✓ These perform arithmetic operations. The + and - can be used as either unary (-z) or binary
(x-y) operators.

✓ Binary: +, -, , /, % (the modulus operator)

✓ Unary: +, - (This is used to specify the sign)

✓ Integer division truncates any fractional part

✓ The result of a modulus operation takes the sign of the first operand

✓ If any operand bit value is the unknown value x, then the entire result value is x

✓ Register data types are used as unsigned values (Negative numbers are stored in two's
complement form).

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2. Relational Operators:

Relational operators compare two operands and return a single bit 1or 0. These operators
synthesize into comparators. Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-
3d001)>3d1 10, however for integers -1.

Table 5.7.1.1: Description of Relational Operators

• The result is a scalar value

• 0 if the relation is false (a is bigger than b)

• 1 if the relation is true ( a is smaller than b)

• x if any of the operands has unknown x bits (if a or b contains X)

Note: If any operand is x or z, then the result of that test is treated as false (0)

3. Bit-wise Operators:

Bitwise operators perform a bit wise operation on two operands. This take each bit in one operand
and perform the operation with the corresponding bit in the other operand. If one operand is shorter
than the other, it will be extended on the left side with zeroes to match the length of the longer
operand

Table 5.7.1.2: Description of Bitwise Operators

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Computations include unknown bits, in the following way:

-> ~x = x

-> 0&x = 0

-> 1&x = x&x = x

-> 1|x = 1

-> 0|x = x|x = x

-> 0^x = 1^x = x^x = x

-> 0^~x = 1^~x = x^~x = x

When operands are of unequal bit length, the shorter operand is zero-filled in the most significant
bit positions.

4. Logical Operators:

Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single
bit operands. They can work on expressions, integers or groups of bits, and treat all values that are
nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements since they
work with expressions.

Table 5.7.1.3: Description of Logical Operators

Expressions connected by && and || are evaluated from left to right

Evaluation stops as soon as the result is known

The result is a scalar value:

✓ 0 if the relation is false

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✓ 1 if the relation is true

✓ x if any of the operands has x (unknown) bits

5. Reduction Operators:

Reduction operators operate on all the bits of an operand vector and return a single-bit value. These
are the unary (one argument) form of the bit-wise operators.

Table 5.7.1.4: Description of Reduction Operators

✓ Reduction operators are unary.

✓ They perform a bit-wise operation on a single operand to produce a single bit result.

✓ Reduction unary NAND and NOR operators operate as AND OR respectively, but with
their outputs negated.

6. Shift Operators:

Shift operators shift the first operand by the number of bits specified by the second operand.
Vacated positions are filled with zeros for both left and right shifts (There is no sign extension).

Table 5.7.1.5: Description of Shift Operators

✓ The left operand is shifted by the number of bit positions given by the right operand.

✓ The vacated bit positions are filled with zeroes.

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7. Concatenation Operator:

✓ The concatenation operator combines two or more operands to form a larger vector.

✓ Concatenations are expressed using the brace characters { and }, with commas separating
the expressions within.

✓ Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results have 24 bits

✓ Unsized constant numbers are not allowed in concatenations.

OPERATOR PRECEDENCE

Table 5.7.1.6: Operator Precedence

5.8 XILINX VERILOG HDL TUTORIAL

First, we need to download and install Xilinx and ModelSim. These tools both have free student
versions. Please accomplish Appendix B, C, and D in that order before continuing with this
tutorial. Additionally, if you wish to purchase your own Spartan3 board, you can do so at Digilent’s
Website. Digilent offers academic pricing. Please note that you must download and install Digilent
Adept software. The software contains the drivers for the board that you need and also provides
the interface to program the board.

5.8.1 INTRODUCTION

Xilinx Tools is a suite of software tools used for the design of digital circuits implemented using
Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device
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(CPLD). The design procedure consists of (a) design entry, (b) synthesis and implementation of
the design, (c) functional simulation and (d) testing and verification. Digital designs can be entered
in various ways using the above CAD tools: using a schematic entry tool, using a hardware
description language (HDL) – Verilog or VHDL or a combination of both. In this lab we will only
use the design flow that involves the use of Verilog HDL.

The CAD tools enable you to design combinational and sequential circuits starting with Verilog
HDL design specifications. The steps of this design procedure are listed below:

1. Create Verilog design input file(s) using template driven editor.

2. Compile and implement the Verilog design file(s).

3. Create the test-vectors and simulate the design (functional simulation) without using a PLD
(FPGA or CPLD).

4. Assign input/output pins to implement the design on a target device.

5. Download bitstream to an FPGA or CPLD device.

6. Test design on FPGA/CPLD device

A Verilog input file in the Xilinx software environment consists of the following segments:

Header: module name, list of input and output ports.

Declarations: input and output ports, registers and wires.

Logic Descriptions: equations, state machines and logic functions.

End: endmodule

All your designs for this lab must be specified in the above Verilog input format. Note that the
state diagram segment does not exist for combinational logic designs.

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Programmable Logic Device: FPGA

In this lab digital designs will be implemented in the Basys2 board which has a Xilinx Spartan3E
–XC3S250E FPGA with CP132 package. This FPGA part belongs to the Spartan family of FPGAs.
These devices come in a variety of packages. We will be using devices that are packaged in 132
pin package with the following part number: XC3S250E-CP132.

5.8.2 CREATING A NEW PROJECT

Creating Projects:

You can use the New Project wizard to easily create different types of projects in the Vivado IDE.
To open the New Project wizard, select File > New Project. This wizard enables you to specify a
project location and name and create the types of projects shown in below figure.

Fig:5.8.2.1. Project Type Page

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Project Name: Write the name of your new project which is user defined.

Project Location: The directory where you want to store the new project in the specified location
in one of your drive. In above window they are stored in location c drive which is not correct, the
location of software and code should not be same location and Clicking on NEXT.

For each of the properties given below, click on the ‘value’ area and select from the list of values
that appear.

✓ Device Family: Family of the FPGA/CPLD used. In this laboratory we will be using the
Spartan3E FPGA’s.

✓ Device: The number of the actual device. For this lab you may enter XC3S250E (this can
be found on the attached prototyping board)

✓ Package: The type of package with the number of pins. The Spartan FPGA used in this
lab is packaged in CP132 package.

✓ Speed Grade: The Speed grade is “-4”.

✓ Synthesis Tool: XST [VHDL/Verilog]

✓ Simulator: The tool used to simulate and verify the functionality of the design. Then click
on NEXT to save the entries.

Opening Designs:

Use the Flow Navigator or Flow menu to select the following commands:

✓ Open Elaborated Design

✓ Open Synthesized Design

✓ Open Implemented Design

The Flow > Open Implemented Design command populates the Vivado IDE as shown in below
figure.

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Fig:5.8.2.2. Implemented Design

All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored in a
subdirectory with the project name.

1. In order to open an existing project in Xilinx Tools, select File->Open Project to show
the list of projects on the machine. Choose the project you want and click OK.
2. If creating a new source file, click on the NEW SOURCE.
3. Creating a Verilog HDL input file for a combinational logic design:
4. In this lab we will enter a design using a structural or RTL description using the Verilog
HDL. You can create a Verilog HDL input file (.v file) using the HDL Editor available
in the Xilinx Vivado Tools (or any text editor).
5. In the previous window, click on the NEW SOURCE

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6. (Note: “Add to project” option is selected by default. If you do not select it then you
will have to add the new source file to the project manually.)
7. Select Verilog Module and in the “File Name:” area, enter the name of the Verilog
source file you are going to create. Also make sure that the option Add to project is
selected so that the source need not be added to the project again. Then click on Next
to accept the entries.
8. In the Port Name column, enter the names of all input and output pins and specify the
Direction accordingly. A Vector/Bus can be defined by entering appropriate bit
numbers in the MSB/LSB columns. Then click on Next> to get a window showing all
the new source information above window. If any changes are to be made, just click on
<Back to go back and make changes. If everything is acceptable, click on Finish > Next
> Next > Finish to continue.
9. Once you click on Finish, the source file will be displayed in the sources window in
the Project Navigator. If a source has to be removed, just right click on the source file
in the Sources in Project window in the Project Navigator and select remove in that.
Then select Project -> Delete Implementation Data from the Project Navigator menu
bar to remove any related files.
10. Editing the Verilog source file
11. The source file will now be displayed in the Project Navigator window (Figure 8). The
source file window can be used as a text editor to make any necessary changes to the
source file. All the input/output pins will be displayed. Save your Verilog program
periodically by selecting the File->Save from the menu. You can also edit Verilog
programs in any text editor and add them to the project directory using “Add Copy
Source”.
12. Here in the above window, we will write the Verilog programming code for specified
design and algorithm in the window.
13. After writing the programming code we will go for the synthesis report.
14. Configuring Project Settings

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15. You can configure the Project Settings in the Settings dialog box to meet your design
needs. These settings include general settings, related to the top module definition and
language options, as well as simulation, elaboration, synthesis, implementation,
bitstream, and IP settings.

Fig:5.8.2.3. Project Settings Dialog Box

16. To open the Settings dialog box, use any of the following methods:
• In the Flow Navigator Project Manager section, click Settings.
• Select Tools > Settings.
• In the main toolbar, click the Settings toolbar button .
• In the Project Summary, click the Edit link next to Settings.
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5.8.3 SYNTHESIS AND IMPLEMENTATION OF THE DESIGN

The design has to be synthesized and implemented before it can be checked for correctness, by
running functional simulation or downloaded onto the prototyping board. With the top-level
Verilog file opened (can be done by double-clicking that file) in the HDL editor window in the
right half of the Project Navigator, and the view of the project being in the Module view , the
implement design option can be seen in the process view. Design entry utilities and Generate
Programming File options can also be seen in the process view.

1. To synthesize the design, double click on the Synthesize Design option in the Processes
window.
2. To implement the design, double click the Implement design option in the Processes
window. It will go through steps like Translate, Map and Place & Route. If any of these
steps could not be done or done with errors, it will place a X mark in front of that,
otherwise a tick mark will be placed after each of them to indicate the successful
completion
3. After synthesis right click on synthesis and click view text report in order to generate
the report of our design.

5.9 SIMULATION PROCEDURE

1. After completion of synthesis, we will go simulation in order to verify the functionality of

the implemented design.
2. Click on Run Simulation and set the module that is need to Run
3. Next double click on Run Behavioral Simulation to check the errors. If no errors are found
then double click on simulate behavioral model to get the output waveforms.
4. After clicking on simulate behavioral model, the simulation widow will appear pass the
input values by making force constant and if it is clock by making force clock.
5. Mention the simulation period and run for certain time and results will appear as shown in
following window.
6. Verify the results to the given input values.

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7. Using the Schematic Window, you can generate a Schematic window for any level of the
logical or physical hierarchy.
8. You can select a logic element in an open window, such as a primitive or net in the Netlist
window, and use the Schematic command in the popup menu to create a Schematic window
for the selected object.

An elaborated design always opens with a Schematic window of the top-level of the design, as
shown in below figure.

Fig:5.9. Schematic Window

The Vivado IDE includes an interactive Project Summary that updates dynamically as design
commands are run and the design progresses through the design flow. It provides project and
design information, such as the project part, board, and state of synthesis and implementation.

It also provides links to detailed information, such as links to the Messages and Reports windows
as well as the Settings dialog box.

As synthesis and implementation complete, DRC violations, timing values, utilization percentages,
and power estimates are also populated. To open the Project Summary, do either of the following:

1. Select Window > Project Summary.

43
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
2. Click the Project Summary toolbar button.

Fig:5.9.1. Project Summary

44
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N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC

CHAPTER-6
RESULTS & ANALYSIS

45
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
6.1 RESULTS & ANALYSIS
The implementation of a 64-bit FPGA-based Arithmetic Logic Unit (ALU) utilizing 4-bit control
signals and reversible logic gates including Peres, Fredkin, Feynman, and Toffoli gates has
demonstrated significant improvements in key performance metrics. The design efficiently
performs 16 arithmetic and logical operations with minimal computational delay, making it well-
suited for high-performance computing. In terms of resource utilization, the design uses only 468
Slice LUTs and 192 Slice Registers, confirming its area-efficient nature. Timing analysis indicates
a maximum delay of 16.585 ns with no constraint violations, suggesting a well-balanced and stable
architecture. All critical paths are optimized with manageable logic and net delays, ensuring
effective data propagation across the system.
The power analysis reveals a total consumption of 39.787W, with a junction temperature of
99.4°C. While this value may appear high, it is an anticipated result given the system’s purpose of
handling 64-bit wide arithmetic and logic operations. The design also exhibits low static power
consumption (0.795W) and efficient usage of logic resources, reinforcing its potential for low-area
VLSI systems. This study demonstrates that the integration of reversible logic with 4-bit control
signals not only enhances operational flexibility but also contributes to optimized power and area
performance.
With appropriate power constraint tuning and further optimization, this reversible ALU
architecture is scalable and accurate, showing excellent promise for next-generation, low-power,
high-speed digital systems.

46
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
RTL SCHEMATIC:

Fig:6.1.1. 32-bit RTL Schematic Fig:6.1.2. 64-bit RTL Schematic

47
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC

Fig:6.1.3. Detail View of the RTL Schematic

48
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
TECHNOLOGY SCHEMATIC:

Fig:6.1.4. 32-bit Technology Schematic

Fig:6.1.5. 64-bit Technology Schematic

49
Dept of ECE,
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 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
SIMULATION RESULTS:

Fig:6.1.6. 32-bit Simulation Waveforms

Fig:6.1.7. 64-bit Simulation Waveforms

50
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
AREA VALUES:

Table 6.1.8: 32-bit Area Values

Table 6.1.9: 64-bit Area Values

51
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
DELAY VALUES:

Table 6.1.10: 32-bit Delay Values

Table 6.1.11: 64-bit Delay Values

52
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
POWER VALUES:

Fig:6.1.12. 32-bit Power Values

Fig:6.1.13. 64-bit Power Values

53
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC

CHAPTER-7

CONCLUSION & FUTURE SCOPE

54
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
7.1 CONCLUSION

The proposed 64-bit FPGA-based ALU employing reversible logic showcases substantial
improvements in computational efficiency, reduced power dissipation, minimized chip area, and
optimized delay. By integrating reversible logic gates such as Peres, Fredkin, Feynman, and
Toffoli, the ALU efficiently performs 16 arithmetic and logical operations while significantly
lowering energy consumption. The implementation of both 64-bit and 32-bit Reversible ALUs
highlights the superior performance of reversible logic when compared to conventional irreversible
logic designs.

The comparative analysis reveals notable reductions in power dissipation, area(no. of LUTs), and
logic delay achieved by utilizing 4-bit control signals with reversible logic gates. This
demonstrates the effectiveness of the proposed approach for low-power VLSI applications.
Moreover, the shift from traditional 1-bit control signals to 4-bit reversible logic control enhances
operational flexibility and efficiency. Beyond ALU design, this work underscores the versatility
of reversible logic in broader digital design applications, such as encoders and other complex
circuits.

The incorporation of additional reversible gates like CNOT, DNG, and HNG further emphasizes
the potential to optimize power, delay, and area in future designs. In summary, this research
establishes the superiority of reversible logic in modern computing architectures, offering a
promising direction for the development of energy-efficient, scalable, and sustainable digital
systems. The innovations presented in this project pave the way for next-generation low-power
FPGA-based solutions in advanced computing environments.

55
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
7.2 FUTURE SCOPE

Applicable to RISC Processors:

The proposed 64-bit FPGA-based ALU using reversible logic has substantial potential for
integration into Reduced Instruction Set Computing (RISC) processors. Since RISC architectures
emphasize simplicity and efficiency through a limited set of instructions, incorporating a
reversible logic-based ALU aligns well with the goal of minimizing power consumption and
reducing circuit complexity. The low-delay and area-efficient characteristics of the proposed
ALU make it an ideal component for building energy-efficient, high-speed RISC cores.
Furthermore, the 4-bit control signal mechanism demonstrated in this design offers a scalable
and modular control strategy, which is crucial for implementing streamlined instruction
execution in RISC processors. With continued research and optimization, this reversible ALU
can be extended to form the arithmetic core of fully reversible RISC processors, paving the way
for the development of low-power embedded systems, portable computing devices, and
quantum-compatible processor architectures. This future integration will contribute to advancing
sustainable computing and next-generation microprocessor designs.

56
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC

CHAPTER-8

REFERENCES

57
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
 64-BIT FPGA BASED ALU EMPLOYING
REVERSIBLE LOGIC
8.1 REFERENCES

[1] Chandni N. Naik, Vaishnavi M. Velvani, Pooja J. Patel, Khushbu G. Parekh, "VLSI Based 16
Bit ALU with Interfacing Circuit", International Journal of Innovative and Emerging Research in
Engineering Volume 2, Issue 3, 2015.

[2] Arvind Rajput, Anil Goyal, “Design and comparison of low power & high speed 4-bit ALU”,
Proc. of 2nd National Conference on Challenges & Opportunities in Information Technology
(COIT-2008), RIMT-IET, Mandi Gobindgarh. March 29, 2008.

[3] Dhanabal R, Bharathi V, Saira Salim, “design of 16-bit low power ALU- dbgpu”, Dhanabal
R et.al / International Journal of Engineering and Technology (IJET), ISSN: 0975-4024, Vol.5
No.3,Jun-Jul 2013.

[4] G. Moore, “Cramming more components onto integrated circuits”, Electronics Magazine, 19
April, 1965.

[5] Jarrod D. Luker and Vinod B. Prasad, “RISC System Design in an FPGA”, Bradley University,
IEEE 2001, pp.532-536.

[6] J.L. Hennessy, “VLSI Processor Architecture”, IEEE Tran-.Computers, vol. C-33, no. 12, pp.
1221-1246, 1984.

[7] Nilam Patel, Prof. J.H.Patil, “FPGA Based Implementation of 16 bit RISC Microcontroller ”,
International Journal of scientific Research, Volume 4, Issue1, January 2015.

[8] Paul P. Chu, Deepak R. Mithani, “32-bit extended function Arithmetic-logic unit on single
chip”, U.S. Patent Document, Vol. 3, Issue 7, July 1984.

[9] Rahul R. Balwaik, Yogesh M. Jain, Amutha Jeyankar, “VLSI design of 16-bit processor”,
International Journal of VLSI and Embedded Systems-IJVES ISSN-2249, Vol04, June 2013.

[10] S. de Pablo, J.A. Cebrián, L.C. Herrero, A.B. Rey (2006), “A very simple 8-bit RISC
processor for FPGA”, RISCuva1 FPGA world 2006.

58
Dept of ECE,
N.B.K.R.I.S.T, Vidyanagar.
International Journal of Innovative Research in Science
Engineering and Technology (IJIRSET)
(A Monthly, Peer Reviewed, Refereed, Scholarly Indexed, Open Access Journal)

Impact Factor: 8.699 Volume 14, Issue 4, April 2025

 |www.ijirset.com |A Monthly, Peer Reviewed & Refereed Journal| e-ISSN: 2319-8753| p-ISSN: 2347-6710|

Volume 14, Issue 4, April 2025

|DOI: 10.15680/IJIRSET.2025.1404640|

64-Bit FPGA based ALU Employing

Reversible Logic
Dr. G. Harinatha Reddy1, Srisailam Bhavya Sree2, Cheelasani Ruchitha3,
Yatham Adi ShankarReddy4, Sirigiri Venkata Praveen Kumar5
Professor & Head, Dept. of ECE, NBKR Institute of Science &Technology, Vidyanagar, India 1
U. G. Student, IV B.Tech ( ECE) , Dept. of ECE, NBKR Institute of Science & Technology, Vidyanagar, India2-5

ABSTRACT: The Arithmetic Logic Unit (ALU) is a critical component in digital system design, responsible for
executing fundamental arithmetic and logical operations. This project presents the design and implementation of a 64-
bit ALU utilizing reversible logic gates, developed using Verilog Hardware Description Language (HDL) and
synthesized on the Xilinx ISE 14.7 platform using an FPGA development board. Reversible logic gates, characterized
by their ability to uniquely map input vectors to output vectors and vice versa, mitigate issues such as data loss and
excessive power dissipation commonly encountered in conventional (irreversible) logic circuits. By leveraging
reversible logic, the proposed ALU design achieves notable improvements in speed and power efficiency over
traditional gate-based architectures. A comprehensive library of reversible gates including AND, OR, NAND, NOR,
and XOR was designed in Verilog HDL to construct the core components of the ALU. These include a full adder, full
subtractor, 2:4 decoder, 3:8 decoder, multiplier, and comparator. The functionality and performance of the proposed
ALU were validated through synthesis and simulation using the Xilinx Vivado design suite. The results confirm the
ALU’s suitability for low-power Very Large Scale Integration (VLSI) applications, demonstrating clear advantages
over conventional ALU designs in terms of energy efficiency and operational speed.

KEYWORDS: Reversible gates, Verilog HDL, Feynman gate, Peres gate, Toffoli gate, Fredkin gate, Arithmetic Logic
Unit.

I. INTRODUCTION

The widespread deployment of microprocessors and digital signal processors has led to a continuous demand for high-
performance arithmetic hardware, positioning it as a critical and ongoing challenge in computer architecture. At the
centre of this innovation lies the Arithmetic Logic Unit (ALU) a core element that serves as the processing engine of any
computing system. The ALU is responsible for executing both arithmetic and logical operations essential for system
functionality. It performs key operations such as addition, subtraction, multiplication, division, and logic operations like
AND, OR, XOR, and NOT. The performance of the ALU directly impacts the speed, power efficiency, and parallelism
of the processor. To meet the growing requirements of modern computing applications including scientific simulations,
AI systems, and embedded applications ALUs are designed with a focus on speed optimization and low power
consumption, often incorporating advanced techniques like pipelining, parallelism, and custom instruction sets. In
today’s processors, cache memory plays a pivotal role in accelerating computation. Acting as a high-speed buffer, it
stores frequently used data and instructions, significantly reducing the time to access slower main memory. This results
in a more responsive processor with improved throughput and computational efficiency. Cache and ALU together
contribute to improved data handling, execution speed, and energy efficiency, laying the foundation for optimized
performance across all modern computing domains. This work focuses on the design and implementation of functional
blocks of a 64-bit ALU using Verilog HDL, targeting VLSI and ASIC-based systems. The ALU is designed as a
combinational logic unit capable of performing key arithmetic and logic operations and is a fundamental building block
in digital system design. With the trend towards miniaturization and complexity, modern ALUs are becoming more
compact while offering enhanced performance. These are frequently used in both general-purpose processors and
application-specific systems.

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Volume 14, Issue 4, April 2025

|DOI: 10.15680/IJIRSET.2025.1404640|
A. Overview of the ALU
An ALU is a digital circuit that processes binary integers through arithmetic and bitwise logical functions. In this
design:
• The ALU performs addition, subtraction, logic functions, and comparisons.
• A multiplexer selects the required operation based on control lines.
• For arithmetic operations, three inputs A, B, and Cin are used.
• Logic functions generally require only A and B.

B. Arithmetic Operations
Arithmetic forms the backbone of all numerical computation. The ALU supports:
• Addition and Subtraction: Implemented using full adders/subtractors.
• Comparison: Includes greater than, less than, and equal to operations.
• These functions are fundamental in CPUs and digital controllers.
The arithmetic unit is designed for accuracy, low latency, and scalability for 64-bit processing, supporting applications
requiring higher numerical precision.

C. Logical Operations
The logical unit executes bitwise operations, which are key in:
• Data masking
• Bit manipulation
• Conditional logic evaluation
Supported operations: AND, OR, NOT, XOR Each gate was coded in Verilog HDL, verified independently, and
integrated into the ALU core. Logic gates form combinational circuits, which are the building blocks of complex logical
functionality. These gates enable execution of Boolean functions that define the logic behaviour of the ALU.

II. LITERATURE SURVEY

Recent advancements in Arithmetic Logic Unit (ALU) design have emphasized optimizing performance metrics such
as speed, power consumption, and chip area. Ravindran and Regeena (2015)[1] proposed a 16-bit ALU utilizing a
combination of CMOS, pseudo-NMOS, and Pass Transistor Logic to enhance performance, employing a Carry Skip
Adder configuration validated through DSCH and Microwind tools. Kumar and Singh (2021)[2] introduced a 4-bit
ALU based on Complementary Energy Path Adiabatic Logic (CEPAL), achieving a 55% improvement in power
efficiency over conventional CMOS designs at 100 MHz and 2.5 V, with analysis conducted using Tanner EDA tools
and 250 nm technology libraries. In embedded systems, Rengasamy et al. (2013)[3] focused on reducing power
consumption in a 16-bit ALU by activating only one functional unit at a time, optimizing key modules like the adder
and multiplier using a Carry Look Ahead Adder and column bypassing techniques, respectively, with the entire design
implemented in Verilog HDL. Buddhini and Wijesinghe (2016)[4] detailed the design and hardware implementation of
a simple 16-bit RISC processor on a Xilinx Spartan-3E FPGA, capable of performing basic ALU operations, modelled
using Verilog and featuring a stack-based I/O transfer system with a simplified instruction set for efficient execution
and re-programmability. Collectively, these studies underscore the importance of strategic design choices in ALU
development, leveraging various logic families, adiabatic logic, and architectural optimizations to enhance performance
while minimizing power consumption and chip area.

III. PROPOSED METHOD

The proposed 64-bit Arithmetic Logic Unit (ALU) leverages reversible logic gates to address power dissipation and
heat generation challenges inherent in traditional ALUs, particularly within Very Large-Scale Integration (VLSI)
designs. By employing gates such as Feynman, Toffoli, Fredkin, Peres, and Haghparast–Navi (HNG), the design
ensures lossless computation, thereby minimizing energy loss and enhancing efficiency. The ALU supports 16
arithmetic and logic operations, controlled via a 4-bit signal, and features a modular architecture composed of cascaded
1-bit reversible units to handle 64-bit operands. This structure facilitates scalability while maintaining performance and
energy efficiency. Key functional units include the Arithmetic Unit for operations like addition and multiplication, the
Logical Unit for operations such as AND and OR, the Shift and Rotate Unit, and the Comparison and Selection Unit.
Collectively, these units contribute to reduced computational delay, high fault tolerance, and minimal signal

IJIRSET©2025 | An ISO 9001:2008 Certified Journal | 10399

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Volume 14, Issue 4, April 2025

|DOI: 10.15680/IJIRSET.2025.1404640|
degradation. The reversible ALU's design aligns with green computing objectives and is well-suited for applications in
digital signal processors, low-power devices, general computing, and emerging technologies like quantum computing.
Furthermore, the design emphasizes optimization parameters such as minimizing constant inputs, garbage outputs, and
quantum cost, which are critical for efficient reversible computing. Experimental implementations using platforms like
Xilinx 80nm technology have demonstrated significant reductions in area and delay compared to conventional designs .
These enhancements not only improve computational efficiency but also make the ALU highly suitable for integration
into advanced computing systems, including those requiring Multiply and Accumulate (MAC) operations common in
artificial intelligence and real-time processing applications

Control signal Operation

0000 sum
0001 a-b
0010 a* b
0011 a|b
0100 ~a
0101 R0
0110 ~(a ^ b)
0111 ~(a & b)
1000 32'd0
1001 ~(a | b)
1010 a&b
1011 IO_STS
1100 INC
1101 b*1
1110 a^b
1111 a*1

Table. 1. 16 operations using 4-bit control signal

Fig. 1. Block Diagram of 64-bit ALU

IJIRSET©2025 | An ISO 9001:2008 Certified Journal | 10400

 |www.ijirset.com |A Monthly, Peer Reviewed & Refereed Journal| e-ISSN: 2319-8753| p-ISSN: 2347-6710|

Volume 14, Issue 4, April 2025

|DOI: 10.15680/IJIRSET.2025.1404640|
IV. EXPERIMENTAL RESULTS

The implementation of a 64-bit FPGA-based Arithmetic Logic Unit (ALU) utilizing 4-bit control signals and reversible
logic gates including Peres, Fredkin, Feynman, and Toffoli gates has demonstrated significant improvements in key
performance metrics. The design efficiently performs 16 arithmetic and logical operations with minimal computational
delay, making it well-suited for high-performance computing. In terms of resource utilization, the design uses only 468
Slice LUTs and 192 Slice Registers, confirming its area-efficient nature. Timing analysis indicates a maximum delay of
16.585 ns with no constraint violations, suggesting a well-balanced and stable architecture. All critical paths are
optimized with manageable logic and net delays, ensuring effective data propagation across the system. The power
analysis reveals a total consumption of 39.787W, with a junction temperature of 99.4°C. While this value may appear
high, it is an anticipated result given the system’s purpose of handling 64-bit wide arithmetic and logic operations. The
design also exhibits low static power consumption (0.795W) and efficient usage of logic resources, reinforcing its
potential for low-area VLSI systems. This study demonstrates that the integration of reversible logic with 4-bit control
signals not only enhances operational flexibility but also contributes to optimized power and area performance. With
appropriate power constraint tuning and further optimization, this reversible ALU architecture is scalable and accurate,
showing excellent promise for next-generation, low-power, high-speed digital systems.

Fig. 2. Simulation Waveforms of 64-bit ALU Fig. 3. Area Values of 64-bit ALU

Fig. 4. Delay Values of 64-bit ALU Fig. 5. Power Values of 64-bit ALU

V. CONCLUSION

The proposed 64-bit FPGA-based ALU employing reversible logic showcases substantial improvements in
computational efficiency, reduced power dissipation, minimized chip area, and optimized delay. By integrating
reversible logic gates such as Peres, Fredkin, Feynman, and Toffoli, the ALU efficiently performs 16 arithmetic and
logical operations while significantly lowering energy consumption. The implementation of both 64-bit and 32-bit

IJIRSET©2025 | An ISO 9001:2008 Certified Journal | 10401

 |www.ijirset.com |A Monthly, Peer Reviewed & Refereed Journal| e-ISSN: 2319-8753| p-ISSN: 2347-6710|

Volume 14, Issue 4, April 2025

|DOI: 10.15680/IJIRSET.2025.1404640|
Reversible ALUs highlights the superior performance of reversible logic when compared to conventional irreversible
logic designs. The comparative analysis reveals notable reductions in power dissipation, area(no. of LUTs), and logic
delay achieved by utilizing 4-bit control signals with reversible logic gates. This demonstrates the effectiveness of the
proposed approach for low-power VLSI applications. Moreover, the shift from traditional 1-bit control signals to 4-bit
reversible logic control enhances operational flexibility and efficiency. Beyond ALU design, this work underscores the
versatility of reversible logic in broader digital design applications, such as encoders and other complex circuits. The
incorporation of additional reversible gates like CNOT, DNG, and HNG further emphasizes the potential to optimize
power, delay, and area in future designs. In summary, this research establishes the superiority of reversible logic in
modern computing architectures, offering a promising direction for the development of energy-efficient, scalable, and
sustainable digital systems. The innovations presented in this project pave the way for next-generation low-power
FPGA-based solutions in advanced computing environments.

REFERENCES

[1] Chandni N. Naik, Vaishnavi M. Velvani, Pooja J. Patel, Khushbu G. Parekh, "VLSI Based 16 Bit ALU with
Interfacing Circuit", International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue
3, 2015.
[2] Arvind Rajput, Anil Goyal, “Design and comparison of low power & high speed 4-bit ALU”, Proc. of 2nd
National Conference on Challenges & Opportunities in Information Technology (COIT-2008), RIMT-IET,
Mandi Gobindgarh. March 29, 2008.
[3] Dhanabal R, Bharathi V, Saira Salim, “design of 16-bit low power ALU- dbgpu”, Dhanabal R et.al /
International Journal of Engineering and Technology (IJET), ISSN: 0975-4024, Vol.5 No.3,Jun-Jul 2013.
[4] G. Moore, “Cramming more components onto integrated circuits”, Electronics Magazine, 19 April, 1965.
[5] Jarrod D. Luker and Vinod B. Prasad, “RISC System Design in an FPGA”, Bradley University, IEEE 2001,
pp.532-536.
[6] J.L. Hennessy, “VLSI Processor Architecture”, IEEE Tran-.Computers, vol. C-33, no. 12, pp. 1221-1246, 1984.
[7] Nilam Patel, Prof. J.H.Patil, “FPGA Based Implementation of 16 bit RISC Microcontroller ”, International
Journal of scientific Research, Volume 4, Issue1, January 2015.
[8] Paul P. Chu, Deepak R. Mithani, “32-bit extended function Arithmetic-logic unit on single chip”, U.S. Patent
Document, Vol. 3, Issue 7, July 1984.
[9] Rahul R. Balwaik, Yogesh M. Jain, Amutha Jeyankar, “VLSI design of 16-bit processor”, International Journal
of VLSI and Embedded Systems-IJVES ISSN-2249, Vol04, June 2013.
[10] [10] S. de Pablo, J.A. Cebrián, L.C. Herrero, A.B. Rey (2006), “A very simple 8-bit RISC processor for
FPGA”, RISCuva1 FPGA world 2006.

IJIRSET©2025 | An ISO 9001:2008 Certified Journal | 10402

(A Monthly, Peer Reviewed, Refereed, Multidisciplinary, Scholarly Indexed, Open
Access Journal since 2012)

Impact
Factor
8.699

The Board of IJIRSET is hereby Awarding this Certificate to

Dr. G. Harinatha Reddy

Professor & Head, Department of ECE, NBKR Institute of Science
&Technology, Vidyanagar, India

in Recognition of Publication of the Paper Entitled

“64-Bit FPGA Based ALU Employing Reversible Logic”

in IJIRSET, Volume 14, Issue 4, April 2025
(A Monthly, Peer Reviewed, Refereed, Multidisciplinary, Scholarly Indexed, Open
Access Journal since 2012)

Impact
Factor
8.699

The Board of IJIRSET is hereby Awarding this Certificate to

Srisailam Bhavya Sree

U. G. Student, IV B.Tech ( ECE) , Department of ECE, NBKR Institute of
Science & Technology, Vidyanagar, India

in Recognition of Publication of the Paper Entitled

“64-Bit FPGA Based ALU Employing Reversible Logic”

in IJIRSET, Volume 14, Issue 4, April 2025
(A Monthly, Peer Reviewed, Refereed, Multidisciplinary, Scholarly Indexed, Open
Access Journal since 2012)

Impact
Factor
8.699

The Board of IJIRSET is hereby Awarding this Certificate to

Cheelasani Ruchitha
U. G. Student, IV B.Tech ( ECE) , Department of ECE, NBKR Institute of
Science & Technology, Vidyanagar, India

in Recognition of Publication of the Paper Entitled

“64-Bit FPGA Based ALU Employing Reversible Logic”

in IJIRSET, Volume 14, Issue 4, April 2025
(A Monthly, Peer Reviewed, Refereed, Multidisciplinary, Scholarly Indexed, Open
Access Journal since 2012)

Impact
Factor
8.699

The Board of IJIRSET is hereby Awarding this Certificate to

Yatham Adi Shankar Reddy

U. G. Student, IV B.Tech ( ECE) , Department of ECE, NBKR Institute of
Science & Technology, Vidyanagar, India

in Recognition of Publication of the Paper Entitled

“64-Bit FPGA Based ALU Employing Reversible Logic”

in IJIRSET, Volume 14, Issue 4, April 2025
(A Monthly, Peer Reviewed, Refereed, Multidisciplinary, Scholarly Indexed, Open
Access Journal since 2012)

Impact
Factor
8.699

The Board of IJIRSET is hereby Awarding this Certificate to

Sirigiri Venkata Praveen Kumar

U. G. Student, IV B.Tech ( ECE) , Department of ECE, NBKR Institute of
Science & Technology, Vidyanagar, India

in Recognition of Publication of the Paper Entitled

“64-Bit FPGA Based ALU Employing Reversible Logic”

in IJIRSET, Volume 14, Issue 4, April 2025